WO2020012810A1

WO2020012810A1 - Silicon carbide semiconductor device

Info

Publication number: WO2020012810A1
Application number: PCT/JP2019/021277
Authority: WO
Inventors: 田中　聡
Original assignee: 住友電気工業株式会社
Priority date: 2018-07-11
Filing date: 2019-05-29
Publication date: 2020-01-16
Also published as: JPWO2020012810A1

Abstract

This silicon carbide semiconductor device has a silicon carbide semiconductor chip and a resin. The silicon carbide semiconductor chip includes a silicon carbide substrate and an electrode on the silicon carbide substrate. The silicon carbide substrate has: a first principal surface in contact with the electrode; a second principal surface on the opposite side to the first principal surface; an outer peripheral surface contiguous with each of the first principal surface and the second principal surface; an outer peripheral region including the outer peripheral surface; an inner region surrounded by the outer peripheral region and provided with a silicon carbide semiconductor element; and a first trench positioned in the first principal surface of the outer peripheral region. The resin covers each of the first principal surface and the outer peripheral surface and is provided inside the first trench.

Description

Silicon carbide semiconductor device

The present disclosure relates to a silicon carbide semiconductor device. This application claims the priority based on Japanese Patent Application No. 2018-131496 filed on July 11, 2018. The entire contents described in the Japanese patent application are incorporated herein by reference.

Japanese Patent Application Laid-Open No. 2014-139967 (Patent Document 1) discloses a trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

JP 2014-139967 A

珪素 A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide semiconductor chip and a resin. The silicon carbide semiconductor chip includes a silicon carbide substrate and an electrode on the silicon carbide substrate. The silicon carbide substrate has a first main surface in contact with the electrode, a second main surface opposite to the first main surface, an outer peripheral surface continuous with each of the first main surface and the second main surface, and an outer peripheral surface including the outer peripheral surface. A region, an inner region surrounded by the outer peripheral region and provided with the silicon carbide semiconductor element, and a first groove located on the first main surface of the outer peripheral region. The resin covers each of the first main surface and the outer peripheral surface and is provided inside the first groove.

FIG. 1 is a schematic vertical sectional view showing a configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a schematic plan view showing a configuration of the silicon carbide semiconductor chip according to the first embodiment. FIG. 3 is a schematic sectional view taken along line III-III in FIG. FIG. 4 is a schematic sectional view taken along line IV-IV in FIG. FIG. 5 is a schematic vertical sectional view showing a configuration of a first modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a schematic vertical sectional view showing a configuration of a second modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 7 is a schematic vertical sectional view showing a configuration of a third modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is a schematic vertical sectional view showing a configuration of a fourth modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a schematic vertical cross-sectional view showing a configuration of a fifth modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 10 is a schematic longitudinal sectional view showing a configuration of a sixth modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 11 is a schematic vertical sectional view showing a configuration of a seventh modification of the silicon carbide semiconductor device according to the first embodiment. FIG. 12 is a schematic plan view showing the configuration of the silicon carbide semiconductor chip according to the second embodiment. FIG. 13 is a schematic plan view showing the configuration of the silicon carbide semiconductor chip according to the third embodiment. FIG. 14 is a schematic plan view showing the configuration of the silicon carbide semiconductor chip according to the fourth embodiment. FIG. 15 is a schematic plan view showing the configuration of the silicon carbide semiconductor chip according to the fifth embodiment.

[Overview of Embodiment of the Present Disclosure]
First, an outline of an embodiment of the present disclosure will be described. In the crystallographic description in this specification, [] indicates the individual orientation, <> indicates the collective orientation, () indicates the individual plane, and indicates the collective plane with ｛｝. In addition, the fact that a crystallographic index is negative is usually expressed by attaching a “-” (bar) to a number, but in this specification, a minus sign is added before the number. I have.

(1) Silicon carbide semiconductor device 100 according to the present disclosure includes silicon carbide semiconductor chip 30 and resin 8. Silicon carbide semiconductor chip 30 includes silicon carbide substrate 10 and electrodes 28 on silicon carbide substrate 10. Silicon carbide substrate 10 has a first main surface 1 in contact with electrode 28, a second main surface 2 opposite to first main surface 1, and an outer peripheral surface connected to each of first main surface 1 and second main surface 2. 3, an outer peripheral region 50 including the outer peripheral surface 3, an inner region 40 surrounded by the outer peripheral region 50 and provided with the silicon carbide semiconductor element 90, and a first groove located on the first main surface 1 of the outer peripheral region 50. 7 are provided. The resin 8 covers each of the first main surface 1 and the outer peripheral surface 3 and is provided inside the first groove 7.

(2) In silicon carbide semiconductor device 100 according to the above (1), first groove 7 includes planar side surface 5 continuing to first main surface 1 and planar bottom surface 6 continuing to side surface 5. You may go out.

(3) In silicon carbide semiconductor device 100 according to (2) above, the angle formed between side surface 5 and bottom surface 6 may be 90 °.

(4) In silicon carbide semiconductor device 100 according to (2), the angle formed between side surface 5 and bottom surface 6 may be greater than 90 °.

(5) In silicon carbide semiconductor device 100 according to (2) above, the angle formed between side surface 5 and bottom surface 6 may be smaller than 90 °.

(6) In the silicon carbide semiconductor device 100 according to any one of the above (2) to (5), the resin 8 may be in contact with each of the side surface 5 and the bottom surface 6.

(7) In the silicon carbide semiconductor device 100 according to any one of the above (1) to (6), the depth of the first groove 7 may be 0.1 μm or more and 30 μm or less.

(8) In the silicon carbide semiconductor device 100 according to any one of the above (1) to (6), the width of the opening 19 of the first groove 7 may be 0.1 μm or more and 30 μm or less.

(9) In the silicon carbide semiconductor device 100 according to any one of the above (1) to (6), the value obtained by dividing the width of the opening 19 of the first groove 7 by the depth of the first groove 7 is 0.1. It may be 25 or more and 2 or less.

(10) In the silicon carbide semiconductor device 100 according to any one of the above (1) to (9), the second groove 82 and the third groove 83 which are located on the first main surface 1 of the outer peripheral region 50 and are separated from each other. And a fourth groove 84.

(11) In silicon carbide semiconductor device 100 according to (10) above, silicon carbide substrate 10 may have a rectangular shape in plan view. The first groove 7, the second groove 82, the third groove 83, and the fourth groove 84 may be located at four corners of a quadrangle, respectively.

(12) In the silicon carbide semiconductor device 100 according to any one of the above (1) to (9), the first groove 7 may surround the internal region 40 in plan view.

[Details of Embodiment of the Present Disclosure]
Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference characters, and description thereof will not be repeated.

(1st Embodiment)
First, the configuration of silicon carbide semiconductor device 100 according to the first embodiment will be described.

As shown in FIG. 1, silicon carbide semiconductor device 100 according to the first embodiment mainly includes silicon carbide semiconductor chip 30, resin 8, metal frame 74, and solder layer 73. The metal frame 74 is, for example, a copper frame. The copper frame may be plated with nickel. Silicon carbide semiconductor chip 30 is provided on metal frame 74 via solder layer 73. From another viewpoint, solder layer 73 is located between silicon carbide semiconductor chip 30 and metal frame 74. Resin 8 covers silicon carbide semiconductor chip 30 and solder layer 73.

珪素 Silicon carbide semiconductor chip 30 has third main surface 31 and fourth main surface 32. The fourth main surface 32 is on the opposite side of the third main surface 31. Silicon carbide semiconductor chip 30 is in contact with solder layer 73 on fourth main surface 32. Resin 8 covers third main surface 31 of silicon carbide semiconductor chip 30. The resin 8 is in contact with the solder layer 73 and the metal frame 74. Silicon carbide semiconductor chip 30 has silicon carbide substrate 10 (see FIG. 3). Supply of a current or the like to silicon carbide semiconductor chip 30 is performed via a wire or the like (not shown).

FIG. 2 is a schematic plan view showing the configuration of silicon carbide substrate 10. As shown in FIG. 2, silicon carbide substrate 10 has an internal region 40 (active region 40) and an outer peripheral region 50. As shown in FIG. 2, when viewed from a direction perpendicular to first main surface 1 (that is, in a plan view), outer peripheral region 50 surrounds active region 40. The groove 7 (first groove 7) is located on the first main surface 1 of the outer peripheral region 50. The outer peripheral region 50 has a first outer peripheral region 51 and a second outer peripheral region 52. The first outer peripheral region 51 contacts the active region 40. The second outer peripheral region 52 is located outside the first outer peripheral region 51. The shoulder 4 has a corner region 41 and a side region 42.

The second outer peripheral region 52 surrounds the first outer peripheral region 51. The second outer peripheral area 52 constitutes the shoulder 4. In the first outer peripheral area 51, for example, a guard ring 16 (see FIG. 4) is provided. Guard ring 16 surrounds active region 40. The groove 7 is provided in the second outer peripheral region 52. As shown in FIG. 2, the groove 7 may surround the active region 40 when viewed from a direction perpendicular to the first main surface 1. The groove 7 may surround the first outer peripheral region 51 as viewed from a direction perpendicular to the first main surface 1. The groove 7 is annular when viewed from a direction perpendicular to the first main surface 1.

FIG. 3 is a schematic sectional view taken along line III-III in FIG. As shown in FIG. 3, silicon carbide semiconductor element 90 is provided in active region 40. Silicon carbide semiconductor element 90 is, for example, a MOSFET. Silicon carbide semiconductor element 90 includes silicon carbide substrate 10, gate insulating film 24, gate electrode 22, interlayer insulating film 23, source electrode 28, and drain electrode 25. Note that FIG. 2 shows only silicon carbide substrate 10 provided with groove 7, and that gate insulating film 24, gate electrode 22, interlayer insulating film 23, source electrode 28, and drain electrode 25 Omitted.

珪素 Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 15 and a silicon carbide epitaxial layer 20 on silicon carbide single crystal substrate 15. Silicon carbide substrate 10 has first main surface 1, second main surface 2, and outer peripheral surface 3. The second main surface 2 is on the opposite side of the first main surface 1. The outer peripheral surface 3 is continuous with each of the first main surface 1 and the second main surface 2. The first main surface 1 and the outer peripheral surface 3 form a shoulder 4. Silicon carbide epitaxial layer 20 forms first main surface 1. Silicon carbide single crystal substrate 15 forms second main surface 2. Silicon carbide single crystal substrate 15 and silicon carbide epitaxial layer 20 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 15 includes an n-type impurity such as nitrogen (N) and has an n-type (first conductivity type).

{First main surface 1} is, for example, a surface inclined by an off angle of 8 ° or less in the off direction with respect to the {0001} plane or the {0001} plane. First main surface 1 may be, for example, a (000-1) plane or a (0001) plane. The first main surface 1 may be, for example, a surface inclined by an off angle of 8 ° or less with respect to the (000-1) plane in the off direction, or 8 ° or less with respect to the (0001) plane in the off direction. The surface may be inclined by the off angle. The off direction may be, for example, a <11-20> direction or a <1-100> direction. The off angle may be, for example, 1 ° or more, or 2 ° or more. The off angle may be 6 ° or less or 4 ° or less.

When {first main surface 1} is a {0001} surface, first direction 101 is, for example, a <11-20> direction. When first main surface 1 is inclined with respect to the {0001} plane, first direction 101 is a direction in which the <11-20> direction is projected on first main surface 1. Similarly, when first main surface 1 is a {0001} surface, second direction 102 is, for example, a <1-100> direction. When first main surface 1 is inclined with respect to the {0001} plane, second direction 102 is a direction in which the <1-100> direction is projected onto first main surface 1. The first main surface 1 extends along each of the first direction 101 and the second direction 102.

珪素 SiC epitaxial layer 20 mainly has drift region 11, body region 12, source region 13, and contact region 14. Drift region 11 is provided on silicon carbide single crystal substrate 15. Drift region 11 includes an n-type impurity such as nitrogen, for example, and has n-type conductivity. Drift region 11 may have a concentration of an n-type impurity lower than that of silicon carbide single crystal substrate 15.

The body region 12 is provided on the drift region 11. Body region 12 includes a p-type impurity such as aluminum (Al) and has a p-type (second conductivity type) conductivity type. The concentration of p-type impurities in body region 12 may be higher than the concentration of n-type impurities in drift region 11. Body region 12 is separated from each of first main surface 1 and second main surface 2.

Source region 13 is provided on body region 12 so as to be separated from drift region 11 by body region 12. Source region 13 contains an n-type impurity such as nitrogen or phosphorus (P), and has an n-type conductivity. Source region 13 constitutes first main surface 1. The concentration of the n-type impurity in the source region 13 may be higher than the concentration of the p-type impurity in the body region 12. The concentration of the n-type impurity in source region 13 is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

Contact region 14 contains a p-type impurity such as aluminum and has a p-type conductivity. The concentration of the p-type impurity in contact region 14 may be higher than the concentration of the p-type impurity in body region 12. Contact region 14 penetrates source region 13 and is in contact with body region 12. Contact region 14 forms first main surface 1. The concentration of the p-type impurity in contact region 14 is, for example, not less than 1 × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ²⁰ cm ⁻³ .

ゲート As shown in FIG. 3, a gate trench 9 is provided in the first main surface 1. The gate trench 9 includes a side wall surface 91 and a bottom portion 92. The side wall surface 91 is continuous with the first main surface 1. The bottom 92 is continuous with the side wall surface 91. Sidewall surface 91 penetrates source region 13 and body region 12 to reach drift region 11. In other words, the side wall surface 91 includes the source region 13, the body region 12, and the drift region 11. The bottom 92 is in the drift region 11. In other words, the bottom portion 92 is constituted by the drift region 11. Bottom portion 92 is, for example, a plane parallel to second main surface 2. Angle θ1 formed between side wall surface 91 and bottom 92 is, for example, not less than 115 ° and not more than 135 °. Angle θ1 may be, for example, 120 ° or more. Angle θ1 may be, for example, 130 ° or less.

The gate insulating film 24 is, for example, an oxide film. Gate insulating film 24 is made of, for example, a material containing silicon dioxide. Gate insulating film 24 is in contact with each of side wall surface 91 and bottom portion 92 of gate trench 9. Gate insulating film 24 is in contact with drift region 11 at bottom 92. Gate insulating film 24 is in contact with source region 13, body region 12 and drift region 11 on sidewall surface 91. Gate insulating film 24 may be in contact with source region 13 on first main surface 1.

The gate electrode 22 is provided on the gate insulating film 24. Gate electrode 22 is made of, for example, polysilicon containing conductive impurities. Gate electrode 22 is arranged inside gate trench 9. Gate electrode 22 faces drift region 11, body region 12 and source region 13.

The source electrode 28 is in contact with the first main surface 1. Source electrode 28 has contact electrode 21 and source wiring 29. The source wiring 29 is provided on the contact electrode 21. Contact electrode 21 is in contact with source region 13 on first main surface 1. Contact electrode 21 may be in contact with contact region 14 on first main surface 1. Contact electrode 21 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon). The contact electrode 21 is in ohmic contact with the source region 13. The contact electrode 21 may be in ohmic contact with the contact region 14.

The drain electrode 25 is in contact with the second main surface 2. Drain electrode 25 is in contact with silicon carbide single crystal substrate 15 on second main surface 2. Drain electrode 25 is electrically connected to drift region 11. Drain electrode 25 is made of a material containing, for example, NiSi (nickel silicon) or TiAlSi (titanium aluminum silicon).

(4) The interlayer insulating film 23 is provided in contact with each of the gate electrode 22 and the gate insulating film 24. Interlayer insulating film 23 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 23 electrically insulates the gate electrode 22 and the source electrode 28. Part of the interlayer insulating film 23 may be provided inside the gate trench 9. The source wiring 29 may cover the interlayer insulating film 23. Source wiring 29 is made of, for example, a material containing Al.

FIG. 4 is a schematic cross-sectional view taken along the line IV-IV of FIG. As shown in FIG. 2, the IV-IV line is a straight line along the diagonal line of silicon carbide semiconductor chip 30 when viewed from a direction perpendicular to first main surface 1. As shown in FIG. 4, groove 7 is provided in first main surface 1 of outer peripheral region 50 of silicon carbide substrate 10. The groove 7 includes a side surface 5 and a bottom surface 6. The side surface 5 is continuous with the first main surface 1. The bottom surface 6 is continuous with the side surface 5. The side surface 5 is, for example, planar. The bottom surface 6 is, for example, planar. The angle θ2 formed between the side surface 5 and the bottom surface 6 is, for example, greater than 90 °. Angle θ2 is, for example, not less than 115 ° and not more than 135 °. Angle θ2 may be, for example, 120 ° or more. Angle θ2 may be, for example, 130 ° or less. The interval between the pair of side surfaces 5 facing each other in a sectional view increases from the bottom surface 6 toward the first main surface 1 (forward taper). The width 111 of the opening 19 of the groove 7 is larger than the width 113 of the bottom surface 6 of the groove 7.

The two side surfaces 5 of the groove 7 may be asymmetric with respect to a straight line perpendicular to the bottom surface 6. That is, the angle between one side surface 5 and the bottom surface 6 may be different from the angle between the other side surface 5 and the bottom surface. Illustratively, the angle between one side surface 5 and the bottom surface 6 may be greater than 90 °, and the angle between the other side surface 5 and the bottom surface may be less than 90 °.

The groove 7 can be formed by, for example, thermal etching. Specifically, it can be performed by heating in an atmosphere containing a reactive gas having at least one or more halogen atoms. The at least one kind of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), SF ₆ or carbon tetrafluoride (CF ₄ ). For example, thermal etching is performed by using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 800 ° C. or more and 900 ° C. or less. Note that the reaction gas may include a carrier gas in addition to the chlorine gas and the oxygen gas described above. As the carrier gas, for example, a nitrogen gas, an argon gas, a helium gas, or the like can be used. Groove 7 is formed in first main surface 1 of silicon carbide substrate 10 by thermal etching. In this case, the first main surface 1 is a (000-1) plane or a plane inclined in an off direction by an off angle of 8 ° or less with respect to the (000-1) plane. The groove 7 and the gate trench 9 may be formed at the same time.

珪素 As shown in FIG. 4, in outer peripheral region 50, silicon carbide substrate 10 has guard ring 16 and drift region 11. Guard ring 16 includes a p-type impurity such as aluminum (Al) or boron (B), and has a p-type (second conductivity type). Drift region 11 in outer peripheral region 50 is continuous with drift region 11 in active region 40. The drift region 11 in the outer peripheral region 50 forms the groove 7. Each of the side surface 5 and the bottom surface 6 of the groove 7 is constituted by a drift region 11. The groove 7 is located on the outer peripheral side of the guard ring 16. The groove 7 is provided in the second outer peripheral area 52. In the cross section shown in FIG. 4, each of the width of second outer peripheral region 52 and the depth of groove 7 is, for example, 20 μm. At this time, the value obtained by dividing the width of the second outer peripheral region 52 by the depth of the groove 7 is 1. The angle θ2 formed between the side surface 5 and the bottom surface 6 (see FIG. 4) is, for example, in a range from 120 ° to 130 °. The second outer peripheral region 52 includes the outer peripheral surface 3. The groove 7 is located between the guard ring 16 and the outer peripheral surface 3. Guard ring 16 is located on the outer peripheral side of body region 12. Guard ring 16 is located between body region 12 and groove 7.

Insulating film 26 is in contact with body region 12 and guard ring 16 on first main surface 1. Insulating film 26 is made of, for example, a material containing silicon dioxide. The insulating film 26 may be located on the inner peripheral side of the groove 7. The resin 8 is provided inside the groove 7. The resin 8 covers the first main surface 1, the outer peripheral surface 3, and the shoulder 4. The resin 8 may be in contact with the insulating film 26. The resin 8 covers each of the active region 40 and the outer peripheral region 50. The resin 8 may be in contact with the source wiring 29. The groove 7 may be filled with a resin 8.

樹脂 As shown in FIG. 4, the resin 8 is in contact with the drift region 11 on each of the side surface 5 and the bottom surface 6 of the groove 7. The resin 8 is in contact with each of the side surface 5 and the bottom surface 6. The resin 8 is in contact with the corner region 41 of the shoulder 4. The resin 8 is in contact with the side region 42 of the shoulder 4 (see FIG. 2). The resin 8 may be in contact with the drift region 11 on the outer peripheral surface 3. Resin 8 may be in contact with silicon carbide single crystal substrate 15. The resin 8 may be in contact with the drain electrode 25. Resin 8 is resin 8 for sealing silicon carbide semiconductor chip 30. The resin 8 is, for example, an epoxy resin, but is not limited to an epoxy resin. The resin 8 may be a heat-resistant organic resin such as a phenol resin or a maleimide resin, or a resin nanocomposite resin in which inorganic nanoparticles are uniformly monodispersed in a polymer component.

(4) As shown in FIG. 4, the depth 112 of the groove 7 is, for example, 0.1 μm or more and 30 μm or less. The upper limit of the depth 112 of the groove 7 is not particularly limited, but is, for example, 10 μm or less. Preferably, the upper limit of the depth 112 of the groove 7 is 20 μm or less. The lower limit of the depth 112 of the groove 7 is not particularly limited, but is, for example, 1 μm or more. Preferably, the lower limit of the depth 112 of the groove 7 is 3 μm or more. Note that the depth 112 of the groove 7 is a distance between the bottom surface 6 and the first main surface 1 in a direction perpendicular to the first main surface 1.

(4) As shown in FIG. 4, the width 111 of the opening 19 of the groove 7 is, for example, 0.1 μm or more and 30 μm or less. The upper limit of the width 111 of the opening 19 of the groove 7 is not particularly limited, but is, for example, 20 μm or less. Preferably, the upper limit of the width 111 of the opening 19 of the groove 7 is 10 μm or less. The lower limit of the width 111 of the opening 19 of the groove 7 is not particularly limited, but is, for example, 1 μm or more. Preferably, the lower limit of the width 111 of the opening 19 of the groove 7 is 10 μm or more. The width 111 of the opening 19 of the groove 7 is the width of the opening 19 of the groove 7 in a direction parallel to the first main surface 1 in the cross section of FIG. The width 111 of the opening 19 of the groove 7 is a width measured at the boundary between the side surface 5 of the groove 7 and the first main surface 1.

値 As shown in FIG. 4, the value obtained by dividing the width 111 of the opening 19 of the groove 7 by the depth 112 of the groove 7 is, for example, 0.2 or more and 2 or less. The upper limit of the value obtained by dividing the width 111 of the opening 19 of the groove 7 by the depth 112 of the groove 7 is not particularly limited, but is, for example, 1.5 or less. Preferably, the upper limit of the value obtained by dividing the width 111 of the opening 19 of the groove 7 by the depth 112 of the groove 7 is 1 or less.

Next, a configuration of a first modification of silicon carbide semiconductor device 100 according to the first embodiment will be described.

角度 As shown in FIG. 5, the angle θ2 between the side surface 5 and the bottom surface 6 of the groove 7 may be, for example, 90 °. In this case, the angle between the first main surface 1 and the side surface 5 is also 90 °. The interval between the pair of side surfaces 5 facing each other in a sectional view is constant from the bottom surface 6 toward the first main surface 1. Side surface 5 of groove 7 is parallel to outer peripheral surface 3 of silicon carbide substrate 10. The depth of the groove 7 may be larger than the depth of the guard ring 16. The depth of the groove 7 may be larger than the depth of the body region 12.

The groove 7 can be formed using, for example, reactive ion etching. More specifically, silicon carbide substrate 10 is etched with mask layer (not shown) having opening 19 formed on first main surface 1. As an etching method, for example, reactive ion etching, in particular, inductively coupled plasma reactive ion etching can be used. For example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF ₆ ) or a mixed gas of sulfur hexafluoride and oxygen (O ₂ ) as a reaction gas can be used.

Next, the configuration of a second modification of silicon carbide semiconductor device 100 according to the first embodiment will be described.

As shown in FIG. 6, the angle θ2 formed between the side surface 5 and the bottom surface 6 of the groove 7 may be smaller than 90 °, for example. In this case, the angle formed by first main surface 1 and side surface 5 is also smaller than 90 °. Angle θ2 is, for example, not less than 45 ° and not more than 65 °. Angle θ2 may be, for example, 50 ° or more. Angle θ2 may be, for example, 60 ° or less. The distance between the pair of side surfaces 5 facing each other in a sectional view becomes narrower (reverse taper) from the bottom surface 6 toward the first main surface 1. The width 111 of the opening 19 of the groove 7 is smaller than the width 113 of the bottom surface 6 of the groove 7. The depth of the groove 7 may be larger than the depth of the guard ring 16. The depth of the groove 7 may be larger than the depth of the body region 12.

The groove 7 can be formed by, for example, thermal etching. The conditions of the thermal etching are as described above. When forming the groove 7 of the second modified example, the first main surface 1 is a surface inclined in the off direction by an off angle of 8 ° or less with respect to the (0001) plane or the (0001) plane.

Next, the configuration of a third modification of silicon carbide semiconductor device 100 according to the first embodiment will be described.

絶縁 As shown in FIG. 7, the insulating film 26 may be provided inside the groove 7. The insulating film 26 may be in contact with each of the side surface 5 and the bottom surface 6 of the groove 7. In other words, the insulating film 26 may be in contact with the drift region 11 on each of the side surface 5 and the bottom surface 6 of the groove 7. The insulating film 26 is arranged in a part of the groove 7 but does not completely fill the groove 7. Therefore, the resin 8 enters the inside of the groove 7. The resin 8 is provided between a pair of side surfaces 5 facing each other in a sectional view. The resin 8 is in contact with the insulating film 26 inside the groove 7.

Next, a configuration of a fourth modification of silicon carbide semiconductor device 100 according to the first embodiment will be described.

絶縁 As shown in FIG. 8, the insulating film 26 and the stress buffer layer may be provided inside the groove 7. The stress buffer layer 27 is provided on the insulating film 26. The stress buffer layer 27 is made of, for example, a material containing polyimide. The insulating film 26 may be in contact with each of the side surface 5 and the bottom surface 6 of the groove 7. In other words, the insulating film 26 may be in contact with the drift region 11 on each of the side surface 5 and the bottom surface 6 of the groove 7.

(4) The insulating film 26 is disposed in a part of the groove 7, but does not completely fill the groove 7. Similarly, the stress buffer layer 27 is disposed in a part of the groove 7 but does not completely fill the groove 7. Therefore, the resin 8 enters the inside of the groove 7. The resin 8 is provided between a pair of side surfaces 5 facing each other in a sectional view. The resin 8 is in contact with the stress buffer layer 27 inside the groove 7. The stress buffer layer 27 is in contact with the insulating film 26 inside the groove 7.

As shown in FIG. 8, in a cross section perpendicular to first main surface 1, each of insulating film 26 and stress buffer layer 27 may be provided along outer peripheral surface 3 of silicon carbide substrate 10. . The insulating film 26 may be in contact with the resin 8 at the outer peripheral portion of the insulating film 26. Similarly, the stress buffer layer 27 may be in contact with the resin 8 at the outer peripheral portion of the stress buffer layer 27.

Next, a configuration of a fifth modification example of silicon carbide semiconductor device 100 according to the first embodiment will be described.

絶縁 As shown in FIG. 9, each of the insulating film 26 and the stress buffer layer 27 is provided on the first main surface 1, but may not be provided inside the groove 7. The stress buffer layer 27 is provided on the insulating film 26. The stress buffer layer 27 is made of, for example, a material containing polyimide. Each of the insulating film 26 and the stress buffer layer 27 has a through hole 93. The resin 8 enters the groove 7 through the through hole 93. The resin 8 is in contact with the drift region 11 on each of the side surface 5 and the bottom surface 6 of the groove 7. The resin 8 is in contact with each of the side surface 5 and the bottom surface 6. The resin 8 may be in contact with a part of the first main surface 1.

Next, a configuration of a sixth modification of silicon carbide semiconductor device 100 according to the first embodiment will be described.

As shown in FIG. 10, the side surface 5 of the groove 7 may have a first side surface portion 17 and a second side surface portion 18. The first side surface 17 is continuous with the first main surface 1. The second side portion 18 is continuous with each of the first side portion 17 and the bottom surface 6. In a cross-sectional view, the interval between the pair of opposing first side surfaces 17 increases from the bottom surface 6 to the first main surface 1 (forward taper). The interval between the pair of second side surfaces 18 is substantially constant from the bottom surface 6 to the first main surface 1. Each of the pair of second side surfaces 18 extends in a direction substantially perpendicular to the first main surface 1. The angle θ2 formed between the second side surface portion 18 and the bottom surface 6 is, for example, 90 °. The width 111 of the opening 19 of the groove 7 is larger than the width 113 of the bottom surface 6 of the groove 7.

Next, the configuration of a seventh modification of silicon carbide semiconductor device 100 according to the first embodiment will be described.

As shown in FIG. 11, in a cross-sectional view, the interval between the pair of opposing first side surfaces 17 may decrease from the bottom surface 6 to the first main surface 1 (reverse taper). The interval between the pair of second side surfaces 18 is substantially constant from the bottom surface 6 to the first main surface 1. Each of the pair of second side surfaces 18 extends in a direction substantially perpendicular to the first main surface 1. The angle θ2 formed between the second side surface portion 18 and the bottom surface 6 is, for example, 90 °. The width 111 of the opening 19 of the groove 7 is smaller than the width 113 of the bottom surface 6 of the groove 7.

(2nd Embodiment)
Next, the configuration of silicon carbide semiconductor device 100 according to the second embodiment will be described. The silicon carbide semiconductor device 100 according to the second embodiment is different from the silicon carbide semiconductor device 100 according to the first embodiment mainly in the configuration having a plurality of grooves, and other configurations are the same as those in the first embodiment. This is the same as silicon carbide semiconductor device 100. Hereinafter, a description will be given focusing on a configuration different from silicon carbide semiconductor device 100 according to the first embodiment.

As shown in FIG. 12, silicon carbide substrate 10 is located on first main surface 1 of outer peripheral region 50 and is separated from each other by first groove 7, second groove 82, third groove 83, and third groove 83. A fourth groove 84, a fifth groove 85, a sixth groove 86, a seventh groove 87, and an eighth groove 88 may be provided. As shown in FIG. 12, when viewed from a direction perpendicular to first main surface 1, silicon carbide substrate 10 has a quadrangular shape. The first groove 7, the second groove 82, the third groove 83, and the fourth groove 84 are respectively located at four corners of a quadrangle. Specifically, the shape of first main surface 1 is a quadrangle. The first groove 7, the second groove 82, the third groove 83, and the fourth groove 84 are located at four corners of the first main surface 1. The active region 40 is located between the first groove 7 and the fourth groove 84. Similarly, the active region 40 is located between the second groove 82 and the third groove 83. In FIG. 10, an example in which grooves are arranged at eight locations is exemplified, but the number of grooves arranged on each side may be increased.

The fifth groove 85 is located between the first groove 7 and the second groove 82 in a direction parallel to the first direction 101. The sixth groove 86 is located between the third groove 83 and the fourth groove 84 in a direction parallel to the first direction 101. The seventh groove 87 is located between the first groove 7 and the third groove 83 in a direction parallel to the second direction 102. The eighth groove 88 is located between the second groove 82 and the fourth groove 84 in a direction parallel to the second direction 102.

見て As shown in FIG. 12, when viewed from a direction perpendicular to the first main surface 1, the shape of the first groove 7 is a hexagon, specifically, a regular hexagon. Opposite sides of the regular hexagon may be parallel to the first direction 101. The plurality of grooves are spaced apart from each other in each of a direction parallel to the first direction 101 and a direction parallel to the second direction 102. The plurality of grooves are located so as to surround the first outer peripheral region 51.

(Third embodiment)
Next, the configuration of silicon carbide semiconductor device 100 according to the third embodiment will be described. The silicon carbide semiconductor device 100 according to the third embodiment differs from the silicon carbide semiconductor device 100 according to the second embodiment mainly in the configuration in which the shape of the groove is L-shaped. This is the same as silicon carbide semiconductor device 100 according to the second embodiment. Hereinafter, a configuration different from silicon carbide semiconductor device 100 according to the second embodiment will be mainly described.

As shown in FIG. 13, silicon carbide substrate 10 has first groove 7, second groove 82, third groove 83, and fourth groove 84. The first groove 7, the second groove 82, the third groove 83, and the fourth groove 84 are respectively located at four corners of a square. As shown in FIG. 13, when viewed from a direction perpendicular to the first main surface 1, each of the plurality of grooves has an L-shape. Each of the plurality of grooves may be configured by the first region 71 and the second region 72. Each of the first region 71 and the second region 72 is a quadrangle when viewed from a direction perpendicular to the first main surface 1. Each of the first region 71 and the second region 72 may be rectangular when viewed from a direction perpendicular to the first main surface 1.

The first region 71 extends along the second direction 102. The long side direction of the first region 71 is a direction parallel to the second direction 102. The short side direction of the first region 71 is a direction parallel to the first direction 101. The second region 72 extends along the first direction 101. The long side direction of the second region 72 is a direction parallel to the first direction 101. The short side direction of the second region 72 is a direction parallel to the second direction 102. The long side of the first region 71 is in contact with the short side of the second region 72.

溝 A groove may not be provided between the first groove 7 and the second groove 82 in a direction parallel to the first direction 101. A groove may not be provided between the third groove 83 and the fourth groove 84 in a direction parallel to the first direction 101. No groove may be provided between the first groove 7 and the third groove 83 in a direction parallel to the second direction 102. The eighth groove 88 may not have a groove provided between the second groove 82 and the fourth groove 84 in a direction parallel to the second direction 102. A groove provided to surround the chip as shown in FIG. 2 and a groove provided at four corners as shown in FIG. 13 may be combined.

(Fourth embodiment)
Next, the configuration of silicon carbide semiconductor device 100 according to the fourth embodiment will be described. The silicon carbide semiconductor device 100 according to the fourth embodiment differs from the silicon carbide semiconductor device 100 according to the third embodiment mainly in the configuration in which the shape of the groove is rectangular, and the other configurations are the same as those in the third embodiment. This is the same as silicon carbide semiconductor device 100 according to the embodiment. Hereinafter, a description will be given focusing on a configuration different from silicon carbide semiconductor device 100 according to the third embodiment.

見て As shown in FIG. 14, each of the plurality of grooves has a rectangular shape when viewed from a direction perpendicular to the first main surface 1. Each of the plurality of grooves extends in a direction inclined with respect to each of a direction parallel to the first direction 101 and a direction parallel to the second direction 102. In other words, each of the long side and the short side of the rectangle extends in a direction inclined with respect to each of the direction parallel to the first direction 101 and the direction parallel to the second direction 102.

溝 Two grooves facing each other across the active region 40 are parallel to each other. Specifically, the long side of the first groove 7 is parallel to the long side of the fourth groove 84. The short side of the first groove 7 is parallel to the short side of the fourth groove 84. Similarly, the long side of the second groove 82 is parallel to the long side of the third groove 83. The short side of the second groove 82 is parallel to the short side of the third groove 83.

(Fifth embodiment)
Next, the configuration of silicon carbide semiconductor device 100 according to the fifth embodiment will be described. The silicon carbide semiconductor device 100 according to the fifth embodiment is different from the silicon carbide semiconductor device 100 according to the fourth embodiment mainly in the configuration in which the extending directions of the four grooves are all parallel. Is the same as silicon carbide semiconductor device 100 according to the fourth embodiment. Hereinafter, a description will be given focusing on a configuration different from silicon carbide semiconductor device 100 according to the fourth embodiment.

見て As shown in FIG. 15, as viewed from a direction perpendicular to the first main surface 1, all the extending directions of the four grooves may be parallel. Specifically, the long side of the first groove 7 is parallel to each of the long side of the second groove 82, the long side of the third groove 83, and the long side of the fourth groove 84. Similarly, the short side of the first groove 7 is parallel to each of the short side of the second groove 82, the short side of the third groove 83, and the short side of the fourth groove 84.

In the above description, silicon carbide semiconductor device 100 according to the present disclosure has been described by exemplifying a MOSFET having a trench gate, but silicon carbide semiconductor device 100 according to the present disclosure is not limited to this. Silicon carbide semiconductor device 100 according to the present disclosure may be, for example, a planar MOSFET, an IGBT (Insulated Gate Bipolar Transistor), an SBD (Schottky Barrier Diode), a thyristor, a GTO (Gate Turn Off Thyristor), or a PIN diode.

In the above description, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type may be the first conductivity type and the n-type may be the second conductivity type. The concentration of the p-type impurity and the concentration of the n-type impurity in each of the impurity regions can be measured by, for example, SCM (Scanning Capacitance Microscope) or SIMS (Secondary Ion Mass Mass Spectrometry). Furthermore, each of the above embodiments and each of the modifications may be combined with each other as long as there is no technical contradiction.

Next, the function and effect of silicon carbide semiconductor device 100 according to the present disclosure will be described.
Generally, silicon carbide semiconductor chip 30 is covered with resin 8. Moisture that has entered the inside of the resin 8 from the external environment expands at a high temperature to form a space inside. As a result, a crack is generated in the resin 8 by applying a stress to the resin 8. Next, at a low temperature, the space is depressurized by dew condensation inside the space. Therefore, moisture is drawn from the external environment. Next, at high temperatures, the water expands and the space further expands. As a result, cracks formed in the resin 8 elongate. As described above, when silicon carbide semiconductor device 100 is placed in an environment where high and low temperatures are alternately repeated, resin 8 on silicon carbide semiconductor chip 30 may peel off (popcorn phenomenon). In the above, the high temperature is, for example, 150 ° C. The low temperature is, for example, −55 ° C.

れば According to silicon carbide semiconductor device 100 according to the present disclosure, groove 7 is provided in outer peripheral region 50. The resin 8 covers the outer peripheral surface 3 and is provided inside the groove 7. When resin 8 is provided inside groove 7, the contact area between resin 8 and silicon carbide semiconductor chip 30 is larger than when resin 8 is not provided inside groove 7. Therefore, adhesion between resin 8 and silicon carbide semiconductor chip 30 can be improved (anchor effect). As a result, peeling of the resin 8 can be suppressed.

According to silicon carbide semiconductor device 100 according to the present disclosure, the angle formed between side surface 5 and bottom surface 6 may be smaller than 90 °. In this case, the interval between the pair of side surfaces 5 facing each other in a cross-sectional view becomes narrower from the bottom surface 6 toward the first main surface 1. Therefore, when the resin 8 that has entered the inside of the groove 7 is peeled off, the resin 8 is caught on the side surface 5 and the resin 8 is hardly peeled off. As a result, the anchor effect of the resin 8 can be enhanced.

According to silicon carbide semiconductor device 100 according to the present disclosure, silicon carbide semiconductor chip 30 may have a rectangular shape when viewed from a direction perpendicular to first main surface 1. The grooves may be provided at four corners of the square. When silicon carbide semiconductor chip 30 has a quadrangular shape, stress is higher at four corners of the square than at the sides. Therefore, the resin 8 is more easily peeled off at the corners of the square than at the sides. By providing the groove at the corner where the stress becomes high, the peeling of the resin 8 can be effectively suppressed.

According to silicon carbide semiconductor device 100 according to the present disclosure, groove 7 may surround active region 40 when viewed from a direction perpendicular to first main surface 1. Thereby, the peeling of the resin 8 can be suppressed in the entire circumference.

(Sample preparation)
Using the following samples, an experiment for confirming the effect of suppressing resin separation was performed. The vertical dimension x the horizontal dimension of the chip size and the dimensions of the mounting surface of the mounting copper frame in the sample are shown. The first sample has a chip size of 3 mm × 3 mm and a dimension of a mounting surface of a mounting copper frame of 14 mm × 9.5 mm. The second sample has a chip size of 3 mm × 3 mm and a dimension of a mounting surface of a mounting copper frame of 17 mm × 10 mm. The third sample has a chip size of 6 mm × 6 mm and a mounting surface dimension of the mounting copper frame of 14 mm × 9.5 mm. The fourth sample has a chip size of 6 mm × 6 mm, and the dimensions of the mounting surface of the mounting copper frame are 17 mm × 10 mm. The thickness of the chip is from 150 μm to 200 μm. In these samples, two levels were prepared, one in which the groove of the first embodiment (the structure shown in FIG. 4) was provided and one in which the groove for preventing peeling was not provided.

The relationship between the chip size and the dimensions of the mounting surface of the mounting copper frame is not limited to the above example. That is, if the chip size is smaller than the size of the mounting surface of the mounting copper frame other than the sample, the present invention is applicable. For example, if the chip size is 3 mm × 3 mm, the dimension of the mounting surface of the mounting copper frame may be 20 mm × 14 mm. When the chip size is 5 mm × 6 mm, the dimensions of the mounting surface of the mounting copper frame may be 14 mm × 9.5 mm, 17 mm × 10 mm, or 20 mm × 14 mm. When the chip size is 6 mm × 6 mm, the dimension of the mounting surface of the mounting copper frame may be 20 mm × 14 mm. When the chip size is 10 mm × 12 mm, the dimension of the mounting surface of the mounting copper frame may be 20 mm × 14 mm. When the chip size is 12 mm × 12 mm, the dimension of the mounting surface of the mounting copper frame may be 20 mm × 14 mm. Further, as the grooves for suppressing peeling, the grooves of the first to seventh modifications of the first embodiment or the grooves of the second to fifth embodiments can be provided.

(experimental method)
By observing the state before and after the cycle test in an environment where high and low temperatures are alternately repeated, using an ultrasonic microscope using an ultrasonic probe, it is possible to confirm the presence or absence of resin peeling. It is possible. By observing the state of adhesion between the resin and the upper surface of the chip and between the resin and the frame surface, it is possible to determine whether or not peeling has occurred. First, the temperature cycle between the high temperature (150 ° C.) and the low temperature side (−55 ° C.) is repeated 1000 times, more preferably 5000 times. Thereafter, the presence or absence of peeling is determined based on the reflection and transmission analysis of the ultrasonic wave. The occurrence of peeling with a lateral dimension of about 100 μm is used as a criterion for quality judgment.

微小 Fine peeling that cannot be observed with an ultrasonic microscope can be detected by the following method. First, a high-temperature and high-humidity test (for example, a temperature of 85 ° C. and a humidity of 85%) is performed during or after the cycle test. If the resin has a peeled or cracked portion, moisture will enter the resin and the chip will malfunction. By detecting a malfunction of the chip, the presence or absence of resin peeling or cracking is indirectly determined.

(Experimental result)
In the sample not subjected to the peeling suppression measure, peeling occurred in a temperature cycle of less than 1000 times, and operation failure occurred in a high temperature and high humidity test after the cycle test. In particular, it has been confirmed that peeling occurs at a chip corner at a temperature cycle of less than 500 times. On the other hand, in the sample in which the groove structure was formed, there was no peeling at the corners and sides of the chip even after 1000 times or more, and good operation was confirmed in a high-temperature and high-humidity test after the cycle test. The same effect was confirmed in a stricter high-temperature side (175 ° C.) and a low-temperature side (−55 ° C.) in a cycle test of 5000 times, and in a high-temperature and high-humidity test after the cycle test.

(4) Regarding the sample for which no measures were taken to prevent peeling, when the chip size was large and the dimensions of the mounting surface were small, the tendency for peeling to occur quickly in the cycle test was confirmed. Also, it was confirmed that the larger the ratio between the chip size and the mounting surface, the faster the occurrence of peeling. (In this case, the ratio of the chip area / the area of the mounting surface is 3% at the minimum and 3% at the maximum. 51%). Regarding the sample with the peeling suppression measure, the resin peeled off after the cycle test of 5000 times and after the high-temperature and high-humidity test after the cycle test regardless of the above-mentioned chip size and dimensions of the mounting surface. It was confirmed that no problem occurred.

The embodiments and examples disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 {first principal surface, 2} second principal surface, 3} outer peripheral surface, 4 {shoulder portion, 5} side surface, 6} bottom surface, 7} first groove (groove), 8} resin, 9} gate trench, 10} silicon carbide substrate, 11} drift region, 12 body region, 13 source region, 14 contact region, 15 silicon carbide single crystal substrate, 16 guard ring, 17 first side surface, 18 second side surface, 19 opening, 20 silicon carbide epitaxial layer, 21 contact electrode, 22 Gate electrode, 23 interlayer insulating film, 24 gate insulating film, 25 drain electrode, 26 insulating film, 27 stress buffer layer, 28 source electrode, 29 source wiring, 30 silicon carbide semiconductor chip, 31 third main surface, 32 fourth main Surface, 40 ° inner region (active region), 41 ° corner region, 42 ° side region, 50 ° outer peripheral region, 51 ° first outer peripheral region portion, 5 Second outer peripheral area portion, 71 {first area, 72} second area, 73 # solder layer, 74 # metal frame, 82 # second groove, 83 # third groove, 84 # fourth groove, 85 # fifth groove, 86 # sixth groove, 87 7th groove, 88th eighth groove, 90th silicon carbide semiconductor element, 91th side wall surface, 92th bottom, 93th through hole, 100th silicon carbide semiconductor device, 101 first direction, 102 second direction, 111,113 width, 112th thickness .

Claims

A silicon carbide semiconductor chip,
The silicon carbide semiconductor chip includes a silicon carbide substrate, and an electrode on the silicon carbide substrate,
The silicon carbide substrate,
A first main surface in contact with the electrode;
A second main surface opposite to the first main surface;
An outer peripheral surface connected to each of the first main surface and the second main surface;
An outer peripheral region including the outer peripheral surface,
An inner region surrounded by the outer peripheral region and provided with a silicon carbide semiconductor element;
A first groove located on the first main surface of the outer peripheral region;
A silicon carbide semiconductor device, comprising: a resin that covers each of the first main surface and the outer peripheral surface and is provided inside the first groove.
2. The silicon carbide semiconductor device according to claim 1, wherein the first groove includes a planar side surface connected to the first main surface and a planar bottom surface connected to the side surface. 3.
3. The silicon carbide semiconductor device according to claim 2, wherein an angle formed between the side surface and the bottom surface is 90 °.
3. The silicon carbide semiconductor device according to claim 2, wherein an angle formed between the side surface and the bottom surface is larger than 90 °.
3. The silicon carbide semiconductor device according to claim 2, wherein an angle formed between the side surface and the bottom surface is smaller than 90 °.
The silicon carbide semiconductor device according to any one of claims 2 to 5, wherein the resin is in contact with each of the side surface and the bottom surface.
The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the depth of the first groove is 0.1 μm or more and 30 μm or less.
The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the width of the opening of the first groove is 0.1 μm or more and 30 μm or less.
7. The silicon carbide according to claim 1, wherein a value obtained by dividing a width of the opening of the first groove by a depth of the first groove is 0.25 or more and 2 or less. Semiconductor device.
10. The silicon carbide substrate according to claim 1, further comprising a second groove, a third groove, and a fourth groove located on the first main surface of the outer peripheral region and separated from each other. 2. The silicon carbide semiconductor device according to item 1.
The shape of the silicon carbide substrate is a quadrangle in plan view,
The silicon carbide semiconductor device according to claim 10, wherein said first groove, said second groove, said third groove, and said fourth groove are respectively located at four corners of said square.
The silicon carbide semiconductor device according to any one of claims 1 to 9, wherein the first groove surrounds the internal region in plan view.