WO2020012120A1 - Process for manufacturing electronic-component packages and electronic-component package obtained by means of this process - Google Patents

Process for manufacturing electronic-component packages and electronic-component package obtained by means of this process Download PDF

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Publication number
WO2020012120A1
WO2020012120A1 PCT/FR2019/051729 FR2019051729W WO2020012120A1 WO 2020012120 A1 WO2020012120 A1 WO 2020012120A1 FR 2019051729 W FR2019051729 W FR 2019051729W WO 2020012120 A1 WO2020012120 A1 WO 2020012120A1
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WO
WIPO (PCT)
Prior art keywords
connection
electronic component
encapsulation
connection pads
face
Prior art date
Application number
PCT/FR2019/051729
Other languages
French (fr)
Inventor
Laurent Berdalle
Christophe MATHIEU M.
Original Assignee
Linxens Holding
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Linxens Holding filed Critical Linxens Holding
Priority to CN201980046879.4A priority Critical patent/CN112470261A/en
Priority to SG11202100314PA priority patent/SG11202100314PA/en
Priority to EP19749397.6A priority patent/EP3821458A1/en
Publication of WO2020012120A1 publication Critical patent/WO2020012120A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/48177—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Definitions

  • the invention relates to the field of manufacturing processes for electronic component packages, such as for example integrated circuit packages of the "QFN" type (for "Quad Flat No-Lead” in English).
  • document EP2846355A1 describes a process in which
  • a dielectric material in the form of a strip; this strip extending in a longitudinal direction and having two main faces, one of which is at least partially covered with a sheet of electrically conductive material,
  • connection units are produced in the sheet of electrically conductive material, these connection units being distributed along the longitudinal direction with a determined pitch, each connection unit comprising a connection face with connection pads, these connection pads being intended for the electrical connection of the integrated circuit box, for example on a printed circuit,
  • an electronic component is placed on the strip at each connection unit and it is connected to at least some of the connection pads of the connection unit at which it is placed, and
  • the electronic component is wrapped in an encapsulation material, at each connection unit.
  • the electronic component is placed in a cavity in a housing molded by injection on the strip and in a mold, at each connection unit. Then, the electronic component is coated in a resin deposited in this cavity.
  • the invention provides another method of manufacturing integrated circuit packages.
  • the electronic component is also placed in a cavity before its encapsulation (or coating; in this text the terms coating and encapsulation are used as synonyms, just as coated or encapsulated), but on the one hand this cavity is produced differently, and on the other hand the encapsulation is carried out by dispensation, that is to say by depositing the encapsulation material in the cavity, without using a mold.
  • the cavity is blind. Its bottom is formed by a layer of flexible and removable material which is removed after encapsulation of the electronic component.
  • the electronic component can be encapsulated by coating, in a plastic, a resin, etc. after having been deposited on a support, without it being necessary, beforehand, to form a housing by injecting a plastic material into a mold, or to use an independent mold to inject the coating material.
  • the method according to the invention makes it possible to use at least one material (dielectric material, electrically conductive material, etc.), or some of the materials, moreover necessary for the production of the connection tracks, to form at least one part of a blind cavity which will then be used to receive the encapsulation material.
  • the method according to the invention makes it possible in particular to produce integrated circuit packages of the "QFN" type in which an electronic component (in this case an electronic chip) is encapsulated to form miniaturized components for surface mounting (“ SMCs ”). It can also be used to make SIM cards (“Subscriber Identification Module”, or “Subscriber Identity Module” in English) with flush contacts for electrical connection with the device in which this SIM card is inserted.
  • SIM cards Subscriber Identification Module
  • SIM Identity Module Subscriber Identity Module
  • the method according to the invention optionally includes one or other of the characteristics mentioned in claims 2 to 7, considered in isolation or in combination with one or more others.
  • the invention is an electronic component box intended for surface mounting on an electrical circuit, this box being manufactured according to a process such as that mentioned above.
  • the characteristics of this box correspond to those mentioned in claim 8.
  • the electronic component housing according to the invention optionally includes one or the other of the characteristics mentioned in claims 9 to 11, considered in isolation or in combination with one or more others.
  • Figure 2 shows a top view of an example of an electrical circuit strip at different stages of a method according to the invention
  • Figure 2A shows an enlarged part of Figure 2;
  • FIG. 3 shows an electrical circuit connection unit for the implementation of a method according to the invention, before installation of an electronic component at this connection unit;
  • FIG. 4 shows the electrical circuit connection unit of Figure 3, after installation and overmolding of an electronic component at this connection unit;
  • FIG. 5 shows, schematically seen from below an example of an integrated circuit package obtained according to a method according to the invention
  • FIG. 6 shows, schematically in perspective the integrated circuit package of Figure 5.
  • FIG. 1 A first example of implementation of the method according to the invention is shown in Figure 1. It is described below in connection with the manufacture of an integrated circuit box of the "QFN" type. This implementation example includes the following steps:
  • the strip 10 extends in a longitudinal direction L in which it is unwound; this strip 10 has two main faces 10A, 10B; the strip 10 has a thickness of, for example, 75 ⁇ m or 110 ⁇ m;
  • the strip 10 is coated with dielectric material, at least partially, on one (in this case the main face 10A) of its main faces 10A, 10B with an adhesive 20 which can be reactivated when hot (of epoxy resin type) modified) (Fig. lb);
  • - Perforations 30 are made in the strip 10 of dielectric material coated with the adhesive 20 to form drive notches on the edges of the strip 10 of dielectric material as well as cavities; these perforations 30 are produced, for example by punching; the cavities are distributed with a pitch defined by the desired distance between the integrated circuit boxes (Fig. le);
  • a sheet 40 of electrically conductive metallic material is laminated on the face
  • this sheet 40 of electrically conductive material is for example a sheet of copper - or one of its alloys - 70mpi thick;
  • the sheet 40 of electrically conductive material is etched for example by photo lithography to define and produce patterns 50 (alternatively the patterns 50 are completely, or only partially, cut out mechanically before lamination of the sheet 40 of electrically conductive material, on the face of the strip 10 of dielectric material comprising the adhesive 20); these patterns 50, and the connection units which they comprise are distributed along the longitudinal direction L with a fixed pitch; the patterns 50 include in particular connection units connected by conductive tracks (Fig. le and Fig.
  • connection units a blind or non-opening cavity 60 on one face of the strip 10 of the dielectric material; one and / or the other of the two faces of the sheet 40 of electrically conductive material are optionally metallized; this metallization (for example Ni / Au or Ag) is, for example, suitable for "QFN" type component transfer methods on an electrical circuit and / or for methods of connection to connection pads to electronic component 90 (see below) in relation to Fig. li);
  • connection pads 45 make it possible, on the one hand, to connect the “QFN” type component to an electrical circuit and, on the other hand, to connect an electronic component 90 (FIG. 1f and FIG. li );
  • this layer 80 of removable material is for example made up of a strip with a non-permanent adhesive or has a face coated with a non-permanent adhesive; it may for example be a polypropylene film coated with a layer of rubber-based adhesive, or a polyimide film coated with a layer of silicone-based adhesive; optionally the adhesive layer is protected by a non-stick protective film; it can be the reference 1285 from the company SCAPA, or the reference SMX-P30S from the company SEEMEX Inc.
  • this layer 80 of removable material constitutes a bottom for the openings 70 cut in the previous step; a blind or non-opening cavity 60 is thus formed; the cavity 60 is therefore closed by a bottom consisting of the removable layer 80 and on its periphery by the edge cut from the strip
  • the removable layer 80 is in contact with the connection pads 45 and thus protects one of their faces during the subsequent encapsulation step;
  • an electronic component 90 (for example an electronic chip) is deposited in the cavity 60, for example on an adhesive face of the removable layer 80 deposited in the previous step (Fig. 1h);
  • the electronic component 90 is connected for example by wire connection (wire bonding) or flip chip to the connection pads 45 (for the example illustrated in this document, it is a wire connection between the connection pads 45 and the connection pads of the electronic component 90 - see Fig. li);
  • connection pads 45 are isolated from each other by punching in order to allow an individual electrical test of the components of the “QFN” type (FIG. 1j); in FIG. 1j and in FIGS. 3 and 4, the dotted lines schematically represent the short circuit 48 present in the electrically conductive sheet 40, before this step making it possible to electrically isolate the connection pads 45 from each other; thus after this step, although the electronic component housings 110 are not yet individualized (see below),
  • connection pads 45 it is possible to mount an electronic component 90, and to connect it to the connection pads 45, then to test it; this step is optional, especially if the electronic components 90 are only tested after individualization of their respective housing 110 (see FIGS. 5 and 6); - The electronic component 90, the connection pads 45 and a portion of the strip
  • thermosetting resin for example by dispensing (for example according to the technology called “dam & f ⁇ ll” in English) of thermosetting resin, with an encapsulation material 100, from place to place, to form the components of type "QFN" at not desired (Fig. lk); one can use a product having the reference “Delo DF570-580" as encapsulation material; in this case this product corresponds to what is called in English "Black thermal resins for encapsulation";
  • FIG. 2 schematically shows a strip 10 of dielectric material with patterns 50 etched in the sheet 40 of electrically conductive material.
  • the patterns 50 include conductive tracks 52 and connection units 54.
  • the conductive tracks 52 are used in particular to bring electric current during an electrolytic deposition implemented for the metallization of the connection pads 45.
  • units 54 are shown after cutting the connection pads 45 (see also Figure 3).
  • areas of cutouts 56 also produced by punching are shown to isolate the connection pads 45 from one another (see also FIG. 4).
  • connection pads 45 have not already been isolated from one another during a step such as that shown in Figure lj), they can be concomitantly in the final step of individualization of the housings 110 of electronic component (Fig. lm).
  • FIG. 6 shows in particular a housing 110 of electronic component obtained by the above method.
  • This electronic component housing 110 constitutes an element intended for surface mounting on an electrical circuit (a printed circuit for example). It has a connection face 112 and at least one electronic component 90 coated (encapsulated) in an encapsulation material 100 is connected to connection pads 45 flush, just like one face of the electronic component 90, on the connection face 112 , at the level of the encapsulation material 100.
  • This housing 110 comprises two rows of connection tracks 45. They are located on the connection face 112, each respectively at a side 114 and an edge of the housing 110, the two sides 114 of the housing 110 each comprising a row of connection tracks 45 being opposite one another. These connection tracks 45 are therefore either directly connected to the electronic component 90 (chip transfer technology called “flip-chip”), or connected to the electronic component 90 via connection wires (technology called “wire-bonding" "flip-chip transfer technology called "flip-chip"
  • the strip 10 extends in a longitudinal direction L in which it is unwound; this strip 10 has two main faces 10A, 10B; the strip 10 has a thickness of, for example, 75 ⁇ m or 110 ⁇ m;
  • the strip 10 is coated with dielectric material, at least partially, on one (in this case the main face 10A) of its main faces 10A, 10B with an adhesive 20 (Fig. 7b) suitable for sticking temporarily the dielectric material 10 with an electrically conductive material 40 (Fig. 7d); the complex thus produced with the strip 10 covered with the adhesive forms a layer of flexible and removable material 80 ’;
  • Perforations 30 are made in the strip 10 of dielectric material coated with the adhesive 20; in particular cavities are made, for example by punching, to form drive notches on the edges of the strip 10 of dielectric material (Fig. 7c); - A sheet 40 of electrically conductive metal material is laminated on the face
  • this sheet 40 of electrically conductive material is for example a sheet of copper - or one of its alloys - 105mhi of minimum thickness;
  • the sheet 40 of electrically conductive material is etched for example by photolithography to define and produce patterns (alternatively the patterns are completely or partially only cut mechanically before lamination of the sheet 40 of electrically conductive material on the strip 10 of material dielectric) (Figs.
  • connection units 7e and 7f these patterns, and the connection units which they comprise are distributed along the longitudinal direction L with a fixed pitch; the patterns include in particular connection units connected by conductive tracks; at this stage, the connection units therefore comprise a blind or non-opening cavity 60 on one face of the dielectric material; one and / or the other of the two faces of the sheet 40 of electrically conductive material are optionally metallized; this metallization (for example Ni / Au or Ag) is for example suitable for methods of transferring a component of the “QFN” type onto an electrical circuit and / or of connection to connection pads 45 to the electronic component 90 (see also below in relation to Fig. 7g);
  • the electronic component 90 is connected for example by wire connection (wire-bonding) or flip chip to the connection pads 45 (for the example illustrated in this document, it is a wire connection between the connection pads 45 and the connection pads of the electronic component 90 - see Fig. 7g);
  • the electronic component 90, the connection pads 45 and a portion of the dielectric material are encapsulated for example in a resin 100 (to form what is called a glob-top), filling the cavities 60 by dispensing from place to place, to form the “QFN” type components at the desired pitch (Fig. 7h);
  • the resin 100 is flattened or flattened (Fig. 7h ’);
  • the strip 10 of dielectric material is removed (peeled) (Fig. 7i) (with the adhesive 20); the strip 10 of dielectric material therefore played the role of a layer of flexible and removable material, the electronic components 90 or modules of the “QFN” type are then electrically tested and individualized for a transfer step (“pick and place” in English) later on an electrical circuit; this stage can be concomitant or consecutive of a step of short-circuiting the connection pads 45; this step can be concomitant or consecutive with a step of cutting the edges of the cavity 60 made of the conductive material (Fig. 7j).
  • the electronic components 90 obtained by this second embodiment of the method according to the invention are similar or similar to those which are, or could have been, obtained using the first example and illustrated by Figures 2 to 6.

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Abstract

The invention relates to a process for manufacturing integrated-circuit packages (110), wherein a cavity is made in a strip of dielectric material covered with a leaf of electrically conductive material. An electronic component (90) is placed in the cavity and it is encapsulated by filling the cavity at least partially with an encapsulation material (100). The bottom of the blind cavity being formed of a layer of flexible and removable material which is removed after encapsulation. The invention also relates to integrated-circuit packages (110) manufactured according to this process. These integrated-circuit packages (110) are for example QFN packages.

Description

Procédé de fabrication de boîtiers de composant électronique et boîtier de composant électronique obtenu par ce procédé  Method for manufacturing electronic component boxes and electronic component box obtained by this method
[ooi] L’invention concerne le domaine des procédés de fabrication de boîtiers de composant électronique, tels que par exemple des boîtiers de circuit intégré de type «QFN » (pour « Quad Flat No-Lead » en anglais). [ooi] The invention relates to the field of manufacturing processes for electronic component packages, such as for example integrated circuit packages of the "QFN" type (for "Quad Flat No-Lead" in English).
[002] On connaît déjà des procédés de fabrication de boîtiers de composant électronique dans lesquels on réalise en continu des portions de circuits électriques auxquels on connecte un composant électronique (puce électronique, diode électroluminescente, etc.) qui est ensuite encapsulé, par surmoulage par injection ou par enrobage dans une résine. Des portions de circuit électriques munis d’un composant électronique sont alors individualisés afin d’être utilisées par exemple comme composants pour montage en surface (« Surface Mount Components » ou « SMCs » en anglais).  Processes are already known for manufacturing electronic component housings in which portions of electrical circuits are continuously produced to which an electronic component is connected (electronic chip, light-emitting diode, etc.) which is then encapsulated, by overmolding by injection or by coating in a resin. Portions of the electrical circuit provided with an electronic component are then individualized in order to be used for example as components for surface mounting (“Surface Mount Components” or “SMCs” in English).
[003] Par exemple, le document EP2846355A1 décrit un procédé dans lequel  For example, document EP2846355A1 describes a process in which
- on fournit un matériau diélectrique sous forme d’une bande ; cette bande s’étendant dans une direction longitudinale et ayant deux faces principales, dont l’une est au moins partiellement recouverte d’un feuillet de matériau électriquement conducteur,  - providing a dielectric material in the form of a strip; this strip extending in a longitudinal direction and having two main faces, one of which is at least partially covered with a sheet of electrically conductive material,
- on réalise une pluralité d’unités de connexion dans le feuillet de matériau électriquement conducteur, ces unités de connexion étant distribuées le long de la direction longitudinale avec un pas déterminé, chaque unité de connexion comprenant une face de connexion avec des plages de connexion, ces plages de connexion étant destinées à la connexion électrique du boîtier de circuit intégré, par exemple sur un circuit imprimé,  a plurality of connection units are produced in the sheet of electrically conductive material, these connection units being distributed along the longitudinal direction with a determined pitch, each connection unit comprising a connection face with connection pads, these connection pads being intended for the electrical connection of the integrated circuit box, for example on a printed circuit,
- on place un composant électronique sur la bande au niveau de chaque unité de connexion et on le connecte à au moins certaines des plages de connexion de l’unité de connexion au niveau de laquelle il est placé, et  - an electronic component is placed on the strip at each connection unit and it is connected to at least some of the connection pads of the connection unit at which it is placed, and
- on enrobe le composant électronique dans un matériau d’encapsulation, au niveau de chaque unité de connexion.  - the electronic component is wrapped in an encapsulation material, at each connection unit.
[004] Dans ce procédé, le composant électronique est placé dans une cavité ménagée dans un boîtier surmoulé par injection sur la bande et dans un moule, au niveau de chaque unité de connexion. Puis, le composant électronique est enrobé dans une résine déposée dans cette cavité.  In this method, the electronic component is placed in a cavity in a housing molded by injection on the strip and in a mold, at each connection unit. Then, the electronic component is coated in a resin deposited in this cavity.
[005] L’invention propose un autre procédé de fabrication de boîtiers de circuit intégré. The invention provides another method of manufacturing integrated circuit packages.
[006] Ce procédé correspond à la revendication 1. [007] Ainsi, le composant électronique est aussi placé dans une cavité avant son encapsulation (ou enrobage ; dans ce texte les termes enrobage et encapsulation sont utilisés comme synonymes, tout comme enrobé ou encapsulé), mais d’une part cette cavité est réalisée différemment, et d’autre part l’encapsulation est réalisée par dispense, c’est-à-dire en déposant le matériau d’encapsulation dans la cavité, sans utiliser de moule. La cavité est borgne. Son fond est formé d’une couche de matériau flexible et amovible qui est retirée après encapsulation du composant électronique. This method corresponds to claim 1. Thus, the electronic component is also placed in a cavity before its encapsulation (or coating; in this text the terms coating and encapsulation are used as synonyms, just as coated or encapsulated), but on the one hand this cavity is produced differently, and on the other hand the encapsulation is carried out by dispensation, that is to say by depositing the encapsulation material in the cavity, without using a mold. The cavity is blind. Its bottom is formed by a layer of flexible and removable material which is removed after encapsulation of the electronic component.
[008] Grâce à l’invention, le composant électronique peut être encapsulé par enrobage, dans une matière plastique, une résine, etc. après avoir été déposé sur un support, sans qu’il soit nécessaire, préalablement, de former un boîtier par injection d’une matière plastique dans un moule, ni d’utiliser un moule indépendant pour injecter la matière d’enrobage. Le procédé selon l’invention permet d’utiliser au moins un matériau (matériau diélectrique, matériau électriquement conducteur, etc.), ou certains des matériaux, par ailleurs nécessaire(s) à la réalisation des pistes de connexion, pour former au moins une partie d’une cavité borgne qui servira ensuite pour recevoir le matériau d’encapsulation.  Thanks to the invention, the electronic component can be encapsulated by coating, in a plastic, a resin, etc. after having been deposited on a support, without it being necessary, beforehand, to form a housing by injecting a plastic material into a mold, or to use an independent mold to inject the coating material. The method according to the invention makes it possible to use at least one material (dielectric material, electrically conductive material, etc.), or some of the materials, moreover necessary for the production of the connection tracks, to form at least one part of a blind cavity which will then be used to receive the encapsulation material.
[009] Le procédé selon l’invention permet notamment de réaliser des boîtiers de circuit intégré de type «QFN » dans lesquels un composant électronique (en l’occurrence une puce électronique) est encapsulé pour former des composants miniaturisés pour montage en surface ( « SMCs »). Il peut également être mis en œuvre pour réaliser des cartes SIM (« Module d’identification de l’Abonné », soit « Subscriber Identity Module » en anglais) avec des contacts affleurants pour une connexion électrique avec le dispositif dans lequel cette carte SIM est insérée.  The method according to the invention makes it possible in particular to produce integrated circuit packages of the "QFN" type in which an electronic component (in this case an electronic chip) is encapsulated to form miniaturized components for surface mounting (" SMCs ”). It can also be used to make SIM cards (“Subscriber Identification Module”, or “Subscriber Identity Module” in English) with flush contacts for electrical connection with the device in which this SIM card is inserted.
[ooio] Le procédé selon l’invention comporte éventuellement, l’une ou l’autre des caractéristiques mentionnées dans les revendications 2 à 7, considérée isolément ou en combinaison d’une ou plusieurs autres.  [Ooio] The method according to the invention optionally includes one or other of the characteristics mentioned in claims 2 to 7, considered in isolation or in combination with one or more others.
[ooi 1] Selon un autre aspect, l’invention est un boîtier de composant électronique destiné à un montage en surface sur un circuit électrique, ce boîtier étant fabriqué selon un procédé tel que celui mentionné précédemment. Les caractéristiques de ce boîtier correspondent à celles mentionnées à la revendication 8.  [ooi 1] According to another aspect, the invention is an electronic component box intended for surface mounting on an electrical circuit, this box being manufactured according to a process such as that mentioned above. The characteristics of this box correspond to those mentioned in claim 8.
[0012] Le boîtier de composant électronique selon l’invention comporte éventuellement, l’une ou l’autre des caractéristiques mentionnées dans les revendications 9 à 11, considérée isolément ou en combinaison d’une ou plusieurs autres. [0013] D’autres caractéristiques et avantages de l’invention apparaîtront à la lecture de la description détaillée qui suit, ainsi que sur les dessins annexés. Sur ces dessins : The electronic component housing according to the invention optionally includes one or the other of the characteristics mentioned in claims 9 to 11, considered in isolation or in combination with one or more others. Other features and advantages of the invention will appear on reading the detailed description which follows, as well as in the accompanying drawings. In these drawings:
- les figures la à lm représentent schématiquement les différentes étapes d’un premier exemple de mise en œuvre du procédé selon l’invention ;  - Figures la to lm schematically represent the different stages of a first example of implementation of the method according to the invention;
- la figure 2 représente vue de dessus un exemple de bande de circuit électrique à différentes étapes d’un procédé selon l’invention ; la figure 2A représente une partie agrandie de la figure 2 ;  - Figure 2 shows a top view of an example of an electrical circuit strip at different stages of a method according to the invention; Figure 2A shows an enlarged part of Figure 2;
- la figure 3 représente une unité de connexion de circuit électrique pour la mise en œuvre d’un procédé selon l’invention, avant mise en place d’un composant électronique au niveau de cette unité de connexion ;  - Figure 3 shows an electrical circuit connection unit for the implementation of a method according to the invention, before installation of an electronic component at this connection unit;
- la figure 4 représente l’unité de connexion de circuit électrique de la figure 3, après mise en place et surmoulage d’un composant électronique au niveau de cette unité de connexion ;  - Figure 4 shows the electrical circuit connection unit of Figure 3, after installation and overmolding of an electronic component at this connection unit;
- la figure 5 représente, schématiquement vu de dessous un exemple de boîtier de circuit intégré obtenu selon un procédé conforme à l’invention ;  - Figure 5 shows, schematically seen from below an example of an integrated circuit package obtained according to a method according to the invention;
- la figure 6 représente, schématiquement en perspective le boîtier de circuit intégré de la figure 5 ; et  - Figure 6 shows, schematically in perspective the integrated circuit package of Figure 5; and
- les figures 7a à 7j représentent schématiquement les différentes étapes d’un deuxième exemple de mise en œuvre du procédé selon l’invention.  - Figures 7a to 7j schematically represent the different stages of a second example of implementation of the method according to the invention.
[0014] Un premier exemple de mise en œuvre du procédé selon l’invention est représenté sur la figure 1. Il est décrit ci-dessous en relation avec la fabrication d’un boîtier de circuit intégré de type « QFN ». Cet exemple de mise en œuvre comporte les étapes suivantes :  A first example of implementation of the method according to the invention is shown in Figure 1. It is described below in connection with the manufacture of an integrated circuit box of the "QFN" type. This implementation example includes the following steps:
[0015] - on fournit une bande 10 de matériau diélectrique (Fig. la) ; par exemple, le matériau diélectrique est du verre-epoxy, flexible et en rouleau (pour une mise en œuvre du procédé de dite de « rouleau à rouleau - soit « reel-to-reel » ou « roll-to-roll » en anglais) ; la bande 10 s’étend dans une direction longitudinale L selon laquelle elle est déroulée ; cette bande 10 a deux faces principales 10A, 10B ; la bande 10 a une épaisseur par exemple de 75 pm ou de 110 pm ;  - providing a strip 10 of dielectric material (Fig. La); for example, the dielectric material is glass-epoxy, flexible and in roll (for an implementation of the process known as of “roll to roll - either“ reel-to-reel ”or“ roll-to-roll ”in English ); the strip 10 extends in a longitudinal direction L in which it is unwound; this strip 10 has two main faces 10A, 10B; the strip 10 has a thickness of, for example, 75 μm or 110 μm;
[0016] - on enduit la bande 10 de matériau diélectrique, au moins partiellement, sur l’une (en l’occurrence la face principale 10A) de ses faces principales 10A, 10B avec un adhésif 20 réactivable à chaud (de type résine epoxy modifiée) (Fig. lb) ; [0017] - des perforations 30 sont réalisées dans la bande 10 de matériau diélectrique enduite de l’adhésif 20 pour former des crans d’entrainement sur les bords de la bande 10 de matériau diélectrique ainsi que des cavités ; ces perforations 30 sont réalisées, par exemple par poinçonnage ; les cavités sont distribuées avec un pas défini par la distance souhaitée entre les boîtiers de circuit intégré (Fig. le) ; - The strip 10 is coated with dielectric material, at least partially, on one (in this case the main face 10A) of its main faces 10A, 10B with an adhesive 20 which can be reactivated when hot (of epoxy resin type) modified) (Fig. lb); - Perforations 30 are made in the strip 10 of dielectric material coated with the adhesive 20 to form drive notches on the edges of the strip 10 of dielectric material as well as cavities; these perforations 30 are produced, for example by punching; the cavities are distributed with a pitch defined by the desired distance between the integrated circuit boxes (Fig. le);
[0018] - un feuillet 40 de matériau électriquement conducteur métallique est laminé sur la face - A sheet 40 of electrically conductive metallic material is laminated on the face
10A de la bande 10 de matériau diélectrique comportant l’adhésif 20 (Fig. ld) ; ce feuillet 40 de matériau électriquement conducteur est par exemple un feuillet de cuivre - ou d’un de ses alliages - de 70mpi d’épaisseur ; 10A of the strip 10 of dielectric material comprising the adhesive 20 (FIG. Ld); this sheet 40 of electrically conductive material is for example a sheet of copper - or one of its alloys - 70mpi thick;
[0019] - le feuillet 40 de matériau électriquement conducteur est gravé par exemple par photo lithogravure pour définir et réaliser des motifs 50 (alternativement les motifs 50 sont complètement, ou en partie seulement, découpés mécaniquement avant lamination du feuillet 40 de matériau électriquement conducteur, sur la face de la bande 10 de matériau diélectrique comportant l’adhésif 20) ; ces motifs 50, et les unités de connexion qu’ils comprennent sont distribuées le long de la direction longitudinale L avec un pas fixe ; les motifs 50 comprennent notamment des unités de connexion reliées par des pistes conductrices (Fig. le et Fig. 2) ; à cette étape, il demeure au niveau d’au moins certaines unités de connexion, une cavité borgne ou non-débouchante 60 sur une face de la bande 10 du matériau diélectrique ; l’une et/ou l’autre des deux faces du feuillet 40 de matériau électriquement conducteur sont éventuellement métallisées ; cette métallisation (par exemple Ni/ Au ou Ag) est par exemple adaptée aux procédés de report de composant de type « QFN » sur un circuit électrique et/ou aux procédés de connexion à des plages de connexion au composant électronique 90 (voir plus loin en relation avec la Fig. li) ;  The sheet 40 of electrically conductive material is etched for example by photo lithography to define and produce patterns 50 (alternatively the patterns 50 are completely, or only partially, cut out mechanically before lamination of the sheet 40 of electrically conductive material, on the face of the strip 10 of dielectric material comprising the adhesive 20); these patterns 50, and the connection units which they comprise are distributed along the longitudinal direction L with a fixed pitch; the patterns 50 include in particular connection units connected by conductive tracks (Fig. le and Fig. 2); at this stage, it remains at at least some connection units, a blind or non-opening cavity 60 on one face of the strip 10 of the dielectric material; one and / or the other of the two faces of the sheet 40 of electrically conductive material are optionally metallized; this metallization (for example Ni / Au or Ag) is, for example, suitable for "QFN" type component transfer methods on an electrical circuit and / or for methods of connection to connection pads to electronic component 90 (see below) in relation to Fig. li);
[0020] - d’autres éléments de motif 55 (par exemple en forme de peignes, voir Fig. lf et Fig. - other pattern elements 55 (for example in the form of combs, see Fig. Lf and Fig.
2) sont ensuite découpés par poinçonnage mécanique ou par gravure chimique, dans le feuillet 40 de matériau électriquement conducteur, au niveau de la cavité 60, afin de former les plages de connexion 45 ; une ouverture traversante 70 est aussi formée au centre de chaque unité de connexion entre les plages de connexion 45 ; les plages de connexion 45 permettent de réaliser, d’une part, la connexion du composant de type « QFN » sur un circuit électrique et, d’autre part, la connexion d’un composant électronique 90 (Fig. lf et Fig. li) ; 2) are then cut by mechanical punching or by chemical etching, in the sheet 40 of electrically conductive material, at the level of the cavity 60, in order to form the connection pads 45; a through opening 70 is also formed in the center of each connection unit between the connection pads 45; the connection pads 45 make it possible, on the one hand, to connect the “QFN” type component to an electrical circuit and, on the other hand, to connect an electronic component 90 (FIG. 1f and FIG. li );
[0021] - une couche 80 de matériau amovible et flexible, destinée à obturer la cavité 60 du côté du feuillet 40 de matériau électriquement conducteur, est déposée temporairement sur ce feuillet 40 de matériau électriquement conducteur (Fig. lg) ; cette couche 80 de matériau amovible est par exemple constituée d’une bande avec un adhésif non-permanent ou comporte une face revêtue d’un adhésif non permanent ; il peut s’agir par exemple d’un film de polypropylène revêtu d’une couche d’adhésif à base de caoutchouc, ou d’un film de polyimide revêtu d’une couche d’adhésif à base de silicone ; éventuellement la couche d’adhésif est protégée par un film anti-adhésif de protection; il peut s’agir de la référence 1285 de la société SCAPA, ou la référence SMX-P30S de la société SEEMEX Inc. (une société basée à Séoul en Corée du Sud) ou encore la référence PS1030-06A de la marque INNOX (commercialisée par la société Shinha Inc. basée à Gyungi Do en Corée du Sud); cette couche 80 de matériau amovible constitue un fond pour les ouvertures 70 découpées à l’étape précédente ; une cavité 60 borgne ou non-débouchante est ainsi formée ; la cavité 60 est donc fermée par un fond constitué de la couche 80 amovible et sur sa périphérie par la tranche découpée dans la bande- A layer 80 of removable and flexible material, intended to close the cavity 60 on the side of the sheet 40 of electrically conductive material, is temporarily deposited on this sheet 40 of electrically conductive material (Fig. lg); this layer 80 of removable material is for example made up of a strip with a non-permanent adhesive or has a face coated with a non-permanent adhesive; it may for example be a polypropylene film coated with a layer of rubber-based adhesive, or a polyimide film coated with a layer of silicone-based adhesive; optionally the adhesive layer is protected by a non-stick protective film; it can be the reference 1285 from the company SCAPA, or the reference SMX-P30S from the company SEEMEX Inc. (a company based in Seoul in South Korea) or the reference PS1030-06A from the brand INNOX (marketed by the company Shinha Inc. based in Gyungi Do in South Korea); this layer 80 of removable material constitutes a bottom for the openings 70 cut in the previous step; a blind or non-opening cavity 60 is thus formed; the cavity 60 is therefore closed by a bottom consisting of the removable layer 80 and on its periphery by the edge cut from the strip
10 du matériau diélectrique et dans le feuillet 40 de matériau électriquement conducteur ; la couche 80 amovible est au contact des plages de connexion 45 et protège ainsi une de leur face pendant l’étape d’encapsulation ultérieure ; 10 of the dielectric material and in the sheet 40 of electrically conductive material; the removable layer 80 is in contact with the connection pads 45 and thus protects one of their faces during the subsequent encapsulation step;
[0022] - un composant électronique 90 (par exemple une puce électronique) est déposé dans la cavité 60, par exemple sur une face adhésive de la couche 80 amovible déposée à l’étape précédente (Fig. lh);  - an electronic component 90 (for example an electronic chip) is deposited in the cavity 60, for example on an adhesive face of the removable layer 80 deposited in the previous step (Fig. 1h);
[0023] - le composant électronique 90 est connecté par exemple par connexion par fil (wire- bonding) ou flip chip aux plages de connexion 45 (pour l’exemple illustré dans ce document, il s’agit d’une connexion par fil entre les plages de connexion 45 et les plots de connexion du composant électronique 90 - voir Fig. li) ;  - the electronic component 90 is connected for example by wire connection (wire bonding) or flip chip to the connection pads 45 (for the example illustrated in this document, it is a wire connection between the connection pads 45 and the connection pads of the electronic component 90 - see Fig. li);
[0024] - les plages de connexion 45 sont isolées les unes des autres par poinçonnage afin de permettre un test électrique individuel des composants de type « QFN » (Fig. lj) ; sur la figure lj et sur les figures 3 et 4, les traits pointillés représentent schématiquement le court-circuit 48 présent dans le feuillet 40 électriquement conducteur, avant cette étape permettant d’isoler électriquement les plages de connexion 45 les unes des autres ; ainsi après cette étape, bien que les boîtiers 110 de composant électronique ne soient pas encore individualisés (voir plus loin), - The connection pads 45 are isolated from each other by punching in order to allow an individual electrical test of the components of the “QFN” type (FIG. 1j); in FIG. 1j and in FIGS. 3 and 4, the dotted lines schematically represent the short circuit 48 present in the electrically conductive sheet 40, before this step making it possible to electrically isolate the connection pads 45 from each other; thus after this step, although the electronic component housings 110 are not yet individualized (see below),
11 est possible de monter un composant électronique 90, et de le connecter aux plages de connexion 45, puis de le tester ; cette étape est facultative, notamment si les composants électroniques 90 ne sont testés qu’ après individualisation de leur boîtier 110 respectif (voir Figs. 5 et 6); [0025] - le composant électronique 90, les plages de connexion 45 et une portion de la bandeIt is possible to mount an electronic component 90, and to connect it to the connection pads 45, then to test it; this step is optional, especially if the electronic components 90 are only tested after individualization of their respective housing 110 (see FIGS. 5 and 6); - The electronic component 90, the connection pads 45 and a portion of the strip
10 de matériau diélectrique sont encapsulés par exemple par dispense (par exemple selon la technologie appelée « dam&fïll » en anglais) de résine thermodurcissable, avec un matériau d’encapsulation 100, de place en place, pour former les composants de type « QFN » au pas souhaité (Fig. lk); on peut utiliser un produit ayant la référence « Delo DF570-580 » comme matériau d’encapsulation ; dans ce cas ce produit correspond à ce que l’on appelle en anglais « Black thermal resins for encapsulation » ; 10 of dielectric material are encapsulated for example by dispensing (for example according to the technology called "dam & fïll" in English) of thermosetting resin, with an encapsulation material 100, from place to place, to form the components of type "QFN" at not desired (Fig. lk); one can use a product having the reference "Delo DF570-580" as encapsulation material; in this case this product corresponds to what is called in English "Black thermal resins for encapsulation";
[0026] - la couche 80 amovible destinée à obturer la cavité du côté du feuillet 40 électriquement conducteur, est retirée (pelée) (Fig. 11) ;  - The removable layer 80 intended to close the cavity on the side of the electrically conductive sheet 40, is removed (peeled) (Fig. 11);
[0027] - les boîtiers 110 ou modules de type « QFN » sont ensuite testés électriquement et individualisés par découpe (Fig. lm)., avant une étape de report (« pick and place » en anglais) ultérieure sur un circuit électrique  - the boxes 110 or “QFN” type modules are then electrically tested and individualized by cutting (Fig. Lm)., Before a subsequent “pick and place” step on an electrical circuit
[0028] On notera que les étapes des Figures la) à lg), par exemple, qui concernent la fabrication d’un support (structure correspondant à la bande 10 de matériau diélectrique, de l’adhésif 20 et du feuillet 40 de matériau électriquement conducteur) peuvent être réalisées chez un industriel, tandis que les étapes suivantes, qui concernent la mise en place et la connexion d’un composant électronique 90 sur ce support, peuvent être réalisées chez un autre industriel.  Note that the steps of Figures la) to lg), for example, which relate to the manufacture of a support (structure corresponding to the strip 10 of dielectric material, the adhesive 20 and the sheet 40 of electrically material conductor) can be carried out at an industrial, while the following steps, which relate to the establishment and connection of an electronic component 90 on this support, can be carried out at another industrial.
[0029] La figure 2 représente schématiquement une bande 10 de matériau diélectrique avec des motifs 50 gravés dans le feuillet 40 de matériau électriquement conducteur. A titre d’illustration, les résultats respectifs de différentes étapes du procédé mentionné ci-dessus sont représentés sur une même figure (Fig. 2), alors qu’en réalité ces étapes sont mises en œuvre les unes après les autres. Les motifs 50 comportent des pistes conductrices 52 et des unités de connexion 54. Les pistes conductrices 52 servent notamment à amener du courant électrique lors d’un dépôt électrolytique mis en œuvre pour la métallisation des plages de connexion 45. Sur cette figure, des unités de connexion 54 sont représentées après découpe des plages de connexion 45 (voir également la figure 3). Sur l’une des unités de connexion 54 (voir zone agrandie 2A), sont aussi représentées des zones des découpes 56 réalisées par poinçonnage pour isoler les plages de connexion 45 les unes des autres (voir également la figure 4). Par ailleurs, des traits pointillés 58 délimitent la zone qui sera ensuite découpée après encapsulation du composant électronique 90 et de ses connexions (voir également les figures 5 et 6). On notera que si les plages de connexion 45 n’ont pas été déjà isolées les unes des autres lors d’une étape telle que celle représentée sur la figure lj), elles peuvent l’être de manière concomitante à l’étape finale d’individualisation des boîtiers 110 de composant électronique (Fig. lm). Figure 2 schematically shows a strip 10 of dielectric material with patterns 50 etched in the sheet 40 of electrically conductive material. By way of illustration, the respective results of different stages of the method mentioned above are shown in the same figure (Fig. 2), when in reality these stages are implemented one after the other. The patterns 50 include conductive tracks 52 and connection units 54. The conductive tracks 52 are used in particular to bring electric current during an electrolytic deposition implemented for the metallization of the connection pads 45. In this figure, units 54 are shown after cutting the connection pads 45 (see also Figure 3). On one of the connection units 54 (see enlarged area 2A), areas of cutouts 56 also produced by punching are shown to isolate the connection pads 45 from one another (see also FIG. 4). Furthermore, dotted lines 58 delimit the area which will then be cut out after encapsulation of the electronic component 90 and its connections (see also Figures 5 and 6). It will be noted that if the connection pads 45 have not already been isolated from one another during a step such as that shown in Figure lj), they can be concomitantly in the final step of individualization of the housings 110 of electronic component (Fig. lm).
[0030] La figure 6 montre en particulier un boîtier 110 de composant électronique obtenu par le procédé ci-dessus. Ce boîtier 110 de composant électronique constitue un élément destiné à un montage en surface sur un circuit électrique (un circuit imprimé par exemple). Il comporte une face de connexion 112 et au moins un composant électronique 90 enrobé (encapsulé) dans un matériau d’encapsulation 100 est connecté à des plages de connexion 45 affleurant, tout comme une face du composant électronique 90, sur la face de connexion 112, au niveau du matériau d’encapsulation 100. Ce boîtier 110 comporte deux rangées de pistes de connexion 45. Elles sont situées sur la face de connexion 112, chacune respectivement au niveau d’un côté 114 et d’une arête du boîtier 110, les deux côtés 114 du boîtier 110 comportant chacun une rangée de pistes de connexion 45 étant opposés l’un à l’autre. Ces pistes de connexion 45 sont donc soit directement connectées au composant électronique 90 (technologie de report de puce dit « flip- chip »), soit connectées au composant électronique 90 par l’intermédiaire de fils de connexion (technologie dite de « wire-bonding »  Figure 6 shows in particular a housing 110 of electronic component obtained by the above method. This electronic component housing 110 constitutes an element intended for surface mounting on an electrical circuit (a printed circuit for example). It has a connection face 112 and at least one electronic component 90 coated (encapsulated) in an encapsulation material 100 is connected to connection pads 45 flush, just like one face of the electronic component 90, on the connection face 112 , at the level of the encapsulation material 100. This housing 110 comprises two rows of connection tracks 45. They are located on the connection face 112, each respectively at a side 114 and an edge of the housing 110, the two sides 114 of the housing 110 each comprising a row of connection tracks 45 being opposite one another. These connection tracks 45 are therefore either directly connected to the electronic component 90 (chip transfer technology called "flip-chip"), or connected to the electronic component 90 via connection wires (technology called "wire-bonding" "
[0031] Un deuxième exemple de mise en œuvre du procédé selon l’invention représenté sur la figure 7. Il est décrit ci-dessous en relation avec la fabrication d’un boîtier de circuit intégré de type « QFN ». Cet exemple de mise en œuvre comporte les étapes suivantes :  A second example of implementation of the method according to the invention shown in Figure 7. It is described below in connection with the manufacture of an integrated circuit box of the "QFN" type. This implementation example includes the following steps:
[0032] - on fournit une bande 10 de matériau diélectrique (Fig. 7a) ; par exemple, le matériau diélectrique est du verre-epoxy, flexible et en rouleau (pour une mise en œuvre du procédé de dite de « rouleau à rouleau - soit « reel-to-reel » ou « roll-to-roll » en anglais) ; la bande 10 s’étend dans une direction longitudinale L selon laquelle elle est déroulée ; cette bande 10 a deux faces principales 10A, 10B ; la bande 10 a une épaisseur par exemple de 75 pm ou de 110 pm ;  - providing a strip 10 of dielectric material (Fig. 7a); for example, the dielectric material is glass-epoxy, flexible and in roll (for an implementation of the process known as of “roll to roll - either“ reel-to-reel ”or“ roll-to-roll ”in English ); the strip 10 extends in a longitudinal direction L in which it is unwound; this strip 10 has two main faces 10A, 10B; the strip 10 has a thickness of, for example, 75 μm or 110 μm;
[0033] - on enduit la bande 10 de matériau diélectrique, au moins partiellement, sur l’une (en l’occurrence la face principale 10A) de ses faces principales 10A, 10B avec un adhésif 20 (Fig. 7b) adapté pour coller temporairement le matériau diélectrique 10 avec un matériau électriquement conducteur 40 (Fig. 7d) ; le complexe ainsi réalisé avec la bande 10 recouverte de l’adhésif forme une couche de matériau flexible et amovible 80’ ;  - The strip 10 is coated with dielectric material, at least partially, on one (in this case the main face 10A) of its main faces 10A, 10B with an adhesive 20 (Fig. 7b) suitable for sticking temporarily the dielectric material 10 with an electrically conductive material 40 (Fig. 7d); the complex thus produced with the strip 10 covered with the adhesive forms a layer of flexible and removable material 80 ’;
[0034] - des perforations 30 sont réalisées dans la bande 10 de matériau diélectrique enduit de l’adhésif 20 ; en particulier des cavités sont réalisées, par exemple par poinçonnage, pour former des crans d’entrainement sur les bords de la bande 10 de matériau diélectrique (Fig. 7c) ; [0035] - un feuillet 40 de matériau électriquement conducteur métallique est laminé sur la face- Perforations 30 are made in the strip 10 of dielectric material coated with the adhesive 20; in particular cavities are made, for example by punching, to form drive notches on the edges of the strip 10 of dielectric material (Fig. 7c); - A sheet 40 of electrically conductive metal material is laminated on the face
10A de la bande 10 de matériau diélectrique comportant l’adhésif 20 (Fig. 7d) ; ce feuillet 40 de matériau électriquement conducteur est par exemple un feuillet de cuivre - ou d’un de ses alliages - de 105mhi d’épaisseur minimale ; 10A of the strip 10 of dielectric material comprising the adhesive 20 (Fig. 7d); this sheet 40 of electrically conductive material is for example a sheet of copper - or one of its alloys - 105mhi of minimum thickness;
[0036] - le feuillet 40 de matériau électriquement conducteur est gravé par exemple par photolithogravure pour définir et réaliser des motifs (alternativement les motifs sont complètement ou en partie seulement découpés mécaniquement avant lamination du feuillet 40 de matériau électriquement conducteur sur la bande 10 de matériau diélectrique) (Figs. 7e et 7f) ; ces motifs, et les unités de connexion qu’ils comprennent sont distribuées le long de la direction longitudinale L avec un pas fixe ; les motifs comprennent notamment des unités de connexion reliées par des pistes conductrices ; à cette étape, les unités de connexion comporte donc une cavité borgne ou non-débouchante 60 sur une face du matériau diélectrique ; l’une et/ou l’autre des deux faces du feuillet 40 de matériau électriquement conducteur sont éventuellement métallisées ; cette métallisation (par exemple Ni/ Au ou Ag) est par exemple adaptée aux procédés de report de composant de type « QFN » sur un circuit électrique et/ou de connexion à des plages de connexion 45 au composant électronique 90 (voir aussi plus loin en relation avec la Fig. 7g) ;  - The sheet 40 of electrically conductive material is etched for example by photolithography to define and produce patterns (alternatively the patterns are completely or partially only cut mechanically before lamination of the sheet 40 of electrically conductive material on the strip 10 of material dielectric) (Figs. 7e and 7f); these patterns, and the connection units which they comprise are distributed along the longitudinal direction L with a fixed pitch; the patterns include in particular connection units connected by conductive tracks; at this stage, the connection units therefore comprise a blind or non-opening cavity 60 on one face of the dielectric material; one and / or the other of the two faces of the sheet 40 of electrically conductive material are optionally metallized; this metallization (for example Ni / Au or Ag) is for example suitable for methods of transferring a component of the “QFN” type onto an electrical circuit and / or of connection to connection pads 45 to the electronic component 90 (see also below in relation to Fig. 7g);
[0037] - un composant électronique 90 est déposé dans une cavité 60 (Fig. 7f);  - an electronic component 90 is deposited in a cavity 60 (Fig. 7f);
[0038] - le composant électronique 90 est connecté par exemple par connexion par fil (wire- bonding) ou flip chip aux plages de connexion 45 (pour l’exemple illustré dans ce document, il s’agit d’une connexion par fil entre les plages de connexion 45 et les plots de connexion du composant électronique 90 - voir Fig.7g) ;  - the electronic component 90 is connected for example by wire connection (wire-bonding) or flip chip to the connection pads 45 (for the example illustrated in this document, it is a wire connection between the connection pads 45 and the connection pads of the electronic component 90 - see Fig. 7g);
[0039] - le composant électronique 90, les plages de connexion 45 et une portion du matériau diélectrique sont encapsulés par exemple dans une résine 100 (pour former ce que l’on appelle un glob-top), en remplissant par dispense les cavités 60 de place en place, pour former les composants de type « QFN » au pas souhaité (Fig. 7h) ;  - The electronic component 90, the connection pads 45 and a portion of the dielectric material are encapsulated for example in a resin 100 (to form what is called a glob-top), filling the cavities 60 by dispensing from place to place, to form the “QFN” type components at the desired pitch (Fig. 7h);
[0040] - de manière facultative, la résine 100 est aplatie ou érasée (Fig. 7h’);  - optionally, the resin 100 is flattened or flattened (Fig. 7h ’);
[0041] - la bande 10 de matériau diélectrique est retirée (pelée) (Fig. 7i) (avec l’adhésif 20) ; la bande 10 de matériau diélectrique a donc joué le rôle d’une couche de matériau flexible et amovible ;les composants électroniques 90 ou modules de type « QFN » sont ensuite testés électriquement et individualisés pour une étape de report (« pick and place » en anglais) ultérieure sur un circuit électrique ; cette étape peut être concomitante ou consécutive d’une étape de décourt-circuitage des plages de connexion 45; cette étape peut être concomitante ou consécutive d’une étape de découpe des bords de la cavité 60 constitués du matériau conducteur(Fig. 7j). - The strip 10 of dielectric material is removed (peeled) (Fig. 7i) (with the adhesive 20); the strip 10 of dielectric material therefore played the role of a layer of flexible and removable material, the electronic components 90 or modules of the “QFN” type are then electrically tested and individualized for a transfer step (“pick and place” in English) later on an electrical circuit; this stage can be concomitant or consecutive of a step of short-circuiting the connection pads 45; this step can be concomitant or consecutive with a step of cutting the edges of the cavity 60 made of the conductive material (Fig. 7j).
[0042] Les composants électroniques 90 obtenus par ce deuxième mode de mise en œuvre du procédé selon l’invention sont semblables ou similaires à ceux qui sont, ou auraient pu être, obtenus à l’aide du premier exemple et illustrés par les figures 2 à 6.  The electronic components 90 obtained by this second embodiment of the method according to the invention are similar or similar to those which are, or could have been, obtained using the first example and illustrated by Figures 2 to 6.
On notera que les étapes des Figures 7a) à 7e), par exemple, qui concernent la fabrication d’un support peuvent être réalisées chez un industriel, tandis que les étapes suivantes, qui concernent la mise en place et la connexion d’un composant électronique 90 sur ce support, peuvent être réalisées chez un autre industriel.  It will be noted that the steps of Figures 7a) to 7e), for example, which relate to the manufacture of a support can be carried out at an industrial, while the following steps, which relate to the installation and connection of a component electronics 90 on this support, can be carried out at another manufacturer.

Claims

Revendications claims
1. Procédé de fabrication de boîtiers de circuit intégré, dans lequel 1. A method of manufacturing integrated circuit packages, in which
- on fournit un matériau diélectrique sous forme d’une bande (10) s’étendant dans une direction longitudinale (L), cette bande (10) ayant deux faces principales (10A, 10B), dont l’une (10A) est au moins partiellement recouverte d’un feuillet (40) de matériau électriquement conducteur,  - providing a dielectric material in the form of a strip (10) extending in a longitudinal direction (L), this strip (10) having two main faces (10A, 10B), one of which (10A) is at less partially covered with a sheet (40) of electrically conductive material,
- on réalise une pluralité d’unités de connexion (54) dans le feuillet (40) de matériau électriquement conducteur, ces unités de connexion (54) étant distribuées le long de la direction longitudinale (L) avec un pas déterminé, chaque unité de connexion (54) comprenant une face de connexion (112) avec des plages de connexion (45), ces plages de connexion (45) étant destinées à la connexion électrique du boîtier de circuit intégré (110),  - a plurality of connection units (54) are produced in the sheet (40) of electrically conductive material, these connection units (54) being distributed along the longitudinal direction (L) with a determined pitch, each unit of connection (54) comprising a connection face (112) with connection pads (45), these connection pads (45) being intended for the electrical connection of the integrated circuit box (110),
- on place un composant électronique (90) au niveau de chaque unité de connexion (54) dans une cavité (60) borgne, le fond de cette cavité (60) borgne étant formé d’une couche de matériau flexible et amovible (80, 80’),  an electronic component (90) is placed at each connection unit (54) in a blind cavity (60), the bottom of this blind cavity (60) being formed from a layer of flexible and removable material (80, 80 '),
-on connecte un composant électronique (90) à au moins certaines des plages de connexion (45) de l’unité de connexion (54) au niveau de laquelle il est placé,  - an electronic component (90) is connected to at least some of the connection pads (45) of the connection unit (54) at which it is placed,
- on enrobe le composant électronique (90) dans un matériau d’encapsulation (100), au niveau de chaque unité de connexion (54),  - the electronic component (90) is coated with an encapsulation material (100), at each connection unit (54),
- on retire la couche de matériau flexible et amovible (80, 80’) après encapsulation du composant électronique (90),  - the layer of flexible and removable material (80, 80 ’) is removed after encapsulation of the electronic component (90),
caractérisé par le fait que le composant électronique (90) est enrobé dans un matériau d’encapsulation (100) par dispense de ce matériau dans la cavité (60) borgne.  characterized in that the electronic component (90) is embedded in an encapsulation material (100) by dispensing this material in the blind cavity (60).
2. Procédé selon la revendication 1, dans lequel les plages de connexion (45) sont au contact de la couche de matériau flexible et amovible (80, 80’), avant que celle-ci ne soit retirée, et affleurent, sur la face de connexion (112), au niveau du matériau d’encapsulation (100) après que la couche de matériau flexible et amovible (80, 80’) ait été retirée. 2. Method according to claim 1, in which the connection pads (45) are in contact with the layer of flexible and removable material (80, 80 '), before this is removed, and are flush with the face. connection (112), at the encapsulation material (100) after the layer of flexible and removable material (80, 80 ') has been removed.
3. Procédé selon la revendication 1 ou 2, comprenant, avant encapsulation du composant électronique (90), une étape consistant à isoler au moins certaines des plages de connexion (45) les unes des autres. 3. Method according to claim 1 or 2, comprising, before encapsulation of the electronic component (90), a step consisting in isolating at least some of the connection pads (45) from each other.
4. Procédé selon la revendication 1 ou 2, comprenant, après encapsulation du composant électronique (90), une étape consistant à isoler au moins certaines des plages de connexion (45) les unes des autres.  4. Method according to claim 1 or 2, comprising, after encapsulation of the electronic component (90), a step consisting in isolating at least some of the connection pads (45) from each other.
5. Procédé selon la revendication 4, dans lequel l’étape consistant à isoler au moins certaines des plages de connexion (45) les unes des autres est concomitante d’une étape consistant à individualiser des composants électroniques (90) correspondant chacun respectivement à une unité de connexion (54).  5. Method according to claim 4, in which the step consisting in isolating at least some of the connection pads (45) from each other is concomitant with a step consisting in individualizing electronic components (90) each corresponding respectively to a connection unit (54).
6. Procédé selon l’une des revendications précédentes, dans lequel la couche de matériau flexible et amovible (80) comporte une face revêtue d’un adhésif non permanent.  6. Method according to one of the preceding claims, wherein the layer of flexible and removable material (80) has a face coated with a non-permanent adhesive.
7. Procédé selon l’une des revendications précédentes, mis en œuvre de rouleau à rouleau dans lequel les plages de connexion (45) sont isolées les unes des autres et dans lequel les composants électroniques (90) sont testés électriquement individuellement avant individualisation.  7. Method according to one of the preceding claims, implemented from roll to roll in which the connection pads (45) are isolated from each other and in which the electronic components (90) are tested electrically individually before individualization.
8. Boîtier de composant électronique destiné à un montage en surface sur un circuit électrique, ce boîtier de composant (110) étant fabriqué selon un procédé conforme à l’une des revendications précédentes, comportant une face de connexion (112) et au moins un composant électronique (90) encapsulé dans un matériau d’encapsulation (100) et connecté à des plages de connexion (45), lesquelles plages de connexion (45) et le composant électronique (90)affleurant sur la face de connexion (112), au niveau du matériau d’encapsulation (100).  8. Electronic component housing intended for surface mounting on an electrical circuit, this component housing (110) being manufactured according to a method according to one of the preceding claims, comprising a connection face (112) and at least one electronic component (90) encapsulated in an encapsulation material (100) and connected to connection pads (45), which connection pads (45) and the electronic component (90) flush with the connection face (112), at the encapsulation material (100).
9. Boîtier selon la revendication 8, dans lequel le matériau d’encapsulation (100) est contenu dans une cavité (60) au moins en partie limitée au niveau de sa périphérie par un bord de la bande (10) de matériau diélectrique.  9. Housing according to claim 8, in which the encapsulation material (100) is contained in a cavity (60) at least partially limited at its periphery by an edge of the strip (10) of dielectric material.
10. Boîtier selon l’une des revendications 8 et 9, comportant au moins deux rangées de pistes de connexion situées chacune sur la face de connexion (112) au niveau d’un côté (114) du boîtier de composant (110), ces pistes de connexion étant soit directement connectées au composant électronique (90), soit connectées au composant électronique (90) par l’intermédiaire de fils de connexion. 10. Housing according to one of claims 8 and 9, comprising at least two rows of connection tracks each located on the connection face (112) at one side (114) of the component housing (110), these connection tracks being either directly connected to the electronic component (90), or connected to the electronic component (90) via connection wires.
11. Boîtier selon l’une des revendications 8 à 10, dans lequel une face du composant électronique (90) affleure sur la face de connexion (112), au niveau du matériau d’encapsulation (100) et des plages de connexion (45). 11. Housing according to one of claims 8 to 10, in which one face of the electronic component (90) is flush with the connection face (112), at the level of the encapsulation material (100) and of the connection pads (45 ).
PCT/FR2019/051729 2018-07-13 2019-07-10 Process for manufacturing electronic-component packages and electronic-component package obtained by means of this process WO2020012120A1 (en)

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EP19749397.6A EP3821458A1 (en) 2018-07-13 2019-07-10 Process for manufacturing electronic-component packages and electronic-component package obtained by means of this process

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FR1856526A FR3083920A1 (en) 2018-07-13 2018-07-13 METHOD FOR MANUFACTURING ELECTRONIC COMPONENT PACKAGES AND ELECTRONIC COMPONENT PACKAGE OBTAINED BY THIS PROCESS

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US20070114641A1 (en) * 2005-11-21 2007-05-24 Stmicroelectronics Asia Pacific Pte Ltd Ultra-thin quad flat no-lead (QFN) package
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