CN112470261A - Method for manufacturing an electronic component package and electronic component package obtained by the method - Google Patents

Method for manufacturing an electronic component package and electronic component package obtained by the method Download PDF

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Publication number
CN112470261A
CN112470261A CN201980046879.4A CN201980046879A CN112470261A CN 112470261 A CN112470261 A CN 112470261A CN 201980046879 A CN201980046879 A CN 201980046879A CN 112470261 A CN112470261 A CN 112470261A
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China
Prior art keywords
connection
electronic component
package
connection pads
face
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Pending
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CN201980046879.4A
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Chinese (zh)
Inventor
劳伦特·贝达勒
M·克里斯托夫·马蒂厄
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Linxens Holding SAS
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Linxens Holding SAS
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Publication of CN112470261A publication Critical patent/CN112470261A/en
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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Abstract

The invention relates to a method of manufacturing an integrated circuit package (110), wherein cavities are made in a strip of dielectric material covered with a sheet of conductive material. An electronic component (90) is placed in the cavity and encapsulated by at least partially filling the cavity with an encapsulating material (100). The bottom of the blind cavity is formed by a layer of flexible and removable material which is removed after encapsulation. The invention also relates to an integrated circuit package (110) manufactured according to the method. The integrated circuit package (110) is, for example, a QFN package.

Description

Method for manufacturing an electronic component package and electronic component package obtained by the method
The present invention relates to the field of methods of manufacturing electronic component packages, such as, for example, "QFN" (Quad Flat No-lead, english) type integrated circuit packages.
Methods of manufacturing electronic component packages are known in which portions of an electrical circuit (ports) to which electronic components (electrical chips, light emitting diodes, etc.) are connected are continuously generated, the electronic components then being encapsulated in resin by injection molding or by potting. The portion of the circuit equipped with the electronic components is then singulated so as to be used as surface mount components ("surface mount components" or "SMCs" in english).
For example, document EP2846355A1 describes a process in which
-providing a dielectric material in the form of a strip; the strip extending in a longitudinal direction and having two main surfaces, one of which is at least partially covered with a sheet of electrically conductive material,
-manufacturing a plurality of connection units in the sheet of electrically conductive material, the connection units being distributed at a determined pitch in the longitudinal direction, each connection unit comprising a connection face with connection pads intended for electrical connection of the integrated circuit package, for example to a printed circuit board,
-an electronic component is placed on the strip in each connection unit and is connected to at least some of the connection pads of the connection unit in which the electronic component is placed, and
in each connection unit, the electronic components are potted in an encapsulating material.
In the method, in each connection unit, the electronic components are placed in cavities formed in the package by injection moulding on the strip and in a mould. Next, the electronic components are potted in a resin disposed within the cavity.
The present invention provides another method for manufacturing an integrated circuit package.
The method corresponds to claim 1.
Thus, the electronic component is also placed within its encapsulation (or potting; in this context the terms "potting" and "encapsulation" are used as synonyms, also as "encapsulated" or "encapsulated", within the cavity, but on the one hand the cavity is created differently and on the other hand the encapsulation is performed by dispensing (dispense), i.e. by arranging encapsulating material within the cavity, without using a mould. The cavity is a blind cavity. The bottom of the cavity is formed by a layer of flexible and removable material which is removed after encapsulation of the electronic component.
By virtue of the present invention, it is possible to encapsulate an electronic component in plastic, resin, or the like by potting after the plastic, resin, or the like has been arranged on a carrier, without having to form an encapsulation by injecting the plastic into a mold in advance or use a separate mold to inject a potting material. The method according to the invention makes it possible to use at least one or more materials (dielectric, conductive, etc.) which are further required to produce the connecting rail to form at least part of a blind cavity which will subsequently be used to contain the encapsulating material.
The method according to the invention makes it possible in particular to produce integrated circuit packages of the "QFN" type, in which electronic components, in the present case electronic chips, are packaged as miniaturized components ("SMCs") for surface mounting. It can also be used to produce SIM cards ("Subscriber Identity modules" in the english text) with flush contacts for making electrical connections with the device in which the SIM card is inserted.
The method according to the invention optionally comprises one or the other of the features mentioned in claims 2 to 7, considered alone or in combination with one or more other features.
According to another aspect, the invention relates to an electronic component package intended for surface mounting on an electric circuit, the package being manufactured using a method as described above. The features of the package correspond to those mentioned in claim 8.
The electronic component package according to the invention optionally comprises one or other of the features mentioned in claims 9 to 11, considered alone or in combination with one or more other features.
Other features and advantages of the present invention will become apparent from a reading of the following detailed description and a review of the associated drawings. In these drawings:
figures 1a to 1m schematically show the steps of a first embodiment of the method according to the invention;
figure 2 shows a top view of an example of a circuit strip at various stages of the method according to the invention; FIG. 2A shows an enlarged portion of FIG. 2;
fig. 3 shows a circuit connection unit for implementing the method according to the invention, wherein the electronic components are placed in the connection unit before;
fig. 4 shows the circuit connection unit of fig. 3 after the electronic components have been placed and overmoulded in the connection unit;
figure 5 schematically shows a bottom view of an example of an integrated circuit package obtained using a method according to the invention;
fig. 6 schematically shows a perspective view of the integrated circuit package of fig. 5; and
figures 7a to 7j schematically show the steps of a second embodiment implemented according to the method of the invention.
A first embodiment of the method according to the invention is shown in fig. 1. The first embodiment is described below with respect to the fabrication of a "QFN" type integrated circuit package. This embodiment comprises the steps of:
-providing a strip 10 of dielectric material (fig. 1 a); for example, the dielectric material is glass epoxy, flexible and in roll form (for implementing the so-called "roll-to-roll" method, "reel-to-reel" or "roll-to-roll" in english); the strip 10 extends in the longitudinal direction L, rolling out (tworoule) in the longitudinal direction L; the strip 10 has two major surfaces 10A, 10B; the strip 10 has a thickness such as 75 μm or 110 μm;
at least partially coating one of the main surfaces 10A, 10B of the strip of dielectric material 10 (in the present case on the main surface 10A) with an adhesive 20 (modified epoxy type), the adhesive 20 being activatable by heat (fig. lb);
creating perforations 30 in the strip of dielectric material 10 coated with adhesive 20 so as to form aligned notches (crans d' entrainement) and cavities at the edges of the strip of dielectric material 10; these perforations 30 are produced, for example, by punching; the cavities are distributed at a pitch defined by the desired distance between the integrated circuit packages (fig. 1 c);
laminating the sheet 40 of conductive metal material to the face 10A of the strip 10 of dielectric material comprising the adhesive 20 (fig. 1 d); the sheet 40 of conductive material is, for example, a 70 μm thick sheet of copper or a sheet of copper alloy.
Etching the sheet of conductive material 40, for example by photolithography, to define and create the pattern 50 (or, mechanically cutting the pattern 50, either completely or only partially, before the sheet of conductive material 40 is laminated to the face of the strip of dielectric material 10 comprising the adhesive 20); these patterns 50 and the connection units they comprise are distributed at set intervals in the longitudinal direction L; the pattern 50 comprises, among other things, connection units connected by conductive tracks (fig. 1e and 2); in this step, in at least some of the connection units, a blind or blind cavity 60 remains on one side of the strip 10 of dielectric material; one or both of the two faces of the sheet of conductive material 40 may optionally be metallised; this (e.g. Ni/Au or Ag) metallization is for example suitable for a method of transferring a "QFN" type component to a circuit and/or for connecting connection pads to an electronic component 90 (see described below with respect to fig. 1 i);
then, cutting other pattern elements 55 (e.g. comb-shaped elements, see fig. 1f and 2) in the sheet 40 of conductive material at the height of the cavities 60 by mechanical punching or chemical etching to form connection pads 45; a through port 70 is also formed at the center of each connection unit between the connection pads 45; the connection pads 45 allow, on the one hand, the connection of components of the "QFN" type to the circuit and, on the other hand, the connection of electronic components 90 (fig. 1f and 1 i);
temporarily arranging (dpoes) a layer of removable and flexible material 80 (fig. 1g) on this sheet of conductive material 40, the layer of removable and flexible material 80 being intended to close the cavity 60 on one side of the sheet of conductive material 40; the layer of removable material 80 consists, for example, of a strip with a non-permanent adhesive, or comprises a face coated with a non-permanent adhesive; for example, the removable material layer 80 may be a polypropylene film coated with a rubber-based adhesive layer or a polyimide film coated with a silicone-based adhesive layer; optionally, the adhesive layer is protected by a protective non-stick film; it may be a product of reference number 1285 of SCAPA company, or a product of reference number SMX-P30S of SEEMEX corporation (a company located in seoul, korea), or a product of reference number PS1030-06A of indox brand (sold by Shinha corporation located in kyonggi tract, korea); the layer of removable material 80 forms the bottom of the opening 70 cut in the previous step; thus forming a blind or blind cavity 60; thus, the cavity 60 is closed at the bottom by the removable layer 80 and on its perimeter by the edge faces cut out of the strips 10 of dielectric material and of the sheet 40 of conductive material; the removable layer 80 is in contact with the connection pads 45 and thus protects one face of the connection pads 45 during subsequent packaging steps;
arranging an electronic component 90, e.g. an electronic chip, in the cavity 60, e.g. on the adhesive face of the removable layer 80 arranged in the previous step (fig. 1 h);
connecting the electronic component 90 to the connection pads 45 using, for example, techniques such as wire bonding or flip chip (in the example illustrated herein, the connection pads 45 and the lands of the electronic component 90 are wire bonded-see fig. 1 i);
the connection pads 45 are mutually isolated by stamping to allow individual electrical testing of "QFN" type components (fig. 1 j); in fig. 1j and fig. 3 and 4, before this step of allowing the connection pads 45 to be electrically isolated from each other, the broken line schematically represents the short-circuit 48 present in the conductive sheet 40; therefore, after this step, although the electronic component package 110 has not been singulated (see below), it is feasible to mount the electronic component 90, and connect the electronic component 90 to the connection pads 45, and then test it; this step is optional, especially in the case where electronic components 90 are only tested after singulation of respective packages 110 (see fig. 5 and 6);
encapsulating the electronic components 90, the connection pads 45 and a portion of the strip 10 of dielectric material at various positions with an encapsulating material 100, for example by dispensing a thermosetting resin (for example, using a technique known in english as "dam & fill") to form a component of the "QFN" type with the desired pitch (fig. 1 k); the product of reference number "Delo DF 570-580" may be used as packaging material; in this case, the product corresponds to what is called "Black thermal resins for encapsulation" in english;
removing (peeling off) the removable layer 80 intended to close the cavity at one side of the conductive sheet 40 (fig. 1 l);
next, before the subsequent step, known in english as "pick-and-place", the "QFN" type package 110 or module is electrically tested and transferred to the circuit in the pick-and-place step, by dicing single cuts (fig. 1 m).
It is noted that the steps of fig. 1a) to 1g), for example relating to the manufacture of the carrier (corresponding to the structure of the strips of dielectric material 10, the adhesive 20 and the sheets of conductive material 40), may be performed by one manufacturer, while the subsequent steps relating to the transfer and connection of the electronic components 90 to the carrier may be performed by another manufacturer.
Fig. 2 schematically shows a strip 10 of dielectric material with a pattern 50 etched in a sheet 40 of conductive material. By way of illustration, the corresponding results of the various steps of the method described above are shown in the same figure (fig. 2), whereas in practice these steps are carried out sequentially. The pattern 50 includes conductive traces 52 and connection elements 54. The conductive tracks 52 are used, inter alia, to supply an electric current during the electrolytic deposition, enabling the metallization of the connection pads 45. In this figure, the connection unit 54 is shown after cutting the connection pads 45 (see also fig. 3). In one connection unit 54 (see enlarged region 2A), the region of the cut-outs 56 made by stamping is also shown, in order to isolate the connection pads 45 from one another (see also fig. 4). In addition, the dashed line 58 delimits this area, which is subsequently cut away after encapsulating the electronic component 90 and its connection (see also fig. 5 and 6). It should be noted that the connection pads 45 (fig. 1m) may be isolated simultaneously in the final step of singulating the electronic component package 110 if the connection pads 45 have not been isolated from each other yet during a step such as shown in fig. 1 j.
Fig. 6 particularly shows an electronic component package 110 obtained using the method described above. The electronic component package 110 constitutes a component intended for surface mounting on a circuit, such as a printed circuit board, for example. The electronic component package 110 includes a connection face 112, and at least one electronic component 90 potted (encapsulated) in the encapsulating material 100 is connected to the connection pads 45, the connection pads 45 being on the connection face 112, as one face of the electronic component 90, flush with the encapsulating material 100. The package 110 comprises two rows of connection rails 45. Two rows of connection rails 45 are located on the connection face 112, each of which is adjacent to one side 114 and one edge of the package 110, two sides 114 of the package 110 each include one row of connection rails 45, and the two sides 114 each include one row of connection rails 45 opposite to each other. These connection tracks 45 are therefore connected either directly to the electronic component 90 (so-called "flip-chip" technology) or via bonding wires to the electronic component 90 (so-called "wire-bonding" technology).
A second embodiment of the method according to the invention is shown in fig. 7. The second embodiment is described below with respect to the fabrication of a "QFN" type integrated circuit package. This embodiment comprises the steps of:
-providing a strip 10 of dielectric material (fig. 7 a); for example, the dielectric material is glass epoxy, flexible and in roll form (for implementing the so-called "roll-to-roll" method, "reel-to-reel" or "roll-to-roll" in english); the strip 10 extends in the longitudinal direction L, rolling out in the longitudinal direction L; the strip 10 has two major surfaces 10A, 10B; the strip 10 has a thickness such as 75 μm or 110 μm;
at least partially coating one of the main surfaces 10A, 10B of the strip of dielectric material 10 (in the present case on the main surface 10A) with an adhesive 20 (fig. 7B), the adhesive 20 being suitable for temporarily bonding the dielectric material 10 to the conductive material 40 (fig. 7 d); the composite thus produced with the adhesive-covered strip 10 forms a flexible and removable layer of material 80';
-creating perforations 30 in the strip of dielectric material 10 coated with the adhesive 20; in particular, cavities are produced, for example by stamping, to form alignment notches at the edges of the strip 10 of dielectric material (fig. 7 c);
laminating the sheet 40 of conductive metal material to the face 10A of the strip 10 of dielectric material comprising the adhesive 20 (fig. 7 d); the sheet 40 of conductive material is, for example, a copper sheet or a copper alloy sheet having a minimum thickness of 105 μm.
Etching the sheet of conductive material 40, for example by photolithography, to define and create the pattern (or mechanically cutting it out completely or only partially before the sheet of conductive material 40 is laminated to the strip of dielectric material 10) (fig. 7e and 7 f); the patterns and the connection units comprised by them are distributed at set intervals along the longitudinal direction L; the pattern comprises, inter alia, connection elements connected by conductive tracks; thus, in this step, the connection unit comprises a blind or blind cavity 60 on one side of the dielectric material; one or both of the two faces of the sheet of conductive material 40 may optionally be metallised; such as a method suitable for transferring a "QFN" type component to a circuit and/or a method suitable for connecting the connection pads 45 to the electronic component 90 (see also below with respect to fig. 7 g);
arranging the electronic component 90 in the cavity 60 (fig. 7 f);
connecting the electronic component 90 to the connection pads 45 using, for example, wire bonding or flip chip technology (in the example illustrated herein, the connection pads 45 and the lands of the electronic component 90 are wire bonded-see fig. 7 g);
by completely filling the cavities 60 with the dispensing, the electronic components 90, the connection pads 45 and a length of dielectric material are encapsulated, for example in a resin 100 (to form a so-called resin cap) to form "QFN" type components with the required pitch (fig. 7 h);
optionally, the resin 100 is flattened or tamped (erase) (fig. 7 h');
-removing (peeling off) the strip of dielectric material 10 (fig. 7i) (with the adhesive 20); the strip 10 of dielectric material thus acts as a flexible and removable layer of material; then the step of electrical testing and singulation of the electronic components 90 or "QFN" type modules for subsequent transfer to the circuit (known in english as "pick-and-place"); this step can be carried out simultaneously with or successively to the step of short-circuiting the connection pads 45; this step may be performed simultaneously or sequentially with the step of cutting the edges of the cavity 60 in the conductive material (fig. 7 j).
The electronic components 90 obtained by the second embodiment of the method according to the invention are identical or similar to those obtained using the first embodiment and shown in fig. 2 to 6.
It should be noted that for example the steps in fig. 7a) to 7e) relating to the manufacture of the carrier may be performed by one manufacturer, whereas the subsequent steps relating to the transfer and connection of the electronic component 90 to the carrier may be performed by another manufacturer.

Claims (11)

1. A method of manufacturing an integrated circuit package, wherein
-providing the dielectric material in the form of a strip (10) extending in a longitudinal direction (L), the strip (10) having two main surfaces (10A, 10B), wherein one main surface (10A) is at least partially covered with a sheet (40) of electrically conductive material,
-producing a plurality of connection units (54) in the sheet (40) of electrically conductive material, the connection units (54) being distributed at a determined pitch along a longitudinal direction (L), each connection unit (54) comprising a connection face (112) with connection pads (45), the connection pads (45) being intended for electrical connection of the integrated circuit package (110),
-placing an electronic component (90) in a blind cavity (60) in each connection unit (54), the bottom of said blind cavity (60) being formed by a layer (80, 80') of flexible and removable material,
-connecting electronic components (90) to at least some of the connection pads (45) of a connection unit (54) in which the electronic components are placed,
-potting the electronic components (90) in an encapsulating material (100) in each connection unit (54),
-removing the flexible and removable material layer (80, 80') after encapsulation of the electronic component (90),
characterized in that the electronic component (90) is potted in an encapsulating material (100) by dispensing the encapsulating material (100) within the blind cavity (60).
2. Method according to claim 1, characterized in that the connection pads (45) are in contact with the layer of flexible and removable material (80, 80') before the layer of flexible and removable material (80, 80') is removed, and that the connection pads (45) are flush with the packaging material (100) on the connection face (112) after the layer of flexible and removable material (80, 80') is removed.
3. The method according to claim 1 or 2, comprising: -a step of isolating at least some of the connection pads (45) from each other before the packaging of the electronic component (90).
4. The method according to claim 1 or 2, comprising: -a step of isolating at least some of the connection pads (45) from each other after the encapsulation of the electronic component (90).
5. The method of claim 4, comprising: the step of isolating at least some of said connection pads (45) from each other is carried out simultaneously with the step of singulating the electronic components (90), each of said electronic components (90) corresponding to a respective one of the connection units (54).
6. Method according to any one of the preceding claims, characterized in that said layer (80) of flexible and removable material comprises a face coated with a non-permanent adhesive.
7. The method according to any of the preceding claims, characterized in that it is carried out in a roll-to-roll manner, wherein the connection pads (45) are mutually isolated, and wherein the electronic components (90) are individually electrically tested before singulation.
8. An electronic component package intended for surface mounting on a circuit, characterized in that the component package (110) is manufactured using the method according to any of the preceding claims, the electronic component package comprising: a connection face (112) and at least one electronic component (90), the at least one electronic component (90) being encapsulated in an encapsulating material (100) and being connected to a connection pad (45), the connection pad (45) and the electronic component (90) being flush with the encapsulating material (100) on the connection face (112).
9. The package according to claim 8, characterized in that the encapsulating material (100) is contained in a cavity (60), the cavity (60) being delimited on its perimeter at least partially by the edges of the strip of dielectric material (10).
10. Package according to any of claims 8 and 9, characterized in that it comprises at least two rows of connection rails, each on the connection face (112) of one side (114) of the component package (110), which connection rails are connected directly to the electronic component (90) or to the electronic component (90) by means of connection lines.
11. Package according to any of claims 8 to 10, characterized in that one face of the electronic component (90) is flush with the encapsulating material (100) and the connection pads (45) on the connection face (112).
CN201980046879.4A 2018-07-13 2019-07-10 Method for manufacturing an electronic component package and electronic component package obtained by the method Pending CN112470261A (en)

Applications Claiming Priority (3)

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FR1856526A FR3083920A1 (en) 2018-07-13 2018-07-13 METHOD FOR MANUFACTURING ELECTRONIC COMPONENT PACKAGES AND ELECTRONIC COMPONENT PACKAGE OBTAINED BY THIS PROCESS
FR1856526 2018-07-13
PCT/FR2019/051729 WO2020012120A1 (en) 2018-07-13 2019-07-10 Process for manufacturing electronic-component packages and electronic-component package obtained by means of this process

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FR3083920A1 (en) 2020-01-17
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