WO2020007376A1

WO2020007376A1 - Semiconductor memory

Info

Publication number: WO2020007376A1
Application number: PCT/CN2019/099649
Authority: WO
Inventors: 彭泽忠
Original assignee: 成都皮兆永存科技有限公司
Priority date: 2018-07-06
Filing date: 2019-08-07
Publication date: 2020-01-09
Also published as: CN109244079A

Abstract

A semiconductor memory, relating to the technology of memories. The present invention comprises: at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips arranged in parallel; vertical posts arranged in a same layer and between two adjacent conductive strips, the included angle between the axis of a vertical post and the axis of a conductive strip being greater than 30°; storage units are provided at where the vertical posts and the conductive strips intersect, and a storage unit comprises a first conductive type region, a second conductive type region, and an insulating medium region arranged between the first conductive type region and the second conductive type region; a vertical post conductive region is provided along the axial direction of a vertical post, and the vertical post conductive region forms an electrical connection with the first conductive type region of the storage unit; a conductive material region is provided along the axis of a conductive strip, and the conductive material region forms an electrical connection with the second conductive type region of the storage unit. The present invention has high storage density, low cost, and high reliability.

Description

Semiconductor memory

Technical field

The invention relates to memory technology.

Background technique

Current technologies include erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, NAND-flash memory, rigid magnetic disks, compact discs (CDs), and digital versatile discs (DVDs) Various digital storage technologies, including Blu-ray Discs registered by the Blu-ray Disc Association, have been widely used for data storage for more than 50 years. However, the life of a storage medium is usually less than 5 to 10 years. The anti-fuse storage technology developed for large data storage cannot meet the needs of mass data storage due to its very expensive and low storage density.

Summary of the invention

The technical problem to be solved by the present invention is to provide a high-density, low-cost semiconductor memory. The technical solution adopted by the present invention to solve the technical problem is a semiconductor memory, which is characterized by:

At least two conductive strip layers, each conductive strip layer including at least 3 parallel conductive strips;

Pillars arranged on the same layer and between two adjacent conductive bars, the angle between the axis of the column and the axis of the conductive bars is greater than 30 °;

A memory cell is provided at the intersection of the pillar and the conductive strip, the memory cell includes a first conductive type region, a second conductive type region, and an insulating dielectric region provided between the first conductive type region and the second conductive type region;

The pillar is provided with a pillar conductive region along its axis direction, and the pillar conductive region forms an electrical connection with the first conductivity type region of the memory cell;

The conductive strip is provided with a conductive material region along its axis, and the conductive material region forms an electrical connection with the second conductive type region of the memory cell;

The materials of the first conductive type region and the second conductive type region are two semiconductor materials with different doping types, respectively;

Alternatively, the materials of the first conductive type region and the second conductive type region are respectively two types of Schottky materials that are required to generate Schottky contact;

Each conductive bar and each column is provided with a circuit interface for connecting with an external circuit.

Further, the pillars are arranged in M × N rows and columns, and M and N are both integers greater than 2. The pillars in the same column are disposed between two adjacent conductive bars in the same layer.

The axes of the columns are parallel to each other and perpendicular to the axes of the conductive bars, and the axes of the conductive bars in the same layer are parallel to each other.

Further, the positional relationship between the axes of the conductive strips of two adjacent layers is different planes and perpendicular to each other.

The material of the conductive strip is the same as that of the second conductive type region;

In the radial direction, the column is divided into two layers, the inner layer is the conductive area of the column, the material of which is the same as that of the first conductive type, and the material of the outer layer is the same as that of the insulating medium. The area is the insulating medium area of the memory cell.

The upright is a cylindrical or other shape upright

An external circuit interface is provided at the end of the upright post and the conductive strip.

A low-impedance region is provided along the axis of the conductive strip. The material of the low-resistance region is a metal or other highly doped semiconductor, or a metal-silicon compound.

The conductive strips on the same layer are numbered sequentially from 1 according to any arrangement direction of the conductive strips. The conductive strips with an odd number form a circuit connection with each other, and the conductive strips with an even number form a circuit connection with each other;

Each row of columns is connected to a row circuit interface corresponding to the row, and each column of columns is connected to a column circuit interface corresponding to the column.

The “two semiconductor materials having different doping types” means that if one of them is a p-type semiconductor, the other is an n-type semiconductor.

The upright post and the conductive strip of the present invention form a cross positional relationship. For a pillar provided between two adjacent conductive strips on the same layer, the intersections between the two conductive strips are located on both sides of the pillar, that is, one on each side of the pillar. Storage unit. One post has two storage units at the intersection with a layer of conductive strip, so the invention has the effect of high-density storage.

The invention has the characteristics of high storage density, low cost and high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an equivalent structure of a memory cell of the present invention.

FIG. 2 is a schematic structural diagram of a storage unit according to the present invention.

Figure 3 is a schematic diagram of the first arrangement of the columns.

Figure 4 is a schematic diagram of a second arrangement of the columns.

FIG. 5 is a schematic structural diagram of Embodiment 1 of the present invention.

FIG. 6 is a schematic structural diagram of Embodiment 2 of the present invention.

FIG. 7 is a schematic structural diagram of Embodiment 3 of the present invention.

FIG. 8 is a schematic structural diagram of Embodiment 4 of the present invention.

FIG. 9 is a schematic structural diagram of Embodiment 5 of the present invention.

detailed description

See Figures 1 and 2.

The memory cell of the present invention has a three-layer structure, which can be a "p-type semiconductor-insulating medium-n-type semiconductor" structure, or a "metal-insulating medium-semiconductor" structure. Metal and semiconductor materials, after the dielectric is broken down, the metal and semiconductor form a Schottky contact. FIG. 1 is a simplified schematic diagram of a memory cell structure, 12 is an insulating dielectric region, and the first conductivity type region 11 and the second conductivity type region 13 may be a p-type semiconductor and an n-type semiconductor, or the first conductivity type region 11 and the second conductivity type region, respectively. The conductive type regions 13 are a metal and a semiconductor material, respectively.

In the actual structure, 11, 12, and 13 in FIG. 1 correspond to parts of 21, 22, and 23 in the ellipse dotted area in FIG. 2, respectively. In FIG. 2, 21 and 24 are two conductive strips of the same layer and adjacent to each other, and are filled with an insulating dielectric material between the two and outside the column area.

The Schottky contact referred to in the present invention refers to a Schottky contact having a diode characteristic (unidirectional conduction characteristic).

Referring to FIG. 2, a memory cell is formed at the intersection of the pillar and the conductive strip, which is shown by the oval dotted area in FIG. 2. As far as the memory cell is concerned, one end of the memory cell forms an electrical connection with the conductor region 23 of the pillar, and the other end of the memory cell forms an electrical connection with the conductive strip 21.

In this embodiment, the pillar is cylindrical, and its conductor region is located on the inner layer and the outer layer is an insulating material along the radial direction. The material of the conductor region of the pillar is the same as that of the first conductivity type region of the storage unit, and the material of the conductive material region of the conductive strip is the same as that of the second conductivity type region of the memory cell. A part of the conductive cell forms a first conductive type region of the memory cell, and a part of the conductive strip forms a second conductive type region of the memory cell. In this embodiment, the first conductivity type region is an n-type semiconductor region, and the second conductivity type region is a p-type semiconductor region.

The columns are arranged in M × N rows and columns, and M and N are both integers greater than 2. The bottom surface or cross section of the pillars are arranged in rows and columns. A schematic diagram of the plan view is shown in FIG. 3. A preferred mode is a coplanar relationship between the bottom surfaces of the columns.

Another arrangement of the columns is that the rows are staggered. A schematic diagram of the plan view is shown in Figure 4. Even other forms that do not strictly follow the column and column distribution.

Example 1

Referring to FIG. 5, the conductive strips are arranged in layers, and each layer is provided with at least 3 conductive strips in parallel. A preferred manner is that the conductive strips are arranged in parallel. The state that the conductive strips in the same layer are not parallel also belongs to the scope of the present invention. In FIG. 5, for the conductive strips of the same layer, according to the arrangement direction of the conductive strips, the conductive strips with an odd number are connected to the same reference point on the circuit, and the conductive strips with an even number are connected to another reference point on the circuit.

The columns in the same row (or in the same row) are arranged between two adjacent conductive bars on the same layer, or in other words, columns are arranged in the gap formed by the adjacent two conductive bars, and the columns intersect with the two conductive bars at the intersection Set the storage unit. The pillar and two conductive strips on the same layer form two intersections, which are respectively located on both sides of the pillar, and the two storage units are respectively located on both sides of the pillar.

The angle between the axis of the column and the axis of the conductive strip is greater than 30 °. Preferably, the axis of the column is perpendicular to the axis of the conductive strip, and the two form a perpendicular relationship between different planes. It is also feasible if the axis of the column and the axis of the conductive strip are non-orthogonal, but the cost is higher in the manufacturing process.

Example 2

Referring to FIG. 6, the difference between this embodiment and Embodiment 1 is that the directions of two adjacent conductive strips in this embodiment are perpendicular to each other.

Example 3

See Figure 7. The difference between this implementation and Embodiment 1 is that for each layer of conductive strips, the conductive strips with an odd number form a circuit connection with each other according to the arrangement direction of the conductive strips, or are electrically connected to the same reference point;

The even-numbered conductive strips form a circuit connection with each other, which essentially groups the conductive strips of the same layer. This method ensures that the two memory cells distributed on the left and right sides of the pillars at the same level of the conductive strip are independent of each other.

Such a conductive bar grouping method can also be applied to the second embodiment.

Example 4

As an improved embodiment, referring to FIG. 8, a low-impedance region 25 is provided along the axis of the conductive strip inside the conductive strip to enhance the conductivity of the conductive strip.

Example 5

This embodiment is an improvement on the circuit connection of the pillar. The posts in the same row are electrically connected to the common reference point of the row, and the posts in the same column are electrically connected to the common reference point of the column, so that the posts can be connected to the external circuit in rows and columns, not shown in Figures 6 and 7. This feature is shown in FIG. 9. Fig. 9 can be regarded as a simplified schematic diagram of the bottom view angle of Fig. 6 or Fig. 7, wherein the circle represents the conductive area of the column, which is connected by

row lines

911, 912, 913 in rows, and by

column lines

921, 922, 923 in columns.

Claims

A semiconductor memory, including:

At least two conductive strip layers, each conductive strip layer including at least 3 parallel conductive strips;

Pillars arranged on the same layer and between two adjacent conductive bars, the angle between the axis of the column and the axis of the conductive bars is greater than 30 °;

A memory cell is provided at the intersection of the pillar and the conductive strip, the memory cell includes a first conductive type region, a second conductive type region, and an insulating dielectric region provided between the first conductive type region and the second conductive type region;

The pillar is provided with a pillar conductive region along its axis direction, and the pillar conductive region forms an electrical connection with the first conductivity type region of the memory cell;

The conductive strip is provided with a conductive material region along its axis, and the conductive material region forms an electrical connection with the second conductive type region of the memory cell;

The materials of the first conductive type region and the second conductive type region are two semiconductor materials with different doping types, respectively;

Alternatively, the materials of the first conductive type region and the second conductive type region are respectively two types of Schottky materials that are required to generate Schottky contact;

Each conductive bar and each column is provided with a circuit interface for connecting with an external circuit.
The semiconductor memory according to claim 1, wherein the pillars are arranged in M × N rows and columns, and M and N are integers greater than two, and the pillars in the same column are disposed on two adjacent conductive strips on the same layer. between.
The semiconductor memory according to claim 1, wherein the axes of the pillars are parallel to each other and perpendicular to the axis of the conductive bars, and the axes of the conductive bars in the same layer are parallel to each other.
The semiconductor memory according to claim 1, wherein the positional relationship between the axes of the conductive strips of two adjacent layers is different and perpendicular to each other.
The semiconductor memory according to claim 1, wherein:

The material of the conductive strip is the same as that of the second conductive type region;

In the radial direction, the column is divided into two layers, the inner layer is the conductive area of the column, the material of which is the same as that of the first conductive type, and the material of the outer layer is the same as that of the insulating medium. The area is the insulating medium area of the memory cell.
The semiconductor memory according to claim 1, wherein the pillar is a cylindrical pillar.
The semiconductor memory according to claim 1, wherein an external circuit interface is provided on an end of the pillar and the conductive strip.
The semiconductor memory according to claim 1, wherein a low-impedance region is provided inside the conductive strip along an axis thereof.
The semiconductor memory according to claim 7, wherein a material of the low-resistance region is a metal, a highly doped semiconductor, or a metal-silicon compound.
The semiconductor memory according to claim 2, characterized in that among the conductive strips on the same layer, the conductive strips are sequentially numbered from 1 according to any arrangement direction of the conductive strips, and the conductive strips with odd serial numbers form a circuit connection with each other. The even-numbered conductive strips form a circuit connection with each other;

Each row of columns is connected to a row circuit interface corresponding to the row, and each column of columns is connected to a column circuit interface corresponding to the column.