CN110610943A - High-density three-dimensional structure semiconductor memory and preparation method - Google Patents
High-density three-dimensional structure semiconductor memory and preparation method Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
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- 238000003860 storage Methods 0.000 claims abstract description 20
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- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 20
- 238000005520 cutting process Methods 0.000 claims description 12
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- 239000003989 dielectric material Substances 0.000 claims description 6
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
A high-density three-dimensional structure semiconductor memory and a preparation method relate to the semiconductor memory technology. The memory comprises a three-dimensional memory body and a selective MOS tube region; the three-dimensional memory bank includes: at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips in parallel; the vertical columns are arranged on the same layer and between two adjacent conductive strips, the axes of the vertical columns are perpendicular to the axes of the conductive strips, and the vertical columns have conductivity; a storage unit is arranged at the intersection of the upright post and the conductive strip; the MOS transistor is characterized in that the selected MOS transistor is of a layered planar structure, and the substrate, the doped region, the gate dielectric region and the gate region of the selected MOS transistor are all planar structures perpendicular to the axis of the upright column. The memory can be completely realized based on a standard MOS process, and has lower cost and higher yield.
Description
Technical Field
The present invention relates to semiconductor memory technology.
Background
Prior art 1 3D FALSH MEMORIES (ISBN 978-94-017-7510-6, ISBN 978-94-017-7512-0(eBook), DOI 10.1007/978-94-017-7512-0) discloses a three-dimensional memory, see FIG. 8.12, which adopts concentric cylinder structure as the main body of the selective MOS tube structure, the process is very complicated and the cost is high.
Chinese patent application 201810736865.2 discloses a semiconductor memory device having memory cells at the intersections of pillars and conductive strips, and particularly for pillars located between two conductive strips on the same layer, the same pillar intersects both conductive strips on the same layer, and there is a memory cell at each of the two intersections (located on both sides of the pillar).
Disclosure of Invention
The invention aims to solve the technical problem of providing a high-density three-dimensional structure semiconductor memory with low cost and a preparation method thereof.
The technical scheme adopted by the invention for solving the technical problems is that the high-density three-dimensional structure semiconductor memory comprises a three-dimensional memory body and a selective MOS tube region; the three-dimensional memory bank includes:
at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips in parallel;
the vertical columns are arranged on the same layer and between two adjacent conductive strips, the axes of the vertical columns are perpendicular to the axes of the conductive strips, and the vertical columns have conductivity;
a storage unit is arranged at the intersection of the upright post and the conductive strip;
the selective MOS tube is of a layered planar structure, and the substrate, the doped region, the gate dielectric region and the gate region of the selective MOS tube are planar structures perpendicular to the axis of the upright column.
The invention also provides a preparation method of the high-density three-dimensional structure semiconductor memory, which comprises the following steps:
A. the preparation method of the selective MOS tube region comprises the following steps: preparing and forming a row line, a column line and a selective MOS tube array by adopting a planar MOS tube preparation process, wherein a first connecting end of each selective MOS tube in the array is connected to a first array outgoing line, and a second connecting end of each selective MOS tube is connected to a second array outgoing line; the aforementioned first array lead-out line and second array lead-out line may be a row line and a column line, respectively.
The first connecting ends of the selected MOS tubes are all grid ends, the second connecting ends are all source ends, and the third connecting ends are all drain ends;
or the first connection ends of the selected MOS tubes are all grid ends, the second connection ends are all drain ends, and the third connection ends are all source ends;
B. the preparation method of the three-dimensional memory comprises the following steps: and C, preparing and forming a three-dimensional storage body with a stand column, wherein the stand column is electrically connected with the third connecting end of each MOS tube in the step A.
Further, the three-dimensional memory bank includes:
at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips in parallel;
the upright columns are arranged on the same layer and between two adjacent conductive strips, and the axes of the upright columns are perpendicular to the axes of the conductive strips;
a storage unit is arranged at the intersection of the upright post and the conductive strip, and comprises a first conductive type area, a second conductive type area and an insulating medium area arranged between the first conductive type area and the second conductive type area;
the upright post is provided with an upright post conductive area along the axial direction of the upright post, and the upright post conductive area is electrically connected with the first conductive type area of the storage unit;
the conductive strip is provided with a conductive material area along the axis of the conductive strip, and the conductive material area is electrically connected with the second conductive type area of the memory unit;
the first conductive type region and the second conductive type region are made of two semiconductor materials with different doping types;
or the first conductive type region and the second conductive type region are respectively made of two types of Schottky materials required for generating Schottky contact;
each conductive bar and each upright post are provided with circuit interfaces for connecting with an external circuit.
Regarding the schottky contact, an ohmic contact without diode characteristics is formed when the semiconductor doping concentration is high, and a contact with diode characteristics is formed when the doping concentration is low.
The step B comprises the following steps:
1) a step of forming a base structure: arranging a preset number of layers of conductive medium layers and insulating medium layers in a manner of overlapping the conductive medium layers and the insulating medium layers in a staggered manner to form a basic structure body;
2) a step of forming a interdigital structure on a base structure: the method comprises the following steps that a dividing structure penetrating through the top layer to the bottom layer of a basic structure body is arranged, the basic structure body is divided into two staggered finger structures, each finger structure comprises at least two finger strips and a public connecting strip, and each finger strip in the same finger structure is connected with the public connecting strip in the finger structure; the dividing structure comprises a cylindrical hole array and an isolation groove filled with an insulating material; the area between two adjacent finger strips is called an inter-finger area, and the cylindrical holes in the same inter-finger area are cylindrical holes in the same row;
3) a step of forming a pillar-shaped memory cell: according to a preset memory structure, arranging required middle layer dielectric materials on the inner wall of the cylindrical hole layer by layer, and finally filling a core dielectric material in the cylindrical hole to form a core dielectric material layer; the core medium material filled in the cylindrical hole forms the upright post.
Or, the step B includes:
1) forming a base structure: arranging a preset number of layers of conductive medium layers and insulating medium layers in a manner of overlapping the conductive medium layers and the insulating medium layers in a staggered manner to form a basic structure body;
2) grooving the base layer structure: at least 3 parallel strip-shaped grooves penetrating from the top layer to the bottom layer are formed in the basic structure body, the isolation grooves are mutually independent, and the adjacent edges of every two adjacent strip-shaped grooves are long edges of the strip-shaped grooves;
3) arranging storage medium layers required by a preset storage structure on the inner wall of the strip-shaped groove layer by layer;
4) filling a core medium in the cavity of the strip-shaped groove to form a core medium layer, namely the upright column in the step A;
5) the end area of the strip-shaped groove is provided with an isolation groove which penetrates from the top layer to the bottom layer, the strip-shaped grooves are connected end to end into a curve from the shape of the isolation groove, and the isolation groove is immersed into the strip-shaped groove so that the conductive media on the two sides of the strip-shaped groove in the long edge direction form insulation isolation; a cutting slotted hole penetrating from the top layer to the bottom layer is formed in the strip-shaped groove, the cutting slotted hole invades the basic structure body adjacent to the long edge of the strip-shaped groove, and the strip-shaped groove is divided into at least 3 independent storage bodies by the cutting slotted hole;
6) and filling insulating media in the isolation grooves and the cutting groove holes.
The invention has the advantages that the selective MOS tube can be realized by adopting the traditional planar process, the problem of high cost caused by a concentric cylinder structure in the prior art is avoided, the memory can be completely realized based on the standard MOS process, and the memory has lower cost and higher yield.
Drawings
Fig. 1 is a schematic view of a three-dimensional memory bank according to embodiment 1 of the present invention.
Fig. 2 is a schematic diagram of the structure of the selective MOS transistor of the prior art 1.
Fig. 3 is a schematic circuit connection diagram of the selective MOS transistor of the present invention.
Fig. 4 is a schematic structural view (top view) of a selected MOS transistor region according to the present invention.
Fig. 5 is a partially enlarged schematic view of fig. 4.
Fig. 6 is a schematic structural diagram of a selective MOS transistor.
Fig. 7 is a schematic cross-sectional view of a three-dimensional memory bank according to embodiment 2 of the present invention.
Detailed Description
The invention provides a preparation method of a high-density three-dimensional structure semiconductor memory, which comprises the following steps:
A. the preparation method of the selective MOS tube region comprises the following steps: preparing and forming a row line, a column line and a selective MOS tube array by adopting a planar MOS tube preparation process, wherein a first connecting end of each selective MOS tube in the array is connected to a first array outgoing line, and a second connecting end of each selective MOS tube is connected to a second array outgoing line; the aforementioned first array lead-out line and second array lead-out line may be a row line and a column line, respectively.
The first connecting ends of the selected MOS tubes are all grid ends, the second connecting ends are all source ends, and the third connecting ends are all drain ends;
or the first connection ends of the selected MOS tubes are all grid ends, the second connection ends are all drain ends, and the third connection ends are all source ends;
B. the preparation method of the three-dimensional memory comprises the following steps: and C, preparing and forming a three-dimensional storage body with a stand column, wherein the stand column is electrically connected with the third connecting end of each MOS tube in the step A.
Example 1
Fig. 1 is a schematic structural diagram of a semiconductor memory disclosed in chinese patent 201810736865.2, and the specific principle and structure thereof are shown in the patent application text, which is used as a three-dimensional memory in the present invention. The three-dimensional memory bank includes: at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips in parallel; the vertical columns are arranged on the same layer and between two adjacent conductive strips, the axes of the vertical columns are perpendicular to the axes of the conductive strips, and the vertical columns have conductivity; and a storage unit is arranged at the intersection of the upright post and the conductive strip.
Fig. 2 is a schematic diagram of a selective MOS structure of prior art 1, in which a drain region 60, a gate region 61 and a source region 62 are concentrically arranged in a cylinder, and the process is very complicated.
Fig. 3 shows the circuit connection relationship of the pillar connection points, and the hatched area of fig. 3 represents the pillar connection points, each of which is connected to one of the selection MOS transistors. The gate of each selection MOS transistor is connected to the column line (first array connection line), and the source is connected to the row line (second array connection line).
Fig. 1 to 3 are schematic diagrams only, and show a 3 × 3 pillar distribution form, which means that the number of pillars in the actual process is larger. Fig. 4 shows a column distribution of 8 × 4, and 42 in fig. 4 is a column connection point.
Referring to fig. 4 to 6, the invention is directed to a structure of a selection MOS transistor portion suitable for the three-dimensional memory, the selection MOS transistor portion of the invention is a layered planar structure, a gate connection line 41 is used as a first array connection line to connect gates of an entire array of MOS transistors, a metal line 43 is used as a second array connection line to connect drain regions of an entire row (when the structure shown in fig. 5 is adopted), and 44 is a conductive connection point of the drain region and the second array connection line. The source and drain regions are provided in the active region 45.
The structure of fig. 5 includes two MOS transistors, S denotes a source region, G denotes a gate region, and D denotes a drain region. Fig. 6 shows an alternative MOS transistor structure, in which the substrate 1, the source region 2, the drain region 3, the gate dielectric region 4 and the gate region 5 are all planar structures perpendicular to the conductive pillar.
The term "layered planar structure" used in the present invention means that the spatial structure is planar and layered, for example, the source region, the gate region, the drain region and the substrate shown in fig. 6 are in the form of flat plates (a plane with thickness, the plane being perpendicular to the axis of the pillar), and the cross section shown in fig. 6 is parallel to the axis of the pillar; the upper surface of the source region and the upper surface of the drain region are perpendicular to the axis of the pillar, which is easily accomplished by existing standard semiconductor process fabrication, as will be clearly understood by those of ordinary skill.
Example 2
Referring to fig. 7, the difference between the present embodiment and embodiment 1 is that the three-dimensional memory of the present embodiment adopts the three-dimensional programmable memory disclosed in chinese patent application 201811117240.4, "method for manufacturing a three-dimensional programmable memory", and the method for manufacturing the three-dimensional memory includes the following steps:
1) forming a base structure: arranging a preset number of layers of conductive medium layers and insulating medium layers in a manner of overlapping the conductive medium layers and the insulating medium layers in a staggered manner to form a basic structure body;
2) grooving the base layer structure: at least 3 parallel strip-shaped grooves penetrating from the top layer to the bottom layer are formed in the basic structure body, the isolation grooves are mutually independent, and the adjacent edges of every two adjacent strip-shaped grooves are long edges of the strip-shaped grooves;
3) arranging storage medium layers required by a preset storage structure on the inner wall of the strip-shaped groove layer by layer;
4) filling a core medium in the cavity of the strip-shaped groove to form a core medium layer 71, namely the upright column in the step A;
5) the end area of the strip-shaped groove is provided with an isolation groove which penetrates from the top layer to the bottom layer, the strip-shaped grooves are connected end to end into a curve from the shape of the isolation groove, and the isolation groove is immersed into the strip-shaped groove so that the conductive media on the two sides of the strip-shaped groove in the long edge direction form insulation isolation; a cutting slotted hole penetrating from the top layer to the bottom layer is formed in the strip-shaped groove, the cutting slotted hole invades the basic structure body adjacent to the long edge of the strip-shaped groove, and the strip-shaped groove is divided into at least 3 independent storage bodies by the cutting slotted hole;
6) and filling insulating media in the isolation grooves and the cutting groove holes.
Claims (5)
1. The high-density three-dimensional structure semiconductor memory comprises a three-dimensional memory body and a selective MOS tube region; the three-dimensional memory bank includes:
at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips in parallel;
the vertical columns are arranged on the same layer and between two adjacent conductive strips, the axes of the vertical columns are perpendicular to the axes of the conductive strips, and the vertical columns have conductivity;
a storage unit is arranged at the intersection of the upright post and the conductive strip;
the MOS transistor is characterized in that the selected MOS transistor is of a layered planar structure, and the substrate, the doped region, the gate dielectric region and the gate region of the selected MOS transistor are all planar structures perpendicular to the axis of the upright column.
2. The method for manufacturing a high-density three-dimensional structure semiconductor memory according to claim 1, comprising the steps of:
A. the preparation method of the selective MOS tube region comprises the following steps: preparing and forming a row line, a column line and a selective MOS tube array by adopting a planar MOS tube preparation process, wherein a first connecting end of each selective MOS tube in the array is connected to a first array outgoing line, and a second connecting end of each selective MOS tube is connected to a second array outgoing line;
the first connecting ends of the selected MOS tubes are all grid ends, the second connecting ends are all source ends, and the third connecting ends are all drain ends;
or the first connection ends of the selected MOS tubes are all grid ends, the second connection ends are all drain ends, and the third connection ends are all source ends;
B. the preparation method of the three-dimensional memory comprises the following steps: and C, preparing and forming a three-dimensional storage body with a stand column, wherein the stand column is electrically connected with the third connecting end of each MOS tube in the step A.
3. The method of manufacturing a high-density three-dimensional structure semiconductor memory according to claim 2, wherein the three-dimensional memory bank includes:
at least two conductive strip layers, each conductive strip layer comprising at least 3 conductive strips in parallel;
the upright columns are arranged on the same layer and between two adjacent conductive strips, and the axes of the upright columns are perpendicular to the axes of the conductive strips;
a storage unit is arranged at the intersection of the upright post and the conductive strip, and comprises a first conductive type area, a second conductive type area and an insulating medium area arranged between the first conductive type area and the second conductive type area;
the upright post is provided with an upright post conductive area along the axial direction of the upright post, and the upright post conductive area is electrically connected with the first conductive type area of the storage unit;
the conductive strip is provided with a conductive material area along the axis of the conductive strip, and the conductive material area is electrically connected with the second conductive type area of the memory unit;
the first conductive type region and the second conductive type region are made of two semiconductor materials with different doping types;
or the first conductive type region and the second conductive type region are respectively made of two types of Schottky materials required for generating Schottky contact;
each conductive bar and each upright post are provided with circuit interfaces for connecting with an external circuit.
4. The method for manufacturing a high-density three-dimensional structure semiconductor memory according to claim 2, wherein the step B includes:
1) a step of forming a base structure: arranging a preset number of layers of conductive medium layers and insulating medium layers in a manner of overlapping the conductive medium layers and the insulating medium layers in a staggered manner to form a basic structure body;
2) a step of forming a interdigital structure on a base structure: the method comprises the following steps that a dividing structure penetrating through the top layer to the bottom layer of a basic structure body is arranged, the basic structure body is divided into two staggered finger structures, each finger structure comprises at least two finger strips and a public connecting strip, and each finger strip in the same finger structure is connected with the public connecting strip in the finger structure; the dividing structure comprises a cylindrical hole array and an isolation groove filled with an insulating material; the area between two adjacent finger strips is called an inter-finger area, and the cylindrical holes in the same inter-finger area are cylindrical holes in the same row;
3) a step of forming a pillar-shaped memory cell: according to a preset memory structure, arranging required middle layer dielectric materials on the inner wall of the cylindrical hole layer by layer, and finally filling a core dielectric material in the cylindrical hole to form a core dielectric material layer; the core medium material filled in the cylindrical hole forms the upright post.
5. The method for manufacturing a high-density three-dimensional structure semiconductor memory according to claim 2, wherein the step B includes:
1) forming a base structure: arranging a preset number of layers of conductive medium layers and insulating medium layers in a manner of overlapping the conductive medium layers and the insulating medium layers in a staggered manner to form a basic structure body;
2) grooving the base layer structure: at least 3 parallel strip-shaped grooves penetrating from the top layer to the bottom layer are formed in the basic structure body, the isolation grooves are mutually independent, and the adjacent edges of every two adjacent strip-shaped grooves are long edges of the strip-shaped grooves;
3) arranging storage medium layers required by a preset storage structure on the inner wall of the strip-shaped groove layer by layer;
4) filling a core medium in the cavity of the strip-shaped groove to form a core medium layer, namely the upright column in the step A;
5) the end area of the strip-shaped groove is provided with an isolation groove which penetrates from the top layer to the bottom layer, the strip-shaped grooves are connected end to end into a curve from the shape of the isolation groove, and the isolation groove is immersed into the strip-shaped groove so that the conductive media on the two sides of the strip-shaped groove in the long edge direction form insulation isolation; a cutting slotted hole penetrating from the top layer to the bottom layer is formed in the strip-shaped groove, the cutting slotted hole invades the basic structure body adjacent to the long edge of the strip-shaped groove, and the strip-shaped groove is divided into at least 3 independent storage bodies by the cutting slotted hole;
6) and filling insulating media in the isolation grooves and the cutting groove holes.
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