Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F8/00—Arrangements for software engineering
  • G06F8/60—Software deployment
  • G06F8/61—Installation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/32—Circuit design at the digital level
  • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F9/5061—Partitioning or combining of resources
  • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2111/00—Details relating to CAD techniques
  • G06F2111/04—Constraint-based CAD
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F8/00—Arrangements for software engineering
  • G06F8/30—Creation or generation of source code
  • G06F8/34—Graphical or visual programming

Definitions

• each sub-schematic is compiled into binary code that is loaded and executed in the corresponding device.
• Fig. 12 is a block diagram of a graphical representation of a module in accordance with an embodiment of the present invention. This same graphical representation may be used for a module and instances of the module.
• the graphical representation (also referred to as a module symbol), is a rectangle block with square-shaped input and output pins positioned at the edges. In other embodiments, the graphical representation and the pins can be presented as other shapes.
• Fig. 13 is a block diagram of a schematic 130 in accordance with an embodiment of the present invention.
• This schematic 130 is a system schematic representing the distributed heterogeneous computing and control system 10.
• the schematic 130 includes multiple module symbols, each graphically representing an instance of a module.
• a second process 182 the computer node parses every virtual wire in the system schematic. In parsing the virtual wires, each virtual wire in the system schematic is examined. If the virtual wire connects two module instances with the same device property (i.e., the two modules instances are parsed into the same sub-schematic), in a third process 183, the computer node preserves the virtual wire at the location between the two module instances in the sub-schematic. If the virtual wire connects two module instances with different device properties (i.e., the two modules instances are parsed into separate sub-schematics), in a fourth process 184, the computer node adds a comm module instance to each of the separate sub-schematics.
• An embodiment of an addressing method in the present invention addresses a component of a schematic as a combination of: (i) a device ID, (ii) a path to the component, and (iii) name of the component.
• the device ID is set to the simulation virtual device ID of Designer.
• the device ID identifies a device in the distributed heterogeneous system associated with the sub-schematic.
• the path of the component is defined as the hierarchical path, such that the path defines a name of each module instance to be traversed in hierarchical order within the system schematic or sub-schematic to reach the given component.
• Fig. 19 illustrates a system schematic that contains a module instance, Module l.
• Fig. 21 is a block diagram of components 211, 212, 213, 214 of a comm module 210 in accordance with an embodiment of the present invention.
• the components 211, 212, 213, 214 are module instances that form a functional schematic of the comm module 210.
• the functional schematic enables communication and data flow over a network between two instances of the comm module 210 executed in different devices.
• the design software sets the receive address of the comm module instance 234 to“/device_A/*”, so that the comm module instance 234 receives any data packets with a destination address matching a component of the sub-schematic in“device A”, such as addresses
• control program locates such a sub- schematic, in a third process 273, the control program executes the sub-schematic. If the control program does not locate such a sub-schematic, in a fourth process 274, the control program takes no additional action. The control program then continues execution.
• the design software also adds comm module instances 303, 304, such as described in Fig. 18, to replace the virtual wires to which to the probe and the plot module instances 301, 302 are connected.
• the design software couples the probe module instance 301 to the added comm module instance 303 and couples the chart module instance to the added comm module instance 304.
• the source code may define and use various data structures and communication messages.
• the source code may be in a computer executable form (e.g., via an interpreter), or the source code may be converted (e.g., via a translator, assembler, or compiler) into a computer executable form.
• Hardware logic including programmable logic for use with a programmable logic device
• implementing all or part of the functionality previously described herein may be designed using traditional manual methods, or may be designed, captured, simulated, or documented electronically using various tools, such as Computer Aided Design (CAD), a hardware description language (e.g., VHDL or AHDL), or a PLD programming language (e.g., PALASM, ABEL, or CUPL).
• CAD Computer Aided Design
• a hardware description language e.g., VHDL or AHDL
• PLD programming language e.g., PALASM, ABEL, or CUPL

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Software Systems (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Evolutionary Computation (AREA)
• Geometry (AREA)
• Stored Programmes (AREA)
• Computer And Data Communications (AREA)

Priority Applications (3)

Applications Claiming Priority (4)

Publications (1)

Family

ID=67003688

Family Applications (1)

Country Status (5)

Cited By (1)

Families Citing this family (13)

Citations (1)

Family Cites Families (43)

• 2019
  • 2019-06-05 US US16/431,966 patent/US10685155B2/en active Active
  • 2019-06-05 EP EP19733279.4A patent/EP3803569A1/en active Pending
  • 2019-06-05 JP JP2020567518A patent/JP7381502B2/ja active Active
  • 2019-06-05 CN CN201980037005.2A patent/CN112292664B/zh active Active
  • 2019-06-05 WO PCT/US2019/035502 patent/WO2019236657A1/en not_active Ceased

Patent Citations (1)

Also Published As

Similar Documents

Legal Events