WO2019229791A1 - Inverter device and inverter system - Google Patents

Abstract

An inverter device (3x) comprises: a voltage detection unit (33x) that detects a direct-current voltage between DC busbars (2x) and outputs a detected voltage (Vdcx); a regeneration circuit (34x) that has a series circuit of a resistor (341x) and a switching element (342x) connected between the DC busbars (2x), and that processes regenerative power from a power conversion unit (31x); and a regeneration control unit (35x). The regeneration control unit (35x) controls the switching element (342x) on the basis of a comparison between the detected voltage (Vdcx), and a set start voltage (Von) and stop voltage (Voff), and when the switching element (342x) is in an off state, the regeneration control unit detects a voltage drop in the detected voltage (Vdcx) by a set determination voltage (Vmin) or more, and controls the switching element (342x).

Description

Inverter device and inverter system

The present application relates to an inverter device that converts DC power into AC power, and an inverter system that includes a plurality of inverter devices, and particularly relates to regenerative power processing.

In an inverter system configured by connecting a plurality of inverter devices in parallel, in order to process regenerative power supplied from a load such as a motor, each inverter device has a regenerative circuit having a resistor, Conventional techniques for consuming with resistors are known.
In the technique described in Patent Document 1, a regenerative circuit is configured by a series circuit of a resistor and a switching element, and the on-voltage level of the switching element in the regenerative circuit is independent depending on the regenerative operation state of the inverter device. To make it variable. Thereby, the power consumption of the regenerative circuit of each inverter device can be equalized with a simple system configuration without requiring information exchange between the inverter devices or between the host system and the inverter device.

JP 2010-110139 A

In the conventional method described above, the inverter device responsible for processing regenerative power is sequentially changed by changing the on-voltage level. However, among the plurality of inverter devices, only the inverter device having the lowest on-voltage level processes the regenerative power, so that the total regenerative power is limited. In addition, the load on the regenerative circuit of each inverter device tends to be excessive, and there is a problem that the regenerative circuit is deteriorated.

The present application discloses a technique for solving the above-described problems, and is an inverter device that can prevent deterioration of the regenerative circuit by preventing the load of the regenerative circuit from becoming excessive, and other inverters An object of the present invention is to provide an inverter device that can increase the total regenerative power when the device is operated in parallel with the device.

In addition, in an inverter system in which a plurality of inverter devices are operated in parallel, the load of the regenerative circuit of each inverter device can be prevented from being excessively suppressed, deterioration of the regenerative circuit can be suppressed, and regenerative power can be increased. To do.

An inverter device disclosed in the present application includes a power converter that converts DC power from a DC bus into AC power and supplies power to a load, a smoothing capacitor connected between the DC buses, and a DC between the DC buses. A voltage detection unit for detecting a voltage, a series circuit of a resistor and a switching element connected between the DC buses, a regenerative circuit for processing regenerative power from the power conversion unit, and the regenerative circuit And a regeneration control unit that controls the switching element. The regeneration control unit includes a first control unit and a second control unit. The first control unit controls the switching element based on a comparison between a detection voltage from the voltage detection unit and a preset start voltage and stop voltage. The second control unit controls the switching element by detecting a voltage drop of the detection voltage at a predetermined determination voltage or higher when the switching element is in an OFF state.

The inverter system disclosed in the present application includes a plurality of the inverter devices, and the DC buses of the plurality of inverter devices are connected in parallel.

According to the inverter device disclosed in the present application, it is possible to prevent the load of the regenerative circuit from becoming excessive, and to suppress deterioration of the regenerative circuit. In parallel operation with other inverter devices, the total regenerative power can be increased and continuous operation can be performed with good reliability.

In addition, according to the inverter system disclosed in the present application, the load on the regenerative circuit of each inverter device can be prevented from being excessively suppressed to suppress deterioration of the regenerative circuit, and continuous operation can be performed with good reliability. The regenerative power can be increased.

It is a figure which shows schematic structure of the inverter system by Embodiment 1. FIG. It is a figure explaining the regeneration control part of the inverter apparatus by Embodiment 1. FIG. It is a figure explaining the starting voltage and stop voltage in each inverter apparatus by Embodiment 1. FIG. It is a figure which shows the start voltage, stop voltage, and determination voltage in each inverter apparatus by Embodiment 1. FIG. 4 is a flowchart illustrating an operation of a regeneration control unit of the inverter device according to the first embodiment. It is a figure explaining the regenerative electric power process of each inverter apparatus by Embodiment 1. FIG. 6 is a block diagram illustrating a configuration of a regeneration control unit according to Embodiment 2. FIG. FIG. 10 is a diagram illustrating a configuration of a first control unit of a regeneration control unit according to Embodiment 2. It is a figure which shows the structure of the 2nd control part of the regeneration control part by Embodiment 2. FIG. FIG. 10 is a wave diagram of each part for explaining the operation of the regeneration control unit according to the second embodiment.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a schematic configuration of an inverter system according to the first embodiment.
As shown in FIG. 1, the inverter system 100 includes three inverter devices 3x, 3y, and 3z connected in parallel on the DC side, and each inverter device 3x, 3y, and 3z receives DC power from the DC power supply 1. This is a system that converts AC power and drives the motors 4x, 4y, and 4z, which are the respective loads. The DC buses 2x, 2y, and 2z of the inverter devices 3x, 3y, and 3z are connected in parallel on the DC power source 1 side of the inverter devices 3x, 3y, and 3z and connected to the DC power source 1.
The inverter system 100 may include the DC power supply 1 and the motors 4x, 4y, and 4z, or one or both of the DC power supply 1 and the motors 4x, 4y, and 4z may be provided outside the inverter system 100. .

The motors 4x, 4y, and 4z are three-phase motors. For example, three servo motors that perform three-axis operations of the x-axis, y-axis, and z-axis are used.
Motors 4x, 4y, and 4z are not limited to three-phase motors. Further, the number of the motors 4x, 4y, 4z and the number of the inverter devices 3x, 3y, 3z may be a plurality other than 3, and the inverter devices 3x, 3y, 3z that drive the motors 4x, 4y, 4z are provided. Any device connected in parallel on the DC side may be used.

The inverter devices 3x, 3y, and 3z include DC buses 2x, 2y, and 2z, power conversion units 31x, 31y, and 31z, smoothing capacitors 32x, 32y, and 32z, and voltage detection units 33x, 33y, and 33z. Furthermore, the inverter devices 3x, 3y, and 3z include regenerative circuits 34x, 34y, and 34z that process regenerative power, and regenerative control units 35x, 35y, and 35z that control the regenerative circuits 34x, 34y, and 34z. The regenerative circuits 34x, 34y, 34z include a series circuit of resistors 341x, 341y, 341z and switching elements 342x, 342y, 342z.
Note that Cx *, Cy *, and Cz * are the command values of the inverter devices 3x, 3y, and 3z given to the power converters 31x, 31y, and 31z from the outside, and Vdcx, Vdcy, and Vdcz are the voltage detectors 33x, The detection voltages Imx, Imy, and Imz from 33y and 33z are state information of the motors 4x, 4y, and 4z.

The command values Cx *, Cy *, Cz * are, for example, a desired rotation speed, a desired torque, or a desired movement distance (rotation angle) including time change information of the motors 4x, 4y, 4z. Each motor 4x, motor 4y, and motor 4z is, for example, an x-axis, y-axis, or z-axis operation motor of a stacker device, or a robot root operation motor, a joint operation motor, or a wrist operation motor. The desired movement is different. Therefore, the command values Cx *, Cy *, Cz * of the inverter devices 3x, 3y, 3z are generally different from each other.

The state information Imx, Imy, Imz is position information about the axes of the motors 4x, 4y, 4z. This is obtained from a rotation position information detection circuit such as a resolver or encoder attached to the motors 4x, 4y, and 4z.
Each command value Cx *, Cy *, Cz * is different, or each motor 4x, 4y, 4z has a different frictional force, so that the state information Imx, Imy, Imz of each motor 4x, 4y, 4z is also different. It is common.

The detection voltages Vdcx, Vdcy, and Vdcz are obtained by detecting the DC voltage Vdc between the DC buses 2x, 2y, and 2z by the voltage detection units 33x, 33y, and 33z. Each of the voltage detectors 33x, 33y, 33z includes, for example, a resistor having a high resistance value R1 (hereinafter, resistor R1) and a resistor having a low resistance value R2 (hereinafter, resistors) between the DC buses 2x, 2y, and 2z. And a circuit in which R2) is connected in series. Then, after analog / digital (A / D) conversion is performed on the voltage value across the resistor R2, it is multiplied by {(R1 + R2) / R2} to obtain detection voltages Vdcx, Vdcy, and Vdcz.
Since the DC buses 2x, 2y, and 2z are connected in parallel, the actual DC voltage Vdc between the DC buses 2x, 2y, and 2z is common. However, the detection voltages Vdcx, Vdcy, and Vdcz individually include detection errors due to element variations such as resistors R1 and R2 and A / D converters of the voltage detection units 33x, 33y, and 33z. There is no guarantee that they will be identical.

Hereinafter, the inverter device 3x will be described in detail. Since the inverter devices 3y and 3z are the same as the inverter device 3x, detailed description thereof is omitted.
A smoothing capacitor 32x is connected between the DC buses 2x, and the smoothing capacitor 32x equalizes the voltage of DC power and temporarily stores regenerative power.
The voltage detector 33x detects the voltage Vdc between the DC buses 2x, that is, the voltage of the smoothing capacitor 32x, and outputs a detection voltage Vdcx.

The power conversion unit 31x includes a main circuit having a switching element and a control circuit. Then, based on the command value Cx *, the state information Imx, and the detection voltage Vdcx, the DC power from the DC bus 2x is converted into AC power having an arbitrary amplitude and frequency, and the motor 4x is supplied with electric power. Drive.
Further, when the motor 4x decelerates or stops, the power conversion unit 31x supplies regenerative power generated by the motor 4x functioning as a generator to the DC bus 2x. That is, when the motor 4x generates regenerative power, the regenerative power is supplied to the DC bus 2x via the power converter 31x.

Since the DC buses 2x, 2y, and 2z of the three inverter devices 3x, 3y, and 3z are connected in parallel, the regenerative power from the power conversion unit 31x is not only the smoothing capacitor 32x in the inverter device 3x but also the inverter device 3y. The smoothing capacitor 32y and the smoothing capacitor 32z in the inverter device 3z are also charged.

The regenerative circuit 34x is configured by a series circuit in which a resistor 341x and a switching element 342x are connected in series between the DC bus 2x. The switching element 342x in the regenerative circuit 34x is controlled to be turned on / off, that is, in a conductive state or a cut-off state by a control signal SWx that is an output of the regenerative control unit 35x.
In this case, the case where the control signal SWx turns on the switching element 342x is referred to as “1” level as the state of the control signal SWx. The case where the control signal SWx turns off the switching element 342x is referred to as “0” level as the state of the control signal SWx.

When the control signal SWx is at the “1” level, in the regenerative circuit 34x, the switching element 342x is turned on, and the regenerative power stored in the smoothing capacitor 32x is consumed and processed by the resistor 341x.
Since the DC buses 2x, 2y, and 2z of the three inverter devices 3x, 3y, and 3z are connected in parallel, when the switching element 342x in the regenerative circuit 34x of the inverter device 3x is turned on, only the smoothing capacitor 32x in the inverter device 3x. Instead, all the electric power stored in the smoothing capacitors 32x, 32y, 32z in the three inverter devices 3x, 3y, 3z is consumed by the resistor 341x of the regenerative circuit 34x.

The regeneration control unit 35x outputs a control signal SWx to the regeneration circuit 34x based on the detected voltage Vdcx from the voltage detection unit 33x.
In this embodiment, as shown in FIG. 2, the regeneration control unit 35x is configured to include a processor (microprocessor) 5 that performs arithmetic processing using software. The processor 5 outputs a read command to the storage circuit 6 and reads necessary information (no load voltage Vdc0, start voltage Von, stop voltage Voff, determination voltage Vmin, compensation voltage δ) from the storage circuit 6. These necessary information will be described later. Then, the processor 5 calculates and outputs the control signal SWx.
In addition, although the case where the storage circuit 6 using a register or a memory is installed outside the processor 5 is illustrated, the internal storage unit of the processor 5 may be used as the storage circuit.

The no-load voltage Vdc0, the start voltage Von, the stop voltage Voff, the determination voltage Vmin, and the compensation voltage δ are values that are preset and stored, and are the same values with no difference between the three inverter devices 3x, 3y, and 3z. .
It is assumed that the DC power source 1 performs full-wave rectification on commercial AC power having an effective value of 200 V and supplies power to the DC buses 2x, 2y, and 2z. When all the motors 4x, 4y, and 4z are stopped, that is, the no-load voltage Vdc0 that is the DC voltage Vdc at no load is about 283V.

The start voltage Von is a voltage set in advance to start the regenerative power process, and the stop voltage Voff is a voltage set in advance to stop the regenerative power process. When the detection voltage Vdcx rises above the start voltage Von, the regenerative control unit 35x sets the control signal SWx to “1” level and starts regenerative power processing. When the detection voltage Vdcx drops and reaches the stop voltage Voff by the regenerative power process, the regenerative control unit 35x changes the control signal SWx to “0” level and stops the regenerative power process.

Furthermore, when the regenerative control unit 35x detects that the detection voltage Vdcx has dropped when the control signal SWx is at “0” level, the regenerative power processing is performed by setting the control signal SWx to “1” level. Start. Then, the regeneration control unit 35x generates the second stop voltage Vspx using the compensation voltage δ, and when the detection voltage Vdcx drops and reaches the second stop voltage Vspx by the regenerative power process, the control signal SWx is set to the “0” level. To stop the regenerative power processing.
Here, the start voltage Von is 380V, the stop voltage Voff is 350V, and the determination voltage Vmin is 365V.

It is assumed that the detection error due to the element variation of the voltage detection unit 33x is 2% or less. Hereinafter, with respect to the voltage value of the detection voltage Vdcx, the voltage value of the actual voltage is described with a unit of VR.
The voltage detection unit 33x may determine that the detection voltage Vdcx has reached the start voltage Von (= 380 V) when the DC voltage Vdc is in the range from 373 VR to 388 VR. Similarly, there is a possibility that the voltage detection unit 33x determines that the detection voltage Vdcx becomes the stop voltage Voff (= 350V) when the DC voltage Vdc is in the range from 343VR to 357VR.

The actual voltages when the detection voltages Vdcx, Vdcy, and Vdcz from the voltage detection units 33x, 33y, and 33z of the inverter devices 3x, 3y, and 3z coincide with the start voltage Von (= 380 V) are defined as Vonx, Vony, and Vonz. Further, actual voltages when the detection voltages Vdcx, Vdcy, Vdcz coincide with the stop voltage Voff (= 350 V) are Voffx, Voffy, Voffz. That is, Vonx is an actual voltage when Vdcx = Von, and Voffx is an actual voltage when Vdcx = Voff.
As shown in FIG. 3, the maximum possible voltage of each Vonx, Vony, and Vonz is 388 VR, and the minimum possible voltage is 373 VR. In addition, the maximum possible voltage of each Voffx, Voffy, and Voffz is 357 VR, and the minimum possible voltage is 343 VR.

The determination voltage Vmin is set between the start voltage Von and the stop voltage Voff. However, since the actual voltage corresponding to the start voltage Von and the stop voltage Voff is between the minimum possible voltage and the maximum possible voltage as described above, it corresponds to the minimum possible voltage corresponding to the start voltage Von and the stop voltage Voff. The determination voltage Vmin is set between the maximum possible voltage.
Here, the determination voltage Vmin is taken as an example of a median value of 365 V between the start voltage Von and the stop voltage Voff, and the minimum possible voltage (= 373 VR) corresponding to the start voltage Von and the maximum possible corresponding to the stop voltage Voff. Voltage (= 357 VR).

The actual voltages when the detection voltages Vdcx, Vdcy, Vdcz coincide with the determination voltage Vmin (= 365 V) are defined as Vminx, Vminy, Vminz. The maximum possible voltage of each Vminx, Vminy, and Vminz is 372 VR, and the minimum possible voltage is 358 VR.
In this embodiment, the start voltage Von (= 380 V), the stop voltage Voff (= 350 V), and the determination voltage Vmin (= 365 V) set in the regeneration control units 35 x, 35 y, and 35 z of the inverter devices 3 x, 3 y, and 3 z. Let the actual voltage corresponding to the values shown in FIG.

Next, operation | movement of the regeneration control part 35x is demonstrated below based on the flowchart shown in FIG.
First, when the inverter system 100 starts to operate, the control signal SWx is initialized to “0” level (step S01).
Next, it is determined whether or not the inverter system 100 is in the operation end process (step S02). If the inverter system 100 is in the operation end process, the operation of the regeneration control unit 35x is also ended.
If the inverter system 100 is not in the operation end process in step S02, it is determined whether or not the detected voltage Vdcx is equal to or higher than the no-load voltage Vdc0 (step S10), and if the detected voltage Vdcx is less than the no-load voltage Vdc0. Return to step S02. This is a function that does not operate the regeneration control unit 35x in a state where regenerative power is not generated in the entire inverter system 100.

In step S10, if the detection voltage Vdcx is equal to or higher than the no-load voltage Vdc0, it is determined whether or not the detection voltage Vdcx is equal to or higher than the start voltage Von (step S11), and if the detection voltage Vdcx is equal to or higher than the start voltage Von. The control signal SWx is set to “1” level (step S12).
Next, it is determined whether or not the detection voltage Vdcx is equal to or lower than the stop voltage Voff (step S13). When the detection voltage Vdcx is higher than the stop voltage Voff, the process returns to step S12, and the control signal SWx is maintained at the “1” level.
If the detection voltage Vdcx is equal to or lower than the stop voltage Voff in step S13, the control signal SWx is changed to “0” level (step S14), and the process returns to step S02. If regenerative power is continuously generated, the processing from step S10 is resumed.

In step S11, if the detection voltage Vdcx is less than the start voltage Von, it is determined whether or not the detection voltage Vdcx is greater than or equal to the determination voltage Vmin (step S20). If the detection voltage Vdcx is less than the determination voltage Vmin, step is performed. Return to S02.
In step S20, if the detection voltage Vdcx is equal to or higher than the determination voltage Vmin, it is determined whether or not the detection voltage Vdcx has continuously dropped. Here, it is determined whether or not the detection voltage Vdcx has dropped for three periods continuously in the system clock (step S21).

The processing in step S21 can be realized, for example, by temporarily storing the data of the detection voltage Vdcx for three cycles with the system clock and sequentially comparing the data for determination. Here, detecting the voltage drop continuously for three cycles is to prevent malfunction due to noise of the detection voltage Vdcx, and is not limited to three cycles. If the influence of the noise of the detection voltage Vdcx is small, the time width for continuously detecting the voltage drop can be reduced. On the contrary, if the influence of the noise of the detection voltage Vdcx is large, it is necessary to increase the time width for continuously detecting the voltage drop.

If there is no continuous voltage drop in the detected voltage Vdcx in step S21, the process returns to step S02.
In step S21, when it is detected that the detection voltage Vdcx has continuously dropped, the detection voltage Vdcx at that time is stored as the second start voltage Vstx. Further, the second stop voltage Vspx is generated and stored by the following equation (1) (step S22).
Vspx = Vstx− (Von−Voff) + δ (1)
When the minimum possible voltage corresponding to the start voltage Von is represented by Vonmin and the maximum possible voltage corresponding to the stop voltage Voff is represented by Voffmax, the compensation voltage δ is set so as to satisfy the following expression (2).
Vonmin ≧ Vonmin− (Von−Voff) + δ ≧ Voffmax (2)
That is, 30 ≧ δ ≧ 14
Here, the compensation voltage δ is 20V.

Next, the control signal SWx is set to “1” level (step S23).
Next, it is determined whether or not the detection voltage Vdcx is equal to or lower than the second stop voltage Vspx (step S24). When the detection voltage Vdcx is higher than the second stop voltage Vspx, the process returns to step S23, and the control signal SWx is maintained at the “1” level.
If the detection voltage Vdcx is equal to or lower than the second stop voltage Vspx in step S24, the control signal SWx is changed to “0” level (step S25), and the process returns to step S02. If regenerative power is continuously generated, the processing from step S10 is resumed.

As described above, the regeneration control unit 35x controls the regeneration circuit 34x by the processing of Step S01 to Step S25. The control related to steps S10 to S14 is a first control unit, and the control related to steps S20 to S25 is a second control unit.
The first control unit controls the regeneration circuit 34x based on a comparison between the detection voltage Vdcx, the start voltage Von, and the stop voltage Voff. That is, when the detection voltage Vdcx rises above the start voltage Von, the regenerative power process is started. When the detection voltage Vdcx drops and reaches the stop voltage Voff, the regenerative power process is stopped.

In the second control unit, by detecting that the regenerative circuit 34y of another inverter device, for example, the inverter device 3y is performing regenerative power processing, in step S21, detecting that the detection voltage Vdcx has continuously dropped. Detect. Further, by detecting this continuous voltage drop in the region of the determination voltage Vmin or higher, it is ensured that the continuous voltage drop is caused by the regenerative power process of the other inverter device 3y.
And the 2nd control part starts regenerative electric power processing so that other regenerative circuit 34y may track also in its regenerative circuit 34x. Further, the second stop voltage Vspx is generated to be equal to or higher than the maximum possible voltage corresponding to the stop voltage Voff, and when the detection voltage Vdcx drops and reaches the second stop voltage Vspx, the regenerative power process is stopped.

Next, the aspect of the regenerative power process of the three inverter devices 3x, 3y, and 3z will be described with reference to FIG. Note that variations in the detection voltages Vdcx, Vdcy, Vdcz by the voltage detection units 33x, 33y, 33z of the inverter devices 3x, 3y, 3z are based on the voltage values shown in FIG.
Among the three inverter devices 3x, 3y, and 3z, the lowest actual voltages Vonx, Vony, and Vonz when the detection voltages Vdcx, Vdcy, and Vdcz coincide with the start voltage Von (= 380 V) = 373VR).

When the DC voltage Vdc, which is the actual voltage, rises to Vonx (= 373 VR) or higher, the detection voltage Vdcx of the inverter device 3 x becomes higher than the start voltage Von (= 380 V), and the regenerative control unit 35 x performs switching elements of the regenerative circuit 34 x. 342x is turned on to start regenerative power processing. Thereafter, when the DC voltage Vdc drops to Voffx (= 357 VR) or lower, the detection voltage Vdcx drops to lower than the stop voltage Voff (= 350 V), and the regenerative control unit 35x switches the switching element 342x of the regenerative circuit 34x. The regenerative power process is stopped by turning it off (see steps S11 to S14).

When the regenerative power process is started in the inverter device 3x at the DC voltage Vdc = Vonx (= 373VR), the DC voltage Vdc drops, so that the detection voltages Vdcy and Vdcz of the inverter devices 3y and 3z also drop.

In the inverter device 3y, the DC voltage Vdc drops before reaching Vony (= 380VR) in a region equal to or higher than Vminy (= 365VR) corresponding to the determination voltage Vmin, and the regeneration control unit 35y causes the detection voltage Vdcy to continue. Detect voltage drop. Then, the second stop voltage Vspy (= 363 V) is generated with the detection voltage Vdcy as the second start voltage Vsty (= 373 V). In this case, the voltage drop is small, and the actual voltage (= 373VR) of the second start voltage Vsty is described as the same voltage as Vonx. The regenerative control unit 35y turns on the switching element 342y of the regenerative circuit 34y and starts regenerative power processing. Thereafter, when the detection voltage Vdcy drops and becomes equal to or lower than the second stop voltage Vspy (= 363 V), the regenerative control unit 35y turns off the switching element 342y of the regenerative circuit 34y and stops the regenerative power process (steps S20 to S25). reference).

Similarly, in the inverter device 3z, the DC voltage Vdc drops before reaching Vonz (= 387VR) in a region equal to or higher than Vminz (= 372VR) corresponding to the determination voltage Vmin, and the regeneration control unit 35z receives the detection voltage Vdcz. The continuous voltage drop is detected. Then, the second stop voltage Vspz (= 356 V) is generated with the detection voltage Vdcz as the second start voltage Vstz (= 366 V). Also in this case, the voltage drop is small, and the actual voltage (= 373VR) of the second start voltage Vstz is described as the same voltage as Vonx. Subsequently, the regenerative control unit 35z turns on the switching element 342z of the regenerative circuit 34z and starts regenerative power processing. Thereafter, when the detection voltage Vdcz drops and becomes equal to or lower than the second stop voltage Vspz (= 356 V), the regenerative control unit 35z turns off the switching element 342z of the regenerative circuit 34z and stops the regenerative power process (steps S20 to S25). reference).

The time when the regenerative control unit 35x of the inverter device 3x starts the regenerative power process is earlier than the time when the regenerative control units 35y and 35z of the inverter devices 3y and 3z start the regenerative power process. Moreover, the time when the regenerative control unit 35x of the inverter device 3x stops the regenerative power process is later than the time when the regenerative control units 35y and 35z of the inverter devices 3y and 3z stop the regenerative power process.
In the inverter devices 3y and 3z, the regeneration controllers 35y and 35z perform the process of step S25, and then proceed to step S02 → step S10 → step S11 → step S20 → step S02. This loop continues until the regeneration control unit 35x of the inverter device 3x finishes the process of step S14.

When regenerative power is generated at the time when the regeneration control unit 35x of the inverter device 3x finishes the process of step S14, the regeneration control units 35x, 35y, and 35z of the inverter devices 3x, 3y, and 3z are both step S02. → Restart the process of step S10 → step S11. On the other hand, when regenerative power is not generated at the time when the regeneration control unit 35x of the inverter device 3x finishes the process of step S14, the loop of step S02 → step S10 → step S02 is circulated.

As described above, in the inverter device 3x according to this embodiment, the first control unit of the regeneration control unit 35x performs the detection voltage Vdcx from the voltage detection unit 33x and the preset start voltage Von and stop voltage Voff. Based on the comparison, the switching element 342x of the regenerative circuit 34x is controlled. Then, the second control unit of the regeneration control unit 35x controls the switching element 342x by detecting a voltage drop of the detection voltage Vdcx at a predetermined determination voltage Vmin or higher when the switching element 342x is in the OFF state.
For this reason, the inverter device 3x detects the regenerative power processing by the other inverter device 3y (3z) connected in parallel by detecting that the detection voltage Vdcx has continuously dropped, and the other inverter device 3y. The regenerative power process can be started so as to follow (3z). Thereby, it can prevent that the load of the regeneration circuit 34x becomes heavy, and can suppress degradation of the regeneration circuit 34x. Moreover, when performing parallel operation with the other inverter devices 3y and 3z, the entire regenerative power can be increased.

In the inverter system 100 in which a plurality of inverter devices 3x, 3y, and 3z are operated in parallel, it is possible to prevent only one inverter device 3x (3y and 3z) from performing regenerative power processing. When a large amount of regenerative power is generated, it is not processed only by the resistor 341x of the regenerative circuit 34x of the inverter device 3x that has started the regenerative power processing first, but the regenerative circuits 34x, 34y of all the inverter devices 3x, 3y, 3z. 34z can perform regenerative power processing. For this reason, the effect shown below is acquired.

Since the regenerative power is consumed simultaneously by the plurality of regenerative circuits 34x, 34y, 34z, the bias of the processing time of each regenerative circuit 34x, 34y, 34z is reduced, and the regenerative circuits 34x, 34y, 34z, especially resistors 341x, 341y. , 341z can be extended in life.
Further, since the regenerative power is consumed by the plurality of regenerative circuits 34x, 34y, 34z at the same time, the total regenerative power increases, and the ratings of the resistors 341x, 341y, 341z in the regenerative circuits 34x, 34y, 34z are increased. The possibility of exceeding power consumption is reduced. For this reason, the operation stop frequency of each inverter apparatus 3x, 3y, 3z can be reduced, and the reliability of inverter apparatus 3x, 3y, 3z and the inverter system 100 improves.

Furthermore, in this embodiment, since the regeneration control unit 35x is configured using the processor 5, the number of parts of the regeneration control unit 35x is small, and a small and inexpensive inverter device 3x can be realized, and the failure frequency is reduced. , Improve reliability.
Note that the processor 5 of the regeneration control unit 35x can be shared with the microprocessor in the control circuit of the power conversion unit 31x, so that cost reduction, downsizing, and failure frequency can be reduced.

Note that δa (= (Von−Voff) −δ) may be used instead of δ as the compensation voltage used in the above embodiment. In this case, the second stop voltage Vspx is calculated by Vstx−δa. The compensation voltage δa is set so as to satisfy the following expression.
Vonmin ≧ Vonmin−δa ≧ Voffmax
That is, 16 ≧ δa ≧ 0
In this case, assuming that δa = 10V, the same operation as in the above embodiment in which δ = 20V is obtained.

Embodiment 2. FIG.
Next, an inverter device and an inverter system according to Embodiment 2 will be described. In the first embodiment, the regeneration control unit 35x in the inverter device 3x is configured to include the processor 5. However, in the second embodiment, an operational amplifier, a comparator, a logic circuit, a storage element, a register, a flip-flop, and the like The regeneration control unit 35x is configured by a circuit that operates by hardware. Except for the configuration of the regeneration control unit 35x, the configuration is the same as that of the first embodiment.
Also in this case, the inverter system is configured by connecting the three inverter devices 3x, 3y, and 3z in parallel. Hereinafter, the regeneration control unit 35x in the inverter device 3x will be described in detail. Since it is the same also about the other regeneration control parts 35y and 35z, detailed description is abbreviate | omitted.

Similar to the first embodiment, the regeneration control unit 35x outputs the control signal SWx to the regeneration circuit 34x based on the detection voltage Vdcx from the voltage detection unit 33x. Also in this case, the no-load voltage Vdc0, the start voltage Von, the stop voltage Voff, the determination voltage Vmin, and the compensation voltage δ are preset and stored, and are set to the same voltage values as in the first embodiment.
Further, when the detection voltage Vdcx rises above the start voltage Von, the regenerative control unit 35x sets the control signal SWx to the “1” level and starts regenerative power processing. When the detection voltage Vdcx drops and reaches the stop voltage Voff by the regenerative power process, the regenerative control unit 35x changes the control signal SWx to “0” level and stops the regenerative power process.

Furthermore, when the regenerative control unit 35x detects that the detection voltage Vdcx has dropped when the control signal SWx is at “0” level, the regenerative power processing is performed by setting the control signal SWx to “1” level. Start. Then, the regeneration control unit 35x generates the second stop voltage Vspx using the compensation voltage δ, and when the detection voltage Vdcx drops and reaches the second stop voltage Vspx by the regenerative power process, the control signal SWx is set to the “0” level. To stop the regenerative power processing.

FIG. 7 is a block diagram showing a configuration of the regeneration control unit 35x according to the second embodiment.
Note that the system clock for managing the operation time and the power supply circuit of each hardware are omitted.
As shown in FIG. 7, the regeneration control unit 35x includes a first control unit 36x, a second control unit 37x, and a combining unit 38x.
The first control unit 36x receives the detection voltage Vdcx from the voltage detection unit 33x, and outputs a signal SW1x and a regenerative voltage width Vd. The second control unit 37x receives the detection voltage Vdcx from the voltage detection unit 33x, the signal SW1x and the regenerative voltage width Vd from the first control unit 36x, and outputs a signal SW2x.

The synthesizing unit 38x receives the signal SW1x from the first control unit 36x and the signal SW2x from the second control unit 37x, and outputs a control signal SWx that is a logical sum of these signals. That is, SWx = SW1x + SW2x.

FIG. 8 is a diagram illustrating a configuration of the first control unit 36x of the regeneration control unit 35x according to the second embodiment. As shown in FIG. 8, the first control unit 36x includes a first storage circuit 361, a second storage circuit 362, comparators 363 and 364, a state determination circuit 365, and a subtractor 366.
The first and second memory circuits 361 and 362 are constituted by, for example, a register or a semiconductor memory. The first memory circuit 361 stores the start voltage Von, and the second memory circuit 362 stores the stop voltage Voff.

The comparators 363 and 364 are composed of, for example, operational amplifiers and comparators. The comparator 363 compares the detection voltage Vdcx with the start voltage Von output from the first memory circuit 361. When Vdcx ≧ Von, the signal F1x is set to “1” level, and when Vdcx <Von, the signal F1x Is set to “0” level and output. The comparator 364 compares the detection voltage Vdcx with the stop voltage Voff output from the second memory circuit 362, sets the signal F2x to “1” level when Vdcx ≦ Voff, and sets the signal F2x when Vdcx> Voff. Is set to “0” level and output.

The state determination circuit 365 is configured by, for example, a set-reset type flip-flop (RS-FF), inputs the signal F1x to the S terminal, inputs the signal F2x to the R terminal, and outputs the signal SW1x. The signal SW1x output from the state determination circuit 365 becomes “1” level when the signal F1x changes from “0” level to “1” level, and the time when the signal F2x changes from “0” level to “1” level. The level becomes “0” and continues at other times without changing the level of the signal SW1x.
That is, the signal SW1x becomes “1” level when the detection voltage Vdcx becomes equal to or higher than the start voltage Von, and then changes to “0” level when the detection voltage Vdcx drops and becomes equal to or lower than the stop voltage Voff.

The subtractor 366 outputs a value obtained by subtracting the stop voltage Voff output from the second storage circuit 362 from the start voltage Von output from the first storage circuit 361, that is, Von−Voff as the regenerative voltage width Vd. The regenerative voltage width Vd outputs 30 V (Von−Voff = 380 V−350 V) regardless of the element variation of the voltage detector 33x.

FIG. 9 is a diagram illustrating a configuration of the second control unit 37x of the regeneration control unit 35x according to the second embodiment. As shown in FIG. 9, the second control unit 37x includes first to fourth delay circuits 371 to 374, third and fourth storage circuits 375 and 376, and comparators 377 to 379. Further, negative logic circuits 390 and 393, logical product circuits 391 and 392, a value determination circuit 394, a subtracter 395, an adder 396, and a state determination circuit 397 are provided.
The first to fourth delay circuits 371 to 374 and the third and fourth memory circuits 375 and 376 are constituted by, for example, a register or a semiconductor memory. The comparators 377 to 379 are constituted by operational amplifiers or comparators, for example.

The first to fourth delay circuits 371 to 374 delay the input signal by one system clock cycle and output it.
The first delay circuit 371 outputs a signal VdcxΔ1 that is delayed by one system clock cycle with respect to the detection voltage Vdcx. The comparator 377 compares the signal VdcxΔ1 that is the output of the first delay circuit 371 with the detection voltage Vdcx. When VdcxΔ1 ≧ Vdcx, the signal F3x is set to “1” level, and when VdcxΔ1 <Vdcx, the signal F3x is set to “ Set to "0" level and output. When the detection voltage Vdcx drops, the signal F3x becomes “1” level.
The second delay circuit 372 outputs a signal F3xΔ1 delayed by one system clock cycle with respect to the signal F3x that is the output of the comparator 377. The third delay circuit 373 outputs a signal F3xΔ2 delayed by one system clock cycle with respect to F3xΔ1 that is the output of the second delay circuit 372.

The third memory circuit 375 stores the determination voltage Vmin, and the fourth memory circuit 376 stores the compensation voltage δ.
The comparator 378 compares the detection voltage Vdcx with the determination voltage Vmin output from the third memory circuit 375. When Vdcx ≧ Vmin, the signal F4x is set to “1” level, and when Vdcx <Vmin, the signal F4x Is set to “0” level and output.
The negative logic circuit 390 receives the signal SW1x that is the output of the first control unit 36x, and inverts the level of the input signal. When the level of the signal SW1x is “1” level, the signal F5x is set to “0” level, and when the level of the signal SW1x is “0” level, the signal F5x is set to “1” level and output.

The AND circuit 391 includes five output signals F3x and F4x from the comparators 377 and 378, five output signals F3xΔ1 and F3xΔ2 from the second and third delay circuits 372 and 373, and an output signal F5x from the negative logic circuit 390. A signal is input, and a signal G1x that is a logical product of these signals is generated. The signal G1x is at “1” level only when all five signals input to the AND circuit 391 are at “1” level.
That is, when the level of the signal SW1x is “0”, the detection voltage Vdcx is equal to or higher than the determination voltage Vmin, and the detection voltage Vdcx drops continuously for three periods by the system clock, the signal G1x is “1”. "Become a level.

The fourth delay circuit 374 outputs a signal G1xΔ1 that is delayed by one system clock cycle with respect to the signal G1x that is the output of the AND circuit 391.
The negative logic circuit 393 receives the signal G1xΔ1 and inverts the level of the input signal. When the level of the signal G1xΔ1 is “1” level, the signal G2x is set to “0” level, and when the level of the signal G1xΔ1 is “0” level, the signal G2x is set to “1” level and output.
The logical product circuit 392 receives the signal G1x, which is the output of the logical product circuit 391, and the G2x, which is the output of the negative logical circuit 393, and outputs a signal T0x that is the logical product of these signals. This signal T0x is a time signal indicating the timing when the signal G1x changes from the “0” level to the “1” level, and is a pulse for one cycle of the system clock holding the rising timing of the signal G1x.

The value determination circuit 394 is configured by, for example, a D-type flip-flop (D-FF), inputs a signal T0x as a time signal, inputs a detection voltage Vdcx to a D terminal, and outputs a second start voltage Vstx. . The detection voltage Vdcx at the rising time of the signal T0x is output as the second start voltage Vstx.
The regenerative voltage width Vd and the second start voltage Vstx from the first control unit 36x are input to the subtractor 395, and the subtractor 395 generates a value Vax obtained by subtracting the regenerative voltage width Vd from the second start voltage Vstx. Output. That is, Vax = Vstx−Vd = Vstx− (Von−Voff).
The output Vax of the subtracter 395 and the compensation voltage δ output from the fourth memory circuit 376 are input to the adder 396 and added to output the second stop voltage Vspx. Vspx = Vstx− (Von−Voff) + δ.

The comparator 379 compares the second stop voltage Vspx, which is the output of the adder 396, with the detection voltage Vdcx, sets the signal F6x to “1” level when Vdcx ≦ Vspx, and sets the signal F6x when Vdcx> Vspx. Set to "0" level and output.
The state determination circuit 397 is composed of, for example, a set-reset type flip-flop (RS-FF), and inputs the signal T0x from the AND circuit 392 to the S terminal, inputs the signal F6x to the R terminal, and outputs the signal SW2x Is output. The signal SW2x output from the state determination circuit 397 becomes “1” level when the signal T0x changes from “0” level to “1” level, and the time when the signal F6x changes from “0” level to “1” level. The level becomes “0” and continues at other times without changing the level of the signal SW2x.

In other words, the signal SW2x is “1” when the level of the signal SW1x is “0”, the detection voltage Vdcx is equal to or higher than the determination voltage Vmin, and the detection voltage Vdcx is “1” at the time when the voltage drops continuously for three cycles by the system clock. "Become a level. Thereafter, when the detection voltage Vdcx drops and becomes equal to or lower than the second stop voltage Vspx, the level changes to “0” level.

Next, the operation of the regeneration control units 35x, 35y, and 35z of the three inverter devices 3x, 3y, and 3z will be described based on the wave diagram of each unit shown in FIG. Note that variations in the detection voltages Vdcx, Vdcy, Vdcz by the voltage detection units 33x, 33y, 33z of the inverter devices 3x, 3y, 3z are based on the voltage values shown in FIG. Moreover, the aspect of the regenerative power process of the inverter devices 3x, 3y, and 3z is the same as that shown in FIG.

The voltage waveform shown in FIG. 10 is a DC voltage Vdc, which is an actual voltage, and a voltage VdcΔ1 obtained by delaying the DC voltage Vdc by one system clock cycle. Comparing the detection voltages Vdcx, Vdcy, Vdcz with each Von, Voff, Vmin is to compare Vdc with each Vonx, Vony, Vonz, Voffx, Voffy, Voffz, Vminx, Vminy, Vminz in actual voltage It is. The voltage VdcΔ1 is an actual voltage corresponding to the voltage VdcxΔ1 (VdcyΔ1, VdczΔ1).
Here, the generated second stop voltages Vspy (= 363 V) and Vspz (= 356 V) are also indicated by the corresponding actual voltage 363 VR.

When the DC voltage Vdc rises and becomes equal to or higher than Vminx and Vminy (= 365VR) at time T1, the detection voltages Vdcx and Vdcy become equal to or higher than the determination voltage Vmin, and the signals F4x and F4y become “1” level.
When DC voltage Vdc further rises and becomes equal to or higher than Vminz (= 372VR) at time T2, detection voltage Vdcz becomes equal to or higher than determination voltage Vmin, and signal F4z becomes “1” level.
When the DC voltage Vdc further rises and becomes Vonx (= 373VR) or more at time T3, the detection voltage Vdcx becomes more than the start voltage Von, and the signal F1x becomes “1” level. As a result, the signal SW1x becomes “1” level, and the control signal SWx of the inverter device 3x also becomes “1” level. In the inverter device 3x, the regenerative power process is started, and the DC voltage Vdc drops.

At time T4, when the DC voltage Vdc becomes lower than the voltage VdcΔ1, the signal F3 (F3x, F3y, F3z) becomes the “1” level. As a result, at time T5 after one cycle of the system clock, the signal F3Δ1 (F3xΔ1, F3yΔ1, F3zΔ1) becomes the “1” level.
Further, at time T6 after one cycle of the system clock, the signal F3Δ2 (F3xΔ2, F3yΔ2, F3zΔ2) becomes the “1” level. At this time, the levels of the signals SW1y and SW1z continue to be “0” level, and the signals G1y and G1z become “1” level. At the same time, the signals T0y and T0z rise to the “1” level. Further, the signals T0y and T0z become “0” level after one cycle of the system clock by the signals G2y and G2z generated based on the signals G1y and G1z.
When the signals T0y and T0z become “1” level, the signals SW2y and SW2z become “1” level, and the control signals SWy and SWz of the inverter devices 3y and 3z also become “1” level. Then, in the inverter devices 3y and 3z, the regenerative power process is started.

At time T7, when the DC voltage Vdc becomes less than Vminz (= 372VR), the detection voltage Vdcz becomes less than the determination voltage Vmin, the signal F4z becomes “0” level, and the signal G1z becomes “0” level.
When the DC voltage Vdc becomes less than Vminx and Vminy (= 365VR) at time T8, the detection voltages Vdcx and Vdcy become less than the determination voltage Vmin, and the signals F4x and F4y become “0” level. Then, the signal G1y becomes “0” level.

At time T9, when the DC voltage Vdc becomes 363 VR (actual voltage corresponding to Vspy, Vspz) or lower, the detection voltage Vdcz becomes lower than the second stop voltages Vspy, Vspz, and the signals F6y, F6z become “1” level. As a result, the signals SW2y and SW2z become “0” level, and the control signals SWy and SWz of the inverter devices 3y and 3z also become “0” level. Then, in the inverter devices 3y and 3z, the regenerative power process is stopped.
At time T10, when the DC voltage Vdc becomes Voffx (= 357VR) or less, the detection voltage Vdcz becomes less than the stop voltage Voff, and the signal F2x becomes “1” level. As a result, the signal SW1x becomes “0” level, and the control signal SWx of the inverter device 3x also becomes “0” level. In the inverter device 3x, the regenerative power process is stopped.

When the regenerative power processing of all the inverter devices 3x, 3y, and 3z is stopped, the DC voltage Vdc rises, so that the signal F2x becomes “0” level. Thereafter, when the detection voltage Vdcz exceeds the second stop voltages Vspy and Vspz at time T11, the signals F6y and F6z also become “0” level.
Thereafter, when regenerative power is generated, the above operation is repeated.

This second embodiment also has the same effect as the first embodiment. That is, it is possible to prevent the load on the regenerative circuit 34x of the inverter device 3x from becoming excessive, and to suppress the deterioration of the regenerative circuit 34x. Moreover, when performing parallel operation with the other inverter devices 3y and 3z, the entire regenerative power can be increased.
Further, in the inverter system 100 that operates the plurality of inverter devices 3x, 3y, and 3z in parallel, it is possible to prevent only one inverter device 3x (3y, 3z) from performing the regenerative power process. When a large amount of regenerative power is generated, it is not processed only by the resistor 341x of the regenerative circuit 34x of the inverter device 3x that has started the regenerative power processing first, but the regenerative circuits 34x, 34y of all the inverter devices 3x, 3y, 3z. 34z can perform regenerative power processing.

Furthermore, since software calculation processing is not used for regenerative power processing, the load of calculation processing by software is reduced in the entire inverter device 3x, and urgency such as arm short circuit protection and ground fault protection is required in the inverter device 3x. The response time for the protection processing to be performed can be shortened. Thereby, there is an effect in avoiding failure or extending the life of the inverter device 3x.

Although this application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments may be applied to particular embodiments. The present invention is not limited to this, and can be applied to the embodiments alone or in various combinations.
Accordingly, innumerable modifications not illustrated are envisaged within the scope of the technology disclosed in the present application. For example, the case where at least one component is deformed, the case where the component is added or omitted, the case where the at least one component is extracted and combined with the component of another embodiment are included.

2x, 2y, 2z DC bus, 3x, 3y, 3z inverter device, 31x, 31y, 31z power converter, 32x, 32y, 32z smoothing capacitor, 33x, 33y, 33z voltage detector, 34x, 34y, 34z regeneration circuit, 35x, 35y, 35z regeneration control unit, 36x first control unit, 37x second control unit, 341x, 341y, 341z resistor, 342x, 342y, 342z switching element, Vdcx, Vdcy, Vdcz detection voltage, Vmin judgment voltage, Von Start voltage, Voff stop voltage, Vstx second start voltage, Vspx second stop voltage, δ, δa compensation voltage.

Claims (12)

1. A power converter that converts DC power from the DC bus into AC power and supplies the load to the load;
   A smoothing capacitor connected between the DC buses;
   A voltage detector for detecting a DC voltage between the DC buses;
   A series circuit of a resistor and a switching element connected between the DC buses, and a regenerative circuit for processing regenerative power from the power converter;
   A regeneration control unit that controls the switching element of the regeneration circuit;
   The regeneration control unit
   A first control unit that controls the switching element based on a comparison between a detection voltage from the voltage detection unit and a preset start voltage and stop voltage;
   An inverter device comprising: a second control unit that detects a voltage drop of the detection voltage at a predetermined determination voltage or higher when the switching element is in an OFF state and controls the switching element.
2. 2. The inverter device according to claim 1, wherein the second control unit of the regeneration control unit detects the voltage drop when the detection voltage drops continuously for a set time or more at the determination voltage or more.
3. The inverter device according to claim 1, wherein the determination voltage is set between the start voltage and the stop voltage.
4. The second control unit of the regeneration control unit generates a second stop voltage between the determination voltage and the stop voltage, detects a voltage drop of the detection voltage above the determination voltage, and detects the switching element. 4. The inverter device according to claim 3, wherein the switching element is turned off when the detection voltage drops and reaches the second stop voltage.
5. The second control unit of the regenerative control unit holds the detected voltage at the time when the voltage drop is detected as a second start voltage, and the second control unit based on the second start voltage and a preset compensation voltage. The inverter apparatus of Claim 4 which produces | generates a stop voltage.
6. The inverter device according to claim 5, wherein the compensation voltage is set based on a detection error range of the detection voltage so that the second stop voltage is higher than the stop voltage.
7. The inverter device according to claim 3, wherein the determination voltage is set based on a detection error range of the detection voltage.
8. The first control unit of the regeneration control unit turns on the switching element when the detected voltage becomes equal to or higher than the start voltage, and then turns off the switching element when the detected voltage drops and reaches the stop voltage. The inverter device according to any one of claims 1 to 7.
9. The inverter device according to any one of claims 1 to 8, wherein the regeneration control unit includes a processor that performs arithmetic processing using software.
10. The inverter device according to claim 1, wherein the regeneration control unit is configured by a circuit that operates as hardware.
11. An inverter system comprising a plurality of inverter devices according to any one of claims 1 to 10, wherein the DC buses of the plurality of inverter devices are connected in parallel.
12. When the regenerative power is processed, the regenerative control unit of at least one of the plurality of inverter devices operates the regenerative circuit by the first control unit, and all other inverter devices 12. The inverter system according to claim 11, wherein the regeneration control unit operates the regeneration circuit by the second control unit.

Images