WO2019227838A1 - 一种芯片上电复位电路 - Google Patents

一种芯片上电复位电路 Download PDF

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WO2019227838A1
WO2019227838A1 PCT/CN2018/112048 CN2018112048W WO2019227838A1 WO 2019227838 A1 WO2019227838 A1 WO 2019227838A1 CN 2018112048 W CN2018112048 W CN 2018112048W WO 2019227838 A1 WO2019227838 A1 WO 2019227838A1
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chip
mosfet
power supply
reset
power
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PCT/CN2018/112048
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高超
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郑州云海信息技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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  • the present invention relates to the field of communication technologies, and in particular, to a chip power-on reset circuit.
  • the PCA9555IO expander chip is more and more applied to the server with its smaller size and higher transmission performance, which solves the problem of insufficient BMC IO pin and achieves the expansion of I2C signals to Sideband signals.
  • the present invention provides a chip power-on reset circuit.
  • the MOS tube is used as a switching device to control the power signal of the chip, thereby solving the chip power-on reset problem when the hard disk is suspended.
  • a chip power-on reset circuit including:
  • Chip power supply three MOSFET tubes and reset chip, among them,
  • the reset pin of the reset chip is connected to the gate of the first MOSFET tube (Q1); the source of the first MOSFET tube (Q1) is connected to the ground of the DC power source, and the drain of the first MOSFET tube (Q1) is The electrodes are respectively connected to the DC power supply voltage and the gate of the second MOSFET (Q2); the source of the second MOSFET (Q2) is connected to the ground of the DC power and the drain of the second MOSFET (Q2) Connected to the DC power supply voltage and the gate of the third MOSFET (Q3), the drain of the third MOSFET (Q3) is connected to the chip's power supply operating voltage, and the source of the third MOSFET (Q3) Connected to chip power.
  • the chip is a PCA9555 chip.
  • the working voltage of the PCA9555 chip power supply is 3.3V.
  • the DC power supply voltage is 12V.
  • this application solves the problem of chip power-on reset when the hard disk is suspended.
  • the power consumption of the entire board can be reduced and more effective.
  • Ground protection chip to improve the reliability of the overall server operation.
  • FIG. 1 is a schematic diagram of a chip hardware circuit in the prior art
  • FIG. 2 is a schematic diagram of a chip hardware circuit of this embodiment.
  • first, second, and third embodiments in the following embodiments are only for distinguishing different MOSFET tubes or different voltages of the MOSFET tubes, and the present application does not limit the same.
  • MOSFET metal-oxide semiconductor field effect transistor.
  • MOSFET Q1 controls the voltage conduction of the gate and drain.
  • Figure 1 is a schematic diagram of the chip hardware circuit in the prior art. As shown in Figure 1, the power signal is sent to the PCA9555 chip. The PCA9555 chip cannot control the power signal. After the back-end hard disk fails, the PCA9555 chip cannot be reset.
  • FIG. 2 is a schematic diagram of a chip hardware circuit of this embodiment. As shown in FIG. 2, the chip power-on reset circuit includes:
  • Chip power supply, three MOSFET tubes and a reset chip wherein the reset pin of the reset chip is connected to the gate of the first MOSFET tube (Q1); the source of the first MOSFET tube (Q1) is connected to the ground of the DC power supply Connected, the drain of the first MOSFET (Q1) is connected to the DC power supply voltage and the gate of the second MOSFET (Q2) respectively; the source of the second MOSFET (Q2) is connected to the ground of the DC power
  • the drain of the second MOSFET (Q2) is connected to the DC power supply voltage and the gate of the third MOSFET (Q3), and the drain of the third MOSFET (Q3) is connected to the power supply voltage of the chip.
  • the source of the third MOSFET (Q3) is connected to a chip power source.
  • the embodiment of the present application has the beneficial effect of controlling the power signal of the chip by modifying the hardware circuit and using the MOSFET tube as the switching device to solve the problem of chip power-on reset when the hard disk is suspended.
  • the whole board can be reduced. Power consumption protects the chip more effectively and improves the reliability of the overall operation of the server.
  • the technology in the embodiments of the present application can be implemented by means of software plus a necessary universal hardware platform. Based on such an understanding, the technical solutions in the embodiments of the present application can be embodied in the form of software products that are essentially or contribute to the existing technology.
  • the computer software products are stored in a storage medium such as a USB flash drive, mobile Hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disks or compact discs and other media that can store program code, including several instructions to make a computer device (can be A personal computer, a server, or a second device, a network device, etc.) executes all or part of the steps of the method described in each embodiment of the present invention.
  • a storage medium such as a USB flash drive, mobile Hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disks or compact discs and other media that can store program code, including several instructions to make a computer device (can be A
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请实施例提供一种芯片上电复位电路，包括：芯片电源、三个MOSFET管和复位芯片，其中，所述复位芯片的复位脚与第一MOSFET管的栅极相连；所述第一MOSFET管的源极与直流电源的地相连，所述第一MOSFET管的漏极分别与直流电源电压、第二MOSFET管的栅极相连；所述第二MOSFET管的源极与直流电源的地相连，所述第二MOSFET管的漏极分别与直流电源电压、第三MOSFET管的栅极相连，所述第三MOSFET管的漏极与芯片的电源工作电压相连，所述第三MOSFET管的源极与芯片电源相连；通过修改硬件电路，以MOSFET管作为开关器件对芯片的电源信号进行控制，解决硬盘挂起时的芯片上电复位问题，通过对POWER的控制可以降低整板的功耗，更有效地保护芯片，提高服务器整体运行的可靠性。

Description

一种芯片上电复位电路
本申请要求于2018年5月31日提交中国专利局、申请号为201810549221.2、申请名称为“一种芯片上电复位电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，特别是涉及一种芯片上电复位电路。
背景技术
目前PCA9555IO expander芯片以其更小巧的规格尺寸和更高的传输性能越来越多的应用在服务器中，很好的解决了BMC IO pin不足的问题,实现了I2C信号到Sideband信号的拓展。
随着服务器的飞速发展，客户新的需求也开始增长，其中要求当硬盘被挂起hang住以后，需要主板进行热启动时能够对PCA9555进行复位，以此来恢复硬盘正常运行。因此，需要控制PCA9555上电信号，对PCA9555芯片进行复位。现有的PCA9555芯片的硬件电路中PCA9555芯片的电源信号无法控制，当后端硬盘发生故障以后，不能对PCA9555芯片进行上电复位，导致硬盘运行中断。
因此，亟需一种芯片上电复位电路，能够对PCA9555芯片的电源信号进行控制，解决硬盘挂起时的芯片上电复位问题。
发明内容
针对现有技术的不足，本发明提供了一种芯片上电复位电路，通过修改硬件电路，以MOS管作为开关器件对芯片的电源信号进行控制，解决硬盘挂起时的芯片上电复位问题。
第一方面，提供一种芯片上电复位电路，包括：
芯片电源、三个MOSFET管和复位芯片，其中，
所述复位芯片的复位脚与第一MOSFET管(Q1)的栅极相连；所述第一MOSFET管(Q1)的源极与直流电源的地相连，所述第一MOSFET管(Q1)的漏极分别与直流电源电压、第二MOSFET管(Q2)的栅极相连；所述第二MOSFET管(Q2)的源极与直流电源的地相连，所述第二MOSFET管(Q2)的漏极分别与直流电源电压、第三MOSFET管(Q3)的栅极相连，所述第三MOSFET管(Q3)的漏极与芯片的电源工作电压相连，所述第三MOSFET管(Q3)的源极与芯片电源相连。
结合第一方面，在第一方面的第一种可能的实现方式中，所述芯片为PCA9555芯片。
结合第一方面，在第一方面的第二种可能的实现方式中，所述PCA9555芯片电源的工作电压为3.3V。
结合第一方面，在第一方面的第三种可能的实现方式中，所述直流电源电压为12V。
因此，本申请通过修改硬件电路，以MOSFET管作为开关器件对芯片的电源信号进行控制，解决硬盘挂起时的芯片上电复位问题，通过对POWER的控制可以降低整板的功耗，更有效地保护芯片，提高服务器整体运行的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中芯片硬件电路示意图；
图2是本实施例芯片硬件电路示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基 于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
应理解，下列实施例中第一、第二、第三只是为了区分所指的是不同的MOSFET管、或者MOSFET管不同的电压等，本申请不做限定。
下面对本申请中出现的关键术语进行解释。
MOSFET(MOS)：表示金属-氧化物半导体场效应晶体管，MOSFET Q1的栅极端的高低电平控制栅极和漏极的电压导通。图1即为现有技术中芯片硬件电路示意图，如图1所示，电源信号发送给PCA9555芯片，PCA9555芯片对电源信号无法控制，后端硬盘发生故障以后，不能对PCA9555芯片进行复位。
图2为本实施例芯片硬件电路示意图，如图2所示，所述芯片上电复位电路包括：
芯片电源、三个MOSFET管和复位芯片，其中，所述复位芯片的复位脚与第一MOSFET管(Q1)的栅极相连；所述第一MOSFET管(Q1)的源极与直流电源的地相连，所述第一MOSFET管(Q1)的漏极分别与直流电源电压、第二MOSFET管(Q2)的栅极相连；所述第二MOSFET管(Q2)的源极与直流电源的地相连，所述第二MOSFET管(Q2)的漏极分别与直流电源电压、第三MOSFET管(Q3)的栅极相连，所述第三MOSFET管(Q3)的漏极与芯片的电源工作电压相连，所述第三MOSFET管(Q3)的源极与芯片电源相连。
(1)将复位信号Reset作为电源的控制信号，当复位信号Reset为高电平时，MOSFET管Q1导通，Q2断开，Q3导通，此时PCA9555芯片的电源输出PCA9555_POWER为3.3V，芯片处于正常工作状态；
(2)当复位信号Reset为低电平时，MOSFET管Q1断开，Q2导通，Q3断开，此时PCA9555芯片的电源输出PCA9555_POWER为0V，芯片处于断 电状态。
从以上描述可知，可以通过外部复位信号来控制PCA9555芯片电源的复位。
因此，本申请实施例有益效果为通过修改硬件电路，以MOSFET管作为开关器件对芯片的电源信号进行控制，解决硬盘挂起时的芯片上电复位问题，通过对POWER的控制可以降低整板的功耗，更有效地保护芯片，提高服务器整体运行的可靠性，本实施例所能达到的技术效果可以参见上文中的描述，此处不再赘述。
本领域的技术人员可以清楚地了解到本申请实施例中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本申请实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中如U盘、移动硬盘、只读存储器(ROM，Read-OnlyMemory)、随机存取存储器(RAM，RandomAccessMemory)、磁碟或者光盘等各种可以存储程序代码的介质，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者第二设备、网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。
本说明书中各个实施例之间相同相似的部分互相参见即可。尤其，对于终端实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例中的说明即可。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部 单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
尽管通过参考附图并结合优选实施例的方式对本发明进行了详细描述，但本发明并不限于此。在不脱离本发明的精神和实质的前提下，本领域普通技术人员可以对本发明的实施例进行各种等效的修改或替换，而这些修改或替换都应在本发明的涵盖范围内/任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (4)

  1. 一种芯片上电复位电路，其特征在于，包括：
    芯片电源、三个MOSFET管和复位芯片，其中，
    所述复位芯片的复位脚与第一MOSFET管的栅极相连；所述第一MOSFET管的源极与直流电源的地相连，所述第一MOSFET管的漏极分别与直流电源电压、第二MOSFET管的栅极相连；所述第二MOSFET管的源极与直流电源的地相连，所述第二MOSFET管的漏极分别与直流电源电压、第三MOSFET管的栅极相连，所述第三MOSFET管的漏极与芯片的电源工作电压相连，所述第三MOSFET管的源极与芯片电源相连。
  2. 根据权利要求1所述的电路，其特征在于，所述芯片为PCA9555芯片。
  3. 根据权利要求1或2所述的电路，其特征在于，所述PCA9555芯片电源的工作电压设置为3.3V。
  4. 根据权利要求3所述的电路，其特征在于，所述直流电源电压设置为12V。
PCT/CN2018/112048 2018-05-31 2018-10-26 一种芯片上电复位电路 WO2019227838A1 (zh)

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