WO2019227800A1 - 阵列基板、显示面板及显示器 - Google Patents

阵列基板、显示面板及显示器 Download PDF

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Publication number
WO2019227800A1
WO2019227800A1 PCT/CN2018/107591 CN2018107591W WO2019227800A1 WO 2019227800 A1 WO2019227800 A1 WO 2019227800A1 CN 2018107591 W CN2018107591 W CN 2018107591W WO 2019227800 A1 WO2019227800 A1 WO 2019227800A1
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Prior art keywords
layer
metal layer
array substrate
metal
capacitor
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PCT/CN2018/107591
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English (en)
French (fr)
Inventor
韩约白
成露
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武汉华星光电技术有限公司
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Priority to US16/208,514 priority Critical patent/US10690978B2/en
Publication of WO2019227800A1 publication Critical patent/WO2019227800A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel, and a display.
  • a GOA Gate Driver On Array
  • Each shift register is connected to a scan line.
  • the level signal charges the capacitor in the shift register, so that the scanning line of this row outputs a high level signal, and then the high level signal output by the scanning line of the next row is used to realize the reset.
  • the capacity of the capacitor must be large enough to work stably to ensure that the scanning lines of this row output high-level signals.
  • the capacitance of the GOA circuit of the existing design needs to be further improved.
  • the present application provides an array substrate, a display panel, and a display, which increase the capacitance capacity.
  • the GOA circuit of which includes a polysilicon layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer sequentially stacked, and the polysilicon layer and the first metal layer are at least Partial insulation overlaps to form a capacitor.
  • the second metal layer and the first metal layer at least partially insulate and overlap to form a capacitor.
  • the GOA circuit further includes at least one metal layer in contact with the first metal layer.
  • the at least one The metal layer is at least partially insulated and overlapped with the second metal layer and / or the polysilicon layer to form a capacitor.
  • the GOA circuit of an array substrate includes a polysilicon layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer stacked in this order.
  • the polysilicon layer and the first The metal layer is at least partially insulated and overlapped to form a capacitor
  • the second metal layer and the first metal layer are at least partially insulated and overlapped to form a capacitor.
  • the GOA circuit further includes at least one metal layer in contact with the first metal layer.
  • the at least one metal layer is at least partially insulated and overlapped with the second metal layer and / or the polysilicon layer to form a capacitor.
  • a display provided by the present application is provided with a GOA circuit on an array substrate of a display panel.
  • the GOA circuit includes a polysilicon layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal that are sequentially stacked.
  • Layer, the polysilicon layer and the first metal layer are at least partially insulated and overlapped to form a capacitor
  • the second metal layer and the first metal layer are at least partially insulated and overlapped to form a capacitor
  • the GOA circuit further includes a first metal layer and the first metal layer.
  • Layer is in contact with at least one metal layer, and the at least one metal layer is at least partially insulated and overlapped with the second metal layer and / or the polysilicon layer to form a capacitor.
  • At least one metal layer is added in the present application, the additional metal layer is in contact with the first metal layer of the existing GOA circuit, and is at least partially insulated and overlapped with the second metal layer and / or the polysilicon layer of the existing GOA circuit to form
  • the capacitance is equivalent to adding at least one capacitor in series, and the final capacitance of the GOA circuit increases.
  • FIG. 1 is a structural cross-sectional view of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a pixel structure of an embodiment of the liquid crystal display panel shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a GOA circuit according to a first embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a GOA circuit according to an embodiment of the prior art
  • FIG. 5 is a schematic structural diagram of a GOA circuit according to a second embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a GOA circuit according to another embodiment of the prior art.
  • FIG. 7 is a structural cross-sectional view of a display according to an embodiment of the present application.
  • the main purpose of this application is to add at least one metal layer, the added at least one metal layer is in contact with the first metal layer of the existing GOA circuit, and is at least partly in contact with the second metal layer and / or the polysilicon layer of the existing GOA circuit.
  • the insulation is overlapped to form a capacitor, which is equivalent to adding at least one capacitor in series with the existing capacitor on the basis of the existing capacitor.
  • the final capacitance of the GOA circuit is increased, and the area of the capacitor is still the area occupied by one of the capacitors. That is, the capacitance capacity is increased without increasing the capacitance area, in other words, the capacitance area is reduced without reducing the capacitance capacity, thereby facilitating the narrow bezel design of the LCD.
  • FIG. 1 is a structural cross-sectional view of a display panel according to a first embodiment of the present application.
  • the display panel is the liquid crystal display panel 10, of course, the type of the display panel is not limited to this.
  • the liquid crystal display panel 10 includes a color filter substrate (Color substrate, referred to as a CF substrate, also referred to as a color filter substrate) 11 and an array substrate (Thin Film Transistor Substrate, referred to as a TFT substrate) which are relatively spaced apart. (Also referred to as a thin film transistor substrate or an Array substrate) 12 and a liquid crystal (liquid crystal molecule) 13 filled between the two substrates.
  • the liquid crystal 13 is located in a liquid crystal cell formed by superposing the array substrate 12 and the color filter substrate 11.
  • the array substrate 12 includes a plurality of data lines 121 arranged in a column direction, a plurality of scan lines 122 arranged in a row direction, and the scan lines 122 and the data lines 121.
  • Each scan line 122 is connected to the gate driver 21 to provide a scanning voltage to each pixel region 123.
  • Each data line 121 is connected to a source.
  • the electrode driver 22 supplies a gray-scale voltage to each pixel region 123.
  • the gate driver 21 is provided with a GOA circuit.
  • the GOA circuit includes various layers of a layered structure stacked on a substrate substrate of the array substrate 12 in order: a polysilicon layer 31, a first insulating layer 32, a first metal layer M 1 , a second insulating layer 33, The second metal layer M 2 , the third insulating layer 34, and the third metal layer M 3 .
  • the polysilicon layer 31 may be formed synchronously with the polysilicon semiconductor layer of the TFT of the array substrate 12.
  • the first metal layer M 1 may be formed synchronously with the gate electrode of the TFT
  • the second metal layer M 2 may be formed synchronously with the TFT.
  • the source electrode (or drain electrode) is formed synchronously, and the third metal layer M 3 may be formed synchronously with the common electrode layer or the pixel electrode layer of the array substrate 12. Further, the above-mentioned materials and processes for simultaneously forming each layer structure may be the same.
  • the array substrate 12 is provided with a first via hole 124 penetrating the second insulating layer 33 and the first insulating layer 32, a second via hole 125 penetrating the third insulating layer 34 and the second insulating layer 33, and a second metal layer.
  • M 2 is connected to the first metal layer M 1 through the first via hole 124
  • the third metal layer M 3 is connected to the first metal layer M 1 through the second via hole 125.
  • the first metal layer M 1 and the polysilicon layer 31 at least partially overlap, and the overlapping first metal layer M 1 and the polysilicon layer 31 are insulated by a first insulating layer 32 sandwiched therebetween to form a first capacitor C 1 .
  • the second metal layer M 2 and the first metal layer M 1 at least partially overlap, and the overlapped second metal layer M 2 and the first metal layer M 1 are insulated by a second insulating layer 33 sandwiched therebetween, so that A second capacitor C 2 is formed.
  • the third metal layer M 3 and the second metal layer M 2 at least partially overlap, and the overlapped third metal layer M 3 and the second metal layer M 2 are insulated by a third insulating layer 34 sandwiched therebetween, so that A third capacitor C 3 is formed.
  • the first capacitor C 1 , the second capacitor C 2 and the third capacitor C 3 are connected in series in this order. .
  • a first metal layer M 1, M 2 and the second metal layer a third metal layer of the array substrate M 3 four layers of the conductive layer 12, see FIG. 4, the conventional The technique is simply to contact the second metal layer M 2 with the polysilicon layer 31.
  • the third metal layer M 3 is not in contact with the first metal layer M 1.
  • the capacitance area of the GOA circuit of the prior art and the present application is the same, but the prior art only includes the first capacitor C.
  • the two capacitors, 1 and the second capacitor C 2 have a capacity smaller than that of the three capacitors in this application.
  • the first insulating layer 32 may be a gate insulating layer (GI) of the TFT
  • the second insulating layer 33 may be an interlayer dielectric isolation (ILD) of the TFT.
  • a common electrode layer is located between the pixel electrode layer and the source-drain electrode (layer), and for example, silicon nitrogen is used between the common electrode layer and the pixel electrode layer.
  • the compound (SiN x ) is made of a passivation layer with a thickness of 100 nm.
  • the third insulating layer 34 may include a planarization layer (Planarization Layer, PLN) and a passivation layer of the TFT.
  • Planarization Layer Planarization Layer, PLN
  • the present application may etch and remove the flat layer between the third metal layer M 3 and the second metal layer M 2 , leaving only the Passivation layer.
  • FIG. 5 is a schematic structural diagram of a GOA circuit according to a second embodiment of the present application.
  • the GOA circuit of this embodiment further includes a fourth insulating layer 30 and a fourth metal layer M 0 , that is, the GOA circuit of this embodiment includes a polysilicon layer 31, a first metal layer M 1 , Five conductive layers are the second metal layer M 2 , the third metal layer M 3 , and the fourth metal layer M 0 .
  • the fourth metal layer M 0 is disposed directly under the polysilicon layer 31, and the fourth insulating layer 30 is disposed between the fourth metal layer M 0 and the polysilicon layer 31.
  • the fourth metal layer M 0 may be formed in synchronization with a light shield (LS) layer of the array substrate 12.
  • the array substrate 12 is provided with a third via hole 126 penetrating the first insulating layer 32 and the fourth insulating layer 30.
  • the first metal layer M 1 is connected to the fourth metal layer M 0 through the third via hole 126, and the polysilicon layer 31 is at least partially overlapped with the fourth metal layer M 0 , and the overlapping polysilicon layer 31 and the fourth metal layer M 0 are insulated by a fourth insulating layer 30 located therebetween to form a fourth capacitor C 4 . Since the first metal layer M 1 is in contact with the fourth metal layer M 0 , the fourth capacitor C 4 , the first capacitor C 1 , the second capacitor C 2 and the third capacitor C 3 are connected in series in this order.
  • a final circuit is a first capacitance GOA capacitor C 1, the second capacitor C 2, the capacity of the four capacitor and the third capacitor C 3 and the fourth capacitor C 4, the capacitance area It is only the area occupied by one of the capacitors. It can be seen that this embodiment can also increase the capacitance without increasing the capacitance area. In other words, this embodiment can reduce the capacitance area without reducing the capacitance, which is beneficial to the LCD. Narrow border design.
  • the second metal layer M 2 is only in contact with the polysilicon layer 31.
  • the same reference numerals are used in this application to identify structural elements with the same name.
  • the third metal layer M 3 is not in contact with the first metal layer M 1 , and the polysilicon layer 31 and the fourth metal layer M 0 are not in contact. As shown in FIGS.
  • the prior art and the GOA circuit of the present application The capacitors have the same area, but the prior art only includes two capacitors, namely a first capacitor C 1 and a second capacitor C 2 , whose capacity is less than the capacity of the four capacitors in this application.
  • the GOA circuit of the present application may also be provided with a fourth metal layer M 0 without a third metal layer M 3.
  • the final capacitance of the GOA circuit is the first capacitor C. 1.
  • the sum of the capacitances of the three capacitors, the second capacitor C 2 and the fourth capacitor C 4 , and the capacitor area is only the area occupied by the original capacitor.
  • This embodiment can also increase the capacitor without increasing the capacitor area. In other words, this embodiment can also reduce the capacitance area without reducing the capacitance, which is beneficial to the narrow frame design of the LCD.
  • the embodiment of the present application further provides a display as shown in FIG. 7.
  • the display is a liquid crystal display 70.
  • the liquid crystal display 70 includes the above-mentioned liquid crystal display panel 10 and a backlight module 71 that provides light to the liquid crystal display panel 10. Since the liquid crystal display 70 also has the above-mentioned design of the array substrate 12, it also has the same beneficial effects.

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Abstract

本申请公开一种阵列基板、显示面板及显示器。本申请增设至少一金属层，该增设的金属层与现有GOA电路的第一金属层接触，并且与现有GOA电路的第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容，相当于增加了至少一个串联的电容，GOA电路的电容容量得以增大，而电容面积仍为现有电容所占的面积，有利于LCD的窄边框设计。

Description

阵列基板、显示面板及显示器 【技术领域】
本申请涉及显示技术领域，具体而言涉及一种阵列基板、显示面板及显示器。
【背景技术】
在显示面板，如液晶显示面板中，GOA(Gate Driver On Array,阵列基板行驱动)电路通常由多个移位寄存器组成，每一移位寄存器连接一条扫描线，利用上一行扫描线输出的高电平信号对移位寄存器中的电容充电，使得本行的扫描线输出高电平信号，再利用下一行扫描线输出的高电平信号实现复位。其中，电容的容量必须足够大才能稳定工作以确保本行的扫描线输出高电平信号。现有设计的GOA电路的电容容量需要进一步提升。
【发明内容】
有鉴于此，本申请提供一种阵列基板、显示面板及显示器，增大了电容容量。
本申请提供的一种阵列基板，其GOA电路包括依次叠设的多晶硅层、第一绝缘层、第一金属层、第二绝缘层以及第二金属层，所述多晶硅层和第一金属层至少部分绝缘重叠以形成电容，所述第二金属层和第一金属层至少部分绝缘重叠以形成电容，所述GOA电路还包括与所述第一金属层接触的至少一金属层，所述至少一金属层与所述第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容。
本申请提供的一种显示面板，其阵列基板的GOA电路包括依次叠设的多晶硅层、第一绝缘层、第一金属层、第二绝缘层以及第二金属层，所述多晶硅层和第一金属层至少部分绝缘重叠以形成电容，所述第二金属层和第一金属层至少部分绝缘重叠以形成电容，所述GOA电路还包括与所述第一金属层接触的至少一金属层，所述至少一金属层与所述第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容。
本申请提供的一种显示器，其显示面板的阵列基板上设置有GOA电路，所述GOA电路包括依次叠设的多晶硅层、第一绝缘层、第一金属层、第二绝缘层以及第二金属层，所述多晶硅层和第一金属层至少部分绝缘重叠以形成电容，所述第二金属层和第一金属层至少部分绝缘重叠以形成电容，所述GOA电路还包括与所述第一金属层接触的至少一金属层，所述至少一金属层与所述第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容。
有益效果：本申请增设至少一金属层，该增设的金属层与现有GOA电路的第一金属层接触，并且与现有GOA电路的第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容，相当于增加了至少一个串联的电容，GOA电路最终的电容容量增大。
【附图说明】
图1是本申请一实施例的显示面板的结构剖视图；
图2是图1所示液晶显示面板一实施例的像素结构示意图；
图3是本申请第一实施例的GOA电路的结构示意图；
图4是现有技术一实施例的GOA电路的结构示意图；
图5是本申请第二实施例的GOA电路的结构示意图；
图6是现有技术另一实施例的GOA电路的结构示意图；
图7是本申请一实施例的显示器的结构剖视图。
【具体实施方式】
本申请的主要目的是：增设至少一金属层，该增设的至少一金属层与现有GOA电路的第一金属层接触，并且与现有GOA电路的第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容，相当于在现有电容的基础上增加了至少一个与现有电容串联的电容，GOA电路最终的电容容量得以增大，而其电容面积仍为其中一个电容所占的面积，即，在不增加电容面积的同时增大电容容量，换言之，在不减少电容容量的情况下减少电容面积，从而有利于LCD的窄边框设计。
下面结合附图对本申请的各个实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述实施例及其技术特征可以相互组合。并且，全文所采 用的方向性术语，例如“上”、“下”等，均是为了更好的描述各个实施例，并非用于限制本申请的保护范围。
图1是本申请第一实施例的显示面板的结构剖视图。在本实施例中，显示面板为液晶显示面板10，当然，显示面板的类型不以此为限。如图1所示，所述液晶显示面板10包括相对间隔设置的彩膜基板(Color Filter Substrate，简称CF基板,又称彩色滤光片基板)11和阵列基板(Thin Film Transistor Substrate，简称TFT基板,又称薄膜晶体管基板或Array基板)12以及填充于两基板之间的液晶(液晶分子)13，该液晶13位于阵列基板12和彩膜基板11叠加形成的液晶盒内。
结合图2所示液晶显示面板10的像素结构示意图，所述阵列基板12包括沿列方向设置的多条数据线121、沿行方向设置的多条扫描线122以及由扫描线122和数据线121定义的多个像素区域123。其中，每一像素区域123连接对应的一条数据线121和一条扫描线122，各条扫描线122连接于栅极驱动器21以分别对各像素区域123提供扫描电压，各条数据线121连接于源电极驱动器22以对各像素区域123提供灰阶电压。其中，该栅极驱动器21中设有GOA电路。
请参阅图3，所述GOA电路包括依次层叠于阵列基板12的衬底基材上的各层结构：多晶硅层31、第一绝缘层32、第一金属层M l、第二绝缘层33、第二金属层M 2、第三绝缘层34、以及第三金属层M 3。其中，多晶硅层31可以与阵列基板12的TFT的多晶硅半导体层同步形成，同理，所述第一金属层M l可以与TFT的栅电极同步形成，所述第二金属层M 2可以与TFT的源电极(或漏电极)同步形成，所述第三金属层M 3可以与阵列基板12的公共电极层或像素电极层同步形成。进一步地，上述同步形成各层结构的材料和工艺可以相同。
所述阵列基板12设有贯穿第二绝缘层33和第一绝缘层32的第一过孔124、以及贯穿第三绝缘层34和第二绝缘层33的第二过孔125，第二金属层M 2通过第一过孔124与第一金属层M 1连接，第三金属层M 3通过第二过孔125与第一金属层M 1连接。
第一金属层M 1与多晶硅层31至少部分重叠，重叠部分的第一金属层M 1和多晶硅层31通过夹持于两者之间的第一绝缘层32绝缘，以形成第一电容C 1。第二金属层M 2与第一金属层M 1至少部分重叠，重叠部分的第二金属层M 2和第一金属层M 1通过夹持于两者之间的第二绝缘层33绝缘，以形成第二电容C 2。第三金属层M 3与第二金属层M 2至少部分重叠，重叠部分的第三金属层M 3和第 二金属层M 2通过夹持于两者之间的第三绝缘层34绝缘，以形成第三电容C 3。而由于第二金属层M 2与多晶硅层31接触，且第三金属层M 3与第一金属层M 1接触，因此第一电容C 1、第二电容C 2和第三电容C 3依次串联。
在图3所示的区域，GOA电路最终的电容容量为第一电容C 1、第二电容C 2和第三电容C 3这三个电容的容量之和，而电容面积仅为其中一个电容(原有电容)所占的面积，可见，本申请能够在不增加电容面积的同时增大电容容量，换言之，本申请能够在不减少电容容量的情况下减少电容面积，从而能够有利于LCD(Liquid Crystal Display,液晶显示器)的窄边框设计。
对于具有图3所示的多晶硅层31、第一金属层M 1、第二金属层M 2及第三金属层M 3这四层导电层的阵列基板12，请参阅图4所示，现有技术仅是将第二金属层M 2与多晶硅层31接触。为便于描述，本申请采用相同的标号来标识相同名称的结构元件。第三金属层M 3与第一金属层M 1并未接触，结合图3和图4所示，现有技术与本申请的GOA电路的电容面积相同，但现有技术仅包含第一电容C 1和第二电容C 2这两个电容，其容量小于本申请中三个电容的容量。
请继续参阅图3，所述第一绝缘层32可以为TFT的栅极绝缘层(Gate Insulation Layer,GI)，第二绝缘层33可以为TFT的介质隔离层(Interlayer dielectric isolation,ILD)。在第三金属层M 3与像素电极层同步形成的应用场景中，公共电极层位于像素电极层和源漏电极(层)之间，公共电极层和像素电极层之间设置有采用例如硅氮化合物(SiN x)制备的厚度为100nm的钝化层，因此，第三绝缘层34可以包括TFT的平坦层(Planarization Layer,PLN)和钝化层。当然，为了降低第三绝缘层34的厚度，以此增加第三电容C 3的容量，本申请可以刻蚀去除第三金属层M 3和第二金属层M 2之间的平坦层，仅保留钝化层。
图5是本申请第二实施例的GOA电路的结构示意图。本申请采用相同的标号来标识相同名称的结构元件。在前述实施例的描述基础上，本实施例的GOA电路还包括第四绝缘层30和第四金属层M 0，即，本实施例的GOA电路包括多晶硅层31、第一金属层M 1、第二金属层M 2、第三金属层M 3、及第四金属层M 0这五层导电层。其中，第四金属层M 0设于多晶硅层31的正下方，第四绝缘层30设置于第四金属层M 0和多晶硅层31之间。该第四金属层M 0可以与阵列基板12的遮光金属(light shield,LS)层同步形成，所谓遮光金属层在TFT中设置于多晶硅半导体层的正下方以用于防止漏光。
另外，阵列基板12设有贯穿第一绝缘层32和第四绝缘层30的第三过孔126，第一金属层M 1通过第三过孔126与第四金属层M 0连接，且多晶硅层31与第四金属层M 0至少部分重叠，重叠部分的多晶硅层31和第四金属层M 0通过位于两者之间的第四绝缘层30绝缘，以形成第四电容C 4。而由于第一金属层M 1与第四金属层M 0接触，因此第四电容C 4、第一电容C 1、第二电容C 2和第三电容C 3依次串联。
在图5所示的区域，GOA电路最终的电容容量为第一电容C 1、第二电容C 2、第三电容C 3和第四电容C 4这四个电容的容量之和，而电容面积仅为其中一个电容所占的面积，可见，本实施例也能够在不增加电容面积的同时增大电容容量，换言之，本实施例能够在不减少电容容量的情况下减少电容面积，有利于LCD的窄边框设计。
对于具有图5所示的第四金属层M 0、多晶硅层31、第一金属层M 1、第二金属层M 2及第三金属层M 3这五层导电层的阵列基板12，请参阅图6所示，现有技术仅是将第二金属层M 2与多晶硅层31接触。为便于描述，本申请采用相同的标号来标识相同名称的结构元件。第三金属层M 3与第一金属层M 1并未接触，多晶硅层31和第四金属层M 0也并未接触，结合图5和图6所示，现有技术与本申请的GOA电路的电容面积相同，但现有技术仅包含第一电容C 1和第二电容C 2这两个电容，其容量小于本申请中四个电容的容量。
应理解，在前述主要目的的基础上，本申请的GOA电路也可以设置第四金属层M 0，而未设置第三金属层M 3，此时，GOA电路最终的电容容量为第一电容C 1、第二电容C 2和第四电容C 4这三个电容的容量之和，而电容面积仅为原有电容所占的面积，本实施例也能够在不增加电容面积的同时增大电容容量，换言之，本实施例也能够在不减少电容容量的情况下减少电容面积，有利于LCD的窄边框设计。
本申请实施例还提供一种如图7所示的显示器，在本实施例中，显示器为液晶显示器70，当然，显示器的类型不限于此。该液晶显示器70包括上述液晶显示面板10以及为液晶显示面板10提供光线的背光模组71。由于该液晶显示器70也具有上述阵列基板12的上述设计，因此亦具有相同的有益效果。
应理解，以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均 同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其GOA电路包括依次叠设的多晶硅层、第一绝缘层、第一金属层、第二绝缘层以及第二金属层，所述多晶硅层和第一金属层至少部分绝缘重叠以形成电容，所述第二金属层和第一金属层至少部分绝缘重叠以形成电容，其中，所述GOA电路还包括与所述第一金属层接触的至少一金属层，所述至少一金属层与所述第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容。
  2. 根据权利要求1所述的阵列基板，其中，所述至少一金属层包括第三金属层，所述第三金属层与所述阵列基板的公共电极层或像素电极层同步形成。
  3. 根据权利要求2所述的阵列基板，其中，所述第三金属层与所述像素电极层同步形成，所述第三金属层和所述第二金属层之间通过第三绝缘层绝缘重叠，所述第三绝缘层为所述阵列基板的钝化层，所述钝化层位于所述公共电极层和像素电极层之间。
  4. 根据权利要求2所述的阵列基板，其中，所述第三金属层与所述像素电极层同步形成，所述第三金属层和所述第二金属层之间通过第三绝缘层绝缘重叠，所述第三绝缘层包括所述阵列基板的钝化层和平坦层，所述钝化层位于所述公共电极层和像素电极层之间，所述平坦层位于所述公共电极层和第三金属层之间。
  5. 根据权利要求3所述的阵列基板，其中，所述阵列基板设有贯穿所述第三绝缘层和第二绝缘层的过孔，所述第三金属层通过所述过孔与所述第一金属层连接。
  6. 根据权利要求1所述的阵列基板，其中，所述至少一金属层包括叠设于所述多晶硅层下方的第四金属层，所述第四金属层与所述阵列基板的遮光金属层同步形成，所述遮光金属层位于所述阵列基板的多晶硅半导体层的正下方。
  7. 根据权利要求6所述的阵列基板，其中，所述第四金属层和所述多晶硅层之间通过第四绝缘层绝缘重叠，所述第四绝缘层为所述阵列基板的缓冲层，所述缓冲层位于所述遮光金属层和所述阵列基板的多晶硅半导体层之间。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列基板设有贯穿所述第一绝缘层和第四绝缘层的过孔，所述第一金属层通过所述过孔与所述第四金属层连接。
  9. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板的GOA电路包括依次叠设的多晶硅层、第一绝缘层、第一金属层、第二绝缘层以及第二金属层，所述多晶硅层和第一金属层至少部分绝缘重叠以形成电容，所述第二金属层和第一金属层至少部分绝缘重叠以形成电容，其中，所述GOA电路还包括与所述第一金属层接触的至少一金属层，所述至少一金属层与所述第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容。
  10. 根据权利要求9所述的显示面板，其中，所述至少一金属层包括第三金属层，所述第三金属层与所述阵列基板的公共电极层或像素电极层同步形成。
  11. 根据权利要求10所述的显示面板，其中，所述第三金属层与所述像素电极层同步形成，所述第三金属层和所述第二金属层之间通过第三绝缘层绝缘重叠，所述第三绝缘层为所述阵列基板的钝化层，所述钝化层位于所述公共电极层和像素电极层之间。
  12. 根据权利要求10所述的显示面板，其中，所述第三金属层与所述像素电极层同步形成，所述第三金属层和所述第二金属层之间通过第三绝缘层绝缘重叠，所述第三绝缘层包括所述阵列基板的钝化层和平坦层，所述钝化层位于所述公共电极层和像素电极层之间，所述平坦层位于所述公共电极层和第三金属层之间。
  13. 根据权利要求11所述的显示面板，其中，所述阵列基板设有贯穿所述第三绝缘层和第二绝缘层的过孔，所述第三金属层通过所述过孔与所述第一金属层连接。
  14. 根据权利要求9所述的显示面板，其中，所述至少一金属层包括叠设于所述多晶硅层下方的第四金属层，所述第四金属层与所述阵列基板的遮光金属层同步形成，所述遮光金属层位于所述阵列基板的多晶硅半导体层的正下方。
  15. 根据权利要求14所述的显示面板，其中，所述第四金属层和所述多晶硅层之间通过第四绝缘层绝缘重叠，所述第四绝缘层为所述阵列基板的缓冲层，所述缓冲层位于所述遮光金属层和所述阵列基板的多晶硅半导体层之间。
  16. 根据权利要求15所述的显示面板，其中，所述阵列基板设有贯穿所述第一绝缘层和第四绝缘层的过孔，所述第一金属层通过所述过孔与所述第四金属层连接。
  17. 一种显示器，其中，所述显示器包括显示面板，所述显示面板的阵列基板上设置有GOA电路，所述GOA电路包括依次叠设的多晶硅层、第一绝缘层、 第一金属层、第二绝缘层以及第二金属层，所述多晶硅层和第一金属层至少部分绝缘重叠以形成电容，所述第二金属层和第一金属层至少部分绝缘重叠以形成电容，其中，所述GOA电路还包括与所述第一金属层接触的至少一金属层，所述至少一金属层与所述第二金属层和/或多晶硅层至少部分绝缘重叠以形成电容。
  18. 根据权利要求17所述的显示器，其中，所述至少一金属层包括第三金属层，所述第三金属层与所述阵列基板的公共电极层或像素电极层同步形成。
  19. 根据权利要求18所述的显示器，其中，所述第三金属层与所述像素电极层同步形成，所述第三金属层和所述第二金属层之间通过第三绝缘层绝缘重叠，所述第三绝缘层为所述阵列基板的钝化层，所述钝化层位于所述公共电极层和像素电极层之间。
  20. 根据权利要求17所述的显示器，其中，所述至少一金属层包括叠设于所述多晶硅层下方的第四金属层，所述第四金属层与所述阵列基板的遮光金属层同步形成，所述遮光金属层位于所述阵列基板的多晶硅半导体层的正下方。
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CN107785399A (zh) * 2017-10-26 2018-03-09 武汉天马微电子有限公司 一种显示面板及显示装置
CN108020971A (zh) * 2017-12-22 2018-05-11 武汉华星光电技术有限公司 阵列基板、液晶面板以及液晶显示装置

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