WO2019227682A1 - Oled显示面板及oled显示器 - Google Patents

Oled显示面板及oled显示器 Download PDF

Info

Publication number
WO2019227682A1
WO2019227682A1 PCT/CN2018/100465 CN2018100465W WO2019227682A1 WO 2019227682 A1 WO2019227682 A1 WO 2019227682A1 CN 2018100465 W CN2018100465 W CN 2018100465W WO 2019227682 A1 WO2019227682 A1 WO 2019227682A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
metal
disposed
oled display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/100465
Other languages
English (en)
French (fr)
Inventor
陈彩琴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/311,691 priority Critical patent/US10868098B2/en
Publication of WO2019227682A1 publication Critical patent/WO2019227682A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display, and in particular to an OLED display panel and an OLED display.
  • each pixel is generally composed of two thin film transistors and a capacitor, commonly known as a 2T1C circuit.
  • This 2T1C design is sensitive to the following factors: the threshold voltage (Vth) and channel mobility (Mobility) of the TFT, the startup voltage and quantum efficiency of the OLED, and the transient process of the power supply. Therefore, compensation circuits are generally used to reduce the impact, such as 7T1C, 6T1C, 6T2C and so on.
  • the capacitor is used to store the turning-on potential and the compensation potential of the driving TFT.
  • a compensation capacitor is formed between two gate layers. The use of two gate layers will make the process flow more complicated. Conducive to reducing costs.
  • the purpose of the embodiments of the present invention is to provide an OLED display panel and an OLED display, which have the beneficial effect of reducing the process flow.
  • An embodiment of the present invention provides an OLED display panel, which includes a substrate and a first gate layer, an SD metal layer, and an anode metal layer disposed on the substrate;
  • a part of the first gate layer and the SD metal layer and / or the anode metal layer face each other to form a compensation capacitor
  • the SD metal layer is formed with a source electrode, a drain electrode, and a first metal block disposed at intervals; the first metal block is opposite to the first gate layer to form a first compensation capacitor;
  • the anode metal layer includes an anode metal and a second metal block spaced from each other; the second metal block is opposite to the first gate layer to form a third compensation capacitor.
  • the SD metal layer is formed with a source electrode, a drain electrode, and a first metal block arranged at intervals, and the anode metal layer includes an anode metal and a second metal block spaced from each other;
  • the first metal block is opposite to the second metal block to form a second compensation capacitor.
  • the OLED display panel of the present invention further includes a first insulating layer, a second insulating layer, a polysilicon layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer;
  • the first insulation layer is disposed on the substrate, the polysilicon layer is disposed on the first insulation layer, and the second insulation layer is disposed on the polysilicon layer and the first insulation layer;
  • the first gate layer is disposed on the second insulating layer
  • the third insulating layer is disposed on the first gate layer and the second insulating layer
  • the SD metal layer is disposed on the On the third insulating layer
  • the fourth insulating layer is disposed on the SD metal layer and the third insulating layer
  • the anode metal layer is disposed on the fourth insulating layer
  • the fifth insulating layer is disposed On the anode metal layer and the fourth insulating layer.
  • the second insulating layer and the third insulating layer are provided with a drain via and a source via, and the source of the SD metal layer is connected to the source via the source via.
  • the polysilicon layer is electrically connected, and the drain of the SD metal layer is electrically connected to the polysilicon layer through the drain via.
  • the fourth insulating layer is provided with an anode via, and the anode metal layer is electrically connected to the SD metal layer through the anode via.
  • the fifth insulating layer is provided with a first via hole
  • the OLED display panel further includes a light emitting layer and a cathode layer;
  • the light-emitting layer is disposed on the fifth insulating layer, and the cathode layer is disposed on the light-emitting layer;
  • the light emitting layer is electrically connected to the anode metal layer through the first via hole.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be a silicon dioxide layer or a silicon nitride layer.
  • An embodiment of the present invention further provides an OLED display panel including a substrate and a first gate layer, an SD metal layer, and an anode metal layer disposed on the substrate;
  • the SD metal layer is formed with a source electrode, a drain electrode, and a first metal block disposed at intervals; the first metal block is opposite to the first gate layer to form a first A compensation capacitor.
  • the SD metal layer is formed with a source electrode, a drain electrode, and a first metal block arranged at intervals, and the anode metal layer includes an anode metal and a second metal block spaced from each other;
  • the first metal block is opposite to the second metal block to form a second compensation capacitor.
  • the anode metal layer includes an anode metal and a second metal block spaced from each other; the second metal block is opposite to the first gate layer to form a third compensation capacitor.
  • the first metal block is opposite to the second metal block to form a third compensation capacitor.
  • the OLED display panel of the present invention further includes a first insulating layer, a second insulating layer, a polysilicon layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer;
  • the first insulation layer is disposed on the substrate, the polysilicon layer is disposed on the first insulation layer, and the second insulation layer is disposed on the polysilicon layer and the first insulation layer;
  • the first gate layer is disposed on the second insulating layer
  • the third insulating layer is disposed on the first gate layer and the second insulating layer
  • the SD metal layer is disposed on the On the third insulating layer
  • the fourth insulating layer is disposed on the SD metal layer and the third insulating layer
  • the anode metal layer is disposed on the fourth insulating layer
  • the fifth insulating layer is disposed On the anode metal layer and the fourth insulating layer.
  • the second insulating layer and the third insulating layer are provided with a drain via and a source via, and the source of the SD metal layer is connected to the source via the source via.
  • the polysilicon layer is electrically connected, and the drain of the SD metal layer is electrically connected to the polysilicon layer through the drain via.
  • the fourth insulating layer is provided with an anode via, and the anode metal layer is electrically connected to the SD metal layer through the anode via.
  • the fifth insulating layer is provided with a first via hole
  • the OLED display panel further includes a light emitting layer and a cathode layer;
  • the light-emitting layer is disposed on the fifth insulating layer, and the cathode layer is disposed on the light-emitting layer;
  • the light emitting layer is electrically connected to the anode metal layer through the first via hole.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be a silicon dioxide layer or a silicon nitride layer.
  • An OLED display includes an OLED display panel, and the OLED display panel includes:
  • the SD metal layer is formed with a source electrode, a drain electrode, and a first metal block disposed at intervals; the first metal block is opposite to the first gate layer to form a first Compensation capacitor.
  • the SD metal layer is formed with spaced source electrodes, drain electrodes, and first metal blocks, and the anode metal layer includes an anode metal and a second metal block spaced from each other;
  • the first metal block is opposite to the second metal block to form a second compensation capacitor.
  • the anode metal layer includes an anode metal and a second metal block spaced from each other; the second metal block is opposite to the first gate layer to form a third compensation capacitor.
  • the present invention forms a compensation capacitor by partially aligning the first gate layer and the SD metal layer and / or the anode metal layer with each other, and never requires two gate layers to form a compensation capacitor.
  • FIG. 1 is a schematic diagram of a first structure of an OLED display panel in some embodiments of the present invention.
  • FIG. 2 is a schematic diagram of a second structure of an OLED display panel in some embodiments of the present invention.
  • FIG. 3 is a third structural diagram of an OLED display panel in some embodiments of the present invention.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality” is two or more, unless specifically defined otherwise.
  • the "first” or “lower” of the first feature may include the first and second features in direct contact, and may also include the first and second features. Not directly, but through another characteristic contact between them.
  • the first feature is “above”, “above”, and “above” the second feature, including that the first feature is directly above and obliquely above the second feature, or merely indicates that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” of the second feature, including the fact that the first feature is directly below and obliquely below the second feature, or merely indicates that the first feature is less horizontal than the second feature.
  • the present invention provides an OLED display panel including a substrate and a first gate layer, an SD metal layer, and an anode metal layer provided on the substrate; a portion of the first gate layer and the SD metal layer And / or the anode metal layers are partially facing each other to form a compensation capacitor.
  • FIG. 1 is a structural diagram of an OLED display panel in some embodiments of the present invention, including a substrate 10, a first insulating layer 20, a polysilicon layer 30, a second insulating layer 40, a first gate layer GE1, a first The three insulating layers 50, the SD metal layer 60, the fourth insulating layer 70, the anode metal layer 80, the fifth insulating layer 90, the PS layer 100, the light emitting layer (not shown), and the cathode layer (not shown).
  • the first insulating layer 20 is disposed on the substrate 10, the polysilicon layer 30 is disposed on the first insulating layer 20, and the second insulating layer 40 is disposed on the first insulating layer and the polysilicon layer 30.
  • the first gate layer GE1 is disposed on the second insulating layer 40.
  • the third insulating layer 50 is disposed on the first gate layer GE1 and the second insulating layer 40.
  • the SD metal layer 60 is disposed on the third insulating layer 50.
  • the fourth insulating layer 70 is disposed on the SD metal layer 60 and the third insulating layer 50.
  • the anode metal layer 80 is disposed on the fourth insulating layer 70.
  • the fifth insulating layer 90 is disposed on the anode metal layer 80 and the fourth insulating layer 70.
  • the PS layer is disposed on the fifth insulating layer, and the light emitting layer and the cathode layer are disposed on the fifth insulating layer and the PS layer in this order.
  • the substrate 10 is a flexible substrate or a glass substrate.
  • the first insulating layer 20 is a buffer layer, which may be a silicon nitride layer or a silicon dioxide layer, and is deposited on the substrate 10 by a chemical vapor process.
  • the polysilicon layer 30 has an undoped region in the middle and doped regions on both sides of the undoped region.
  • the second insulating layer 40 is an isolation layer, which may be a silicon nitride layer or a silicon dioxide layer, and is deposited on the polysilicon layer 30 and the first insulating layer 20 by a chemical vapor process.
  • the first gate layer GE1 is made of a transparent conductive metal, such as ITO.
  • the third insulating layer 50 is an interlayer dielectric layer, which is a silicon nitride layer or a silicon dioxide layer, and is deposited on the first gate layer GE1 and the second insulating layer 40 by a chemical vapor process.
  • the SD metal layer 60 is made of a transparent conductive metal, such as ITO.
  • a source electrode 61, a drain electrode 62, and a first metal block 63 are formed thereon at intervals from each other.
  • the first metal block 63 is opposite to the first gate layer GE1 to form a first compensation capacitor C1.
  • the fourth insulating layer 70 and the fifth insulating layer 90 may be silicon nitride layers or silicon dioxide layers, and are formed by chemical vapor deposition.
  • the anode metal layer 80 is made of a transparent conductive metal, such as ITO.
  • the second insulating layer and the third insulating layer are provided with a drain via 54 and a source via 55.
  • the source of the SD metal layer is electrically connected to the polysilicon layer through the source via 55, and the SD metal layer
  • the drain electrode is electrically connected to the polysilicon layer through the drain via hole 55.
  • the fourth insulating layer is provided with an anode via 71, and the anode metal layer is electrically connected to the SD metal layer through the anode via 71.
  • the fifth insulating layer is provided with a first via hole; the light emitting layer is electrically connected to the anode metal layer through the first via hole.
  • FIG. 2 is a structural diagram of an OLED display panel in some embodiments of the present invention, including a substrate 10, a first insulating layer 20, a polysilicon layer 30, a second insulating layer 40, a first gate layer GE1, a first The three insulating layers 50, the SD metal layer 60, the fourth insulating layer 70, the anode metal layer 80, the fifth insulating layer 90, the PS layer 100, the light emitting layer (not shown), and the cathode layer (not shown).
  • the first insulating layer 20 is disposed on the substrate 10, the polysilicon layer 30 is disposed on the first insulating layer 20, and the second insulating layer 40 is disposed on the first insulating layer and the polysilicon layer 30.
  • the first gate layer GE1 is disposed on the second insulating layer 40.
  • the third insulating layer 50 is disposed on the first gate layer GE1 and the second insulating layer 40.
  • the SD metal layer 60 is disposed on the third insulating layer 50.
  • the fourth insulating layer 70 is disposed on the SD metal layer 60 and the third insulating layer 50.
  • the anode metal layer 80 is disposed on the fourth insulating layer 70.
  • the fifth insulating layer 90 is disposed on the anode metal layer 80 and the fourth insulating layer 70.
  • the PS layer is disposed on the fifth insulating layer, and the light emitting layer and the cathode layer are disposed on the fifth insulating layer and the PS layer in this order.
  • the substrate 10 is a flexible substrate or a glass substrate.
  • the first insulating layer 20 is a buffer layer, which may be a silicon nitride layer or a silicon dioxide layer, and is deposited on the substrate 10 by a chemical vapor process.
  • the polysilicon layer 30 has an undoped region in the middle and doped regions on both sides of the undoped region.
  • the second insulating layer 40 is an isolation layer, which may be a silicon nitride layer or a silicon dioxide layer, and is deposited on the polysilicon layer 30 and the first insulating layer 20 by a chemical vapor process.
  • the first gate layer GE1 is made of a transparent conductive metal, such as ITO.
  • the third insulating layer 50 is an interlayer dielectric layer, which is a silicon nitride layer or a silicon dioxide layer, and is deposited on the first gate layer GE1 and the second insulating layer 40 by a chemical vapor process.
  • the SD metal layer 60 is made of a transparent conductive metal, such as ITO.
  • a source electrode 61, a drain electrode 62, and a first metal block 63 are formed thereon at intervals from each other.
  • the first metal block 63 is opposite to the first gate layer GE1 to form a first compensation capacitor C1.
  • the fourth insulating layer 70 and the fifth insulating layer 90 may be silicon nitride layers or silicon dioxide layers, and are formed by chemical vapor deposition.
  • the anode metal layer 80 is made of a transparent conductive metal, such as ITO.
  • the anode metal layer 80 includes an anode metal 81 and a second metal block 82 spaced from each other.
  • the second metal block 82 is opposite to the first metal block to form a second compensation capacitor C2.
  • the second insulating layer and the third insulating layer are provided with a drain via 54 and a source via 55.
  • the source of the SD metal layer is electrically connected to the polysilicon layer through the source via 55, and the SD metal layer
  • the drain electrode is electrically connected to the polysilicon layer through the drain via hole 55.
  • the fourth insulating layer is provided with an anode via 71, and the anode metal layer is electrically connected to the SD metal layer through the anode via 71.
  • the fifth insulating layer is provided with a first via hole; the light emitting layer is electrically connected to the anode metal layer through the first via hole.
  • FIG. 3 is a structural diagram of an OLED display panel in some embodiments of the present invention, including a substrate 10, a first insulating layer 20, a polysilicon layer 30, a second insulating layer 40, a first gate layer GE1, a first The three insulating layers 50, the SD metal layer 60, the fourth insulating layer 70, the anode metal layer 80, the fifth insulating layer 90, the PS layer 100, the light emitting layer (not shown), and the cathode layer (not shown).
  • the first insulating layer 20 is disposed on the substrate 10, the polysilicon layer 30 is disposed on the first insulating layer 20, and the second insulating layer 40 is disposed on the first insulating layer and the polysilicon layer 30.
  • the first gate layer GE1 is disposed on the second insulating layer 40.
  • the third insulating layer 50 is disposed on the first gate layer GE1 and the second insulating layer 40.
  • the SD metal layer 60 is disposed on the third insulating layer 50.
  • the fourth insulating layer 70 is disposed on the SD metal layer 60 and the third insulating layer 50.
  • the anode metal layer 80 is disposed on the fourth insulating layer 70.
  • the fifth insulating layer 90 is disposed on the anode metal layer 80 and the fourth insulating layer 70.
  • the PS layer is disposed on the fifth insulating layer, and the light emitting layer and the cathode layer are disposed on the fifth insulating layer and the PS layer in this order.
  • the substrate 10 is a flexible substrate or a glass substrate.
  • the first insulating layer 20 is a buffer layer, which may be a silicon nitride layer or a silicon dioxide layer, and is deposited on the substrate 10 by a chemical vapor process.
  • the polysilicon layer 30 has an undoped region in the middle and doped regions on both sides of the undoped region.
  • the second insulating layer 40 is an isolation layer, which may be a silicon nitride layer or a silicon dioxide layer, and is deposited on the polysilicon layer 30 and the first insulating layer 20 by a chemical vapor process.
  • the first gate layer GE1 is made of a transparent conductive metal, such as ITO.
  • the third insulating layer 50 is an interlayer dielectric layer, which is a silicon nitride layer or a silicon dioxide layer, and is deposited on the first gate layer GE1 and the second insulating layer 40 by a chemical vapor process.
  • the SD metal layer 60 is made of a transparent conductive metal, such as ITO.
  • a source electrode 61 and a drain electrode 62 spaced from each other are formed thereon.
  • the fourth insulating layer 70 and the fifth insulating layer 90 may be silicon nitride layers or silicon dioxide layers, and are formed by chemical vapor deposition.
  • the anode metal layer 80 is made of a transparent conductive metal, such as ITO.
  • the anode metal layer 80 includes an anode metal 81 and a second metal block 82 spaced apart from each other.
  • the first gate layer GE1 is opposite to the first metal block to form a third compensation capacitor C3.
  • the second insulating layer and the third insulating layer are provided with a drain via 54 and a source via 55.
  • the source of the SD metal layer is electrically connected to the polysilicon layer through the source via 55, and the SD metal layer
  • the drain electrode is electrically connected to the polysilicon layer through the drain via hole 55.
  • the fourth insulating layer is provided with an anode via 71, and the anode metal layer is electrically connected to the SD metal layer through the anode via 71.
  • the fifth insulating layer is provided with a first via hole; the light emitting layer is electrically connected to the anode metal layer through the first via hole.
  • the present invention provides an OLED display, which includes the OLED display panel in any one of the above embodiments.
  • the present invention forms a compensation capacitor by partially aligning the first gate layer and the SD metal layer and / or the anode metal layer with each other, and never requires two gate layers to form a compensation capacitor.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供了一种OLED显示面板及OLED显示器，OLED显示面板包括：基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容。本发明具有减少工艺流程的有益效果。

Description

OLED显示面板及OLED显示器 技术领域
本发明涉及显示领域，具体涉及一种OLED显示面板及OLED显示器。
 背景技术
在AMOLED显示装置的显示区域内，像素被设置成包括多行、多列的矩阵状，通常每一像素通常采用由两个薄膜晶体管与一个电容构成，俗称2T1C电路。这种2T1C的设计对下列因素都很敏感：TFT的阈值电压(Vth)和沟道迁移率(Mobility)、OLED的启动电压和量子效率以及供电电源的瞬变过程。故而一般采用补偿电路，来降低影响，例如7T1C,6T1C,6T2C等。
在像素的补偿电路中，电容被用来存储驱动 TFT开启的电位和补偿电位，一般采用两个栅极层之间形成补偿电容，采用两层栅极层会使得工艺流程复杂，较多，不利于降低成本。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明实施例的目的是提供一种OLED显示面板及OLED显示器，具有减少工艺流程的有益效果。
 技术解决方案
本发明实施例提供一种OLED显示面板，其包括：基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；
所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容；
所述SD金属层形成有间隔设置的源极、漏极以及第一金属块；所述第一金属块与所述第一栅极层相对以形成第一补偿电容；
所述阳极金属层包括相互间隔的阳极金属以及第二金属块；所述第二金属块与所述第一栅极层相对以形成第三补偿电容。
在本发明所述的OLED显示面板中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；
所述第一金属块与所述第二金属块相对以形成第二补偿电容。
在本发明所述的OLED显示面板中，还包括第一绝缘层、第二绝缘层、多晶硅层、第三绝缘层、第四绝缘层以及第五绝缘层；
所述第一绝缘层设置于所述基板上，所述多晶硅层设置于所述第一绝缘层上，所述第二绝缘层设置于所述多晶硅层以及所述第一绝缘层上；
所述第一栅极层设置于所述第二绝缘层上，所述第三绝缘层设置于所述第一栅极层以及所述第二绝缘层上，所述SD金属层设置于所述第三绝缘层上，所述第四绝缘层设置于所述SD金属层以及所述第三绝缘层上，所述阳极金属层设置于所述第四绝缘层上，所述第五绝缘层设置于所述阳极金属层以及所述第四绝缘层上。
在本发明所述的OLED显示面板中，所述第二绝缘层以及所述第三绝缘层设置有漏极过孔以及源极过孔，SD金属层的源极通过源极过孔与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔与该多晶硅层电连接。
在本发明所述的OLED显示面板中，第四绝缘层设置有阳极过孔，所述阳极金属层通过所述阳极过孔与所述SD金属层电连接。
在本发明所述的OLED显示面板中，所述第五绝缘层开设有第一过孔；
所述OLED显示面板还包括发光层以及阴极层；
所述发光层设置于所述第五绝缘层上，所述阴极层设置于所述发光层上；
所述发光层通过所述第一过孔与所述阳极金属层电连接。
在本发明所述的OLED显示面板中，所述第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层以及第五绝缘层可以为二氧化硅层或氮化硅层。
本发明实施例还提供一种OLED显示面板，包括：基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；
所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容。
在本发明所述的OLED显示面板中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块；所述第一金属块与所述第一栅极层相对以形成第一补偿电容。
在本发明所述的OLED显示面板中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；
所述第一金属块与所述第二金属块相对以形成第二补偿电容。
在本发明所述的OLED显示面板中，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；所述第二金属块与所述第一栅极层相对以形成第三补偿电容。
所述第一金属块与所述第二金属块相对以形成第三补偿电容。
在本发明所述的OLED显示面板中，还包括第一绝缘层、第二绝缘层、多晶硅层、第三绝缘层、第四绝缘层以及第五绝缘层；
所述第一绝缘层设置于所述基板上，所述多晶硅层设置于所述第一绝缘层上，所述第二绝缘层设置于所述多晶硅层以及所述第一绝缘层上；
所述第一栅极层设置于所述第二绝缘层上，所述第三绝缘层设置于所述第一栅极层以及所述第二绝缘层上，所述SD金属层设置于所述第三绝缘层上，所述第四绝缘层设置于所述SD金属层以及所述第三绝缘层上，所述阳极金属层设置于所述第四绝缘层上，所述第五绝缘层设置于所述阳极金属层以及所述第四绝缘层上。
在本发明所述的OLED显示面板中，所述第二绝缘层以及所述第三绝缘层设置有漏极过孔以及源极过孔，SD金属层的源极通过源极过孔与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔与该多晶硅层电连接。
在本发明所述的OLED显示面板中，第四绝缘层设置有阳极过孔，所述阳极金属层通过所述阳极过孔与所述SD金属层电连接。
在本发明所述的OLED显示面板中，所述第五绝缘层开设有第一过孔；
所述OLED显示面板还包括发光层以及阴极层；
所述发光层设置于所述第五绝缘层上，所述阴极层设置于所述发光层上；
所述发光层通过所述第一过孔与所述阳极金属层电连接。
在本发明所述的OLED显示面板中，所述第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层以及第五绝缘层可以为二氧化硅层或氮化硅层。
一种OLED显示器，其包括OLED显示面板，所述OLED显示面板包括：
基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；
所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容。
在本发明所述的OLED显示器中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块；所述第一金属块与所述第一栅极层相对以形成第一补偿电容。
在本发明所述的OLED显示器中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；
所述第一金属块与所述第二金属块相对以形成第二补偿电容。
在本发明所述的OLED显示器中，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；所述第二金属块与所述第一栅极层相对以形成第三补偿电容。
 有益效果
本发明通过将第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容，从未不需要两个栅极层来形成补偿电容，具有减少工艺流程的有益效果。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一些实施例中的OLED显面板的第一种结构示意图。
图2为本发明一些实施例中的OLED显面板的第二种结构示意图。
图3为本发明一些实施例中的OLED显面板的第三种结构示意图。
 本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明提供了一种OLED显示面板，包括：基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容。
请参阅图1，图1是本发明一些实施例中的OLED显示面板的结构图，包括基板10、第一绝缘层20、多晶硅层30、第二绝缘层40、第一栅极层GE1、第三绝缘层50、SD金属层60、第四绝缘层70、阳极金属层80、第五绝缘层90、PS层100、发光层（图未示）以及阴极层（图未示）。
其中，该第一绝缘层20设置于该基板10上，该多晶硅层30设置于该第一绝缘层20上，第二绝缘层40设置于该第一绝缘层以及该多晶硅层30上。该第一栅极层GE1设置于该第二绝缘层40上。该第三绝缘层50设置于该第一栅极层GE1以及该第二绝缘层40上。该SD金属层60设置于该第三绝缘层50上。该第四绝缘层70设置于该SD金属层60以及该第三绝缘层50上。该阳极金属层80设置于该第四绝缘层70上。该第五绝缘层90设置于该阳极金属层80以及该第四绝缘层70上。该PS层设置于该第五绝缘层上，该发光层以及阴极层依次设置于该第五绝缘层以及该PS层上。
其中，该基板10为柔性基板或者玻璃基板。
其中，该第一绝缘层20为缓冲层，其可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该基板10上。
其中，该多晶硅层30具有位于中部的未掺杂区域以及位于未掺杂区域区域两侧的掺杂区域。
其中，该第二绝缘层40为隔离层，其可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该多晶硅层30以及该第一绝缘层20上。
其中，第一栅极层GE1采用透明导电金属制成，例如ITO。
其中，第三绝缘层50层间介质层，其采用为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该第一栅极层GE1以及该第二绝缘层40上。
其中，该SD金属层60采用透明导电金属制成，例如ITO。其上形成有相互间隔的源极61、漏极62以及第一金属块63。其中，该第一金属块63与该第一栅极层GE1相对以形成第一补偿电容C1。
其中，该第四绝缘层70以及该第五绝缘层90可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积形成。
其中，该阳极金属层80采用透明导电金属制成，例如ITO。
其中，第二绝缘层以及所述第三绝缘层设置有漏极过孔54以及源极过孔55，SD金属层的源极通过源极过孔55与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔55与该多晶硅层电连接。第四绝缘层设置有阳极过孔71，所述阳极金属层通过所述阳极过孔71与所述SD金属层电连接。第五绝缘层开设有第一过孔；所述发光层通过所述第一过孔与所述阳极金属层电连接。
请参阅图2，图2是本发明一些实施例中的OLED显示面板的结构图，包括基板10、第一绝缘层20、多晶硅层30、第二绝缘层40、第一栅极层GE1、第三绝缘层50、SD金属层60、第四绝缘层70、阳极金属层80、第五绝缘层90、PS层100、发光层（图未示）以及阴极层（图未示）。
其中，该第一绝缘层20设置于该基板10上，该多晶硅层30设置于该第一绝缘层20上，第二绝缘层40设置于该第一绝缘层以及该多晶硅层30上。该第一栅极层GE1设置于该第二绝缘层40上。该第三绝缘层50设置于该第一栅极层GE1以及该第二绝缘层40上。该SD金属层60设置于该第三绝缘层50上。该第四绝缘层70设置于该SD金属层60以及该第三绝缘层50上。该阳极金属层80设置于该第四绝缘层70上。该第五绝缘层90设置于该阳极金属层80以及该第四绝缘层70上。该PS层设置于该第五绝缘层上，该发光层以及阴极层依次设置于该第五绝缘层以及该PS层上。
其中，该基板10为柔性基板或者玻璃基板。
其中，该第一绝缘层20为缓冲层，其可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该基板10上。
其中，该多晶硅层30具有位于中部的未掺杂区域以及位于未掺杂区域区域两侧的掺杂区域。
其中，该第二绝缘层40为隔离层，其可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该多晶硅层30以及该第一绝缘层20上。
其中，第一栅极层GE1采用透明导电金属制成，例如ITO。
其中，第三绝缘层50层间介质层，其采用为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该第一栅极层GE1以及该第二绝缘层40上。
其中，该SD金属层60采用透明导电金属制成，例如ITO。其上形成有相互间隔的源极61、漏极62以及第一金属块63。其中，该第一金属块63与该第一栅极层GE1相对以形成第一补偿电容C1。
其中，该第四绝缘层70以及该第五绝缘层90可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积形成。
其中，该阳极金属层80采用透明导电金属制成，例如ITO。该阳极金属层80包括相互间隔的阳极金属81以及第二金属块82，该第二金属块82与该第一金属块相对以形成第二补偿电容C2。
其中，第二绝缘层以及所述第三绝缘层设置有漏极过孔54以及源极过孔55，SD金属层的源极通过源极过孔55与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔55与该多晶硅层电连接。第四绝缘层设置有阳极过孔71，所述阳极金属层通过所述阳极过孔71与所述SD金属层电连接。第五绝缘层开设有第一过孔；所述发光层通过所述第一过孔与所述阳极金属层电连接。
请参阅图3，图3是本发明一些实施例中的OLED显示面板的结构图，包括基板10、第一绝缘层20、多晶硅层30、第二绝缘层40、第一栅极层GE1、第三绝缘层50、SD金属层60、第四绝缘层70、阳极金属层80、第五绝缘层90、PS层100、发光层（图未示）以及阴极层（图未示）。
其中，该第一绝缘层20设置于该基板10上，该多晶硅层30设置于该第一绝缘层20上，第二绝缘层40设置于该第一绝缘层以及该多晶硅层30上。该第一栅极层GE1设置于该第二绝缘层40上。该第三绝缘层50设置于该第一栅极层GE1以及该第二绝缘层40上。该SD金属层60设置于该第三绝缘层50上。该第四绝缘层70设置于该SD金属层60以及该第三绝缘层50上。该阳极金属层80设置于该第四绝缘层70上。该第五绝缘层90设置于该阳极金属层80以及该第四绝缘层70上。该PS层设置于该第五绝缘层上，该发光层以及阴极层依次设置于该第五绝缘层以及该PS层上。
其中，该基板10为柔性基板或者玻璃基板。
其中，该第一绝缘层20为缓冲层，其可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该基板10上。
其中，该多晶硅层30具有位于中部的未掺杂区域以及位于未掺杂区域区域两侧的掺杂区域。
其中，该第二绝缘层40为隔离层，其可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该多晶硅层30以及该第一绝缘层20上。
其中，第一栅极层GE1采用透明导电金属制成，例如ITO。
其中，第三绝缘层50层间介质层，其采用为氮化硅层或者二氧化硅层，采用化学气相工艺沉积于该第一栅极层GE1以及该第二绝缘层40上。
其中，该SD金属层60采用透明导电金属制成，例如ITO。其上形成有相互间隔的源极61、漏极62。
其中，该第四绝缘层70以及该第五绝缘层90可以为氮化硅层或者二氧化硅层，采用化学气相工艺沉积形成。
其中，该阳极金属层80采用透明导电金属制成，例如ITO。该阳极金属层80包括相互间隔的阳极金属81以及第二金属块82，该第一栅极层GE1与该第一金属块相对以形成第三补偿电容C3。
其中，第二绝缘层以及所述第三绝缘层设置有漏极过孔54以及源极过孔55，SD金属层的源极通过源极过孔55与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔55与该多晶硅层电连接。第四绝缘层设置有阳极过孔71，所述阳极金属层通过所述阳极过孔71与所述SD金属层电连接。第五绝缘层开设有第一过孔；所述发光层通过所述第一过孔与所述阳极金属层电连接。
本发明提供了一种OLED显示器，该OLED显示器包括上述任一实施例中的OLED显示面板。
本发明通过将第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容，从未不需要两个栅极层来形成补偿电容，具有减少工艺流程的有益效果。
以上对本发明实施例提供的OLED显示面板及OLED显示器进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种OLED显示面板，其包括：基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；
    所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容；
    所述SD金属层形成有间隔设置的源极、漏极以及第一金属块；所述第一金属块与所述第一栅极层相对以形成第一补偿电容；
    所述阳极金属层包括相互间隔的阳极金属以及第二金属块；所述第二金属块与所述第一栅极层相对以形成第三补偿电容。
  2. 根据权利要求1所述的OLED显示面板，其中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；
    所述第一金属块与所述第二金属块相对以形成第二补偿电容。
  3. 根据权利要求1所述的OLED显示面板，其中，5、根据权利要求1所述的OLED显示面板，其中，还包括第一绝缘层、第二绝缘层、多晶硅层、第三绝缘层、第四绝缘层以及第五绝缘层；
    所述第一绝缘层设置于所述基板上，所述多晶硅层设置于所述第一绝缘层上，所述第二绝缘层设置于所述多晶硅层以及所述第一绝缘层上；
    所述第一栅极层设置于所述第二绝缘层上，所述第三绝缘层设置于所述第一栅极层以及所述第二绝缘层上，所述SD金属层设置于所述第三绝缘层上，所述第四绝缘层设置于所述SD金属层以及所述第三绝缘层上，所述阳极金属层设置于所述第四绝缘层上，所述第五绝缘层设置于所述阳极金属层以及所述第四绝缘层上。
  4. 根据权利要求3所述的OLED显示面板，其中，所述第二绝缘层以及所述第三绝缘层设置有漏极过孔以及源极过孔，SD金属层的源极通过源极过孔与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔与该多晶硅层电连接。
  5. 根据权利要求3所述的OLED显示面板，其中，第四绝缘层设置有阳极过孔，所述阳极金属层通过所述阳极过孔与所述SD金属层电连接。
  6. 根据权利要求3所述的OLED显示面板，其中，所述第五绝缘层开设有第一过孔；
    所述OLED显示面板还包括发光层以及阴极层；
    所述发光层设置于所述第五绝缘层上，所述阴极层设置于所述发光层上；
    所述发光层通过所述第一过孔与所述阳极金属层电连接。
  7. 根据权利要求3所述的OLED显示面板，其中，所述第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层以及第五绝缘层可以为二氧化硅层或氮化硅层。
  8. 一种OLED显示面板，其包括：基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；
    所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容。
  9. 根据权利要求8所述的OLED显示面板，其中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块；所述第一金属块与所述第一栅极层相对以形成第一补偿电容。
  10. 根据权利要求9所述的OLED显示面板，其中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；
    所述第一金属块与所述第二金属块相对以形成第二补偿电容。
  11. 根据权利要求8所述的OLED显示面板，其中，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；所述第二金属块与所述第一栅极层相对以形成第三补偿电容。
  12. 根据权利要求8所述的OLED显示面板，其中，还包括第一绝缘层、第二绝缘层、多晶硅层、第三绝缘层、第四绝缘层以及第五绝缘层；
    所述第一绝缘层设置于所述基板上，所述多晶硅层设置于所述第一绝缘层上，所述第二绝缘层设置于所述多晶硅层以及所述第一绝缘层上；
    所述第一栅极层设置于所述第二绝缘层上，所述第三绝缘层设置于所述第一栅极层以及所述第二绝缘层上，所述SD金属层设置于所述第三绝缘层上，所述第四绝缘层设置于所述SD金属层以及所述第三绝缘层上，所述阳极金属层设置于所述第四绝缘层上，所述第五绝缘层设置于所述阳极金属层以及所述第四绝缘层上。
  13. 根据权利要求12所述的OLED显示面板，其中，所述第二绝缘层以及所述第三绝缘层设置有漏极过孔以及源极过孔，SD金属层的源极通过源极过孔与所述多晶硅层电连接，SD金属层的漏极通过该漏极过孔与该多晶硅层电连接。
  14. 根据权利要求12所述的OLED显示面板，其中，第四绝缘层设置有阳极过孔，所述阳极金属层通过所述阳极过孔与所述SD金属层电连接。
  15. 根据权利要求12所述的OLED显示面板，其中，所述第五绝缘层开设有第一过孔；
    所述OLED显示面板还包括发光层以及阴极层；
    所述发光层设置于所述第五绝缘层上，所述阴极层设置于所述发光层上；
    所述发光层通过所述第一过孔与所述阳极金属层电连接。
  16. 根据权利要求12所述的OLED显示面板，其中，所述第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层以及第五绝缘层可以为二氧化硅层或氮化硅层。
  17. 一种OLED显示器，其OLED显示面板，所述OLED显示面板包括：
    基板以及设置于所述基板上的第一栅极层、SD金属层、阳极金属层；
    所述第一栅极层与所述SD金属层的局部和/或所述阳极金属层是局部相互正对以形成补偿电容。
  18. 根据权利要求17所述的OLED显示器，其中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块；所述第一金属块与所述第一栅极层相对以形成第一补偿电容。
  19. 根据权利要求18所述的OLED显示器，其中，所述SD金属层形成有间隔设置的源极、漏极以及第一金属块，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；
    所述第一金属块与所述第二金属块相对以形成第二补偿电容。
  20. 根据权利要求17所述的OLED显示器，其中，所述阳极金属层包括相互间隔的阳极金属以及第二金属块；所述第二金属块与所述第一栅极层相对以形成第三补偿电容。
PCT/CN2018/100465 2018-05-31 2018-08-14 Oled显示面板及oled显示器 Ceased WO2019227682A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/311,691 US10868098B2 (en) 2018-05-31 2018-08-14 OLED display panel and OLED display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810549841.6 2018-05-31
CN201810549841.6A CN108831906A (zh) 2018-05-31 2018-05-31 Oled显示面板及oled显示器

Publications (1)

Publication Number Publication Date
WO2019227682A1 true WO2019227682A1 (zh) 2019-12-05

Family

ID=64145421

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/100465 Ceased WO2019227682A1 (zh) 2018-05-31 2018-08-14 Oled显示面板及oled显示器

Country Status (3)

Country Link
US (1) US10868098B2 (zh)
CN (1) CN108831906A (zh)
WO (1) WO2019227682A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109860239B (zh) * 2018-12-13 2021-03-16 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法、显示装置
CN110571242B (zh) * 2019-08-12 2021-12-28 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板
US11676532B2 (en) 2020-11-13 2023-06-13 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, display panel, and display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140320544A1 (en) * 2013-04-24 2014-10-30 Samsung Display Co., Ltd. Organic light emitting diode display
CN107452757A (zh) * 2017-07-31 2017-12-08 上海天马微电子有限公司 一种显示面板、其制作方法及显示装置
CN107785399A (zh) * 2017-10-26 2018-03-09 武汉天马微电子有限公司 一种显示面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7987814B2 (en) * 2008-04-07 2011-08-02 Applied Materials, Inc. Lower liner with integrated flow equalizer and improved conductance
US9673267B2 (en) * 2013-03-26 2017-06-06 Lg Display Co., Ltd. Organic light emitting diode display device having a capacitor with stacked storage electrodes and method for manufacturing the same
CN103400548B (zh) * 2013-07-31 2016-03-16 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
KR102280959B1 (ko) * 2013-12-16 2021-07-26 삼성디스플레이 주식회사 표시장치 및 그 제조 방법
GB2540334B (en) * 2015-04-22 2019-12-11 Flexenable Ltd A control component for a current-driven optical media
CN107481938B (zh) * 2017-09-26 2020-02-18 武汉华星光电技术有限公司 显示面板、显示装置及低温多晶硅薄膜晶体管的制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140320544A1 (en) * 2013-04-24 2014-10-30 Samsung Display Co., Ltd. Organic light emitting diode display
CN107452757A (zh) * 2017-07-31 2017-12-08 上海天马微电子有限公司 一种显示面板、其制作方法及显示装置
CN107785399A (zh) * 2017-10-26 2018-03-09 武汉天马微电子有限公司 一种显示面板及显示装置

Also Published As

Publication number Publication date
US10868098B2 (en) 2020-12-15
US20200127071A1 (en) 2020-04-23
CN108831906A (zh) 2018-11-16

Similar Documents

Publication Publication Date Title
CN103066212B (zh) 有机发光显示装置及其制造方法
US10608206B2 (en) Display panel and display device
CN103646950B (zh) 像素结构
CN112951846B (zh) 显示面板及其制造方法、显示装置
CN105140260A (zh) 有机发光二极管阵列基板及其制作方法、显示装置
CN109148480B (zh) 阵列基板
WO2015100808A1 (zh) 一种具有氧化物薄膜电晶体的发光装置及其制造方法
US20220359637A1 (en) Display panel and display device
US20170194405A1 (en) Organic light emitting display and method of manufacturing the same
CN108269855A (zh) 驱动薄膜晶体管以及使用其的有机发光显示装置
WO2021227106A1 (zh) 显示面板及其制作方法
WO2019184321A1 (zh) 阵列基板、显示面板及显示装置
CN110571242A (zh) 阵列基板及显示面板
WO2019227682A1 (zh) Oled显示面板及oled显示器
CN111755462A (zh) 阵列基板及其制造方法
CN109449164B (zh) 一种tft基板、显示面板及显示装置
US20190051707A1 (en) Oled touch display panel and oled touch display
CN116034475A (zh) 显示基板、显示面板及显示装置
WO2022047921A1 (zh) 显示面板
WO2023241297A9 (zh) 显示面板及其制造方法、显示装置
CN115461806B (zh) 像素电路、显示面板及显示装置
CN104992945A (zh) 显示基板及其制作方法以及显示装置
CN110649003A (zh) 半导体基板、阵列基板、逆变器电路及开关电路
US11495620B2 (en) Display panel, fabrication method thereof, and display device
TWI703735B (zh) 半導體基板、陣列基板、逆變器電路及開關電路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18920692

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18920692

Country of ref document: EP

Kind code of ref document: A1