WO2019216159A1 - Power semiconductor module and electric power converter - Google Patents

Power semiconductor module and electric power converter Download PDF

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Publication number
WO2019216159A1
WO2019216159A1 PCT/JP2019/016766 JP2019016766W WO2019216159A1 WO 2019216159 A1 WO2019216159 A1 WO 2019216159A1 JP 2019016766 W JP2019016766 W JP 2019016766W WO 2019216159 A1 WO2019216159 A1 WO 2019216159A1
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WO
WIPO (PCT)
Prior art keywords
lead terminal
power semiconductor
chip
semiconductor module
chip capacitor
Prior art date
Application number
PCT/JP2019/016766
Other languages
French (fr)
Japanese (ja)
Inventor
裕一郎 鈴木
真紀 長谷川
脩平 横山
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三菱電機株式会社
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Filing date
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Publication of WO2019216159A1 publication Critical patent/WO2019216159A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a power semiconductor module and a power conversion device.
  • Patent Document 1 discloses a lead frame, a power chip disposed on the lead frame, and an IC that is disposed on the lead frame and drives the power chip in a transfer mold package.
  • a semiconductor device including a chip and a bootstrap capacitor connected to an IC chip is disclosed.
  • the bootstrap capacitor (BSC) is joined to the lead frame via an insulating adhesive.
  • the bootstrap capacitor has an electrode. The electrode of the bootstrap capacitor and the IC chip are connected via a wire.
  • An object of the present invention is to provide a power semiconductor module that can be miniaturized.
  • the objective of this invention is providing the power converter device which can be reduced in size.
  • a power semiconductor module includes a plurality of lead terminals, a power semiconductor chip, a first chip capacitor, a first electronic element, and a sealing member.
  • the plurality of lead terminals include a first lead terminal and a second lead terminal spaced from the first lead terminal.
  • the first chip capacitor includes a first electrode and a second electrode.
  • the first electronic element is an element different from the power semiconductor chip and the first chip capacitor.
  • the sealing member seals the power semiconductor chip, the first chip capacitor, and the first electronic element.
  • the power semiconductor chip is bonded to at least one of the plurality of lead terminals.
  • the first electrode and the second electrode of the first chip capacitor are joined to the first lead terminal and the second lead terminal, respectively, at the first conductive adhesive portion.
  • a first electronic element is mounted on the first lead terminal.
  • the power conversion device includes a main conversion circuit and a control circuit.
  • the main conversion circuit includes the power semiconductor module, and converts input power and outputs the converted power.
  • the control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
  • the first electrode and the second electrode of the first chip capacitor are the first conductive adhesive portion, and the first lead terminal and the second lead terminal.
  • the thickness of the power semiconductor module can be made thinner and smaller than when the wire is connected to the first chip capacitor.
  • a power conversion device includes a main conversion circuit having the power semiconductor module. Therefore, the power converter according to the present invention can be downsized.
  • FIG. 1 is a schematic plan view of a power semiconductor module according to Embodiment 1.
  • FIG. 2 is a schematic partial enlarged plan view of a region II shown in FIG. 1 of the power semiconductor module according to the first embodiment.
  • FIG. 3 is a schematic partially enlarged cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line III-III shown in FIG.
  • FIG. 4 is a schematic partial enlarged plan view of a region IV shown in FIG. 1 of the power semiconductor module according to the first embodiment.
  • FIG. 5 is a partially enlarged schematic cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line VV shown in FIG.
  • FIG. 3 is a diagram showing a circuit of an electronic element included in the power semiconductor module according to Embodiment 1.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment.
  • FIG. 6 is a partially enlarged plan view for explaining a modification of the power semiconductor module according to the first embodiment.
  • FIG. 6 is a partially enlarged plan view for explaining a modification of the power semiconductor module according to the first embodiment.
  • FIG. 6 is a partially enlarged plan view for explaining a modification of the power semiconductor module according to the first embodiment.
  • FIG. 4 is a diagram showing a flowchart of a method for manufacturing a power semiconductor module according to the first embodiment.
  • FIG. 3 is a schematic plan view showing one step in the method for manufacturing the power semiconductor module according to the first embodiment.
  • FIG. 13 is a schematic partial enlarged sectional view taken along a sectional line XIII-XIII of the process shown in FIG. 12 in the method for manufacturing the power semiconductor module of the first embodiment.
  • FIG. 6 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment.
  • FIG. 6 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment.
  • FIG. 13 is a schematic plan view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the power semiconductor module according to the first embodiment.
  • FIG. 17 is a schematic partial enlarged cross-sectional view taken along a cross-sectional line XVII-XVII in the process shown in FIG. 16 in the method for manufacturing the power semiconductor module according to the first embodiment.
  • FIG. 3 is a diagram showing a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. It is a schematic sectional drawing which shows the power semiconductor module of a comparative example. It is a figure which shows the graph for demonstrating the charging / discharging waveform in the chip capacitor of a power semiconductor module.
  • 6 is a schematic cross-sectional view of a power semiconductor module according to Embodiment 2.
  • FIG. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 10 is a schematic plan view of a power semiconductor module according to a modification example of the second embodiment.
  • FIG. 24 is a schematic partially enlarged plan view of a region XXIV of the power semiconductor module shown in FIG. 23.
  • FIG. 25 is a schematic cross-sectional view taken along line XXV-XXV in FIG. 24.
  • FIG. 10 is a block diagram illustrating a configuration of a power conversion system according to a third embodiment.
  • FIG. ⁇ Configuration of power semiconductor module> 1 is a schematic plan view of a power semiconductor module according to Embodiment 1.
  • FIG. FIG. 2 is a schematic partial enlarged plan view of region II shown in FIG. 1 of the power semiconductor module according to the first embodiment.
  • FIG. 3 is a schematic partial enlarged cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line III-III shown in FIG. 4 is a schematic partial enlarged plan view of region IV shown in FIG. 1 of the power semiconductor module according to the first embodiment.
  • 5 is a partially enlarged schematic cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line VV shown in FIG.
  • FIG. 6 is a diagram illustrating a circuit of an electronic element included in the power semiconductor module according to the first embodiment.
  • the power semiconductor module 1 includes a plurality of lead terminals, a power semiconductor chip 20, first to third chip capacitors 27, 127, 227, a power semiconductor chip 20, and first to third chip capacitors 27, 127, The first to third electronic elements 25, 125, and 225, which are different from 227, and the sealing member 40 are mainly provided.
  • the power semiconductor module 1 may further include a control semiconductor chip 23.
  • the plurality of lead terminals are made of, for example, metal, and the first lead terminal 11, the second lead terminal 12, the third lead terminal 111, the fourth lead terminal 112, and the fifth lead terminal 211. And a sixth lead terminal 212, a seventh lead terminal 13, an eighth lead terminal 14, and a ninth lead terminal 15.
  • the first to ninth lead terminals 11, 12, 111, 112, 211, 212, 13, 14, and 15 are separated from each other.
  • the first chip capacitor 27 includes a first electrode 28a and a second electrode 28b.
  • the first chip capacitor 27 has a structure in which a first electrode 28a and a second electrode 28b are connected to both ends of a ceramic main body 28c.
  • the first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the first conductive adhesive portion 37, respectively. Yes.
  • a first electronic element 25 is mounted on the first lead terminal 11.
  • the second chip capacitor 127 includes a third electrode 128a and a fourth electrode 128b.
  • the second chip capacitor 127 has a structure in which a third electrode 128a and a fourth electrode 128b are connected to both ends of the ceramic main body 128c.
  • the third electrode 128a and the fourth electrode 128b of the second chip capacitor 127 are joined to the third lead terminal 111 and the fourth lead terminal 112 by the second conductive adhesive portion 137, respectively. Yes.
  • a second electronic element 125 is mounted on the third lead terminal 111.
  • the third chip capacitor 227 includes a fifth electrode 228a and a sixth electrode 228b.
  • the third chip capacitor 227 has a structure in which a fifth electrode 228a and a sixth electrode 228b are connected to both ends of the ceramic main body 228c.
  • the fifth electrode 228a and the sixth electrode 228b of the third chip capacitor 227 are joined to the fifth lead terminal 211 and the sixth lead terminal 212 by the third conductive adhesive portion 237, respectively. Yes.
  • a third electronic element 225 is mounted on the fifth lead terminal 211.
  • the plurality of lead terminals include a plurality of pads (for example, a first pad 11a, a second pad 12a, a third pad 111a, a fourth pad 112a, a fifth pad 211a, a sixth pad 212a, a seventh pad).
  • the pad 14a and the eighth pad 15a) may be included.
  • the first lead terminal 11 may include a first pad 11 a that is a wide portion of the first lead terminal 11.
  • the second lead terminal 12 may include a second pad 12 a that is a wide portion of the second lead terminal 12.
  • the third lead terminal 111 may include a third pad 111 a that is a wide portion of the third lead terminal 111.
  • the fourth lead terminal 112 may include a fourth pad 112 a that is a wide portion of the fourth lead terminal 112.
  • the fifth lead terminal 211 may include a fifth pad 211 a that is a wide portion of the fifth lead terminal 211.
  • the sixth lead terminal 212 may include a sixth pad 212 a that is a wider portion of the sixth lead terminal 212.
  • the eighth lead terminal 14 may include a seventh pad 14 a that is a wide portion of the eighth lead terminal 14.
  • the ninth lead terminal 15 may include an eighth pad 15 a that is a wide portion of the ninth lead terminal 15.
  • the ninth lead terminal 15 includes a step portion 15b between the eighth pad 15a and the fifth protruding portion 15c.
  • the step portion 15b includes a first end connected to the eighth pad 15a and a second end opposite to the first end. The second end is above the first end.
  • the plurality of lead terminals include protrusions protruding from the sealing member 40.
  • the protrusion is bent.
  • the first lead terminal 11 includes a first protrusion 11 c that protrudes from the sealing member 40.
  • the first protrusion 11c includes a first protrusion 11d extending horizontally from the first pad 11a and a second protrusion 11e extending upward from the first protrusion 11d.
  • the second lead terminal 12 includes a second protrusion 12 c that protrudes from the sealing member 40.
  • the second protrusion 12c includes a third protrusion 12d extending horizontally from the second pad 12a and a fourth protrusion 12e extending upward from the third protrusion 12d.
  • the third lead terminal 111 includes a third protrusion 111 c that protrudes from the sealing member 40.
  • the third protrusion 111c includes a fifth protrusion 111d extending horizontally from the third pad 111a and a sixth protrusion 111e extending upward from the fifth protrusion 111d.
  • the fourth lead terminal 112 includes a fourth projecting portion 112 c that projects from the sealing member 40.
  • the fourth protrusion 112c includes a seventh protrusion 112d extending horizontally from the fourth pad 112a and an eighth protrusion 112e extending upward from the seventh protrusion 112d.
  • the ninth lead terminal 15 includes a fifth projecting portion 15 c that projects from the sealing member 40.
  • the fifth projecting portion 15c includes a ninth projecting portion 15d extending horizontally from the second end of the stepped portion 15b and a tenth projecting portion 15e extending upward from the ninth projecting portion 15d.
  • electronic components power semiconductor chip 20, control semiconductor chip 23, first chip capacitor 27, first electronic element 25
  • DIP dual in-line package
  • the plurality of lead terminals are made of a conductive material such as copper, aluminum, and alloys thereof.
  • a plating layer may be formed on the surfaces of the plurality of lead terminals to prevent oxidation.
  • Nickel and silver can be used as a material constituting the plating layer.
  • Some of the plurality of lead terminals may be covered with a plating part 17 such as a silver plating part in order to improve the bondability and the mountability.
  • the plated portion 17 may be formed of a material that is less likely to be oxidized than the material constituting the plurality of lead terminals.
  • the material that is less likely to be oxidized than the material constituting the plurality of lead terminals is, for example, a noble metal material such as silver or nickel.
  • the plating part 17 may be formed in the innermost part of the first lead terminal 11.
  • a plating portion 17 may be formed on the innermost portion of the second lead terminal 12.
  • a plating portion 17 may be formed on a part of the eighth pad 15 a of the ninth lead terminal 15.
  • the first lead terminal 11 may include a first through hole 16a.
  • the first through hole 16 a is formed on the outer side (the first protruding portion 11 c side) with respect to the first chip capacitor 27.
  • the first through hole 16a may be formed on the inner side (opposite to the first projecting portion 11c) with respect to the first chip capacitor 27, or on the outer side and the inner side with respect to the first chip capacitor 27. And may be formed.
  • the first through hole 16a and the first electronic element 25 are preferably disposed in regions opposite to each other.
  • the second lead terminal 12 may include a second through hole 16b.
  • the second through hole 16 b is formed on the outer side (the second projecting portion 12 c side) with respect to the first chip capacitor 27.
  • the second through hole 16b may be formed on the inner side (opposite to the second protrusion 12c) with respect to the first chip capacitor 27, or on the outer side and the inner side with respect to the first chip capacitor 27. And may be formed.
  • the power semiconductor chip 20 may be, for example, a reverse conducting IGBT (RC-IGBT), an insulated gate bipolar transistor (IGBT) including a free wheel diode (FWD), a metal oxide semiconductor field effect transistor (MOSFET), or a diode. Good.
  • the power semiconductor chip 20 has a rated current of 1 A or more and a rated voltage of 100 V or more.
  • the power semiconductor chip 20 may be formed of a semiconductor material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).
  • the power semiconductor module 1 may include one power semiconductor chip 20 or a plurality of power semiconductor chips 20. In the present embodiment, the power semiconductor module 1 includes a high voltage power semiconductor chip 20 and a low voltage power semiconductor chip 20. The high voltage power semiconductor chip 20 is bonded to the eighth pad 15 a of the ninth lead terminal 15.
  • the power semiconductor chip 20 is bonded to at least one of the plurality of lead terminals (the ninth lead terminal 15). At least one of the plurality of lead terminals (the ninth lead terminal 15) to which the power semiconductor chip 20 is bonded is the first to eighth lead terminals 11, 12, 111, 112, 211, 212, 13, 14 Is different.
  • the power semiconductor chip 20 is joined to the eighth pad 15 a (particularly, the plating portion 17) of the ninth lead terminal 15 by the solder joint portion 30.
  • the solder joint 30 can efficiently transfer the heat generated in the power semiconductor chip 20 to the ninth lead terminal 15.
  • the power semiconductor chip 20 is electrically connected to a plurality of lead terminals (particularly, the plating portion 17) via the conductive wires 29.
  • a conductive adhesive typified by silver paste or a sintered material containing silver or copper may be used. Since the power semiconductor chip 20 is driven by a three-phase inverter, a total of six power semiconductor chips 20 are mounted, three on the P side and three on the N side.
  • the control semiconductor chip 23 is configured to control the power semiconductor chip 20.
  • the control semiconductor chip 23 may be configured to control the gate voltage of the power semiconductor chip 20.
  • the control semiconductor chip 23 may be configured to detect a current flowing through the power semiconductor chip 20.
  • the power semiconductor module 1 is an intelligent power module (IPM) that includes a power semiconductor chip 20 and a control semiconductor chip 23 configured to control the power semiconductor chip 20.
  • the control semiconductor chip 23 is electrically connected to the power semiconductor chip 20 via a conductive wire 29.
  • the control semiconductor chip 23 is electrically connected to the first lead terminal 11 and the second lead terminal 12 via a conductive wire 29.
  • the power semiconductor module 1 may include one control semiconductor chip 23 or a plurality of control semiconductor chips 23.
  • the power semiconductor module 1 controls the high-voltage control semiconductor chip 23 configured to control the high-voltage power semiconductor chip 20 and the low-voltage power semiconductor chip 20.
  • the low-voltage control semiconductor chip 23 is included.
  • the control semiconductor chip 23 is bonded to at least one of the plurality of lead terminals (eighth lead terminal 14). At least one of the plurality of lead terminals (eighth lead terminal 14) to which the control semiconductor chip 23 is bonded is the first to seventh lead terminals 11, 12, 111, 112, 211, 212, 13 and This is different from the ninth lead terminal 15.
  • the control semiconductor chip 23 is bonded to the seventh pad 14 a of the eighth lead terminal 14 by a conductive bonding portion 33.
  • the conductive joint portion 33 may be, for example, a solder joint portion or a conductive adhesive portion 35 described later.
  • an eighth pad 15a on which the power semiconductor chip 20 is mounted As shown in FIG. 3, an eighth pad 15a on which the power semiconductor chip 20 is mounted, an eighth lead terminal 14 (seventh pad 14a (see FIG. 1)) on which the control semiconductor chip 23 is mounted, and Are offset.
  • the amount of offset can be arbitrarily selected as long as the seventh pad 14a and the eighth pad 15a are not exposed to the outside when sealed by the sealing member 40 and are sufficiently insulated from the outside.
  • the first to third electronic elements 25, 125, and 225 are different types of electronic components from the power semiconductor chip 20, the control semiconductor chip 23, and the first to third chip capacitors 27, 127, and 227.
  • the first to third electronic elements 25, 125, and 225 constitute a part of a control circuit that controls the power semiconductor chip 20.
  • the first to third electronic elements 25, 125, 225 may be passive electronic components.
  • the passive electronic component is, for example, a diode 25a such as a chip diode or a resistor 25b such as a chip resistor.
  • the diode 25a which is an example of a passive electronic component, has, for example, a rated current of less than 1A and a rated voltage of less than 100V.
  • the first to third electronic elements 25, 125, 225 are rectifying semiconductor chips such as chip diodes.
  • the rectifying semiconductor chip may include a resistor 25b as a current limiting resistor in addition to the diode 25a.
  • the rectifying semiconductor chip incorporating the resistor 25b and any one of the first to third chip capacitors 27, 127, 227 may constitute a bootstrap circuit.
  • the first to third electronic elements 25, 125, 225 may be bootstrap diodes (BSD).
  • the bootstrap circuit is a circuit that creates a P-side gate drive power supply only by an N-side gate drive power supply.
  • the bootstrap circuit includes a rectifying semiconductor chip and a capacitor in a circuit of a gate driving unit.
  • the bootstrap circuit is different from a snubber circuit disposed on the output side (between drain and source, between collector and emitter) of a switching element (for example, power semiconductor chip 20).
  • the first electronic element 25 may be electrically connected to the control semiconductor chip 23 via the conductive wire 29 and the first lead terminal 11.
  • the first electronic element 25 may be electrically connected to the seventh lead terminal 13 (particularly, the plating portion 17) via the conductive wire 29.
  • the second and third electronic elements 125 and 225 may be electrically connected to the control semiconductor chip 23 via the conductive wire 29 and the third lead terminal 111 or the fifth lead terminal 211. Good.
  • the second and third electronic elements 125 and 225 may be electrically connected to the seventh lead terminal 13 (particularly, the plating portion 17) via the conductive wire 29.
  • the bootstrap circuit described above for example, three pairs of electronic elements that are rectifying semiconductor chips and chip capacitors are prepared in order to drive the power semiconductor chip 20 for three phases. That is, a pair of the first electronic element 25 and the first chip capacitor 27, a pair of the second electronic element 125 and the second chip capacitor 127, and a third electronic element 225 and the third chip capacitor 227. Prepare a pair, with. At this time, the first to third electronic elements 25, 125, 225 are preferably arranged at equal intervals as shown in FIG. The first to third chip capacitors 27, 127, 227 are also preferably arranged at equal intervals.
  • a pair of the first electronic element 25 and the first chip capacitor 27 corresponding to the three phases, a pair of the second electronic element 125 and the second chip capacitor 127, and the first It is preferable that the relative arrangement of the electronic element and the chip capacitor is the same among the three pairs of the three electronic elements 225 and the third chip capacitor 227. Further, the distance L21 between the first electronic element 25 and the first chip capacitor 27, the distance L22 between the second electronic element 125 and the second chip capacitor 127, and the third electronic element 225. It is preferable that the distance L23 between the first chip capacitor 227 and the third chip capacitor 227 is the same. In this case, variation in wiring resistance between the electronic element of each phase and the chip capacitor can be suppressed.
  • the shape of 212 is preferably the same among the three phases. Specifically, the first lead terminal 11, the third lead terminal 11, and the third lead terminal 11 located on the outer peripheral side from directly below the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227.
  • the lead terminals 111 and the fifth lead terminal 211 preferably have the same shape. Further, the second lead terminal 12 and the fourth lead terminal located on the outer peripheral side from directly below the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227.
  • the sixth lead terminal 212 preferably have the same shape. Then, even when the positions of the first to third chip capacitors 27, 127, and 227 are slightly shifted at the time of mounting, it can be easily compared with the mounting position of the adjacent chip capacitor. As a result, when visual inspection is performed visually, it is easy to notice mounting position deviations of the first to third chip capacitors 27, 127, and 227.
  • the first to third electronic elements 25, 125, and 225 are joined to one of a plurality of lead terminals by a conductive adhesive portion 35. Specifically, the first to third electronic elements 25, 125, and 225 are connected to the first lead terminal 11, the third lead terminal 111, and the fifth lead terminal 211 by the conductive adhesive portion 35, respectively. It is joined.
  • the conductive adhesive portion 35 includes a conductive filler with a first content rate.
  • the conductive adhesive portion 35 includes a first resin and a conductive filler dispersed in the first resin.
  • the conductive filler may be made of, for example, one or more conductive materials selected from the group consisting of silver, nickel, and copper. In the present specification, the conductive filler also includes conductive particles.
  • the first resin may be, for example, an epoxy resin.
  • the first content may be 65% by weight or less, or 60% by weight or less.
  • the 1st content rate represents the ratio of the weight of the electroconductive filler contained in the electroconductive adhesion part 35 with respect to the weight of the electroconductive adhesion part 35 in the unit of weight%.
  • the first to third chip capacitors 27, 127, and 227 may be, for example, surface mount type multilayer ceramic capacitors.
  • the first to third chip capacitors 27, 127, and 227 constitute a part of a control circuit that controls the power semiconductor chip 20.
  • the first to third chip capacitors 27, 127, and 227 may be bootstrap capacitors (BSCs) that constitute a part of the bootstrap circuit.
  • BSCs bootstrap capacitors
  • the capacities of the first to third chip capacitors 27, 127, and 227 are the power consumption of the control semiconductor chip 23, the gate capacity of the power semiconductor chip 20, and the charging time of the first to third chip capacitors 27, 127, and 227. And appropriately determined according to the discharge time.
  • Electronic components joined to a plurality of lead terminals power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225) Among them, the first to third chip capacitors 27, 127, 227 are the tallest.
  • the first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are the first conductive adhesive portion 37, and the first lead terminal 11, the second lead terminal 12, and the like. Are joined to each other. For this reason, the wiring resistance between the 1st electronic element 25 and the 1st chip capacitor 27 can be reduced rather than the case where both are connected using a wire.
  • the first conductive adhesive portion 37 includes a second resin and a conductive filler dispersed in the second resin.
  • the conductive filler included in the first conductive adhesive portion 37 is the same material as the conductive filler included in the conductive adhesive portion 35.
  • the second resin may be an epoxy resin.
  • the second resin may be the same material as the first resin, or may be a different material.
  • the first surface 11s (see FIG. 3) of the first lead terminal 11 facing the first electrode 28a may be made of copper or tin.
  • the second surface 12s (see FIG. 3) of the second lead terminal 12 facing the second electrode 28b may be made of copper or tin.
  • the first surface 11s of the first lead terminal 11 and the second surface 12s of the second lead terminal 12 may be exposed from the plated portion 17 formed of a material that is not easily oxidized.
  • the first surface 11 s of the first lead terminal 11 and the second surface 12 s of the second lead terminal 12 are more easily oxidized than the plated portion 17.
  • the first conductive adhesive portion 37 has a relatively low electrical resistance.
  • the first electrode 28a and the second electrode 28b of the first chip capacitor 27 are preferably made of, for example, gold, silver, or palladium, but may be made of nickel, copper, or tin.
  • the surface of the first electrode 28a and the surface of the second electrode 28b may not be formed of a material that is difficult to be oxidized, such as silver.
  • the surface of the first electrode 28 a and the surface of the second electrode 28 b are more easily oxidized than the plated portion 17.
  • the first conductive adhesive portion 37 has a relatively low electrical resistance. Therefore, even if the first electrode 28a and the second electrode 28b are made of copper or tin, the gap between the first lead terminal 11 and the first chip capacitor 27 via the conductive adhesive portion 35 is not limited. Low resistance and reliable electrical connection and low resistance and reliable electrical connection between the second lead terminal 12 and the first chip capacitor 27 via the first conductive adhesive portion 37 And you can get
  • the first electronic element 25 and the first chip capacitor 27 may be joined to the first lead terminal 11.
  • the distance L2 which is the distance between the first electronic element 25 and the first chip capacitor 27, can be made relatively small.
  • the wiring resistance between the first electronic element 25 and the first chip capacitor 27 can be reduced.
  • the distance L1 (see FIG. 3) that is the distance between the first chip capacitor 27 and the power semiconductor chip 20 is the distance that is the distance between the first electronic element 25 and the first chip capacitor 27. It can be larger than L2.
  • an electric circuit for example, a bootstrap circuit
  • the first electronic element 25 for example, a rectifying semiconductor chip incorporating the diode 25a and the resistor 25b
  • the sealing member 40 includes a part of a plurality of lead terminals, the power semiconductor chip 20, the control semiconductor chip 23, the first to third chip capacitors 27, 127, 227, and the first to third electrons.
  • the elements 25, 125, 225 and the conductive wire 29 are sealed.
  • the sealing member 40 has electrical insulation.
  • the sealing member 40 may be formed of a mold resin.
  • the sealing member 40 may be made of, for example, a resin material selected from the group consisting of epoxy resins, polyimide resins, polyamide resins, polyamideimide resins, fluorine resins, isocyanate resins, silicone resins, and combinations thereof.
  • a base material made of an insulating resin such as an epoxy resin may be used in which a material such as silica or alumina is mixed in order to improve heat conduction.
  • the first protrusion 11c protrudes from the portion 41a of the sealing member 40.
  • the shortest distance d between the portion 41 a of the sealing member 40 and the first chip capacitor 27 may be 5 times or less the thickness of the first lead terminal 11.
  • the thickness of the first lead terminal 11 may be 0.2 mm or more, for example.
  • the thickness of the first lead terminal 11 may be, for example, 2.0 mm or less.
  • the second protrusion 12 c protrudes from the portion 41 b of the sealing member 40.
  • the shortest distance d between the portion 41 b of the sealing member 40 and the first chip capacitor 27 may be 5 times or less the thickness t of the second lead terminal 12.
  • the thickness t of the second lead terminal 12 may be 0.2 mm or more, for example.
  • the thickness t of the second lead terminal 12 may be 2.0 mm or less, for example.
  • the process of sealing the electronic components power semiconductor chip 20, control semiconductor chip 23, first chip capacitor 27, first electronic element 25) with the sealing member 40 (FIGS. 11, 16, and 17).
  • the length of the first lead terminal 11 extending into the cavity 45a of the mold 45 and the length of the second lead terminal 12 extending into the cavity 45a of the mold 45 are reduced.
  • the amount of bending of the plate member is proportional to the cube of the length of the plate member extending from the fixed end, and is the cube of the thickness of the plate member.
  • the first through hole 16 a of the first lead terminal 11 and the second through hole 16 b of the second lead terminal 12 are filled with a sealing member 40. Therefore, due to the difference between the thermal expansion coefficient of the sealing member 40 and the thermal expansion coefficients of the first lead terminal 11 and the second lead terminal 12, the first lead terminal 11 and the second lead terminal. Even if 12 is deformed, the first lead terminal 11 and the second lead terminal 12 are deformed into substantially the same shape starting from the first through hole 16a and the second through hole 16b. Therefore, partial peeling and cracks are prevented from being introduced into the first conductive adhesive portion 37, and the reliability of electrical connection of the first conductive adhesive portion 37 can be improved.
  • the terminal 11 and the sealing member 40 below the second lead terminal 12 are integrated.
  • the sealing member 40 filled in the first through-hole 16a and the second through-hole 16b functions as an anchor against the force of pulling out the first lead terminal 11 and the second lead terminal 12 from the sealing member 40. To do. Therefore, the first lead terminal 11 and the second lead terminal 12 are prevented from being pulled out from the sealing member 40, and the shearing stress is suppressed from being applied to the first conductive adhesive portion 37.
  • the introduction of partial peeling and cracks to the first conductive adhesive portion 37 is suppressed, and the reliability of electrical connection of the first conductive adhesive portion 37 can be improved.
  • the effects described above can also be obtained when the first through hole 16 a and the second through hole 16 b are formed on the inner peripheral side of the first chip capacitor 27.
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device according to the first embodiment.
  • the semiconductor device 2 includes the power semiconductor module 1 and a wiring substrate 51 including a plurality of wirings (for example, wirings 54 and 55) and a plurality of through holes (for example, through holes 52 and 53).
  • the wiring board 51 has a first main surface 51a and a second main surface 51b opposite to the first main surface 51a.
  • the first main surface 51a faces the electronic components (power semiconductor chip 20, control semiconductor chip 23, first chip capacitor 27, first electronic element 25).
  • the plurality of through holes extend from the first main surface 51a to the second main surface 51b.
  • the plurality of wirings are formed on the second main surface 51b.
  • the plurality of lead terminals are inserted into the plurality of through holes of the wiring board 51.
  • the protruding portions of the plurality of lead terminals are joined to the plurality of wirings by solder joints (for example, solder joints 57 and 58).
  • solder joints for example, solder joints 57 and 58.
  • the second protruding portion 11e (see FIG. 1) of the first lead terminal 11 is inserted into a through hole (not shown) of the wiring board 51.
  • the second protruding portion 11e of the first lead terminal 11 is joined to a wiring (not shown) by a solder joint (not shown).
  • the fourth protruding portion 12 e of the second lead terminal 12 is inserted into the through hole 52.
  • the fourth projecting portion 12 e of the second lead terminal 12 is joined to the wiring 54 by a solder joint portion 57.
  • the tenth protruding portion 15 e of the ninth lead terminal 15 is inserted into the through hole 53.
  • the tenth protruding portion 15 e of the ninth lead terminal 15 is joined to the wiring 55 by a solder joint 58.
  • 8 to 10 are partially enlarged plan views for explaining modifications of the power semiconductor module according to the first embodiment.
  • 8 to 10 correspond to FIG. 8 to 10, only the portion corresponding to the region II in FIG. 1 is shown, but the third to sixth lead terminals 111, 112, 211, 212, the second and third chip capacitors 127, 227 and the second and third electronic elements 125 and 225 have the same configuration as that shown in FIGS.
  • the power semiconductor module having the structure shown in FIG. 8 basically has the same configuration as the power semiconductor module 1 shown in FIGS. 1 to 6 and can obtain the same effect.
  • the shape of the two lead terminals 11 and 12 and the arrangement of the first chip capacitor 27 and the first electronic element 25 are different from those of the power semiconductor module 1 shown in FIGS.
  • a part of the second lead terminal 12 has an extending portion that extends inward from the first lead terminal 11.
  • the extending direction which is a direction from the first electrode 28a to the second electrode 28b, is directed inward from the surface of the sealing member 40 of the power semiconductor module 1 (the horizontal direction in FIG. 8).
  • the first electronic element 25 is disposed outside the first chip capacitor 27.
  • the first electronic element 25 is arranged so as to align with the first chip capacitor 27 along the extending direction of the first chip capacitor 27.
  • the first electronic element 25 is disposed at a distance L2 from the first chip capacitor 27.
  • the power semiconductor module having the structure shown in FIG. 9 has basically the same configuration as the power semiconductor module 1 shown in FIGS. 1 to 6 and can obtain the same effects.
  • the shape of the two lead terminals 11 and 12 and the arrangement of the first chip capacitor 27 and the first electronic element 25 are different from those of the power semiconductor module 1 shown in FIGS.
  • the width of the first lead terminal 11 (the width in the left-right direction in FIG. 9, which is the direction inward from the surface of the sealing member 40 in FIG. 1) is shown in FIG. It is wider than the first lead terminal 11.
  • the first chip capacitor 27 is disposed so as to be shifted inward from the first electronic element 25.
  • the first electronic element 25 is disposed at a distance L2 from the first chip capacitor 27.
  • the power semiconductor module having the structure shown in FIG. 10 basically has the same configuration as the power semiconductor module 1 shown in FIGS. 1 to 6 and can obtain the same effects.
  • the shape of the two lead terminals 11 and 12 is different from that of the power semiconductor module 1 shown in FIGS.
  • a plurality of first through holes 16 a are formed in the first lead terminal 11.
  • two first through holes 16 a are arranged so as to sandwich the first chip capacitor 27.
  • the two first through holes 16a are arranged so as to be aligned along the left-right direction in FIG. 10, which is a direction inward from the surface of the sealing member 40 in FIG.
  • a plurality of second through holes 16 b are formed in the second lead terminal 12.
  • two second through holes 16 b are arranged so as to sandwich the first chip capacitor 27.
  • the two second through-holes 16b are arranged so as to be aligned along the left-right direction in FIG. 10, which is a direction inward from the surface of the sealing member 40 in FIG.
  • the anchor effect of the sealing member 40 filled in the first through hole 16a and the second through hole 16b can be further enhanced, the effect of suppressing the peeling of the first chip capacitor 27 is improved. Can do.
  • FIG. 11 is a flowchart of the method for manufacturing the power semiconductor module according to the first embodiment.
  • FIG. 12 is a schematic plan view showing one step of the method for manufacturing the power semiconductor module according to the first embodiment.
  • 13 is a schematic partially enlarged cross-sectional view taken along a cross-sectional line XIII-XIII shown in FIG. 12 in the process shown in FIG. 12 in the method for manufacturing the power semiconductor module of the first embodiment.
  • FIG. 14 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment.
  • FIG. 15 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment.
  • 16 is a schematic plan view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the power semiconductor module according to the first embodiment.
  • 17 is a schematic partially enlarged cross-sectional view taken along a cross-sectional line XVII-XVII shown in FIG. 16 in the method for manufacturing the power semiconductor module according to the first embodiment.
  • FIGS. 11 to 17 a method for manufacturing the power semiconductor module 1 of the first embodiment will be described.
  • the method of manufacturing the power semiconductor module 1 includes electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third.
  • the third electronic elements 25, 125, 225) are joined to the lead frame 10 (S1).
  • the lead frame 10 is prepared.
  • the lead frame 10 can be formed by, for example, punching press processing or etching processing.
  • the lead frame 10 includes a frame portion 10a and a plurality of lead terminals.
  • the plurality of lead terminals include first to ninth lead terminals 11, 12, 111, 112, 211, 212, 13, 14, 15.
  • the plurality of lead terminals extend from the frame portion 10a toward the inside of the opening 10b of the frame portion 10a.
  • the lead frame 10 may further include a terminal connection portion 18.
  • the terminal connecting portion 18 is connected to the plurality of lead terminals in the opening 10b of the frame and connects the plurality of lead terminals to the frame portion 10a.
  • the terminal connecting portion 18 suppresses bending of the plurality of lead terminals in the opening 10b of the frame portion 10a.
  • the lead frame 10 electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, and first to third electronic elements 25, 125, 225) are joined to the lead frame 10.
  • the power semiconductor chip 20 is joined to the ninth lead terminal 15 by the solder joint portion 30.
  • the control semiconductor chip 23 is bonded to the eighth lead terminal 14 by the conductive bonding portion 33.
  • the conductive joint portion 33 may be a solder joint portion or a conductive adhesive portion 35.
  • the first electronic element 25 such as a rectifying semiconductor chip is joined to the first lead terminal 11 by the conductive adhesive portion 35.
  • the conductive adhesive portion 35 As the conductive adhesive portion 35, an Ag paste in which a silver (Ag) filler is dispersed in an epoxy resin is mainly used, but not only silver but other metal fillers including nickel (Ni), copper (Cu), and the like. A metal paste using may be used. For mounting, not only the conductive adhesive portion 35 but also solder or the like mainly containing tin (Sn) or lead (Pb) may be used. When the conductive adhesive portion 35 is used, it can be cured in a lump after mounting other semiconductor chips and electronic elements at the same time. As a result, the manufacturing tact time of the power semiconductor module can be shortened. In addition, since the melting point of the conductive adhesive portion 35 is higher than that of solder containing tin as a main component, the conductive adhesive portion 35 is not melted during reflow mounting.
  • the second and third electronic elements 125 and 225 are also joined to the third lead terminal 111 (see FIG. 4) and the fifth lead terminal 211 (see FIG. 4), respectively.
  • the first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the first conductive adhesive portion 37, respectively.
  • the second and third chip capacitors 127 and 227 are respectively connected to the third to sixth electrodes 128a, 128b, 228a, and 228b (see FIG. 4) from the third to the third. 6 lead terminals 111, 112, 211, 212 (see FIG. 4).
  • a conductive adhesive may be used, or a solder mainly composed of tin (Sn) or lead (Pb) may be used.
  • a solder mainly composed of tin (Sn) or lead (Pb) may be used.
  • the order of mounting each element for example, the power semiconductor chip 20, the control semiconductor chip 23, the first to third electronic elements 25, 125, and 225 which are rectifying semiconductor chips, and the first to third chip capacitors. 27, 127, and 227 may be mounted in this order, but the mounting order can be arbitrarily changed.
  • the conductive wire 29 is made of a material such as aluminum (Al), copper (Cu), gold (Au), silver (Ag), or an alloy thereof.
  • the conductive wire 29 may be a wire having a circular cross section.
  • the diameter ⁇ of the conductive wire 29 may be about 10 ⁇ m to about 500 ⁇ m.
  • an existing bonding method such as ball bonding or wedge bonding is used.
  • the first to third electronic elements 25, 125 If the conductive wires 29 between 225 and the lead terminals are of the same type, they can be joined simultaneously.
  • an optimal conductive wire 29 is selected at each location according to the electrode size of the junction between the control semiconductor chip 23 and the first to third electronic elements 25, 125, 225 and the current capacity flowing through the power semiconductor chip 20. It is desirable. Further, the order of joining these conductive wires 29 can be arbitrarily selected.
  • the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227 are arranged at equal intervals between the phases, that is, at the same pitch P1. To do. By doing so, the efficiency of the mounting process can be improved. For example, consider a case where the first to third chip capacitors 27, 127, and 227 are mounted side by side in the long side direction of the lead frame 10 (the direction indicated by the arrow 70 in FIG. 14) as shown in FIG. In this case, the lead frame 10 (see FIG. 12) is transported at the same pitch in the long side direction indicated by the arrow 70 in FIG. In this state, the first to third chip capacitors 27, 127 and 227 are mounted on the lead frame 10.
  • the suction nozzle that sucks and conveys the first to third chip capacitors 27, 127, and 227 only moves one axis in the short side direction indicated by the arrow 71 in FIG. 14 of the lead frame 10. Implementation work can be performed.
  • the suction nozzle that sucks and conveys the first to third chip capacitors 27, 127, and 227 can be mounted only by moving one axis in the short side direction of the lead frame 10 indicated by the arrow 71. .
  • the method for manufacturing power semiconductor module 1 includes electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, The first to third electronic elements 25, 125, 225) are sealed with the sealing member 40 (S2). Specifically, electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225) are joined.
  • the lead frame 10 is set in the mold 45. Sealing resin is injected into the cavity 45a of the mold 45 by using a transfer molding method or a compression molding method.
  • Electronic components power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225
  • a sealing member 40 Is done.
  • the frame portion 10a, the terminal connection portion 18, and the protruding portions of the plurality of lead terminals are exposed from the sealing member 40. Yes.
  • the shortest distance between the portion 46a of the mold 45 from which the first lead terminal 11 protrudes and the first chip capacitor 27 may be 5 times or less the thickness of the first lead terminal 11.
  • the shortest distance d between the portion 46b of the mold 45 from which the second lead terminal 12 protrudes and the first chip capacitor 27 may be 5 times or less the thickness t of the second lead terminal 12. .
  • the amount of bending of the plate member is proportional to the cube of the length of the plate member extending from the fixed end, and is the cube of the thickness of the plate member.
  • the method for manufacturing power semiconductor module 1 includes processing lead frame 10 (S3). Specifically, the protruding portion of the lead terminal not covered with the sealing member 40 is plated. As the plating, tin (Sn) plating, tin (Sn) -copper (Cu) plating, or the like is selected in order to cope with soldering at the time of board mounting. Note that this plating process may be omitted when the plating process is applied to the entire surface of the plurality of lead terminals in advance, or when it is determined that the surface process is not required for soldering when mounting the board. Thereafter, the frame portion 10a and the terminal connection portion 18 are removed by a mold press or the like, and the power semiconductor module 1 is separated into pieces.
  • the protruding portions for example, the first protruding portion 11c, the second protruding portion 12c, and the fifth protruding portion 15c
  • the power semiconductor module 1 shown in FIGS. 1 to 6 is obtained.
  • the package shape of the power semiconductor module 1 an arbitrary shape such as a DIP type, an SOP type, or a QFN (Quad For Non-Lead Package) type can be selected.
  • FIG. 18 is a flowchart of the semiconductor device manufacturing method according to the first embodiment. With reference to FIG. 18, the manufacturing method of the semiconductor device 2 of the present embodiment will be described.
  • the manufacturing method of the semiconductor device 2 includes preparing the power semiconductor module 1 (S11).
  • the power semiconductor module 1 is prepared by the method for manufacturing the power semiconductor module 1 of the present embodiment.
  • the method for manufacturing the semiconductor device 2 further includes mounting the power semiconductor module 1 on the wiring board 51 (S12). Specifically, the protruding portions of the plurality of lead terminals (for example, the fourth protruding portion 12e of the second lead terminal 12 and the tenth protruding portion 15e of the ninth lead terminal 15) are passed through the plurality of penetrations of the wiring substrate 51. It inserts in a hole (for example, through-holes 52 and 53).
  • the electronic components power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225
  • DIP in-line package
  • a plurality of lead terminal protruding portions (for example, the fourth protruding portion 12e of the second lead terminal 12 and the tenth protruding portion 15e of the ninth lead terminal 15) of the plurality of lead terminals are connected to the wiring substrate 51 by flow soldering. Solder-join to a plurality of wires (for example, wires 54 and 55). Thus, the semiconductor device 2 of the present embodiment shown in FIG. 7 is obtained.
  • the power semiconductor module 1 includes a plurality of lead terminals, a power semiconductor chip 20, a first chip capacitor 27, a first electronic element 25, and a sealing member 40.
  • the plurality of lead terminals include a first lead terminal 11 and a second lead terminal 12 spaced from the first lead terminal 11.
  • the first chip capacitor 27 includes a first electrode 28a and a second electrode 28b.
  • the first electronic element 25 is an element different from the power semiconductor chip 20 and the first chip capacitor 27.
  • the sealing member 40 seals the power semiconductor chip 20, the first chip capacitor 27, and the first electronic element 25.
  • the power semiconductor chip 20 is bonded to a ninth lead terminal 15 that is at least one of a plurality of lead terminals.
  • the first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the first conductive adhesive portion 37, respectively. Yes.
  • a first electronic element 25 is mounted on the first lead terminal 11.
  • FIG. 19 is a schematic cross-sectional view showing a power semiconductor module of a comparative example.
  • the power semiconductor module as a comparative example shown in FIG. 19 basically has the same configuration as that of the power semiconductor module shown in FIG. 3, but the first chip capacitor 27 and the first electronic element 25 are common. The main difference is that the conductive wire 29 is connected to the first chip capacitor 27 in that it is mounted on the lead terminal. The first chip capacitor 27 is connected to the lead terminal by an insulating adhesive 121.
  • the thickness of the control semiconductor chip 23 and the first electronic element 25, which is a rectifying semiconductor chip is usually about several tens of ⁇ m to several hundreds of ⁇ m.
  • the thickness of the first chip capacitor 27 depends on the size of the chip capacitor, the thickness is about 400 ⁇ m to about 1 mm when the size is 1608 standard (about 1.6 mm ⁇ 0.8 mm) or more. Therefore, the first chip capacitor 27 is the thickest part on the lead frame 10. Therefore, the thickness of the power semiconductor module 1 is determined by the thickness of the first chip capacitor 27.
  • the conductive wire 29 is connected to the electrode of the first chip capacitor 27 as shown in FIG. 19, it is compared with the thickness T1 (see FIG. 19) of the power semiconductor module 1 according to this embodiment shown in FIG.
  • the thickness T2 of the power semiconductor module as a comparative example is further increased by that amount.
  • an extra sealing member 40 is used, which not only increases the manufacturing cost but also increases the power semiconductor module itself.
  • the power semiconductor module becomes heavy, for example, when the power semiconductor module is sucked and automatically transported by a transport device including the suction member, it is necessary to improve the suction force of the suction member.
  • the suction member is a vacuum suction device, a higher degree of vacuum is required.
  • the load on the lead terminals may increase and the product life may be shortened.
  • an ultrasonic bonding method is usually used. Therefore, pressure or ultrasonic vibration is applied to the first chip capacitor 27 when the conductive wire 29 is bonded. For this reason, when the conductive wire 29 is connected to the first chip capacitor 27, the first chip capacitor 27 is usually made of ceramic.
  • the power semiconductor module is mounted on one main surface of the double-sided mounting substrate for the first time. Thereafter, in the second mounting operation, the double-sided mounting board is turned over and reflow mounted. Therefore, when the mass of the power semiconductor module is heavy, the gravity acting on the power semiconductor module becomes larger than the surface tension generated by the solder wetted on the terminals of the power semiconductor module when the first reflow mounting is performed. There is a possibility that the semiconductor module falls from the mounting substrate.
  • SOP small outline package
  • the power semiconductor module 1 according to the present embodiment can suppress the occurrence of the above problems in the power semiconductor module as the comparative example shown in FIG.
  • the distance L2 between the first chip capacitor 27 and the first electronic element 25 is shorter than the distance L1 between the first chip capacitor 27 and the power semiconductor chip 20.
  • the first lead terminal 11 has one or more first through holes 16a.
  • One or more second through holes 16 b are formed in the second lead terminal 12.
  • a part of the sealing member 40 is disposed inside each of the one or more first through holes 16a and the one or more second through holes 16b.
  • the first and second lead terminals 11 and 12 are formed by a part of the sealing member 40 disposed inside the one or more first through holes 16a and the one or more second through holes 16b.
  • the portions of the sealing member 40 located on the upper side and the lower side of the are connected.
  • the first and second lead terminals 11 and 12 are firmly fixed by the sealing member 40. Therefore, when stress is applied to the first and second lead terminals 11, 12, the displacement of the first and second lead terminals 11, 12 can be suppressed, and as a result, the first and second lead terminals 11, 12 are caused by the displacement.
  • the peeling of the first chip capacitor 27 from the second lead terminals 11 and 12 can be suppressed.
  • the one or more first through holes 16a and the one or more second through holes 16b may each include a plurality of through holes as shown in FIG. In this case, separation of the first chip capacitor 27 from the first and second lead terminals 11 and 12 can be more reliably suppressed.
  • the plurality of through holes 16 a and 16 b may be arranged at positions where the first chip capacitor 27 is sandwiched.
  • the first lead terminal 11 and the second lead terminal 12 are a first protruding portion 11 c and a second protruding portion, which are protruding portions protruding outward from the first surface of the sealing member 40, respectively.
  • the one or more first through holes 16a are first outer through holes (the first through holes in FIG. 4) that are located on the first projecting portion 11c side of the first lead terminal 11 when viewed from the first chip capacitor 27.
  • the one or more second through-holes 16b are second outer through-holes (the second through-holes in FIG. 4) that are located on the second projecting portion 12c side of the second lead terminal 12 when viewed from the first chip capacitor 27.
  • the first distance W1 between the first chip capacitor 27 and the first outer through hole is equal to the first chip capacitor 27 and the second outer through hole (see FIG. 4 and the second distance W2 between the second through hole 16b).
  • the first distance W1 and the second distance W2 being the same means that the difference between the first distance W1 and the second distance W2 is 1.0 mm or less.
  • the portions where the first and second outer through holes (the first through hole 16a and the second through hole 16b in FIG. 4) are formed are the other parts.
  • the strength is lower than the part.
  • the first and second through holes 16a and 16b which are the first and second outer through holes, are formed.
  • the first and second lead terminals 11 and 12 are deformed with the region as the center of deformation. Therefore, the distance from the first chip capacitor 27 to the center of the deformation is substantially the same in the first and second lead terminals 11 and 12.
  • the first lead terminal 11 and the first chip capacitor 27 are different from the case where the positions where the distances from the first chip capacitor 27 are different from each other in the first and second lead terminals 11 and 12 are the center of deformation.
  • the probability of occurrence of a state in which the amount of displacement of the first connecting portion differs greatly from the amount of displacement of the second connecting portion between the second lead terminal 12 and the first chip capacitor 27 can be reduced. Therefore, it is possible to reduce the probability of occurrence of a problem that the first chip capacitor 27 is separated from the first lead terminal 11 or the second lead terminal 12 due to the difference in the displacement amount.
  • the first electronic element 25 is a first rectifying semiconductor chip.
  • the first rectifying semiconductor chip includes a resistor 25b as shown in FIG.
  • the first rectifying semiconductor chip incorporating the resistor 25b and the first chip capacitor 27 constitute a bootstrap circuit.
  • the plurality of lead terminals include a third lead terminal 111 and a fourth lead terminal 112.
  • the third lead terminal 111 is separated from the first lead terminal 11 and the second lead terminal 12.
  • the fourth lead terminal 112 is separated from the third lead terminal 111.
  • the power semiconductor module 1 further includes a second chip capacitor 127 and a second electronic element 125.
  • the second chip capacitor 127 includes a third electrode 128a and a fourth electrode 128b.
  • the second electronic element 125 is an element different from the power semiconductor chip 20, the first and second chip capacitors 27, 127, and the first electronic element 25.
  • the third electrode 128a and the fourth electrode 128b of the second chip capacitor 127 are joined to the third lead terminal 111 and the fourth lead terminal 112 by the second conductive adhesive portion 137, respectively. Yes.
  • a second electronic element 125 is mounted on the third lead terminal 111.
  • the relative arrangement of the first electronic element 25 with respect to the first chip capacitor 27 is the same as the relative arrangement of the second electronic element 125 with respect to the second chip capacitor 127.
  • the distance L21 between the first chip capacitor 27 and the first electronic element 25 may be the same as the distance L22 between the second chip capacitor 127 and the second electronic element 125.
  • the distance L23 between the third chip capacitor 227 and the third electronic element 225 is the same as the distance L21. Also good.
  • the same relative arrangement means that the first vector from the center of the first chip capacitor 27 to the center of the first electronic element 25 and the center of the second chip capacitor 127 in plan view. Means substantially the same as the second vector from the center toward the center of the second electronic element 125. More specifically, the above-described relative arrangement is the same as the first distance from the center of the first chip capacitor 27 to the center of the first electronic element 25 and the center of the second chip capacitor 127. And the second distance from the second electronic element 125 to the center of the second electronic element 125 is not less than 0% and not more than 10% of the first distance, and the direction of the first vector and the second vector It means that the angle formed by the direction is 0 ° or more and 15 ° or less.
  • first and second chip capacitors 27 and 127 and the first and second electronic elements are arranged at the centers of the first and second chip capacitors 27 and 127 and the first and second electronic elements 25 and 125.
  • the intersection of diagonal lines of the planar shape may be the center.
  • the distance L21 is equal to the distance L22 or the distance L23 when the difference between the distance L22 or the distance L23 and the distance L21 is 0% or more and 10% or less of the distance L21.
  • the wiring resistance of the portion of the circuit constituted by the first chip capacitor 27 and the first electronic element 25 is the first chip capacitor 27 and the first electronic element 25 in the first lead terminal 11. Varies depending on the arrangement.
  • the wiring resistance of the circuit portion constituted by the second chip capacitor 127 and the second electronic element 125 is also different between the second chip capacitor 127 and the second electronic element 125 in the third lead terminal 111. It changes with arrangement. Therefore, if the relative arrangement of the first electronic element 25 with respect to the first chip capacitor 27 and the relative arrangement of the second electronic element 125 with respect to the second chip capacitor 127 are substantially the same, The wiring resistance can also be made substantially the same.
  • FIG. 20 is a diagram illustrating a graph for explaining a charge / discharge waveform in the chip capacitor of the power semiconductor module.
  • the horizontal axis of FIG. 20 indicates time, and the vertical axis indicates the potential of the first chip capacitor 27.
  • FIG. 20 shows the transition of the voltage between the terminals of the first chip capacitor 27 with respect to time.
  • a waveform A indicated by a solid line in FIG. 20 is obtained when the resistance value between the first electronic element 25 which is a rectifying semiconductor chip and the first chip capacitor 27 is larger than the waveform B indicated by a broken line. is there.
  • the power semiconductor chip 20 is driven during the discharge period, that is, during the period during which the first to third chip capacitors 27, 127, and 227 are discharged to drive the gate. It is necessary to tune the charge / discharge sequence for each phase so as not to fall below the lower limit of the voltage value.
  • the circuit design and the charging time are set phase by phase so that the voltage required for driving the gate does not fall during the period in which the power semiconductor chip 20 is driven by discharging the first to third chip capacitors 27, 127, 227. Set to.
  • the first lead terminal 11 has one or more first through holes 16a.
  • One or more second through holes 16 b are formed in the second lead terminal 12.
  • One or more third through holes 16 c are formed in the third lead terminal 111.
  • the fourth lead terminal 112 is formed with one or more fourth through holes 16d.
  • Each of the one or more first through holes 16a, the one or more second through holes 16b, the one or more third through holes 16c, and the one or more fourth through holes 16d, A part of the sealing member 40 is disposed.
  • the first to fourth lead terminals 11, 12, 12 are formed by a part of the sealing member 40 disposed in each of the one or more first to fourth through holes 16 a, 16 b, 16 c, 16 d.
  • the portions of the sealing member 40 located above and below 111 and 112 are connected. Therefore, the first to fourth lead terminals 11, 12, 111, 112 are firmly fixed by the sealing member 40. Therefore, when stress is applied to the first to fourth lead terminals 11, 12, 111, 112, the displacement of the first to fourth lead terminals 11, 12, 111, 112 can be suppressed, and as a result. Separation of the first and second chip capacitors 27, 127 from the first to fourth lead terminals 11, 12, 111, 112 due to the displacement can be suppressed.
  • first through holes 16a In the power semiconductor module 1, one or more first through holes 16a, one or more second through holes 16b, one or more third through holes 16c, and one or more fourth through holes.
  • Each of 16d includes a plurality of through holes.
  • the plurality of through holes may be arranged at positions where the first or second chip capacitors 27, 127 are sandwiched as shown in FIG. 10.
  • the first to fourth lead terminals 11, 12, 111, and 112 are protruding portions (first protruding portion 11 c, first protruding portion) that protrude outward from the first surface of the sealing member 40, respectively.
  • the shape of a part of the first lead terminal 11 which is located on the first protruding portion 11c side of the first lead terminal 11 when viewed from the first chip capacitor 27 and is sealed by the sealing member 40 is
  • the third lead terminal 111 is located on the third protruding portion 111c side when viewed from the second chip capacitor 127, and has the same shape as a part of the third lead terminal 111 sealed by the sealing member 40.
  • the shape of a part of the second lead terminal 12 which is located on the second projecting portion 12c side of the second lead terminal 12 as viewed from the first chip capacitor 27 and sealed by the sealing member 40 is
  • the fourth lead terminal 112 is located on the fourth projecting portion 112 c side when viewed from the second chip capacitor 127 and has the same shape as a part of the fourth lead terminal 112 sealed by the sealing member 40.
  • the shape of the part of the first lead terminal 11 is the same as the shape of the part of the third lead terminal 111 means that the shape of the part of the first lead terminal 11 and the part of the third lead terminal 111 are the same. It means that the external shape of is substantially the same. Specifically, when the part of the outline of the first lead terminal 11 and the part of the outline of the third lead terminal 111 overlap, the length of a part (one side) of the corresponding outline Of the first lead terminal 11 is not less than 10% and not more than 10% of the length of the part of the outline of the part, and a part (one side) of the corresponding outline is extended in the extending direction.
  • the shape of the part of the first lead terminal 11 is assumed to be the same as the shape of the part of the third lead terminal 111.
  • whether or not the shape of the part of the second lead terminal 12 is the same as the shape of the part of the fourth lead terminal 112 is also a method related to the shape of the part of the first and third lead terminals 11 and 111. You may judge by the same method.
  • connection arrangement of the first chip capacitor 27 to the first and second lead terminals 11 and 12 and the connection arrangement of the second chip capacitor 127 to the third and fourth lead terminals 111 and 112 are the same.
  • the shift can be easily found by visual observation.
  • the second electronic element 125 is a second rectifying semiconductor chip.
  • the second rectifying semiconductor chip includes a resistor 25b as in the first electronic element 25 shown in FIG.
  • the second rectifying semiconductor chip incorporating the resistor 25b and the second chip capacitor 127 constitute a bootstrap circuit.
  • the plurality of lead terminals include a fifth lead terminal 211 and a sixth lead terminal 212.
  • the fifth lead terminal 211 is separated from the first to fourth lead terminals 11, 12, 111, and 112.
  • the sixth lead terminal 212 is separated from the fifth lead terminal 211.
  • the power semiconductor module 1 further includes a third chip capacitor 227 and a third electronic element 225.
  • the third chip capacitor 227 includes a fifth electrode 228a and a sixth electrode 228b.
  • the third electronic element 225 is different from the power semiconductor chip 20, the first to third chip capacitors 27, 127, 227, and the first and second electronic elements 25, 125.
  • the fifth electrode 228a and the sixth electrode 228b of the third chip capacitor 227 are joined to the fifth lead terminal 211 and the sixth lead terminal 212 by the third conductive adhesive portion 237, respectively. Yes.
  • a third electronic element 225 is mounted on the fifth lead terminal 211.
  • the first to third chip capacitors 27, 127, 227 are arranged along a first direction which is the vertical direction of FIG.
  • the arrangement pitch P1 in the first direction of the first to third chip capacitors 27, 127, 227 is constant.
  • the arrangement pitch P1 in the first direction of the first to third chip capacitors 27, 127, 227 is constant in the following cases. That is, as shown in FIG.
  • the first chip capacitor 27 has a first end opposite to the side where the second chip capacitor 127 is located, and the second chip capacitor 127 has the first chip capacitor 27.
  • a first distance P1 along the first direction between the second end of the side.
  • the second end portion of the second chip capacitor 127 and the third end portion of the third chip capacitor 227 on the second chip capacitor 127 side Consider a second distance P1 along.
  • the case where the difference between the first distance P1 and the second distance P1 is not less than 0% and not more than 10% of the first distance P1, and the case where the arrangement pitch P1 is constant. To do.
  • the first to third chip capacitors 27, 127, 227 are mounted on the first to sixth lead terminals 11, 12, 111, 112, 211, 212, the first to sixth lead terminals are mounted.
  • the movement of the moving means such as the suction nozzle for moving the first to third chip capacitors 27, 127, 227 is moved while moving the lead frame including 11, 12, 111, 112, 211, 212 at an equal pitch. Only the direction perpendicular to the direction can be used. As a result, the working efficiency of the manufacturing process of the power semiconductor module 1 can be improved.
  • the third electronic element 225 is a third rectifying semiconductor chip.
  • the third rectifying semiconductor chip includes a resistor 25b as in the first electronic element 25 shown in FIG.
  • the third rectifying semiconductor chip incorporating the resistor 25b and the third chip capacitor 227 constitute a bootstrap circuit.
  • FIG. 21 is a schematic cross-sectional view of a power semiconductor module according to the second embodiment.
  • a power semiconductor module 1b according to the second embodiment will be described with reference to FIG.
  • the power semiconductor module 1b of the present embodiment has the same configuration as that of the power semiconductor module 1 of the first embodiment and has the same effects, but is mainly different in the following points.
  • the plurality of lead terminals include protruding portions that protrude from the sealing member 40. These protrusions are bent into a gull wing shape.
  • the first lead terminal 11 includes a first protrusion 11 c (not shown in FIG. 21) that protrudes from the sealing member 40.
  • the second lead terminal 12 includes a second protrusion 12 c that protrudes from the sealing member 40.
  • the ninth lead terminal 15 includes a fifth projecting portion 15 c that projects from the sealing member 40.
  • the first protrusion 11c, the second protrusion 12c, and the fifth protrusion 15c are bent into a gull wing shape.
  • the plurality of lead terminals include a plurality of terminal portions extending along a plurality of pads (for example, the first pad 11a, the second pad 12a, the seventh pad 14a, and the eighth pad 15a).
  • the first protrusion 11c of the first lead terminal 11 further includes a twelfth protrusion (not shown) in addition to the first protrusion 11d and the second protrusion 11e (see FIG. 1). .
  • the twelfth projecting portion extends horizontally from the second projecting portion 11e in the direction opposite to the first projecting portion 11d.
  • the twelfth projecting portion is bent with respect to the second projecting portion 11e.
  • the twelfth projecting portion functions as the first terminal portion of the first lead terminal 11.
  • the second projecting portion 12c of the second lead terminal 12 further includes a thirteenth projecting portion 12f in addition to the third projecting portion 12d and the fourth projecting portion 12e.
  • the thirteenth projecting portion 12f extends from the fourth projecting portion 12e in the opposite direction to the third projecting portion 12d and horizontally.
  • the thirteenth protruding portion 12f is bent with respect to the fourth protruding portion 12e.
  • the thirteenth projecting portion 12 f functions as the second terminal portion of the second lead terminal 12.
  • the fifth protrusion 15c of the ninth lead terminal 15 further includes an eleventh protrusion 15f in addition to the ninth protrusion 15d and the tenth protrusion 15e.
  • the eleventh projecting portion 15f extends from the tenth projecting portion 15e in the direction opposite to the ninth projecting portion 15d and horizontally.
  • the eleventh projecting portion 15f is bent with respect to the tenth projecting portion 15e.
  • the eleventh protruding portion 15 f functions as a third terminal portion of the ninth lead terminal 15.
  • electronic components (the power semiconductor chip 20, the control semiconductor chip 23, the first chip capacitor 27, and the first electronic element 25) are packaged in a small outline package (SOP) system.
  • SOP small outline package
  • the manufacturing method of the power semiconductor module 1b of the present embodiment includes the same steps as the manufacturing method of the power semiconductor module 1 of the first embodiment (see FIG. 11), but mainly differs in the following points.
  • the protruding portions of the lead terminals for example, the first protruding portion 11c, the second protruding portion 12c, and the fifth protruding portion 15c
  • the protruding portions of the lead terminals is bent into a gull wing shape.
  • a plurality of terminal portions (for example, a twelfth protruding portion, a thirteenth protruding portion 12f, and an eleventh protruding portion 15f) are formed on the protruding portions of the plurality of lead terminals.
  • the plurality of terminal portions extend along a plurality of pads (for example, the first pad 11a, the second pad 12a, the seventh pad 14a, and the eighth pad 15a). In this way, the power semiconductor module 1b shown in FIG. 21 is obtained.
  • FIG. 22 is a schematic cross-sectional view of the semiconductor device according to the second embodiment.
  • the semiconductor device 2b of the second embodiment will be described.
  • the semiconductor device 2b of the present embodiment has the same configuration as that of the semiconductor device 2 of the first embodiment and has the same effects, but is mainly different in the following points.
  • the semiconductor device 2b includes a power semiconductor module 1b and a wiring board 51 including a plurality of wirings (for example, wirings 54 and 55).
  • the plurality of wirings are formed on the first main surface 51 a of the wiring board 51.
  • Terminal portions of the plurality of lead terminals are joined to the wiring by solder joints.
  • a twelfth projecting portion (not shown) of the first lead terminal 11 is joined to a wiring (not shown) by a solder joint (not shown).
  • the thirteenth projecting portion 12 f of the second lead terminal 12 is joined to the wiring 54 by a solder joint portion 57.
  • the eleventh protruding portion 15 f of the ninth lead terminal 15 is joined to the wiring 55 by a solder joint 58.
  • the manufacturing method of the semiconductor device 2b of the present embodiment includes the same steps as the manufacturing method of the semiconductor device 2 of the first embodiment (see FIG. 18), but mainly differs in the following points.
  • the electronic components (the power semiconductor chip 20, the control semiconductor chip 23, the first to third chip capacitors 27, 127, 227, and the first to third electronic elements 25, 125, 225) are small. It is packaged by the outline package (SOP) method. Therefore, when the power semiconductor module 1b is mounted on the wiring board 51, a plurality of terminal portions (for example, the thirteenth protruding portion 12f and the eleventh protruding portion 15f) of the plurality of lead terminals are connected to the wiring substrate by reflow soldering. The plurality of wirings 51 (for example, the wirings 54 and 55) are soldered. In this way, the semiconductor device 2b of the present embodiment shown in FIG. 22 is obtained.
  • SOP outline package
  • the reflow soldering in the present embodiment has a higher temperature reached by the package at the time of soldering and the time required for soldering than the flow soldering in the first embodiment. Therefore, when the power semiconductor module 1 b is mounted on the wiring substrate 51 by reflow soldering, a larger thermal stress is applied to the first conductive adhesive portion 37.
  • FIG. 23 is a schematic plan view of a power semiconductor module according to a modification of the second embodiment.
  • 24 is a schematic partial enlarged plan view of a region XXIV of the power semiconductor module shown in FIG.
  • FIG. 25 is a schematic sectional view taken along line XXV-XXV in FIG.
  • the power semiconductor module 1 shown in FIGS. 23 to 24 basically has the same configuration as the power semiconductor module 1b shown in FIG. 21 and provides the same effects, but is mainly different in the following points.
  • the first chip capacitor 27 (see FIGS. 27 and 1) is not shown in FIGS. 23 and 24 for ease of explanation.
  • the first electronic element 25 is disposed diagonally to the first through hole 16 a in the first pad 11 a of the first lead terminal 11. Is desirable.
  • the outer shape of the first pad 11a in plan view is substantially rectangular.
  • the center 85 of the first lead terminal 11 is substantially the first lead hole 16a formed in the first lead terminal 11 and the first electronic element 25 disposed therein. This means the center 85 of the pad 11a.
  • the center 85 may be the center of gravity of the first pad 11a, or may be the center of a circle in contact with the corner of the outer shape of the first pad 11a.
  • the distance w3 from the connection portion between the second protrusion 11e of the first lead terminal 11 and the first pad 11a to the first through hole 16a is from the connection portion to the first electronic element 25. Is smaller than the distance w4.
  • the power semiconductor module 1 includes a plurality of lead terminals including the first lead terminal 11, a power semiconductor chip 20, and a power semiconductor chip 20. Includes different first electronic elements 25 and a sealing member 40.
  • the sealing member 40 seals the power semiconductor chip 20 and the first electronic element 25.
  • the power semiconductor chip 20 is bonded to at least one of the plurality of lead terminals.
  • a first electronic element 25 is mounted on the first lead terminal 11.
  • a first through hole 16 a is formed in the first lead terminal 11. When viewed from the center 85 of the first lead terminal 11, the first through hole 16 a and the first electronic element 25 are disposed in regions opposite to each other.
  • the second protruding portion 11e of the first lead terminal 11 may be subjected to plating necessary for improving solderability when soldered to the wiring board 51 (see FIG. 22).
  • the formed plating layer is, for example, a plating layer containing Sn as a main component.
  • the first through hole 16 a has a function of blocking the plating solution entering the sealing member 40 through the second protruding portion 11 e of the first lead terminal 11.
  • some plating solutions are strongly acidic, and when a metal (for example, Al) constituting the electrode of the first electronic element 25 comes into contact with the plating solution, the electrode corrodes.
  • the first through hole 16a is formed in the vicinity of the connection portion between the second protruding portion 11e and the first pad 11a, thereby preventing the plating solution and moisture from entering.
  • the plating solution or the like that has penetrated spreads mainly along the side of the first pad 11a after being prevented from penetrating into the first through hole 16a.
  • the first electronic element 25 is disposed on the first pad 11a at a position diagonally opposite to the first through hole 16a, or the second protruding portion 11e of the first lead terminal 11 and By making the distance w4 from the connection portion to the first electronic element 25 larger than the distance w3 from the connection portion with the first pad 11a to the first through hole 16a, the plating solution or the like can be removed. The effect of making it difficult to reach the electronic element 25 can be expected.
  • the fourth lead terminal 112 also has a fourth through hole 16d on the outside.
  • the sixth lead terminal 212 between the third lead terminal 111 on which the second electric element 125 is mounted and the fifth lead terminal 211 on which the third electric element 225 is mounted is also outside.
  • a fifth through hole 16 e is also formed in the fifth pad 211 a of the fifth lead terminal 211.
  • the configurations of the third lead terminal 111 and the fifth lead terminal 211 are basically the same as those of the first lead terminal 11.
  • the lead material constituting the first lead terminal 11 is, for example, copper (Cu)
  • the lead material may be corroded by the plating solution. Due to such corrosion of the lead material, there may be a space between the resin and the first lead terminal 11 or the like. If moisture or the like enters through this space, the lifetime of the first electronic element 25 or the like may be shortened by the moisture. Therefore, no electrical element is mounted that is located between the first lead terminal 11 on which the first electrical element 25 is mounted and the third lead terminal 111 on which the second electrical element 125 is mounted. In the fourth lead terminal 112 which is the lead terminal, the fourth through hole 16d is provided, so that intrusion of moisture and the like can be prevented. As a result, the formation of a resin gap around the first electric element 25 can be suppressed.
  • Cu copper
  • a recess 81 is provided between the first electrical element 25 and the plating portion 17 as a pad to which a conductive wire is connected in the first lead terminal 11.
  • the third lead terminal 111 and the fifth lead terminal 211 may be similarly formed with the recess 81.
  • the first lead terminal 11 is located in a region opposite to the first through hole 16a when viewed from the center 85, and the plated portion 17 as an inner terminal portion to which the conductive wire 29 is connected is provided.
  • a concave portion 81 is formed on the side where the plated portion 17 as the inner terminal portion is located when viewed from the center 85.
  • the recess 81 has an effect of preventing the bonding material used when the first electric element 25 or the like is bonded from reaching the plating portion 17 which is an inner terminal portion as a wire pad.
  • the arrangement of the first through-hole 16a and the first electronic element 25 at the first lead terminal 11 and the concave portion 81 may be applied to the power semiconductor module 1 according to the first embodiment. That is, in the first lead terminal 11 of the power semiconductor module 1 shown in FIG. 2, the recess 81 may be provided between the first electric element 25 and the plating part 17 as a pad to which the conductive wire is connected. Further, in each of the second lead terminal 12, the third lead terminal 111, the fourth lead terminal 112, the fifth lead terminal 211, and the sixth lead terminal 212 in FIG. May be provided.
  • Embodiment 3 the power semiconductor modules 1 and 1b according to the first or second embodiment described above are applied to a power conversion device.
  • the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a third embodiment.
  • FIG. 26 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 26 includes a power supply 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source and supplies DC power to the power conversion device 200.
  • the power supply 100 is not specifically limited, For example, it may be comprised with a DC system, a solar cell, or a storage battery, and may be comprised with the rectifier circuit or AC / DC converter connected to the AC system.
  • the power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into another DC power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 26, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. 203.
  • the load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200.
  • the load 300 is not particularly limited, but is an electric motor mounted on various electric devices, and is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner, for example.
  • the main conversion circuit 201 includes a switching element (not shown) and a free wheeling diode (not shown).
  • the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300 by switching the voltage supplied from the power supply 100 by the switching element.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six freewheeling diodes in antiparallel.
  • the power semiconductor modules 1 and 1b according to any one of the first and second embodiments described above are applied to at least one of the switching elements and the free-wheeling diodes of the main conversion circuit 201.
  • Six switching elements are connected in series for every two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase and W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the main conversion circuit 201 is a drive circuit. It has.
  • the drive circuit generates a drive signal for driving the switching element included in the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201.
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element.
  • the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).
  • the control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
  • PWM pulse width modulation
  • the power semiconductor modules 1 and 1b according to either the first embodiment or the second embodiment are applied as the power semiconductor module 202 included in the main conversion circuit 201. Therefore, power converter 200 according to the present embodiment can be reduced in size.
  • the present invention is not limited to this and can be applied to various power conversion devices.
  • a two-level power conversion device is used.
  • a three-level power conversion device or a multi-level power conversion device may be used.
  • the present invention may be applied to a single-phase inverter.
  • the present invention may be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load is an electric motor.
  • the power supply device of an electric discharge machine or a laser processing machine, or an induction heating cooker or a non-contact power supply system It can be incorporated into a power supply.
  • the power conversion device to which the present invention is applied can be used as a power conditioner such as a solar power generation system or a power storage system.

Abstract

The present invention provides a power semiconductor module which is able to be reduced in size. A power semiconductor module (1) according to the present invention is provided with a plurality of lead terminals, a power semiconductor chip (20), a first chip capacitor (27), a first electronic element (25) and a sealing member (40). The plurality of lead terminals include a first lead terminal (11) and a second lead terminal (12). The first chip capacitor (27) comprises a first electrode (28a) and a second electrode (28b). The sealing member (40) seals the power semiconductor chip (20), the first chip capacitor (27) and the first electronic element (25). The power semiconductor chip (20) is bonded to a ninth lead terminal (15), which is one of the plurality of lead terminals. The first electrode (28a) and the second electrode (28b) of the first chip capacitor (27) are respectively bonded to the first lead terminal (11) and the second lead terminal (12) by means of a first conductive bonding part (37). The first electronic element (25) is mounted on the first lead terminal (11).

Description

パワー半導体モジュール及び電力変換装置Power semiconductor module and power conversion device
　本発明は、パワー半導体モジュール及び電力変換装置に関する。 The present invention relates to a power semiconductor module and a power conversion device.
　特開２０１２－１０４６３３号公報（特許文献１）は、トランスファーモールドパッケージ内において、リードフレームと、リードフレーム上に配置されたパワーチップと、リードフレーム上に配置され、かつ、パワーチップを駆動させるＩＣチップと、ＩＣチップに接続されたブートストラップコンデンサとを備える半導体装置を開示している。ブートストラップコンデンサ（ＢＳＣ）は、リードフレーム上に、絶縁性接着剤を介して接合されている。ブートストラップコンデンサは電極を有する。ブートストラップコンデンサの当該電極とＩＣチップとはワイヤを介して接続されている。 Japanese Patent Laying-Open No. 2012-104633 (Patent Document 1) discloses a lead frame, a power chip disposed on the lead frame, and an IC that is disposed on the lead frame and drives the power chip in a transfer mold package. A semiconductor device including a chip and a bootstrap capacitor connected to an IC chip is disclosed. The bootstrap capacitor (BSC) is joined to the lead frame via an insulating adhesive. The bootstrap capacitor has an electrode. The electrode of the bootstrap capacitor and the IC chip are connected via a wire.
特開２０１２－１０４６３３号公報JP 2012-104633 A
　特許文献１のように、ブートストラップコンデンサの電極にワイヤを接続する場合、通常はブートストラップコンデンサの上面にワイヤの端部を接続する。一般的に特許文献１に開示される半導体装置により例示されるパワー半導体モジュールにおいては、ブートストラップコンデンサの厚みが一番厚い。このため、厚みのあるブートストラップコンデンサにワイヤを接続することにより、パワー半導体モジュールの厚みも厚くなる。この結果、パワー半導体モジュールのサイズが大きくなっていた。 As in Patent Document 1, when connecting a wire to the electrode of the bootstrap capacitor, the end of the wire is usually connected to the upper surface of the bootstrap capacitor. Generally, in a power semiconductor module exemplified by the semiconductor device disclosed in Patent Document 1, the bootstrap capacitor has the largest thickness. For this reason, connecting a wire to a thick bootstrap capacitor increases the thickness of the power semiconductor module. As a result, the size of the power semiconductor module has been increased.
　本発明の目的は、小型化が可能なパワー半導体モジュールを提供することである。本発明の目的は、小型化が可能な電力変換装置を提供することである。 An object of the present invention is to provide a power semiconductor module that can be miniaturized. The objective of this invention is providing the power converter device which can be reduced in size.
　本発明に従ったパワー半導体モジュールは、複数のリード端子と、パワー半導体チップと、第１のチップコンデンサと、第１の電子素子と、封止部材と、を備える。複数のリード端子は、第１のリード端子と、当該第１のリード端子から離間されている第２のリード端子とを含む。第１のチップコンデンサは、第１の電極と第２の電極とを含む。第１の電子素子は、パワー半導体チップ及び第１のチップコンデンサとは異なる素子である。封止部材は、パワー半導体チップと第１のチップコンデンサと第１の電子素子とを封止する。パワー半導体チップは複数のリード端子の少なくとも１つに接合されている。第１のチップコンデンサの第１の電極と第２の電極とは、第１の導電性接着部で、第１のリード端子と第２のリード端子とにそれぞれ接合されている。第１のリード端子には第１の電子素子が搭載されている。 A power semiconductor module according to the present invention includes a plurality of lead terminals, a power semiconductor chip, a first chip capacitor, a first electronic element, and a sealing member. The plurality of lead terminals include a first lead terminal and a second lead terminal spaced from the first lead terminal. The first chip capacitor includes a first electrode and a second electrode. The first electronic element is an element different from the power semiconductor chip and the first chip capacitor. The sealing member seals the power semiconductor chip, the first chip capacitor, and the first electronic element. The power semiconductor chip is bonded to at least one of the plurality of lead terminals. The first electrode and the second electrode of the first chip capacitor are joined to the first lead terminal and the second lead terminal, respectively, at the first conductive adhesive portion. A first electronic element is mounted on the first lead terminal.
　本発明に従った電力変換装置は、主変換回路と制御回路とを備える。主変換回路は、上記パワー半導体モジュールを有し、入力される電力を変換して出力する。制御回路は、主変換回路を制御する制御信号を主変換回路に出力する。 The power conversion device according to the present invention includes a main conversion circuit and a control circuit. The main conversion circuit includes the power semiconductor module, and converts input power and outputs the converted power. The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
　本発明に従ったパワー半導体モジュールによれば、第１のチップコンデンサの第１の電極と第２の電極とが、第１の導電性接着部で、第１のリード端子と第２のリード端子とにそれぞれ接合されているので、第１のチップコンデンサにワイヤを接続する場合よりもパワー半導体モジュールの厚みを薄くでき、小型化が可能である。 According to the power semiconductor module of the present invention, the first electrode and the second electrode of the first chip capacitor are the first conductive adhesive portion, and the first lead terminal and the second lead terminal. Thus, the thickness of the power semiconductor module can be made thinner and smaller than when the wire is connected to the first chip capacitor.
　また、本発明に従った電力変換装置は、上記パワー半導体モジュールを有する主変換回路を備える。そのため、本発明に従った電力変換装置は小型化が可能である。 Also, a power conversion device according to the present invention includes a main conversion circuit having the power semiconductor module. Therefore, the power converter according to the present invention can be downsized.
実施の形態１に係るパワー半導体モジュールの概略平面図である。1 is a schematic plan view of a power semiconductor module according to Embodiment 1. FIG. 実施の形態１に係るパワー半導体モジュールの、図１に示される領域ＩＩの概略部分拡大平面図である。2 is a schematic partial enlarged plan view of a region II shown in FIG. 1 of the power semiconductor module according to the first embodiment. FIG. 実施の形態１に係るパワー半導体モジュールの、図１に示される断面線ＩＩＩ－ＩＩＩにおける概略部分拡大断面図である。FIG. 3 is a schematic partially enlarged cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line III-III shown in FIG. 実施の形態１に係るパワー半導体モジュールの、図１に示される領域ＩＶの概略部分拡大平面図である。FIG. 4 is a schematic partial enlarged plan view of a region IV shown in FIG. 1 of the power semiconductor module according to the first embodiment. 実施の形態１に係るパワー半導体モジュールの、図４に示される断面線Ｖ－Ｖにおける部分拡大断面模式図である。FIG. 5 is a partially enlarged schematic cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line VV shown in FIG. 実施の形態１に係るパワー半導体モジュールに含まれる電子素子の回路を示す図である。3 is a diagram showing a circuit of an electronic element included in the power semiconductor module according to Embodiment 1. FIG. 実施の形態１に係る半導体装置の概略断面図である。1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. 実施の形態１に係るパワー半導体モジュールの変形例を説明するための部分拡大平面図である。FIG. 6 is a partially enlarged plan view for explaining a modification of the power semiconductor module according to the first embodiment. 実施の形態１に係るパワー半導体モジュールの変形例を説明するための部分拡大平面図である。FIG. 6 is a partially enlarged plan view for explaining a modification of the power semiconductor module according to the first embodiment. 実施の形態１に係るパワー半導体モジュールの変形例を説明するための部分拡大平面図である。FIG. 6 is a partially enlarged plan view for explaining a modification of the power semiconductor module according to the first embodiment. 実施の形態１に係るパワー半導体モジュールの製造方法のフローチャートを示す図である。FIG. 4 is a diagram showing a flowchart of a method for manufacturing a power semiconductor module according to the first embodiment. 実施の形態１に係るパワー半導体モジュールの製造方法の一工程を示す概略平面図である。FIG. 3 is a schematic plan view showing one step in the method for manufacturing the power semiconductor module according to the first embodiment. 実施の形態１のパワー半導体モジュールの製造方法における図１２に示される工程の、断面線ＸＩＩＩ－ＸＩＩＩにおける概略部分拡大断面図である。FIG. 13 is a schematic partial enlarged sectional view taken along a sectional line XIII-XIII of the process shown in FIG. 12 in the method for manufacturing the power semiconductor module of the first embodiment. 実施の形態１のパワー半導体モジュールの製造方法における、リードフレームにおけるチップコンデンサの配置の一例を説明するための模式図である。FIG. 6 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment. 実施の形態１のパワー半導体モジュールの製造方法における、リードフレームにおけるチップコンデンサの配置の一例を説明するための模式図である。FIG. 6 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment. 実施の形態１に係るパワー半導体モジュールの製造方法における、図１２に示される工程の次工程を示す概略平面図である。FIG. 13 is a schematic plan view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the power semiconductor module according to the first embodiment. 実施の形態１に係るパワー半導体モジュールの製造方法における、図１６に示す工程の、断面線ＸＶＩＩ－ＸＶＩＩにおける概略部分拡大断面図である。FIG. 17 is a schematic partial enlarged cross-sectional view taken along a cross-sectional line XVII-XVII in the process shown in FIG. 16 in the method for manufacturing the power semiconductor module according to the first embodiment. 実施の形態１に係る半導体装置の製造方法のフローチャートを示す図である。FIG. 3 is a diagram showing a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. 比較例のパワー半導体モジュールを示す概略断面図である。It is a schematic sectional drawing which shows the power semiconductor module of a comparative example. パワー半導体モジュールのチップコンデンサにおける充放電波形を説明するためのグラフを示す図である。It is a figure which shows the graph for demonstrating the charging / discharging waveform in the chip capacitor of a power semiconductor module. 実施の形態２に係るパワー半導体モジュールの概略断面図である。6 is a schematic cross-sectional view of a power semiconductor module according to Embodiment 2. FIG. 実施の形態２に係る半導体装置の概略断面図である。FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. 実施の形態２の変形例に係るパワー半導体モジュールの概略平面図である。FIG. 10 is a schematic plan view of a power semiconductor module according to a modification example of the second embodiment. 図２３に示したパワー半導体モジュールの領域ＸＸＩＶの概略部分拡大平面図である。FIG. 24 is a schematic partially enlarged plan view of a region XXIV of the power semiconductor module shown in FIG. 23. 図２４の線分ＸＸＶ－ＸＸＶにおける断面模式図である。FIG. 25 is a schematic cross-sectional view taken along line XXV-XXV in FIG. 24. 実施の形態３に係る電力変換システムの構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a power conversion system according to a third embodiment.
　以下、本発明の実施の形態を説明する。なお、同一の構成には同一の参照番号を付し、その説明は繰り返さない。 Hereinafter, embodiments of the present invention will be described. The same components are denoted by the same reference numerals, and description thereof will not be repeated.
　実施の形態１．
　＜パワー半導体モジュールの構成＞
　図１は、実施の形態１に係るパワー半導体モジュールの概略平面図である。図２は、実施の形態１に係るパワー半導体モジュールの、図１に示される領域ＩＩの概略部分拡大平面図である。図３は、実施の形態１に係るパワー半導体モジュールの、図１に示される断面線ＩＩＩ－ＩＩＩにおける概略部分拡大断面図である。図４は、実施の形態１に係るパワー半導体モジュールの、図１に示される領域ＩＶの概略部分拡大平面図である。図５は、実施の形態１に係るパワー半導体モジュールの、図４に示される断面線Ｖ－Ｖにおける部分拡大断面模式図である。図６は、実施の形態１に係るパワー半導体モジュールに含まれる電子素子の回路を示す図である。 Embodiment 1 FIG.
<Configuration of power semiconductor module>
1 is a schematic plan view of a power semiconductor module according to Embodiment 1. FIG. FIG. 2 is a schematic partial enlarged plan view of region II shown in FIG. 1 of the power semiconductor module according to the first embodiment. FIG. 3 is a schematic partial enlarged cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line III-III shown in FIG. 4 is a schematic partial enlarged plan view of region IV shown in FIG. 1 of the power semiconductor module according to the first embodiment. 5 is a partially enlarged schematic cross-sectional view of the power semiconductor module according to the first embodiment taken along a cross-sectional line VV shown in FIG. FIG. 6 is a diagram illustrating a circuit of an electronic element included in the power semiconductor module according to the first embodiment.
　図１から図６を参照して、実施の形態１のパワー半導体モジュール１を説明する。パワー半導体モジュール１は、複数のリード端子と、パワー半導体チップ２０と、第１から第３のチップコンデンサ２７，１２７，２２７と、パワー半導体チップ２０及び第１から第３のチップコンデンサ２７，１２７，２２７とは異なる種類の第１から第３の電子素子２５，１２５，２２５と、封止部材４０とを主に備える。パワー半導体モジュール１は、制御用半導体チップ２３をさらに備えてもよい。 The power semiconductor module 1 according to the first embodiment will be described with reference to FIGS. The power semiconductor module 1 includes a plurality of lead terminals, a power semiconductor chip 20, first to third chip capacitors 27, 127, 227, a power semiconductor chip 20, and first to third chip capacitors 27, 127, The first to third electronic elements 25, 125, and 225, which are different from 227, and the sealing member 40 are mainly provided. The power semiconductor module 1 may further include a control semiconductor chip 23.
　複数のリード端子は、たとえば金属製であり、第１のリード端子１１と、第２のリード端子１２と、第３のリード端子１１１と、第４のリード端子１１２と、第５のリード端子２１１と、第６のリード端子２１２と、第７のリード端子１３と、第８のリード端子１４と、第９のリード端子１５とをさらに含む。第１から第９のリード端子１１，１２，１１１，１１２，２１１，２１２，１３，１４，１５は、互いに離間されている。 The plurality of lead terminals are made of, for example, metal, and the first lead terminal 11, the second lead terminal 12, the third lead terminal 111, the fourth lead terminal 112, and the fifth lead terminal 211. And a sixth lead terminal 212, a seventh lead terminal 13, an eighth lead terminal 14, and a ninth lead terminal 15. The first to ninth lead terminals 11, 12, 111, 112, 211, 212, 13, 14, and 15 are separated from each other.
　図１から図３に示すように、第１のチップコンデンサ２７は、第１の電極２８ａと第２の電極２８ｂとを含む。第１のチップコンデンサ２７は、セラミック本体部２８ｃの両端に第１の電極２８ａと第２の電極２８ｂとが接続された構造を有する。第１のチップコンデンサ２７の第１の電極２８ａと第２の電極２８ｂとは、第１の導電性接着部３７で、第１のリード端子１１と第２のリード端子１２とにそれぞれ接合されている。第１のリード端子１１には第１の電子素子２５が搭載されている。 1 to 3, the first chip capacitor 27 includes a first electrode 28a and a second electrode 28b. The first chip capacitor 27 has a structure in which a first electrode 28a and a second electrode 28b are connected to both ends of a ceramic main body 28c. The first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the first conductive adhesive portion 37, respectively. Yes. A first electronic element 25 is mounted on the first lead terminal 11.
　図４に示すように、第２のチップコンデンサ１２７は、第３の電極１２８ａと第４の電極１２８ｂとを含む。第２のチップコンデンサ１２７は、セラミック本体部１２８ｃの両端に第３の電極１２８ａと第４の電極１２８ｂとが接続された構造を有する。第２のチップコンデンサ１２７の第３の電極１２８ａと第４の電極１２８ｂとは、第２の導電性接着部１３７で、第３のリード端子１１１と第４のリード端子１１２とにそれぞれ接合されている。第３のリード端子１１１には第２の電子素子１２５が搭載されている。 As shown in FIG. 4, the second chip capacitor 127 includes a third electrode 128a and a fourth electrode 128b. The second chip capacitor 127 has a structure in which a third electrode 128a and a fourth electrode 128b are connected to both ends of the ceramic main body 128c. The third electrode 128a and the fourth electrode 128b of the second chip capacitor 127 are joined to the third lead terminal 111 and the fourth lead terminal 112 by the second conductive adhesive portion 137, respectively. Yes. A second electronic element 125 is mounted on the third lead terminal 111.
　第３のチップコンデンサ２２７は、第５の電極２２８ａと第６の電極２２８ｂとを含む。第３のチップコンデンサ２２７は、セラミック本体部２２８ｃの両端に第５の電極２２８ａと第６の電極２２８ｂとが接続された構造を有する。第３のチップコンデンサ２２７の第５の電極２２８ａと第６の電極２２８ｂとは、第３の導電性接着部２３７で、第５のリード端子２１１と第６のリード端子２１２とにそれぞれ接合されている。第５のリード端子２１１には第３の電子素子２２５が搭載されている。 The third chip capacitor 227 includes a fifth electrode 228a and a sixth electrode 228b. The third chip capacitor 227 has a structure in which a fifth electrode 228a and a sixth electrode 228b are connected to both ends of the ceramic main body 228c. The fifth electrode 228a and the sixth electrode 228b of the third chip capacitor 227 are joined to the fifth lead terminal 211 and the sixth lead terminal 212 by the third conductive adhesive portion 237, respectively. Yes. A third electronic element 225 is mounted on the fifth lead terminal 211.
　複数のリード端子は、複数のパッド（例えば、第１のパッド１１ａ、第２のパッド１２ａ、第３のパッド１１１ａ、第４のパッド１１２ａ、第５のパッド２１１ａ、第６のパッド２１２ａ、第７のパッド１４ａ、第８のパッド１５ａ）を含んでもよい。第１のリード端子１１は、図２に示すように第１のリード端子１１のうち幅広の部分である第１のパッド１１ａを含んでもよい。第２のリード端子１２は、第２のリード端子１２のうち幅広の部分である第２のパッド１２ａを含んでもよい。図４に示すように、第３のリード端子１１１は、第３のリード端子１１１のうち幅広の部分である第３のパッド１１１ａを含んでもよい。第４のリード端子１１２は、第４のリード端子１１２のうち幅広の部分である第４のパッド１１２ａを含んでもよい。第５のリード端子２１１は、第５のリード端子２１１のうち幅広の部分である第５のパッド２１１ａを含んでもよい。第６のリード端子２１２は、第６のリード端子２１２のうち幅広の部分である第６のパッド２１２ａを含んでもよい。第８のリード端子１４は、第８のリード端子１４のうち幅広の部分である第７のパッド１４ａを含んでもよい。第９のリード端子１５は、第９のリード端子１５のうち幅広の部分である第８のパッド１５ａを含んでもよい。第９のリード端子１５は、図３に示すように第８のパッド１５ａと第５の突出部１５ｃとの間に段差部１５ｂを含む。段差部１５ｂは、第８のパッド１５ａに接続されている第１端部と、第１端部とは反対側の第２端部を含む。第２端部は、第１端部よりも上方にある。 The plurality of lead terminals include a plurality of pads (for example, a first pad 11a, a second pad 12a, a third pad 111a, a fourth pad 112a, a fifth pad 211a, a sixth pad 212a, a seventh pad). The pad 14a and the eighth pad 15a) may be included. As shown in FIG. 2, the first lead terminal 11 may include a first pad 11 a that is a wide portion of the first lead terminal 11. The second lead terminal 12 may include a second pad 12 a that is a wide portion of the second lead terminal 12. As shown in FIG. 4, the third lead terminal 111 may include a third pad 111 a that is a wide portion of the third lead terminal 111. The fourth lead terminal 112 may include a fourth pad 112 a that is a wide portion of the fourth lead terminal 112. The fifth lead terminal 211 may include a fifth pad 211 a that is a wide portion of the fifth lead terminal 211. The sixth lead terminal 212 may include a sixth pad 212 a that is a wider portion of the sixth lead terminal 212. The eighth lead terminal 14 may include a seventh pad 14 a that is a wide portion of the eighth lead terminal 14. The ninth lead terminal 15 may include an eighth pad 15 a that is a wide portion of the ninth lead terminal 15. As shown in FIG. 3, the ninth lead terminal 15 includes a step portion 15b between the eighth pad 15a and the fifth protruding portion 15c. The step portion 15b includes a first end connected to the eighth pad 15a and a second end opposite to the first end. The second end is above the first end.
　複数のリード端子は、封止部材４０から突出する突出部を含む。突出部は、折り曲げられている。例えば、第１のリード端子１１は、封止部材４０から突出する第１の突出部１１ｃを含む。第１の突出部１１ｃは、第１のパッド１１ａから水平に延在する第１突出部分１１ｄと、第１突出部分１１ｄから上方に延在する第２突出部分１１ｅとを含む。第２のリード端子１２は、封止部材４０から突出する第２の突出部１２ｃを含む。第２の突出部１２ｃは、第２のパッド１２ａから水平に延在する第３突出部分１２ｄと、第３突出部分１２ｄから上方に延在する第４突出部分１２ｅとを含む。第３のリード端子１１１は、封止部材４０から突出する第３の突出部１１１ｃを含む。第３の突出部１１１ｃは、第３のパッド１１１ａから水平に延在する第５突出部分１１１ｄと、第５突出部分１１１ｄから上方に延在する第６突出部分１１１ｅとを含む。第４のリード端子１１２は、封止部材４０から突出する第４の突出部１１２ｃを含む。第４の突出部１１２ｃは、第４のパッド１１２ａから水平に延在する第７突出部分１１２ｄと、第７突出部分１１２ｄから上方に延在する第８突出部分１１２ｅとを含む。第９のリード端子１５は、封止部材４０から突出する第５の突出部１５ｃを含む。第５の突出部１５ｃは、段差部１５ｂの第２端部から水平に延在する第９突出部分１５ｄと、第９突出部分１５ｄから上方に延在する第１０突出部分１５ｅとを含む。パワー半導体モジュール１では、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１のチップコンデンサ２７、第１の電子素子２５）はデュアルインラインパッケージ（ＤＩＰ）方式でパッケージされている。 The plurality of lead terminals include protrusions protruding from the sealing member 40. The protrusion is bent. For example, the first lead terminal 11 includes a first protrusion 11 c that protrudes from the sealing member 40. The first protrusion 11c includes a first protrusion 11d extending horizontally from the first pad 11a and a second protrusion 11e extending upward from the first protrusion 11d. The second lead terminal 12 includes a second protrusion 12 c that protrudes from the sealing member 40. The second protrusion 12c includes a third protrusion 12d extending horizontally from the second pad 12a and a fourth protrusion 12e extending upward from the third protrusion 12d. The third lead terminal 111 includes a third protrusion 111 c that protrudes from the sealing member 40. The third protrusion 111c includes a fifth protrusion 111d extending horizontally from the third pad 111a and a sixth protrusion 111e extending upward from the fifth protrusion 111d. The fourth lead terminal 112 includes a fourth projecting portion 112 c that projects from the sealing member 40. The fourth protrusion 112c includes a seventh protrusion 112d extending horizontally from the fourth pad 112a and an eighth protrusion 112e extending upward from the seventh protrusion 112d. The ninth lead terminal 15 includes a fifth projecting portion 15 c that projects from the sealing member 40. The fifth projecting portion 15c includes a ninth projecting portion 15d extending horizontally from the second end of the stepped portion 15b and a tenth projecting portion 15e extending upward from the ninth projecting portion 15d. In the power semiconductor module 1, electronic components (power semiconductor chip 20, control semiconductor chip 23, first chip capacitor 27, first electronic element 25) are packaged in a dual in-line package (DIP) system.
　複数のリード端子は、例えば、銅、アルミニウムおよびこれらの合金のような導電性材料で形成されている。複数のリード端子の表面には、酸化防止のためにめっき層を形成してもよい。めっき層を構成する材料としてはニッケルや銀を用いることができる。複数のリード端子の一部は、接合性および実装性を向上させるため、銀めっき部のようなめっき部１７で被覆されてもよい。めっき部１７は、複数のリード端子を構成する材料よりも酸化されにくい材料で形成されてもよい。複数のリード端子を構成する材料よりも酸化されにくい材料は、例えば、銀のような貴金属材料やニッケルなどである。例えば、第１のリード端子１１の最も内側の部分に、めっき部１７が形成されてもよい。第２のリード端子１２の最も内側の部分に、めっき部１７が形成されてもよい。第９のリード端子１５の第８のパッド１５ａの一部に、めっき部１７が形成されてもよい。 The plurality of lead terminals are made of a conductive material such as copper, aluminum, and alloys thereof. A plating layer may be formed on the surfaces of the plurality of lead terminals to prevent oxidation. Nickel and silver can be used as a material constituting the plating layer. Some of the plurality of lead terminals may be covered with a plating part 17 such as a silver plating part in order to improve the bondability and the mountability. The plated portion 17 may be formed of a material that is less likely to be oxidized than the material constituting the plurality of lead terminals. The material that is less likely to be oxidized than the material constituting the plurality of lead terminals is, for example, a noble metal material such as silver or nickel. For example, the plating part 17 may be formed in the innermost part of the first lead terminal 11. A plating portion 17 may be formed on the innermost portion of the second lead terminal 12. A plating portion 17 may be formed on a part of the eighth pad 15 a of the ninth lead terminal 15.
　第１のリード端子１１は、第１の貫通孔１６ａを含んでもよい。本実施の形態では、第１の貫通孔１６ａは、第１のチップコンデンサ２７に対して外側（第１の突出部１１ｃ側）に形成されている。第１の貫通孔１６ａは、第１のチップコンデンサ２７に対して内側（第１の突出部１１ｃとは反対側）に形成されてもよいし、第１のチップコンデンサ２７に対して外側と内側とに形成されてもよい。第１のリード端子１１の中央から見て、第１の貫通孔１６ａと第１の電子素子２５とは互いに反対側の領域に配置されていることが好ましい。第２のリード端子１２は、第２の貫通孔１６ｂを含んでもよい。本実施の形態では、第２の貫通孔１６ｂは、第１のチップコンデンサ２７に対して外側（第２の突出部１２ｃ側）に形成されている。 The first lead terminal 11 may include a first through hole 16a. In the present embodiment, the first through hole 16 a is formed on the outer side (the first protruding portion 11 c side) with respect to the first chip capacitor 27. The first through hole 16a may be formed on the inner side (opposite to the first projecting portion 11c) with respect to the first chip capacitor 27, or on the outer side and the inner side with respect to the first chip capacitor 27. And may be formed. As viewed from the center of the first lead terminal 11, the first through hole 16a and the first electronic element 25 are preferably disposed in regions opposite to each other. The second lead terminal 12 may include a second through hole 16b. In the present embodiment, the second through hole 16 b is formed on the outer side (the second projecting portion 12 c side) with respect to the first chip capacitor 27.
　第１の貫通孔１６ａおよび第２の貫通孔１６ｂを基点に第１のリード端子１１および第２のリード端子１２が同じように変形するため、第１のリード端子１１および第２のリード端子１２がばらばらに変形する場合と比べて、第１のリード端子１１と第２のリード端子１２との間を橋渡しするように配置されている第１のチップコンデンサ２７の剥離が抑制できる。第２の貫通孔１６ｂは、第１のチップコンデンサ２７に対して内側（第２の突出部１２ｃとは反対側）に形成されてもよいし、第１のチップコンデンサ２７に対して外側と内側とに形成されてもよい。 Since the first lead terminal 11 and the second lead terminal 12 are similarly deformed based on the first through hole 16a and the second through hole 16b, the first lead terminal 11 and the second lead terminal 12 are deformed in the same manner. Compared with the case where the first lead terminal 11 and the second lead terminal 12 are bridged, the separation of the first chip capacitor 27 arranged so as to bridge between the first lead terminal 11 and the second lead terminal 12 can be suppressed. The second through hole 16b may be formed on the inner side (opposite to the second protrusion 12c) with respect to the first chip capacitor 27, or on the outer side and the inner side with respect to the first chip capacitor 27. And may be formed.
　パワー半導体チップ２０は、例えば、逆導通ＩＧＢＴ（ＲＣ－ＩＧＢＴ）、フリーホイールダイオード（ＦＷＤ）を含む絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）、金属酸化物半導体電界効果トランジスタ（ＭＯＳＦＥＴ）またはダイオードであってもよい。パワー半導体チップ２０は、例えば、１Ａ以上の定格電流と１００Ｖ以上の定格電圧とを有している。パワー半導体チップ２０は、シリコン（Ｓｉ）、シリコンカーバイド（ＳｉＣ）または窒化ガリウム（ＧａＮ）のような半導体材料で形成されてもよい。パワー半導体モジュール１は、１つのパワー半導体チップ２０を含んでもよいし、複数のパワー半導体チップ２０を含んでもよい。本実施の形態では、パワー半導体モジュール１は、高圧用のパワー半導体チップ２０と、低圧用のパワー半導体チップ２０とを含んでいる。高圧用のパワー半導体チップ２０は、第９のリード端子１５の第８のパッド１５ａに接合されている。 The power semiconductor chip 20 may be, for example, a reverse conducting IGBT (RC-IGBT), an insulated gate bipolar transistor (IGBT) including a free wheel diode (FWD), a metal oxide semiconductor field effect transistor (MOSFET), or a diode. Good. For example, the power semiconductor chip 20 has a rated current of 1 A or more and a rated voltage of 100 V or more. The power semiconductor chip 20 may be formed of a semiconductor material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The power semiconductor module 1 may include one power semiconductor chip 20 or a plurality of power semiconductor chips 20. In the present embodiment, the power semiconductor module 1 includes a high voltage power semiconductor chip 20 and a low voltage power semiconductor chip 20. The high voltage power semiconductor chip 20 is bonded to the eighth pad 15 a of the ninth lead terminal 15.
　パワー半導体チップ２０は、複数のリード端子の少なくとも１つ（第９のリード端子１５）に接合されている。パワー半導体チップ２０が接合されている複数のリード端子の少なくとも１つ（第９のリード端子１５）は、第１から第８のリード端子１１，１２，１１１，１１２，２１１，２１２、１３，１４とは異なっている。パワー半導体チップ２０は、はんだ接合部３０で、第９のリード端子１５の第８のパッド１５ａ（特に、めっき部１７）に接合されている。はんだ接合部３０は、パワー半導体チップ２０で発生する熱を第９のリード端子１５に効率的に伝達させ得る。パワー半導体チップ２０は、導電ワイヤ２９を介して、複数のリード端子（特に、めっき部１７）に電気的に接続されている。なお、はんだ接合部３０に代えて、銀ペーストに代表される導電性接着剤や、銀または銅を含む焼結材料を用いてもよい。パワー半導体チップ２０は、３相のインバータ駆動のため、Ｐ側として３個、Ｎ側として３個の計６個実装している。 The power semiconductor chip 20 is bonded to at least one of the plurality of lead terminals (the ninth lead terminal 15). At least one of the plurality of lead terminals (the ninth lead terminal 15) to which the power semiconductor chip 20 is bonded is the first to eighth lead terminals 11, 12, 111, 112, 211, 212, 13, 14 Is different. The power semiconductor chip 20 is joined to the eighth pad 15 a (particularly, the plating portion 17) of the ninth lead terminal 15 by the solder joint portion 30. The solder joint 30 can efficiently transfer the heat generated in the power semiconductor chip 20 to the ninth lead terminal 15. The power semiconductor chip 20 is electrically connected to a plurality of lead terminals (particularly, the plating portion 17) via the conductive wires 29. In place of the solder joint portion 30, a conductive adhesive typified by silver paste or a sintered material containing silver or copper may be used. Since the power semiconductor chip 20 is driven by a three-phase inverter, a total of six power semiconductor chips 20 are mounted, three on the P side and three on the N side.
　制御用半導体チップ２３は、パワー半導体チップ２０を制御するように構成されている。例えば、制御用半導体チップ２３は、パワー半導体チップ２０のゲート電圧を制御するように構成されてもよい。制御用半導体チップ２３は、パワー半導体チップ２０を流れる電流を検知するように構成されてもよい。パワー半導体モジュール１は、パワー半導体チップ２０と、パワー半導体チップ２０を制御するように構成されている制御用半導体チップ２３とを内蔵するインテリジェントパワーモジュール（ＩＰＭ）である。制御用半導体チップ２３は、導電ワイヤ２９を介して、パワー半導体チップ２０に電気的に接続されている。制御用半導体チップ２３は、導電ワイヤ２９を介して、第１のリード端子１１及び第２のリード端子１２に電気的に接続されている。 The control semiconductor chip 23 is configured to control the power semiconductor chip 20. For example, the control semiconductor chip 23 may be configured to control the gate voltage of the power semiconductor chip 20. The control semiconductor chip 23 may be configured to detect a current flowing through the power semiconductor chip 20. The power semiconductor module 1 is an intelligent power module (IPM) that includes a power semiconductor chip 20 and a control semiconductor chip 23 configured to control the power semiconductor chip 20. The control semiconductor chip 23 is electrically connected to the power semiconductor chip 20 via a conductive wire 29. The control semiconductor chip 23 is electrically connected to the first lead terminal 11 and the second lead terminal 12 via a conductive wire 29.
　パワー半導体モジュール１は、１つの制御用半導体チップ２３を含んでもよいし、複数の制御用半導体チップ２３を含んでもよい。本実施の形態では、パワー半導体モジュール１は、高圧用のパワー半導体チップ２０を制御するように構成されている高圧用の制御用半導体チップ２３と、低圧用のパワー半導体チップ２０を制御するように構成されている低圧用の制御用半導体チップ２３とを含んでいる。 The power semiconductor module 1 may include one control semiconductor chip 23 or a plurality of control semiconductor chips 23. In the present embodiment, the power semiconductor module 1 controls the high-voltage control semiconductor chip 23 configured to control the high-voltage power semiconductor chip 20 and the low-voltage power semiconductor chip 20. The low-voltage control semiconductor chip 23 is included.
　制御用半導体チップ２３は、複数のリード端子の少なくとも１つ（第８のリード端子１４）に接合されている。制御用半導体チップ２３が接合されている複数のリード端子の少なくとも１つ（第８のリード端子１４）は、第１から第７のリード端子１１，１２，１１１，１１２，２１１，２１２，１３及び第９のリード端子１５とは異なっている。制御用半導体チップ２３は、導電接合部３３で、第８のリード端子１４の第７のパッド１４ａに接合されている。導電接合部３３は、例えば、はんだ接合部であってもよいし、後述する導電性接着部３５であってもよい。 The control semiconductor chip 23 is bonded to at least one of the plurality of lead terminals (eighth lead terminal 14). At least one of the plurality of lead terminals (eighth lead terminal 14) to which the control semiconductor chip 23 is bonded is the first to seventh lead terminals 11, 12, 111, 112, 211, 212, 13 and This is different from the ninth lead terminal 15. The control semiconductor chip 23 is bonded to the seventh pad 14 a of the eighth lead terminal 14 by a conductive bonding portion 33. The conductive joint portion 33 may be, for example, a solder joint portion or a conductive adhesive portion 35 described later.
　図３に示すように、パワー半導体チップ２０が実装される第８のパッド１５ａと、制御用半導体チップ２３が実装される第８のリード端子１４（第７のパッド１４ａ（図１参照））とは、オフセットされている。オフセットされる量は、封止部材４０にて封止された時に第７のパッド１４ａおよび第８のパッド１５ａが外部に露出せず、外部から十分に絶縁されていれば、任意に選択できる。 As shown in FIG. 3, an eighth pad 15a on which the power semiconductor chip 20 is mounted, an eighth lead terminal 14 (seventh pad 14a (see FIG. 1)) on which the control semiconductor chip 23 is mounted, and Are offset. The amount of offset can be arbitrarily selected as long as the seventh pad 14a and the eighth pad 15a are not exposed to the outside when sealed by the sealing member 40 and are sufficiently insulated from the outside.
　第１から第３の電子素子２５，１２５，２２５は、パワー半導体チップ２０、制御用半導体チップ２３及び第１から第３のチップコンデンサ２７，１２７，２２７とは異なる種類の電子部品である。第１から第３の電子素子２５，１２５，２２５は、パワー半導体チップ２０を制御する制御回路の一部を構成している。第１から第３の電子素子２５，１２５，２２５は、受動型の電子部品であってもよい。受動型の電子部品は、例えば、チップダイオードのようなダイオード２５ａ、または、チップ抵抗器のような抵抗器２５ｂである。受動型の電子部品の一例であるダイオード２５ａは、例えば、１Ａ未満の定格電流と１００Ｖ未満の定格電圧とを有している。本実施の形態では、第１から第３の電子素子２５，１２５，２２５は、チップダイオードのような整流用半導体チップである。図６に示されるように、整流用半導体チップは、ダイオード２５ａに加えて、電流制限抵抗としての抵抗器２５ｂを内蔵してもよい。抵抗器２５ｂを内蔵する整流用半導体チップと、第１から第３のチップコンデンサ２７，１２７，２２７のいずれか１つとは、ブートストラップ回路を構成してもよい。第１から第３の電子素子２５，１２５，２２５は、ブートストラップダイオード（ＢＳＤ）であってもよい。ブートストラップ回路は、Ｎ側のゲート駆動電源のみでＰ側のゲート駆動電源を作り出す回路である。ブートストラップ回路は、ゲート駆動部の回路に整流用半導体チップとコンデンサとにより構成される。ブートストラップ回路は、スイッチング素子（例えば、パワー半導体チップ２０）の出力側（ドレイン－ソース間、コレクタ－エミッタ間）に配置されるスナバ回路とは異なる。第１の電子素子２５は、導電ワイヤ２９及び第１のリード端子１１を介して、制御用半導体チップ２３に電気的に接続されてもよい。第１の電子素子２５は、導電ワイヤ２９を介して、第７のリード端子１３（特に、めっき部１７）に電気的に接続されてもよい。同様に、第２および第３の電子素子１２５，２２５は、導電ワイヤ２９及び第３のリード端子１１１または第５のリード端子２１１を介して、制御用半導体チップ２３に電気的に接続されてもよい。第２および第３の電子素子１２５，２２５は、導電ワイヤ２９を介して、第７のリード端子１３（特に、めっき部１７）に電気的に接続されてもよい。 The first to third electronic elements 25, 125, and 225 are different types of electronic components from the power semiconductor chip 20, the control semiconductor chip 23, and the first to third chip capacitors 27, 127, and 227. The first to third electronic elements 25, 125, and 225 constitute a part of a control circuit that controls the power semiconductor chip 20. The first to third electronic elements 25, 125, 225 may be passive electronic components. The passive electronic component is, for example, a diode 25a such as a chip diode or a resistor 25b such as a chip resistor. The diode 25a, which is an example of a passive electronic component, has, for example, a rated current of less than 1A and a rated voltage of less than 100V. In the present embodiment, the first to third electronic elements 25, 125, 225 are rectifying semiconductor chips such as chip diodes. As shown in FIG. 6, the rectifying semiconductor chip may include a resistor 25b as a current limiting resistor in addition to the diode 25a. The rectifying semiconductor chip incorporating the resistor 25b and any one of the first to third chip capacitors 27, 127, 227 may constitute a bootstrap circuit. The first to third electronic elements 25, 125, 225 may be bootstrap diodes (BSD). The bootstrap circuit is a circuit that creates a P-side gate drive power supply only by an N-side gate drive power supply. The bootstrap circuit includes a rectifying semiconductor chip and a capacitor in a circuit of a gate driving unit. The bootstrap circuit is different from a snubber circuit disposed on the output side (between drain and source, between collector and emitter) of a switching element (for example, power semiconductor chip 20). The first electronic element 25 may be electrically connected to the control semiconductor chip 23 via the conductive wire 29 and the first lead terminal 11. The first electronic element 25 may be electrically connected to the seventh lead terminal 13 (particularly, the plating portion 17) via the conductive wire 29. Similarly, the second and third electronic elements 125 and 225 may be electrically connected to the control semiconductor chip 23 via the conductive wire 29 and the third lead terminal 111 or the fifth lead terminal 211. Good. The second and third electronic elements 125 and 225 may be electrically connected to the seventh lead terminal 13 (particularly, the plating portion 17) via the conductive wire 29.
　上述したブートストラップ回路について、たとえば３相分のパワー半導体チップ２０を駆動するため、整流用半導体チップである電子素子とチップコンデンサとを３ペア準備する。すなわち、第１の電子素子２５と第１のチップコンデンサ２７とのペア、第２の電子素子１２５と第２のチップコンデンサ１２７とのペア、および第３の電子素子２２５と第３のチップコンデンサ２２７とのペア、を準備する。このとき、図４に示すように第１から第３の電子素子２５，１２５，２２５は等間隔に配置することが好ましい。また、第１から第３のチップコンデンサ２７，１２７，２２７も等間隔で配置することが好ましい。 For the bootstrap circuit described above, for example, three pairs of electronic elements that are rectifying semiconductor chips and chip capacitors are prepared in order to drive the power semiconductor chip 20 for three phases. That is, a pair of the first electronic element 25 and the first chip capacitor 27, a pair of the second electronic element 125 and the second chip capacitor 127, and a third electronic element 225 and the third chip capacitor 227. Prepare a pair, with. At this time, the first to third electronic elements 25, 125, 225 are preferably arranged at equal intervals as shown in FIG. The first to third chip capacitors 27, 127, 227 are also preferably arranged at equal intervals.
　また、図４に示すように、３相に対応する第１の電子素子２５と第１のチップコンデンサ２７とのペア、第２の電子素子１２５と第２のチップコンデンサ１２７とのペア、および第３の電子素子２２５と第３のチップコンデンサ２２７とのペア、という３つのペアの間において、電子素子とチップコンデンサとの相対的な配置が同じであることが好ましい。また、第１の電子素子２５と第１のチップコンデンサ２７との間の距離Ｌ２１と、第２の電子素子１２５と第２のチップコンデンサ１２７との間の距離Ｌ２２と、第３の電子素子２２５と第３のチップコンデンサ２２７との間の距離Ｌ２３とが同じであることが好ましい。この場合、各相の電子素子とチップコンデンサとの間の配線抵抗のばらつきが抑えられる。 4, a pair of the first electronic element 25 and the first chip capacitor 27 corresponding to the three phases, a pair of the second electronic element 125 and the second chip capacitor 127, and the first It is preferable that the relative arrangement of the electronic element and the chip capacitor is the same among the three pairs of the three electronic elements 225 and the third chip capacitor 227. Further, the distance L21 between the first electronic element 25 and the first chip capacitor 27, the distance L22 between the second electronic element 125 and the second chip capacitor 127, and the third electronic element 225. It is preferable that the distance L23 between the first chip capacitor 227 and the third chip capacitor 227 is the same. In this case, variation in wiring resistance between the electronic element of each phase and the chip capacitor can be suppressed.
　さらに、第１から第３の電子素子２５，１２５，２２５と第１から第３のチップコンデンサ２７，１２７，２２７の周囲の第１から第６のリード端子１１，１２，１１１，１１２，２１１，２１２の形状が３相間で同一となっていることが好ましい。具体的には、第１から第３の電子素子２５，１２５，２２５と第１から第３のチップコンデンサ２７，１２７，２２７との直下から外周側に位置する第１のリード端子１１、第３のリード端子１１１、第５のリード端子２１１の形状が同一であることが好ましい。また、第１から第３の電子素子２５，１２５，２２５と第１から第３のチップコンデンサ２７，１２７，２２７との直下から外周側に位置する第２のリード端子１２、第４のリード端子１１２、第６のリード端子２１２の形状が同一であることが好ましい。そうすれば、実装時に第１から第３のチップコンデンサ２７，１２７，２２７の位置が少しずれた場合でも、隣のチップコンデンサの実装位置と容易に比較することができる。この結果、目視で外観検査をする場合、第１から第３のチップコンデンサ２７，１２７，２２７の実装位置ずれに気づきやすい。 Furthermore, the first to sixth lead terminals 11, 12, 111, 112, 211, around the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227, The shape of 212 is preferably the same among the three phases. Specifically, the first lead terminal 11, the third lead terminal 11, and the third lead terminal 11 located on the outer peripheral side from directly below the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227. The lead terminals 111 and the fifth lead terminal 211 preferably have the same shape. Further, the second lead terminal 12 and the fourth lead terminal located on the outer peripheral side from directly below the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227. 112 and the sixth lead terminal 212 preferably have the same shape. Then, even when the positions of the first to third chip capacitors 27, 127, and 227 are slightly shifted at the time of mounting, it can be easily compared with the mounting position of the adjacent chip capacitor. As a result, when visual inspection is performed visually, it is easy to notice mounting position deviations of the first to third chip capacitors 27, 127, and 227.
　第１から第３の電子素子２５，１２５，２２５は、導電性接着部３５で、複数のリード端子の１つに接合されている。特定的には、第１から第３の電子素子２５，１２５，２２５は、導電性接着部３５で、それぞれ第１のリード端子１１、第３のリード端子１１１、および第５のリード端子２１１に接合されている。導電性接着部３５は、第１の含有率で導電性フィラーを含んでいる。導電性接着部３５は、第１の樹脂と、第１の樹脂に分散された導電性フィラーとを含む。導電性フィラーは、例えば、銀、ニッケル及び銅からなる群から選択される１つ以上の導電性材料で構成されてもよい。本明細書において、導電性フィラーは、導電性粒子も含む。第１の樹脂は、例えば、エポキシ樹脂であってもよい。第１の含有率は、６５重量％以下であってもよく、６０重量％以下であってもよい。本明細書において、第１の含有率は、導電性接着部３５の重量に対する導電性接着部３５に含まれる導電性フィラーの重量の比を、重量％の単位で表したものである。 The first to third electronic elements 25, 125, and 225 are joined to one of a plurality of lead terminals by a conductive adhesive portion 35. Specifically, the first to third electronic elements 25, 125, and 225 are connected to the first lead terminal 11, the third lead terminal 111, and the fifth lead terminal 211 by the conductive adhesive portion 35, respectively. It is joined. The conductive adhesive portion 35 includes a conductive filler with a first content rate. The conductive adhesive portion 35 includes a first resin and a conductive filler dispersed in the first resin. The conductive filler may be made of, for example, one or more conductive materials selected from the group consisting of silver, nickel, and copper. In the present specification, the conductive filler also includes conductive particles. The first resin may be, for example, an epoxy resin. The first content may be 65% by weight or less, or 60% by weight or less. In this specification, the 1st content rate represents the ratio of the weight of the electroconductive filler contained in the electroconductive adhesion part 35 with respect to the weight of the electroconductive adhesion part 35 in the unit of weight%.
　第１から第３のチップコンデンサ２７，１２７，２２７は、例えば、表面実装型の積層セラミックコンデンサであってもよい。第１から第３のチップコンデンサ２７，１２７，２２７は、パワー半導体チップ２０を制御する制御回路の一部を構成している。第１から第３のチップコンデンサ２７，１２７，２２７は、ブートストラップ回路の一部を構成するブートストラップコンデンサ（ＢＳＣ）であってもよい。第１から第３のチップコンデンサ２７，１２７，２２７の容量は、制御用半導体チップ２３の消費電力、パワー半導体チップ２０のゲート容量並びに第１から第３のチップコンデンサ２７，１２７，２２７の充電時間及び放電時間に応じて、適切に定められる。複数のリード端子に接合される電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）の中で、第１から第３のチップコンデンサ２７，１２７，２２７が最も背が高い。 The first to third chip capacitors 27, 127, and 227 may be, for example, surface mount type multilayer ceramic capacitors. The first to third chip capacitors 27, 127, and 227 constitute a part of a control circuit that controls the power semiconductor chip 20. The first to third chip capacitors 27, 127, and 227 may be bootstrap capacitors (BSCs) that constitute a part of the bootstrap circuit. The capacities of the first to third chip capacitors 27, 127, and 227 are the power consumption of the control semiconductor chip 23, the gate capacity of the power semiconductor chip 20, and the charging time of the first to third chip capacitors 27, 127, and 227. And appropriately determined according to the discharge time. Electronic components joined to a plurality of lead terminals (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225) Among them, the first to third chip capacitors 27, 127, 227 are the tallest.
　上述のように、第１のチップコンデンサ２７の第１の電極２８ａと第２の電極２８ｂとは、第１の導電性接着部３７で、第１のリード端子１１と第２のリード端子１２とにそれぞれ接合されている。このため、第１の電子素子２５と第１のチップコンデンサ２７との間の配線抵抗を、ワイヤを用いて両者を接続する場合より低減できる。 As described above, the first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are the first conductive adhesive portion 37, and the first lead terminal 11, the second lead terminal 12, and the like. Are joined to each other. For this reason, the wiring resistance between the 1st electronic element 25 and the 1st chip capacitor 27 can be reduced rather than the case where both are connected using a wire.
　第１の導電性接着部３７は、第２の樹脂と、第２の樹脂に分散された導電性フィラーとを含む。本実施の形態では、第１の導電性接着部３７に含まれる導電性フィラーは、導電性接着部３５に含まれる導電性フィラーと同じ材料である。第２の樹脂は、例えば、エポキシ樹脂であってもよい。第２の樹脂は、第１の樹脂と同じ材料であってもよいし、異なる材料であってもよい。 The first conductive adhesive portion 37 includes a second resin and a conductive filler dispersed in the second resin. In the present embodiment, the conductive filler included in the first conductive adhesive portion 37 is the same material as the conductive filler included in the conductive adhesive portion 35. For example, the second resin may be an epoxy resin. The second resin may be the same material as the first resin, or may be a different material.
　第１の電極２８ａに対向する第１のリード端子１１の第１の表面１１ｓ（図３参照）は、銅または錫で構成されてもよい。第２の電極２８ｂに対向する第２のリード端子１２の第２の表面１２ｓ（図３参照）は、銅または錫で構成されてもよい。言い換えると、第１のリード端子１１の第１の表面１１ｓ及び第２のリード端子１２の第２の表面１２ｓは、酸化されにくい材料で形成されているめっき部１７から露出してもよい。第１のリード端子１１の第１の表面１１ｓ及び第２のリード端子１２の第２の表面１２ｓは、めっき部１７よりも酸化されやすい。しかし、第１の導電性接着部３７は相対的に低い電気抵抗を有する。そのため、第１のリード端子１１の第１の表面１１ｓ及び第２のリード端子１２の第２の表面１２ｓにめっき部１７を施さなくても、第１の導電性接着部３７を介した第１のリード端子１１と第１のチップコンデンサ２７との間の低抵抗かつ信頼性を有する電気的接続と、第１の導電性接着部３７を介した第２のリード端子１２と第１のチップコンデンサ２７との間の低抵抗かつ信頼性を有する電気的接続とを得ることができる。 The first surface 11s (see FIG. 3) of the first lead terminal 11 facing the first electrode 28a may be made of copper or tin. The second surface 12s (see FIG. 3) of the second lead terminal 12 facing the second electrode 28b may be made of copper or tin. In other words, the first surface 11s of the first lead terminal 11 and the second surface 12s of the second lead terminal 12 may be exposed from the plated portion 17 formed of a material that is not easily oxidized. The first surface 11 s of the first lead terminal 11 and the second surface 12 s of the second lead terminal 12 are more easily oxidized than the plated portion 17. However, the first conductive adhesive portion 37 has a relatively low electrical resistance. Therefore, even if the plated portion 17 is not applied to the first surface 11 s of the first lead terminal 11 and the second surface 12 s of the second lead terminal 12, the first through the first conductive adhesive portion 37. Low-resistance and reliable electrical connection between the lead terminal 11 and the first chip capacitor 27, and the second lead terminal 12 and the first chip capacitor via the first conductive adhesive portion 37. 27 and an electrical connection having low resistance and reliability can be obtained.
　第１のチップコンデンサ２７の第１の電極２８ａと第２の電極２８ｂとは、たとえば金、銀、パラジウムで構成されていることが好ましいが、ニッケル、銅または錫で構成されてもよい。言い換えると、第１の電極２８ａの表面と第２の電極２８ｂの表面とは、銀のような酸化されにくい材料で形成されていなくてもよい。第１の電極２８ａの表面と第２の電極２８ｂの表面とは、めっき部１７よりも酸化されやすい。しかし、第１の導電性接着部３７は相対的に低い電気抵抗を有する。そのため、第１の電極２８ａと第２の電極２８ｂとが銅または錫で構成されていても、導電性接着部３５を介した第１のリード端子１１と第１のチップコンデンサ２７との間の低抵抗かつ信頼性を有する電気的接続と、第１の導電性接着部３７を介した第２のリード端子１２と第１のチップコンデンサ２７との間の低抵抗かつ信頼性を有する電気的接続とを得ることができる。 The first electrode 28a and the second electrode 28b of the first chip capacitor 27 are preferably made of, for example, gold, silver, or palladium, but may be made of nickel, copper, or tin. In other words, the surface of the first electrode 28a and the surface of the second electrode 28b may not be formed of a material that is difficult to be oxidized, such as silver. The surface of the first electrode 28 a and the surface of the second electrode 28 b are more easily oxidized than the plated portion 17. However, the first conductive adhesive portion 37 has a relatively low electrical resistance. Therefore, even if the first electrode 28a and the second electrode 28b are made of copper or tin, the gap between the first lead terminal 11 and the first chip capacitor 27 via the conductive adhesive portion 35 is not limited. Low resistance and reliable electrical connection and low resistance and reliable electrical connection between the second lead terminal 12 and the first chip capacitor 27 via the first conductive adhesive portion 37 And you can get
　第１の電子素子２５と第１のチップコンデンサ２７とは、第１のリード端子１１に接合されてもよい。そのため、第１の電子素子２５と第１のチップコンデンサ２７との間の間隔である距離Ｌ２（図３参照）を相対的に小さくできる。第１の電子素子２５と第１のチップコンデンサ２７との間の配線抵抗を減少させることができる。また、第１のチップコンデンサ２７とパワー半導体チップ２０との間の間隔である距離Ｌ１（図３参照）を、第１の電子素子２５と第１のチップコンデンサ２７との間の間隔である距離Ｌ２より大きくすることができる。この結果、第１のチップコンデンサ２７に対する、パワー半導体チップ２０から発生する電磁ノイズ及び熱の影響が抑制される。したがって、第１の電子素子２５（例えば、ダイオード２５ａ及び抵抗器２５ｂを内蔵する整流用半導体チップ）と第１のチップコンデンサ２７とを含む電気回路（例えば、ブートストラップ回路）の動作が安定化する。 The first electronic element 25 and the first chip capacitor 27 may be joined to the first lead terminal 11. For this reason, the distance L2 (see FIG. 3), which is the distance between the first electronic element 25 and the first chip capacitor 27, can be made relatively small. The wiring resistance between the first electronic element 25 and the first chip capacitor 27 can be reduced. Further, the distance L1 (see FIG. 3) that is the distance between the first chip capacitor 27 and the power semiconductor chip 20 is the distance that is the distance between the first electronic element 25 and the first chip capacitor 27. It can be larger than L2. As a result, the influence of electromagnetic noise and heat generated from the power semiconductor chip 20 on the first chip capacitor 27 is suppressed. Therefore, the operation of an electric circuit (for example, a bootstrap circuit) including the first electronic element 25 (for example, a rectifying semiconductor chip incorporating the diode 25a and the resistor 25b) and the first chip capacitor 27 is stabilized. .
　封止部材４０は、複数のリード端子の一部と、パワー半導体チップ２０と、制御用半導体チップ２３と、第１から第３のチップコンデンサ２７，１２７，２２７と、第１から第３の電子素子２５，１２５，２２５と、導電ワイヤ２９とを封止する。封止部材４０は、電気的絶縁性を有する。封止部材４０は、モールド樹脂で形成されてもよい。封止部材４０は、例えば、エポキシ樹脂、ポリイミド樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、フッ素系樹脂、イソシアネート系樹脂、シリコーン樹脂及びこれらの組み合わせからなる群から選択される樹脂材料で構成されてもよい。また、封止部材４０として、絶縁性の樹脂、たとえばエポキシ系の樹脂からなる基材に、熱伝導を向上させるためにシリカやアルミナなどの材料が混ざったものを用いてもよい。 The sealing member 40 includes a part of a plurality of lead terminals, the power semiconductor chip 20, the control semiconductor chip 23, the first to third chip capacitors 27, 127, 227, and the first to third electrons. The elements 25, 125, 225 and the conductive wire 29 are sealed. The sealing member 40 has electrical insulation. The sealing member 40 may be formed of a mold resin. The sealing member 40 may be made of, for example, a resin material selected from the group consisting of epoxy resins, polyimide resins, polyamide resins, polyamideimide resins, fluorine resins, isocyanate resins, silicone resins, and combinations thereof. . Further, as the sealing member 40, a base material made of an insulating resin such as an epoxy resin may be used in which a material such as silica or alumina is mixed in order to improve heat conduction.
　第１の突出部１１ｃは、封止部材４０の部分４１ａから突出している。封止部材４０の部分４１ａと第１のチップコンデンサ２７との間の最短距離ｄは、第１のリード端子１１の厚さの５倍以下であってもよい。第１のリード端子１１の厚さは、例えば、０．２ｍｍ以上であってもよい。第１のリード端子１１の厚さは、例えば、２．０ｍｍ以下であってもよい。第２の突出部１２ｃは、封止部材４０の部分４１ｂから突出している。封止部材４０の部分４１ｂと第１のチップコンデンサ２７との間の最短距離ｄは、第２のリード端子１２の厚さｔの５倍以下であってもよい。第２のリード端子１２の厚さｔは、例えば、０．２ｍｍ以上であってもよい。第２のリード端子１２の厚さｔは、例えば、２．０ｍｍ以下であってもよい。 The first protrusion 11c protrudes from the portion 41a of the sealing member 40. The shortest distance d between the portion 41 a of the sealing member 40 and the first chip capacitor 27 may be 5 times or less the thickness of the first lead terminal 11. The thickness of the first lead terminal 11 may be 0.2 mm or more, for example. The thickness of the first lead terminal 11 may be, for example, 2.0 mm or less. The second protrusion 12 c protrudes from the portion 41 b of the sealing member 40. The shortest distance d between the portion 41 b of the sealing member 40 and the first chip capacitor 27 may be 5 times or less the thickness t of the second lead terminal 12. The thickness t of the second lead terminal 12 may be 0.2 mm or more, for example. The thickness t of the second lead terminal 12 may be 2.0 mm or less, for example.
　そのため、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１のチップコンデンサ２７、第１の電子素子２５）を封止部材４０で封止する工程（図１１、図１６及び図１７を参照）において、金型４５の空洞４５ａ内に延在する第１のリード端子１１の長さと、金型４５の空洞４５ａ内に延在する第２のリード端子１２の長さとが減少する。一般に、その一端が固定端である板部材に荷重が加わる場合、板部材の撓み量は、固定端から延在する板部材の長さの３乗に比例し、板部材の厚さの３乗に反比例する。金型４５の空洞４５ａ内に延在する第１のリード端子１１の長さが減少するため、第１のリード端子１１の撓み量が減少する。金型４５の空洞４５ａ内に延在する第２のリード端子１２の長さが減少するため、第２のリード端子１２の撓み量が減少する。第１のリード端子１１と第２のリード端子１２との間の高さの差が低減する。第１の導電性接着部３７に部分的な剥離及びクラックが導入されることが抑制されて、第１の導電性接着部３７の電気的接続の信頼性が向上され得る。 Therefore, the process of sealing the electronic components (power semiconductor chip 20, control semiconductor chip 23, first chip capacitor 27, first electronic element 25) with the sealing member 40 (FIGS. 11, 16, and 17). In the reference), the length of the first lead terminal 11 extending into the cavity 45a of the mold 45 and the length of the second lead terminal 12 extending into the cavity 45a of the mold 45 are reduced. In general, when a load is applied to a plate member whose one end is a fixed end, the amount of bending of the plate member is proportional to the cube of the length of the plate member extending from the fixed end, and is the cube of the thickness of the plate member. Inversely proportional to Since the length of the first lead terminal 11 extending into the cavity 45a of the mold 45 is reduced, the amount of bending of the first lead terminal 11 is reduced. Since the length of the second lead terminal 12 extending into the cavity 45a of the mold 45 is reduced, the amount of bending of the second lead terminal 12 is reduced. The difference in height between the first lead terminal 11 and the second lead terminal 12 is reduced. The introduction of partial peeling and cracks to the first conductive adhesive portion 37 is suppressed, and the reliability of electrical connection of the first conductive adhesive portion 37 can be improved.
　第１のリード端子１１の第１の貫通孔１６ａと第２のリード端子１２の第２の貫通孔１６ｂとは、封止部材４０によって充填されている。そのため、封止部材４０の熱膨張係数と第１のリード端子１１及び第２のリード端子１２の熱膨張係数との間の差に起因して、第１のリード端子１１及び第２のリード端子１２が変形しても、第１のリード端子１１及び第２のリード端子１２は、第１の貫通孔１６ａ及び第２の貫通孔１６ｂを起点にして実質的に同じ形状に変形する。そのため、第１の導電性接着部３７に部分的な剥離及びクラックが導入されることが抑制されて、第１の導電性接着部３７の電気的接続の信頼性が向上され得る。 The first through hole 16 a of the first lead terminal 11 and the second through hole 16 b of the second lead terminal 12 are filled with a sealing member 40. Therefore, due to the difference between the thermal expansion coefficient of the sealing member 40 and the thermal expansion coefficients of the first lead terminal 11 and the second lead terminal 12, the first lead terminal 11 and the second lead terminal. Even if 12 is deformed, the first lead terminal 11 and the second lead terminal 12 are deformed into substantially the same shape starting from the first through hole 16a and the second through hole 16b. Therefore, partial peeling and cracks are prevented from being introduced into the first conductive adhesive portion 37, and the reliability of electrical connection of the first conductive adhesive portion 37 can be improved.
　第１の貫通孔１６ａ及び第２の貫通孔１６ｂに充填された封止部材４０を通じて、第１のリード端子１１及び第２のリード端子１２の上側にある封止部材４０と、第１のリード端子１１及び第２のリード端子１２の下側にある封止部材４０とが一体化されている。第１のリード端子１１及び第２のリード端子１２を封止部材４０から引き抜く力に対して、第１の貫通孔１６ａ及び第２の貫通孔１６ｂに充填された封止部材４０はアンカーとして機能する。そのため、第１のリード端子１１及び第２のリード端子１２が封止部材４０から引き抜かれることが阻止されるとともに、第１の導電性接着部３７にせん断応力が加わることが抑制される。第１の導電性接着部３７に部分的な剥離及びクラックが導入されることが抑制されて、第１の導電性接着部３７の電気的接続の信頼性が向上され得る。なお、上述した効果は第１の貫通孔１６ａおよび第２の貫通孔１６ｂが第１のチップコンデンサ２７より内周側に形成されている場合にも得ることができる。 The sealing member 40 on the upper side of the first lead terminal 11 and the second lead terminal 12 and the first lead through the sealing member 40 filled in the first through hole 16a and the second through hole 16b. The terminal 11 and the sealing member 40 below the second lead terminal 12 are integrated. The sealing member 40 filled in the first through-hole 16a and the second through-hole 16b functions as an anchor against the force of pulling out the first lead terminal 11 and the second lead terminal 12 from the sealing member 40. To do. Therefore, the first lead terminal 11 and the second lead terminal 12 are prevented from being pulled out from the sealing member 40, and the shearing stress is suppressed from being applied to the first conductive adhesive portion 37. The introduction of partial peeling and cracks to the first conductive adhesive portion 37 is suppressed, and the reliability of electrical connection of the first conductive adhesive portion 37 can be improved. The effects described above can also be obtained when the first through hole 16 a and the second through hole 16 b are formed on the inner peripheral side of the first chip capacitor 27.
　＜半導体装置の構成＞
　図７は、実施の形態１に係る半導体装置の概略断面図である。図７を参照して、本実施の形態の半導体装置２を説明する。半導体装置２は、パワー半導体モジュール１と、複数の配線（例えば、配線５４，５５）と複数の貫通孔（例えば、貫通孔５２，５３）とを含む配線基板５１とを備える。配線基板５１は、第１の主面５１ａと、第１の主面５１ａとは反対側の第２の主面５１ｂとを有する。第１の主面５１ａは、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１のチップコンデンサ２７、第１の電子素子２５）に面している。複数の貫通孔は、第１の主面５１ａから第２の主面５１ｂまで延在している。複数の配線は、第２の主面５１ｂ上に形成されている。 <Configuration of semiconductor device>
FIG. 7 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. With reference to FIG. 7, the semiconductor device 2 of the present embodiment will be described. The semiconductor device 2 includes the power semiconductor module 1 and a wiring substrate 51 including a plurality of wirings (for example, wirings 54 and 55) and a plurality of through holes (for example, through holes 52 and 53). The wiring board 51 has a first main surface 51a and a second main surface 51b opposite to the first main surface 51a. The first main surface 51a faces the electronic components (power semiconductor chip 20, control semiconductor chip 23, first chip capacitor 27, first electronic element 25). The plurality of through holes extend from the first main surface 51a to the second main surface 51b. The plurality of wirings are formed on the second main surface 51b.
　複数のリード端子は、配線基板５１の複数の貫通孔に挿入されている。複数のリード端子の突出部分は、はんだ接合部（例えば、はんだ接合部５７，５８）で複数の配線に接合されている。具体的には、第１のリード端子１１の第２突出部分１１ｅ（図１を参照）は、配線基板５１の貫通孔（図示せず）に挿入されている。第１のリード端子１１の第２突出部分１１ｅは、はんだ接合部（図示せず）で配線（図示せず）に接合されている。第２のリード端子１２の第４突出部分１２ｅは、貫通孔５２に挿入されている。第２のリード端子１２の第４突出部分１２ｅは、はんだ接合部５７で配線５４に接合されている。第９のリード端子１５の第１０突出部分１５ｅは、貫通孔５３に挿入されている。第９のリード端子１５の第１０突出部分１５ｅは、はんだ接合部５８で配線５５に接合されている。 The plurality of lead terminals are inserted into the plurality of through holes of the wiring board 51. The protruding portions of the plurality of lead terminals are joined to the plurality of wirings by solder joints (for example, solder joints 57 and 58). Specifically, the second protruding portion 11e (see FIG. 1) of the first lead terminal 11 is inserted into a through hole (not shown) of the wiring board 51. The second protruding portion 11e of the first lead terminal 11 is joined to a wiring (not shown) by a solder joint (not shown). The fourth protruding portion 12 e of the second lead terminal 12 is inserted into the through hole 52. The fourth projecting portion 12 e of the second lead terminal 12 is joined to the wiring 54 by a solder joint portion 57. The tenth protruding portion 15 e of the ninth lead terminal 15 is inserted into the through hole 53. The tenth protruding portion 15 e of the ninth lead terminal 15 is joined to the wiring 55 by a solder joint 58.
　＜パワー半導体モジュールおよび半導体装置の変形例の構成＞
　図８から図１０は、実施の形態１に係るパワー半導体モジュールの変形例を説明するための部分拡大平面図である。図８から図１０は図２に対応する。なお、図８から図１０では図１の領域ＩＩに相当する部分のみを示しているが、第３から第６のリード端子１１１，１１２，２１１，２１２、第２および第３のチップコンデンサ１２７，２２７、第２および第３の電子素子１２５，２２５についても図８から図１０に示した構成と同様の構成となっている。 <Configuration of Modified Examples of Power Semiconductor Module and Semiconductor Device>
8 to 10 are partially enlarged plan views for explaining modifications of the power semiconductor module according to the first embodiment. 8 to 10 correspond to FIG. 8 to 10, only the portion corresponding to the region II in FIG. 1 is shown, but the third to sixth lead terminals 111, 112, 211, 212, the second and third chip capacitors 127, 227 and the second and third electronic elements 125 and 225 have the same configuration as that shown in FIGS.
　図８に示した構造を有するパワー半導体モジュールは、基本的には図１から図６に示したパワー半導体モジュール１と同様の構成を備え、同様の効果を得ることができるが、第１および第２のリード端子１１、１２の形状および第１のチップコンデンサ２７と第１の電子素子２５との配置が図１から図６に示したパワー半導体モジュール１と異なっている。図８に示したパワー半導体モジュールでは、第２のリード端子１２の一部が第１のリード端子１１より内側に延在する延在部分を有する。第１のチップコンデンサ２７は、第１の電極２８ａから第２の電極２８ｂに向かう方向である延在方向がパワー半導体モジュール１の封止部材４０の表面から内側に向かう方向（図８の左右方向）に沿うように配置されている。また、第１の電子素子２５は第１のチップコンデンサ２７より外側に配置されている。第１の電子素子２５は、第１のチップコンデンサ２７の上記延在方向に沿って第１のチップコンデンサ２７と整列するように配置されている。第１の電子素子２５は第１のチップコンデンサ２７と距離Ｌ２を隔てて配置されている。 The power semiconductor module having the structure shown in FIG. 8 basically has the same configuration as the power semiconductor module 1 shown in FIGS. 1 to 6 and can obtain the same effect. The shape of the two lead terminals 11 and 12 and the arrangement of the first chip capacitor 27 and the first electronic element 25 are different from those of the power semiconductor module 1 shown in FIGS. In the power semiconductor module shown in FIG. 8, a part of the second lead terminal 12 has an extending portion that extends inward from the first lead terminal 11. In the first chip capacitor 27, the extending direction, which is a direction from the first electrode 28a to the second electrode 28b, is directed inward from the surface of the sealing member 40 of the power semiconductor module 1 (the horizontal direction in FIG. 8). ). Further, the first electronic element 25 is disposed outside the first chip capacitor 27. The first electronic element 25 is arranged so as to align with the first chip capacitor 27 along the extending direction of the first chip capacitor 27. The first electronic element 25 is disposed at a distance L2 from the first chip capacitor 27.
　図９に示した構造を有するパワー半導体モジュールは、基本的には図１から図６に示したパワー半導体モジュール１と同様の構成を備え、同様の効果を得ることができるが、第１および第２のリード端子１１、１２の形状および第１のチップコンデンサ２７と第１の電子素子２５との配置が図１から図６に示したパワー半導体モジュール１と異なっている。図９に示したパワー半導体モジュールでは、第１のリード端子１１の幅（図１において封止部材４０の表面から内側に向かう方向である図９の左右方向での幅）が図２に示した第１のリード端子１１より広くなっている。また、第１のチップコンデンサ２７が第１の電子素子２５より内側にずれて配置されている。第１の電子素子２５は第１のチップコンデンサ２７と距離Ｌ２を隔てて配置されている。 The power semiconductor module having the structure shown in FIG. 9 has basically the same configuration as the power semiconductor module 1 shown in FIGS. 1 to 6 and can obtain the same effects. The shape of the two lead terminals 11 and 12 and the arrangement of the first chip capacitor 27 and the first electronic element 25 are different from those of the power semiconductor module 1 shown in FIGS. In the power semiconductor module shown in FIG. 9, the width of the first lead terminal 11 (the width in the left-right direction in FIG. 9, which is the direction inward from the surface of the sealing member 40 in FIG. 1) is shown in FIG. It is wider than the first lead terminal 11. In addition, the first chip capacitor 27 is disposed so as to be shifted inward from the first electronic element 25. The first electronic element 25 is disposed at a distance L2 from the first chip capacitor 27.
　図１０に示した構造を有するパワー半導体モジュールは、基本的には図１から図６に示したパワー半導体モジュール１と同様の構成を備え、同様の効果を得ることができるが、第１および第２のリード端子１１、１２の形状が図１から図６に示したパワー半導体モジュール１と異なっている。図１０に示したパワー半導体モジュールでは、第１のリード端子１１に複数の第１の貫通孔１６ａが形成されている。具体的には、第１のリード端子１１において、２つの第１の貫通孔１６ａが第１のチップコンデンサ２７を挟むように配置されている。２つの第１の貫通孔１６ａは、図１において封止部材４０の表面から内側に向かう方向である図１０の左右方向に沿って整列するように配置されている。また、第２のリード端子１２に複数の第２の貫通孔１６ｂが形成されている。具体的には、第２のリード端子１２において、２つの第２の貫通孔１６ｂが第１のチップコンデンサ２７を挟むように配置されている。２つの第２の貫通孔１６ｂは、図１において封止部材４０の表面から内側に向かう方向である図１０の左右方向に沿って整列するように配置されている。この場合、第１の貫通孔１６ａおよび第２の貫通孔１６ｂに充填された封止部材４０のアンカー効果をより高めることができるので、第１のチップコンデンサ２７の剥離抑制の効果を向上させることができる。 The power semiconductor module having the structure shown in FIG. 10 basically has the same configuration as the power semiconductor module 1 shown in FIGS. 1 to 6 and can obtain the same effects. The shape of the two lead terminals 11 and 12 is different from that of the power semiconductor module 1 shown in FIGS. In the power semiconductor module shown in FIG. 10, a plurality of first through holes 16 a are formed in the first lead terminal 11. Specifically, in the first lead terminal 11, two first through holes 16 a are arranged so as to sandwich the first chip capacitor 27. The two first through holes 16a are arranged so as to be aligned along the left-right direction in FIG. 10, which is a direction inward from the surface of the sealing member 40 in FIG. A plurality of second through holes 16 b are formed in the second lead terminal 12. Specifically, in the second lead terminal 12, two second through holes 16 b are arranged so as to sandwich the first chip capacitor 27. The two second through-holes 16b are arranged so as to be aligned along the left-right direction in FIG. 10, which is a direction inward from the surface of the sealing member 40 in FIG. In this case, since the anchor effect of the sealing member 40 filled in the first through hole 16a and the second through hole 16b can be further enhanced, the effect of suppressing the peeling of the first chip capacitor 27 is improved. Can do.
　図８から図１０に示したパワー半導体モジュールにおいて、第１の電子素子２５と第１のチップコンデンサ２７との相対的な配置および距離Ｌ２と、第２の電子素子１２５と第２のチップコンデンサ１２７との相対的な配置および距離と、第３の電子素子２２５と第３のチップコンデンサ２２７との相対的な配置および距離とは、同じになっていることが好ましい。 In the power semiconductor module shown in FIGS. 8 to 10, the relative arrangement and distance L2 between the first electronic element 25 and the first chip capacitor 27, the second electronic element 125, and the second chip capacitor 127. And the relative arrangement and distance between the third electronic element 225 and the third chip capacitor 227 are preferably the same.
　＜パワー半導体モジュールの製造方法＞
　図１１は、実施の形態１に係るパワー半導体モジュールの製造方法のフローチャートを示す図である。図１２は、実施の形態１に係るパワー半導体モジュールの製造方法の一工程を示す概略平面図である。図１３は、実施の形態１のパワー半導体モジュールの製造方法における図１２に示される工程の、図１２に示す断面線ＸＩＩＩ－ＸＩＩＩにおける概略部分拡大断面図である。図１４は、実施の形態１のパワー半導体モジュールの製造方法における、リードフレームにおけるチップコンデンサの配置の一例を説明するための模式図である。図１５は、実施の形態１のパワー半導体モジュールの製造方法における、リードフレームにおけるチップコンデンサの配置の一例を説明するための模式図である。図１６は、実施の形態１に係るパワー半導体モジュールの製造方法における、図１２に示される工程の次工程を示す概略平面図である。図１７は、実施の形態１に係るパワー半導体モジュールの製造方法における、図１６に示す断面線ＸＶＩＩ－ＸＶＩＩにおける概略部分拡大断面図である。図１１から図１７を参照して、実施の形態１のパワー半導体モジュール１の製造方法を説明する。 <Power semiconductor module manufacturing method>
FIG. 11 is a flowchart of the method for manufacturing the power semiconductor module according to the first embodiment. FIG. 12 is a schematic plan view showing one step of the method for manufacturing the power semiconductor module according to the first embodiment. 13 is a schematic partially enlarged cross-sectional view taken along a cross-sectional line XIII-XIII shown in FIG. 12 in the process shown in FIG. 12 in the method for manufacturing the power semiconductor module of the first embodiment. FIG. 14 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment. FIG. 15 is a schematic diagram for explaining an example of the arrangement of chip capacitors in the lead frame in the method for manufacturing the power semiconductor module of the first embodiment. FIG. 16 is a schematic plan view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the power semiconductor module according to the first embodiment. 17 is a schematic partially enlarged cross-sectional view taken along a cross-sectional line XVII-XVII shown in FIG. 16 in the method for manufacturing the power semiconductor module according to the first embodiment. With reference to FIGS. 11 to 17, a method for manufacturing the power semiconductor module 1 of the first embodiment will be described.
　図１１から図１３を参照して、パワー半導体モジュール１の製造方法は、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）をリードフレーム１０に接合すること（Ｓ１）を備える。具体的には、リードフレーム１０が準備される。リードフレーム１０は、たとえば打ち抜きプレス加工、またはエッチング加工により成形され得る。リードフレーム１０は、フレーム部１０ａと、複数のリード端子とを含む。複数のリード端子は、第１から第９のリード端子１１，１２，１１１，１１２，２１１，２１２，１３，１４，１５を含む。複数のリード端子は、フレーム部１０ａから、フレーム部１０ａの開口１０ｂの内側に向けて延在している。リードフレーム１０は、さらに端子接続部１８を含んでもよい。端子接続部１８は、フレームの開口１０ｂ内において、複数のリード端子同士と接続するとともに、複数のリード端子とフレーム部１０ａとを接続している。端子接続部１８は、フレーム部１０ａの開口１０ｂ内において、複数のリード端子が撓むことを抑制する。 Referring to FIGS. 11 to 13, the method of manufacturing the power semiconductor module 1 includes electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third. The third electronic elements 25, 125, 225) are joined to the lead frame 10 (S1). Specifically, the lead frame 10 is prepared. The lead frame 10 can be formed by, for example, punching press processing or etching processing. The lead frame 10 includes a frame portion 10a and a plurality of lead terminals. The plurality of lead terminals include first to ninth lead terminals 11, 12, 111, 112, 211, 212, 13, 14, 15. The plurality of lead terminals extend from the frame portion 10a toward the inside of the opening 10b of the frame portion 10a. The lead frame 10 may further include a terminal connection portion 18. The terminal connecting portion 18 is connected to the plurality of lead terminals in the opening 10b of the frame and connects the plurality of lead terminals to the frame portion 10a. The terminal connecting portion 18 suppresses bending of the plurality of lead terminals in the opening 10b of the frame portion 10a.
　それから、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）をリードフレーム１０に接合する。具体的には、パワー半導体チップ２０を、はんだ接合部３０で第９のリード端子１５に接合する。制御用半導体チップ２３を、導電接合部３３で第８のリード端子１４に接合する。導電接合部３３は、はんだ接合部であってもよいし、導電性接着部３５であってもよい。また、整流用半導体チップのような第１の電子素子２５を、導電性接着部３５で、第１のリード端子１１に接合する。導電性接着部３５としては、エポキシ樹脂中に銀（Ａｇ）フィラーを分散させたＡｇペーストが主に用いられるが、銀に限らずニッケル（Ｎｉ）や銅（Ｃｕ）などを含む他の金属フィラーを用いた金属ペーストでもよい。また、実装には導電性接着部３５だけでなく、錫（Ｓｎ）や鉛（Ｐｂ）を主成分とするはんだ等を使用してもかまわない。導電性接着部３５にすると、他の半導体チップおよび電子素子を実装するときに同時に実装した後に、一括でキュアできる。この結果、パワー半導体モジュールの製造タクトタイムを短縮できる。また、錫を主成分とするはんだよりも導電性接着部３５の融点が高いため、リフロー実装時に当該導電性接着部３５が融解することがない。 Then, electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, and first to third electronic elements 25, 125, 225) are joined to the lead frame 10. To do. Specifically, the power semiconductor chip 20 is joined to the ninth lead terminal 15 by the solder joint portion 30. The control semiconductor chip 23 is bonded to the eighth lead terminal 14 by the conductive bonding portion 33. The conductive joint portion 33 may be a solder joint portion or a conductive adhesive portion 35. Further, the first electronic element 25 such as a rectifying semiconductor chip is joined to the first lead terminal 11 by the conductive adhesive portion 35. As the conductive adhesive portion 35, an Ag paste in which a silver (Ag) filler is dispersed in an epoxy resin is mainly used, but not only silver but other metal fillers including nickel (Ni), copper (Cu), and the like. A metal paste using may be used. For mounting, not only the conductive adhesive portion 35 but also solder or the like mainly containing tin (Sn) or lead (Pb) may be used. When the conductive adhesive portion 35 is used, it can be cured in a lump after mounting other semiconductor chips and electronic elements at the same time. As a result, the manufacturing tact time of the power semiconductor module can be shortened. In addition, since the melting point of the conductive adhesive portion 35 is higher than that of solder containing tin as a main component, the conductive adhesive portion 35 is not melted during reflow mounting.
　第２および第３の電子素子１２５，２２５も、第１の電子素子２５と同様に第３のリード端子１１１（図４参照）および第５のリード端子２１１（図４参照）とそれぞれ接合する。第１のチップコンデンサ２７の第１の電極２８ａと第２の電極２８ｂとを、第１の導電性接着部３７で、第１のリード端子１１と第２のリード端子１２とにそれぞれ接合する。第２および第３のチップコンデンサ１２７，２２７についても、第１のチップコンデンサ２７と同様に、それぞれの第３から第６の電極１２８ａ、１２８ｂ，２２８ａ，２２８ｂ（図４参照）を第３から第６のリード端子１１１，１１２，２１１，２１２（図４参照）に接合する。なお、上述した第１の導電性接着部３７として、導電性接着剤を用いてもよいし、錫（Ｓｎ）や鉛（Ｐｂ）を主成分とするはんだを用いてもよい。各要素を実装する順番については、たとえば、パワー半導体チップ２０、制御用半導体チップ２３、整流用半導体チップである第１から第３の電子素子２５，１２５，２２５、第１から第３のチップコンデンサ２７，１２７，２２７の順に実装してもよいが、任意に実装順序を変えることが可能である。 Similarly to the first electronic element 25, the second and third electronic elements 125 and 225 are also joined to the third lead terminal 111 (see FIG. 4) and the fifth lead terminal 211 (see FIG. 4), respectively. The first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the first conductive adhesive portion 37, respectively. Similarly to the first chip capacitor 27, the second and third chip capacitors 127 and 227 are respectively connected to the third to sixth electrodes 128a, 128b, 228a, and 228b (see FIG. 4) from the third to the third. 6 lead terminals 111, 112, 211, 212 (see FIG. 4). As the first conductive adhesive portion 37 described above, a conductive adhesive may be used, or a solder mainly composed of tin (Sn) or lead (Pb) may be used. Regarding the order of mounting each element, for example, the power semiconductor chip 20, the control semiconductor chip 23, the first to third electronic elements 25, 125, and 225 which are rectifying semiconductor chips, and the first to third chip capacitors. 27, 127, and 227 may be mounted in this order, but the mounting order can be arbitrarily changed.
　次に、導電ワイヤ２９にて制御用半導体チップ２３およびパワー半導体チップ２０、整流用半導体チップである第１から第３の電子素子２５，１２５，２２５、と各リード端子とを接続する。導電ワイヤ２９は、アルミニウム（Ａｌ）、銅（Ｃｕ）、金（Ａｕ），銀（Ａｇ）、およびその合金などの材料からなる。導電ワイヤ２９は断面形状が円形状の線材であってもよい。導電ワイヤ２９の直径φは１０μｍ程度から５００μｍ程度であってもよい。導電ワイヤ２９の接合方法としては、ボールボンドやウェッジボンドなどの既存の接合方法が用いられる。このとき、制御用半導体チップ２３と第１のリード端子１１間、制御用半導体チップ２３とパワー半導体チップ２０間、パワー半導体チップ２０とリード端子間、第１から第３の電子素子２５、１２５、２２５とリード端子間の導電ワイヤ２９が同一の種類のものであれば、同時に接合することが可能となる。一方、制御用半導体チップ２３および第１から第３の電子素子２５，１２５，２２５の接合部の電極サイズや、パワー半導体チップ２０に流す電流容量により、各箇所において最適な導電ワイヤ２９を選択することが望ましい。また、これらの導電ワイヤ２９を接合する順番も任意に選択することができる。 Next, the control semiconductor chip 23 and the power semiconductor chip 20, the first to third electronic elements 25, 125, 225 which are rectifying semiconductor chips, and the lead terminals are connected by the conductive wires 29. The conductive wire 29 is made of a material such as aluminum (Al), copper (Cu), gold (Au), silver (Ag), or an alloy thereof. The conductive wire 29 may be a wire having a circular cross section. The diameter φ of the conductive wire 29 may be about 10 μm to about 500 μm. As a bonding method of the conductive wire 29, an existing bonding method such as ball bonding or wedge bonding is used. At this time, between the control semiconductor chip 23 and the first lead terminal 11, between the control semiconductor chip 23 and the power semiconductor chip 20, between the power semiconductor chip 20 and the lead terminal, the first to third electronic elements 25, 125, If the conductive wires 29 between 225 and the lead terminals are of the same type, they can be joined simultaneously. On the other hand, an optimal conductive wire 29 is selected at each location according to the electrode size of the junction between the control semiconductor chip 23 and the first to third electronic elements 25, 125, 225 and the current capacity flowing through the power semiconductor chip 20. It is desirable. Further, the order of joining these conductive wires 29 can be arbitrarily selected.
　このとき、図４に示すように第１から第３の電子素子２５，１２５，２２５および第１から第３のチップコンデンサ２７，１２７，２２７は各相間で等間隔に、つまり同じピッチＰ１で配置する。このようにすることで、実装プロセスの効率を向上させることができる。例えば、図１４のようにリードフレーム１０の長辺方向（図１４の矢印７０で示す方向）に第１から第３のチップコンデンサ２７、１２７、２２７を並べて実装する場合を考える。この場合、リードフレーム１０（図１２参照）を図１４の矢印７０で示す長辺方向に同じピッチで搬送させる。この状態で、第１から第３のチップコンデンサ２７，１２７，２２７をリードフレーム１０に実装する。この時、当該第１から第３のチップコンデンサ２７，１２７，２２７を吸着して搬送する吸着用ノズルは、リードフレーム１０の図１４の矢印７１で示される短辺方向に１軸移動するだけで実装作業を実施できる。 At this time, as shown in FIG. 4, the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227 are arranged at equal intervals between the phases, that is, at the same pitch P1. To do. By doing so, the efficiency of the mounting process can be improved. For example, consider a case where the first to third chip capacitors 27, 127, and 227 are mounted side by side in the long side direction of the lead frame 10 (the direction indicated by the arrow 70 in FIG. 14) as shown in FIG. In this case, the lead frame 10 (see FIG. 12) is transported at the same pitch in the long side direction indicated by the arrow 70 in FIG. In this state, the first to third chip capacitors 27, 127 and 227 are mounted on the lead frame 10. At this time, the suction nozzle that sucks and conveys the first to third chip capacitors 27, 127, and 227 only moves one axis in the short side direction indicated by the arrow 71 in FIG. 14 of the lead frame 10. Implementation work can be performed.
　また、例えば図１５のようにリードフレーム１０（図１２参照）の矢印７１で示す短辺方向に第１から第３のチップコンデンサ２７，１２７，２２７を並べて実装する場合を考える。リードフレーム１０の搬送方向は矢印７０で示す長辺方向である。この場合、第１から第３のチップコンデンサ２７，１２７，２２７を吸着して搬送する吸着用ノズルは、矢印７１で示すリードフレーム１０の短辺方向に１軸移動するだけで実装作業を実施できる。 Also, consider a case where the first to third chip capacitors 27, 127, 227 are mounted side by side in the short side direction indicated by the arrow 71 of the lead frame 10 (see FIG. 12) as shown in FIG. The conveyance direction of the lead frame 10 is the long side direction indicated by the arrow 70. In this case, the suction nozzle that sucks and conveys the first to third chip capacitors 27, 127, and 227 can be mounted only by moving one axis in the short side direction of the lead frame 10 indicated by the arrow 71. .
　図１１、図１６及び図１７を参照して、パワー半導体モジュール１の製造方法は、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）を封止部材４０で封止すること（Ｓ２）を備える。具体的には、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）が接合されたリードフレーム１０を金型４５にセットする。トランスファーモールド法またはコンプレッションモールド法を用いて、金型４５の空洞４５ａ内に封止樹脂を注入する。電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）が封止部材４０で封止される。フレーム部１０ａ、端子接続部１８、複数のリード端子の突出部（例えば、第１の突出部１１ｃ、第２の突出部１２ｃ及び第５の突出部１５ｃ）は、封止部材４０から露出している。 Referring to FIGS. 11, 16, and 17, the method for manufacturing power semiconductor module 1 includes electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, The first to third electronic elements 25, 125, 225) are sealed with the sealing member 40 (S2). Specifically, electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225) are joined. The lead frame 10 is set in the mold 45. Sealing resin is injected into the cavity 45a of the mold 45 by using a transfer molding method or a compression molding method. Electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225) are sealed with a sealing member 40. Is done. The frame portion 10a, the terminal connection portion 18, and the protruding portions of the plurality of lead terminals (for example, the first protruding portion 11c, the second protruding portion 12c, and the fifth protruding portion 15c) are exposed from the sealing member 40. Yes.
　第１のリード端子１１が突出する金型４５の部分４６ａと第１のチップコンデンサ２７との間の最短距離は、第１のリード端子１１の厚さの５倍以下であってもよい。第２のリード端子１２が突出する金型４５の部分４６ｂと第１のチップコンデンサ２７との間の最短距離ｄは、第２のリード端子１２の厚さｔの５倍以下であってもよい。一般に、その一端が固定端である板部材に荷重が加わる場合、板部材の撓み量は、固定端から延在する板部材の長さの３乗に比例し、板部材の厚さの３乗に反比例する。金型４５の空洞４５ａ内に延在する第１のリード端子１１の長さが減少するため、第１のリード端子１１の撓み量が減少する。金型４５の空洞４５ａ内に延在する第２のリード端子１２の長さが減少するため、第２のリード端子１２の撓み量が減少する。第１の導電性接着部３７に部分的な剥離及びクラックが導入されることが抑制されて、第１の導電性接着部３７の電気的接続の信頼性が向上され得る。 The shortest distance between the portion 46a of the mold 45 from which the first lead terminal 11 protrudes and the first chip capacitor 27 may be 5 times or less the thickness of the first lead terminal 11. The shortest distance d between the portion 46b of the mold 45 from which the second lead terminal 12 protrudes and the first chip capacitor 27 may be 5 times or less the thickness t of the second lead terminal 12. . In general, when a load is applied to a plate member whose one end is a fixed end, the amount of bending of the plate member is proportional to the cube of the length of the plate member extending from the fixed end, and is the cube of the thickness of the plate member. Inversely proportional to Since the length of the first lead terminal 11 extending into the cavity 45a of the mold 45 is reduced, the amount of bending of the first lead terminal 11 is reduced. Since the length of the second lead terminal 12 extending into the cavity 45a of the mold 45 is reduced, the amount of bending of the second lead terminal 12 is reduced. The introduction of partial peeling and cracks to the first conductive adhesive portion 37 is suppressed, and the reliability of electrical connection of the first conductive adhesive portion 37 can be improved.
　図１１を参照して、パワー半導体モジュール１の製造方法は、リードフレーム１０を加工すること（Ｓ３）を備える。具体的には、封止部材４０に覆われていないリード端子の突出部をめっき処理する。めっきとして、基板実装時のはんだ付けに対応するために錫（Ｓｎ）めっきや錫（Ｓｎ）－銅（Ｃｕ）めっきなどが選ばれる。なお、予め複数のリード端子の全面にめっき処理を施している場合や基板実装時のはんだ付けに表面処理が不要と判断した場合、このめっき処理を省略してもよい。その後、金型プレスなどによりフレーム部１０ａ及び端子接続部１８が除去され、パワー半導体モジュール１が個片化される。次に、複数のリード端子の突出部（例えば、第１の突出部１１ｃ、第２の突出部１２ｃ及び第５の突出部１５ｃ）を折り曲げる。こうして、図１から図６に示されるパワー半導体モジュール１が得られる。なお、パワー半導体モジュール１のパッケージ形状として、ＤＩＰ型、ＳＯＰ型、ＱＦＮ（Ｑｕａｄ　Ｆｏｒ　Ｎｏｎ－Ｌｅａｄ　Ｐａｃｋａｇｅ）型など任意の形状を選択できる。 Referring to FIG. 11, the method for manufacturing power semiconductor module 1 includes processing lead frame 10 (S3). Specifically, the protruding portion of the lead terminal not covered with the sealing member 40 is plated. As the plating, tin (Sn) plating, tin (Sn) -copper (Cu) plating, or the like is selected in order to cope with soldering at the time of board mounting. Note that this plating process may be omitted when the plating process is applied to the entire surface of the plurality of lead terminals in advance, or when it is determined that the surface process is not required for soldering when mounting the board. Thereafter, the frame portion 10a and the terminal connection portion 18 are removed by a mold press or the like, and the power semiconductor module 1 is separated into pieces. Next, the protruding portions (for example, the first protruding portion 11c, the second protruding portion 12c, and the fifth protruding portion 15c) of the plurality of lead terminals are bent. Thus, the power semiconductor module 1 shown in FIGS. 1 to 6 is obtained. As the package shape of the power semiconductor module 1, an arbitrary shape such as a DIP type, an SOP type, or a QFN (Quad For Non-Lead Package) type can be selected.
　＜半導体装置の製造方法＞
　図１８は、実施の形態１に係る半導体装置の製造方法のフローチャートを示す図である。図１８を参照して、本実施の形態の半導体装置２の製造方法を説明する。半導体装置２の製造方法は、パワー半導体モジュール１を準備すること（Ｓ１１）を備える。本実施の形態のパワー半導体モジュール１の製造方法によって、パワー半導体モジュール１は準備される。 <Method for Manufacturing Semiconductor Device>
FIG. 18 is a flowchart of the semiconductor device manufacturing method according to the first embodiment. With reference to FIG. 18, the manufacturing method of the semiconductor device 2 of the present embodiment will be described. The manufacturing method of the semiconductor device 2 includes preparing the power semiconductor module 1 (S11). The power semiconductor module 1 is prepared by the method for manufacturing the power semiconductor module 1 of the present embodiment.
　半導体装置２の製造方法は、パワー半導体モジュール１を配線基板５１に実装すること（Ｓ１２）をさらに備える。具体的には、複数のリード端子の突出部分（例えば、第２のリード端子１２の第４突出部分１２ｅ、第９のリード端子１５の第１０突出部分１５ｅ）を、配線基板５１の複数の貫通孔（例えば、貫通孔５２，５３）に挿入する。パワー半導体モジュール１では、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）はデュアルインラインパッケージ（ＤＩＰ）方式でパッケージされている。そのため、フロー式はんだ付けによって、複数のリード端子の突出部分（例えば、第２のリード端子１２の第４突出部分１２ｅ、第９のリード端子１５の第１０突出部分１５ｅ）を、配線基板５１の複数の配線（例えば、配線５４，５５）にはんだ接合する。こうして、図７に示される本実施の形態の半導体装置２が得られる。 The method for manufacturing the semiconductor device 2 further includes mounting the power semiconductor module 1 on the wiring board 51 (S12). Specifically, the protruding portions of the plurality of lead terminals (for example, the fourth protruding portion 12e of the second lead terminal 12 and the tenth protruding portion 15e of the ninth lead terminal 15) are passed through the plurality of penetrations of the wiring substrate 51. It inserts in a hole (for example, through-holes 52 and 53). In the power semiconductor module 1, the electronic components (power semiconductor chip 20, control semiconductor chip 23, first to third chip capacitors 27, 127, 227, first to third electronic elements 25, 125, 225) are dual. Packaged in an in-line package (DIP) system. Therefore, a plurality of lead terminal protruding portions (for example, the fourth protruding portion 12e of the second lead terminal 12 and the tenth protruding portion 15e of the ninth lead terminal 15) of the plurality of lead terminals are connected to the wiring substrate 51 by flow soldering. Solder-join to a plurality of wires (for example, wires 54 and 55). Thus, the semiconductor device 2 of the present embodiment shown in FIG. 7 is obtained.
　＜作用効果＞
　本発明に従ったパワー半導体モジュール１は、複数のリード端子と、パワー半導体チップ２０と、第１のチップコンデンサ２７と、第１の電子素子２５と、封止部材４０と、を備える。複数のリード端子は、第１のリード端子１１と、当該第１のリード端子１１から離間されている第２のリード端子１２とを含む。第１のチップコンデンサ２７は、第１の電極２８ａと第２の電極２８ｂとを含む。第１の電子素子２５は、パワー半導体チップ２０及び第１のチップコンデンサ２７とは異なる素子である。封止部材４０は、パワー半導体チップ２０と第１のチップコンデンサ２７と第１の電子素子２５とを封止する。パワー半導体チップ２０は複数のリード端子の少なくとも１つである第９のリード端子１５に接合されている。第１のチップコンデンサ２７の第１の電極２８ａと第２の電極２８ｂとは、第１の導電性接着部３７で、第１のリード端子１１と第２のリード端子１２とにそれぞれ接合されている。第１のリード端子１１には第１の電子素子２５が搭載されている。 <Effect>
The power semiconductor module 1 according to the present invention includes a plurality of lead terminals, a power semiconductor chip 20, a first chip capacitor 27, a first electronic element 25, and a sealing member 40. The plurality of lead terminals include a first lead terminal 11 and a second lead terminal 12 spaced from the first lead terminal 11. The first chip capacitor 27 includes a first electrode 28a and a second electrode 28b. The first electronic element 25 is an element different from the power semiconductor chip 20 and the first chip capacitor 27. The sealing member 40 seals the power semiconductor chip 20, the first chip capacitor 27, and the first electronic element 25. The power semiconductor chip 20 is bonded to a ninth lead terminal 15 that is at least one of a plurality of lead terminals. The first electrode 28 a and the second electrode 28 b of the first chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the first conductive adhesive portion 37, respectively. Yes. A first electronic element 25 is mounted on the first lead terminal 11.
　このようにすれば、第１のチップコンデンサ２７の第１および第２の電極２８ａ，２８ｂが、それぞれ第１および第２のリード端子１１，１２に第１の導電性接着部３７により接合されているので、当該第１および第２の電極２８ａ，２８ｂと第１及び第２のリード端子１１，１２との接続にワイヤを用いる場合より封止部材４０の厚さを薄くできる。このため、パワー半導体モジュール１を小型化できる。また、パワー半導体モジュール１の軽量化を図ることができる。さらに従来パワー半導体モジュール１外に取り付けていた第１のチップコンデンサ２７を内蔵することにより、配線基板５１の小型化が可能となるためインバータ装置の小型化も可能となる。以下、図面を参照しながら具体的に説明する。図１９は、比較例のパワー半導体モジュールを示す概略断面図である。 In this way, the first and second electrodes 28a and 28b of the first chip capacitor 27 are joined to the first and second lead terminals 11 and 12 by the first conductive adhesive portion 37, respectively. Therefore, the thickness of the sealing member 40 can be made thinner than when a wire is used for connection between the first and second electrodes 28a, 28b and the first and second lead terminals 11, 12. For this reason, the power semiconductor module 1 can be reduced in size. Further, the power semiconductor module 1 can be reduced in weight. Further, by incorporating the first chip capacitor 27 that is conventionally attached outside the power semiconductor module 1, the wiring board 51 can be miniaturized, so that the inverter device can also be miniaturized. Hereinafter, it demonstrates concretely, referring drawings. FIG. 19 is a schematic cross-sectional view showing a power semiconductor module of a comparative example.
　図１９に示す比較例としてのパワー半導体モジュールは、基本的には図３に示したパワー半導体モジュールと同様の構成を備えるが、第１のチップコンデンサ２７と第１の電子素子２５とが共通のリード端子に搭載されている点、第１のチップコンデンサ２７に対して導電ワイヤ２９が接続されている点が主に異なる。第１のチップコンデンサ２７はリード端子に絶縁性接着剤１２１により接続されている。 The power semiconductor module as a comparative example shown in FIG. 19 basically has the same configuration as that of the power semiconductor module shown in FIG. 3, but the first chip capacitor 27 and the first electronic element 25 are common. The main difference is that the conductive wire 29 is connected to the first chip capacitor 27 in that it is mounted on the lead terminal. The first chip capacitor 27 is connected to the lead terminal by an insulating adhesive 121.
　制御用半導体チップ２３および整流用半導体チップである第１の電子素子２５の厚みは、通常数十μｍから数百μｍ程度である。それに対して、第１のチップコンデンサ２７の厚みは、チップコンデンサのサイズにもよるが１６０８規格（約１．６ｍｍ×０．８ｍｍ)以上のサイズとなれば４００μｍ程度から１ｍｍ程度となる。そのため、第１のチップコンデンサ２７がリードフレーム１０上の一番厚い部品となる。そのため、パワー半導体モジュール１の厚みは第１のチップコンデンサ２７の厚みにより決まる。その上、図１９に示すように第１のチップコンデンサ２７の電極に導電ワイヤ２９を接続すると、図３に示す本実施形態に係るパワー半導体モジュール１の厚みＴ１（図１９参照）と比較して、その分だけさらに比較例としてのパワー半導体モジュールの厚みＴ２は厚くなる。 The thickness of the control semiconductor chip 23 and the first electronic element 25, which is a rectifying semiconductor chip, is usually about several tens of μm to several hundreds of μm. On the other hand, although the thickness of the first chip capacitor 27 depends on the size of the chip capacitor, the thickness is about 400 μm to about 1 mm when the size is 1608 standard (about 1.6 mm × 0.8 mm) or more. Therefore, the first chip capacitor 27 is the thickest part on the lead frame 10. Therefore, the thickness of the power semiconductor module 1 is determined by the thickness of the first chip capacitor 27. In addition, when the conductive wire 29 is connected to the electrode of the first chip capacitor 27 as shown in FIG. 19, it is compared with the thickness T1 (see FIG. 19) of the power semiconductor module 1 according to this embodiment shown in FIG. Thus, the thickness T2 of the power semiconductor module as a comparative example is further increased by that amount.
　この場合、余分に封止部材４０を使用することなり、製造コストの増大を招くだけでなく、パワー半導体モジュール自体も重くなる。パワー半導体モジュールが重くなると、例えば吸着部材を備えた搬送装置によりパワー半導体モジュールを吸着して自動搬送する場合、当該吸着部材の吸着力を向上させることが必要となる。吸着部材が真空吸着装置である場合、より高い真空度が求められる。 In this case, an extra sealing member 40 is used, which not only increases the manufacturing cost but also increases the power semiconductor module itself. When the power semiconductor module becomes heavy, for example, when the power semiconductor module is sucked and automatically transported by a transport device including the suction member, it is necessary to improve the suction force of the suction member. When the suction member is a vacuum suction device, a higher degree of vacuum is required.
　また、パワー半導体モジュールの使用時に、当該パワー半導体モジュールに振動が加わると、リード端子への負荷が高まり製品寿命が縮まる恐れがある。また、導電ワイヤ２９を第１のチップコンデンサ２７に接続する際には、通常超音波接合法を用いる。そのため、導電ワイヤ２９の接合時には、第１のチップコンデンサ２７に圧力や超音波の振動が加わる。そのため、第１のチップコンデンサ２７に導電ワイヤ２９を接続すると、第１のチップコンデンサ２７は通常セラミック製であることから、第１のチップコンデンサ２７においてクラック発生の懸念が高まる。 In addition, if vibration is applied to the power semiconductor module when the power semiconductor module is used, the load on the lead terminals may increase and the product life may be shortened. Further, when connecting the conductive wire 29 to the first chip capacitor 27, an ultrasonic bonding method is usually used. Therefore, pressure or ultrasonic vibration is applied to the first chip capacitor 27 when the conductive wire 29 is bonded. For this reason, when the conductive wire 29 is connected to the first chip capacitor 27, the first chip capacitor 27 is usually made of ceramic.
　さらに、スモールアウトラインパッケージ（ＳＯＰ）方式のパッケージで両面実装基板へのリフロー実装を行う場合を考える。この場合、１回目にパワー半導体モジュールを両面実装基板の一方の主面に実装する。その後、２回目の実装作業では当該両面実装基板を裏返してリフロー実装する。そのため、パワー半導体モジュールの質量が重たい場合、１回目のリフロー実装したときに、パワー半導体モジュールの端子に濡れたはんだによって発生する表面張力よりも、パワー半導体モジュールに働く重力の方が大きくなり、パワー半導体モジュールが実装基板から落下する可能性がある。パワー半導体モジュールの落下を防止するため、接着剤などでパワー半導体モジュールを実装基板に固定することも考えられるが、この場合製造コストが増大する。本実施の形態に係るパワー半導体モジュール１は、図１９に示した比較例としてのパワー半導体モジュールにおける上記のような問題の発生を抑制できる。 Furthermore, consider the case of performing reflow mounting on a double-sided mounting board with a small outline package (SOP) type package. In this case, the power semiconductor module is mounted on one main surface of the double-sided mounting substrate for the first time. Thereafter, in the second mounting operation, the double-sided mounting board is turned over and reflow mounted. Therefore, when the mass of the power semiconductor module is heavy, the gravity acting on the power semiconductor module becomes larger than the surface tension generated by the solder wetted on the terminals of the power semiconductor module when the first reflow mounting is performed. There is a possibility that the semiconductor module falls from the mounting substrate. In order to prevent the power semiconductor module from falling, it may be possible to fix the power semiconductor module to the mounting substrate with an adhesive or the like, but in this case, the manufacturing cost increases. The power semiconductor module 1 according to the present embodiment can suppress the occurrence of the above problems in the power semiconductor module as the comparative example shown in FIG.
　上記パワー半導体モジュール１において、第１のチップコンデンサ２７とパワー半導体チップ２０との間の距離Ｌ１より、第１のチップコンデンサ２７と第１の電子素子２５との間の距離Ｌ２が短い。 In the power semiconductor module 1, the distance L2 between the first chip capacitor 27 and the first electronic element 25 is shorter than the distance L1 between the first chip capacitor 27 and the power semiconductor chip 20.
　この場合、パワー半導体チップ２０から第１のチップコンデンサ２７までの距離Ｌ１を大きくできるので、パワー半導体チップ２０において発生する熱やノイズが第１のチップコンデンサ２７に影響を与える可能性を低減できる。このため、第１のチップコンデンサ２７および当該第１のチップコンデンサ２７を含むブートストラップ回路などの動作が、上述した熱やノイズによって不安定化する可能性を低減できる。 In this case, since the distance L1 from the power semiconductor chip 20 to the first chip capacitor 27 can be increased, the possibility that the heat and noise generated in the power semiconductor chip 20 affect the first chip capacitor 27 can be reduced. For this reason, it is possible to reduce the possibility that the operations of the first chip capacitor 27 and the bootstrap circuit including the first chip capacitor 27 become unstable due to the heat and noise described above.
　上記パワー半導体モジュール１において、第１のリード端子１１には、１つ以上の第１の貫通孔１６ａが形成されている。第２のリード端子１２には、１つ以上の第２の貫通孔１６ｂが形成されている。１つ以上の第１の貫通孔１６ａおよび１つ以上の第２の貫通孔１６ｂの内部には、それぞれ封止部材４０の一部が配置されている。 In the power semiconductor module 1, the first lead terminal 11 has one or more first through holes 16a. One or more second through holes 16 b are formed in the second lead terminal 12. A part of the sealing member 40 is disposed inside each of the one or more first through holes 16a and the one or more second through holes 16b.
　この場合、１つ以上の第１の貫通孔１６ａおよび１つ以上の第２の貫通孔１６ｂの内部に配置された封止部材４０の一部により、第１および第２のリード端子１１，１２の上側と下側とに位置する封止部材４０の部分が繋がれた状態となる。このため、第１および第２のリード端子１１，１２が封止部材４０により強固に固定された状態となる。したがって、第１および第２のリード端子１１，１２に応力が加えられた場合に当該第１および第２のリード端子１１，１２の変位を抑制でき、結果的に当該変位に起因する第１および第２のリード端子１１，１２からの第１のチップコンデンサ２７の剥離を抑制できる。 In this case, the first and second lead terminals 11 and 12 are formed by a part of the sealing member 40 disposed inside the one or more first through holes 16a and the one or more second through holes 16b. The portions of the sealing member 40 located on the upper side and the lower side of the are connected. For this reason, the first and second lead terminals 11 and 12 are firmly fixed by the sealing member 40. Therefore, when stress is applied to the first and second lead terminals 11, 12, the displacement of the first and second lead terminals 11, 12 can be suppressed, and as a result, the first and second lead terminals 11, 12 are caused by the displacement. The peeling of the first chip capacitor 27 from the second lead terminals 11 and 12 can be suppressed.
　上記パワー半導体モジュール１において、１つ以上の第１の貫通孔１６ａおよび１つ以上の第２の貫通孔１６ｂは、図１０に示すようにそれぞれ複数の貫通孔を含んでもよい。この場合、第１および第２のリード端子１１，１２から第１のチップコンデンサ２７が剥離することをより確実に抑制できる。第１および第２のリード端子１１，１２において、複数の貫通孔１６ａ、１６ｂは第１のチップコンデンサ２７を挟む位置に配置されてもよい。 In the power semiconductor module 1, the one or more first through holes 16a and the one or more second through holes 16b may each include a plurality of through holes as shown in FIG. In this case, separation of the first chip capacitor 27 from the first and second lead terminals 11 and 12 can be more reliably suppressed. In the first and second lead terminals 11 and 12, the plurality of through holes 16 a and 16 b may be arranged at positions where the first chip capacitor 27 is sandwiched.
　上記パワー半導体モジュール１において、第１のリード端子１１および第２のリード端子１２は、それぞれ封止部材４０における第１の表面から外側に突出した突出部である第１の突出部１１ｃおよび第２の突出部１２ｃを含む。１つ以上の第１の貫通孔１６ａは、第１のチップコンデンサ２７から見て第１のリード端子１１の第１の突出部１１ｃ側に位置する第１の外側貫通孔（図４の第１の貫通孔１６ａ）を含む。１つ以上の第２の貫通孔１６ｂは、第１のチップコンデンサ２７から見て第２のリード端子１２の第２の突出部１２ｃ側に位置する第２の外側貫通孔（図４の第２の貫通孔１６ｂ）を含む。第１のチップコンデンサ２７と第１の外側貫通孔（図４の第１の貫通孔１６ａ）との間の第１の距離Ｗ１は、第１のチップコンデンサ２７と第２の外側貫通孔（図４の第２の貫通孔１６ｂ）との間の第２の距離Ｗ２と同じである。なお、ここで第１の距離Ｗ１と第２の距離Ｗ２とが同じとは、第１の距離Ｗ１と第２の距離Ｗ２との差が１．０ｍｍ以下であることを意味する。 In the power semiconductor module 1, the first lead terminal 11 and the second lead terminal 12 are a first protruding portion 11 c and a second protruding portion, which are protruding portions protruding outward from the first surface of the sealing member 40, respectively. Projecting portion 12c. The one or more first through holes 16a are first outer through holes (the first through holes in FIG. 4) that are located on the first projecting portion 11c side of the first lead terminal 11 when viewed from the first chip capacitor 27. Through-holes 16a). The one or more second through-holes 16b are second outer through-holes (the second through-holes in FIG. 4) that are located on the second projecting portion 12c side of the second lead terminal 12 when viewed from the first chip capacitor 27. Through-holes 16b). The first distance W1 between the first chip capacitor 27 and the first outer through hole (the first through hole 16a in FIG. 4) is equal to the first chip capacitor 27 and the second outer through hole (see FIG. 4 and the second distance W2 between the second through hole 16b). Here, the first distance W1 and the second distance W2 being the same means that the difference between the first distance W1 and the second distance W2 is 1.0 mm or less.
　この場合、第１および第２のリード端子１１，１２において、第１および第２の外側貫通孔（図４の第１の貫通孔１６ａおよび第２の貫通孔１６ｂ）が形成された部分は他の部分より強度が低下する。このため、第１および第２のリード端子１１，１２に応力が加えられた場合に、第１および第２の外側貫通孔である第１の貫通孔１６ａおよび第２の貫通孔１６ｂが形成された領域を変形の中心として、第１および第２のリード端子１１，１２が変形する。そのため、第１のチップコンデンサ２７から当該変形の中心までの距離が第１および第２のリード端子１１，１２においてほぼ同じとなる。この結果、第１および第２のリード端子１１，１２において第１のチップコンデンサ２７からの距離が互いに異なる位置が変形の中心となる場合より、第１のリード端子１１と第１のチップコンデンサ２７との第１の接続部の変位量と、第２のリード端子１２と第１のチップコンデンサ２７との第２の接続部の変位量とが大きく異なるといった状態の発生確率を低減できる。したがって、当該変位量の差に起因して第１のチップコンデンサ２７が第１のリード端子１１または第２のリード端子１２から分離するといった問題の発生確率を低減できる。 In this case, in the first and second lead terminals 11 and 12, the portions where the first and second outer through holes (the first through hole 16a and the second through hole 16b in FIG. 4) are formed are the other parts. The strength is lower than the part. For this reason, when stress is applied to the first and second lead terminals 11, 12, the first and second through holes 16a and 16b, which are the first and second outer through holes, are formed. The first and second lead terminals 11 and 12 are deformed with the region as the center of deformation. Therefore, the distance from the first chip capacitor 27 to the center of the deformation is substantially the same in the first and second lead terminals 11 and 12. As a result, the first lead terminal 11 and the first chip capacitor 27 are different from the case where the positions where the distances from the first chip capacitor 27 are different from each other in the first and second lead terminals 11 and 12 are the center of deformation. The probability of occurrence of a state in which the amount of displacement of the first connecting portion differs greatly from the amount of displacement of the second connecting portion between the second lead terminal 12 and the first chip capacitor 27 can be reduced. Therefore, it is possible to reduce the probability of occurrence of a problem that the first chip capacitor 27 is separated from the first lead terminal 11 or the second lead terminal 12 due to the difference in the displacement amount.
　上記パワー半導体モジュール１において、第１の電子素子２５は、第１の整流用半導体チップである。 In the power semiconductor module 1, the first electronic element 25 is a first rectifying semiconductor chip.
　上記パワー半導体モジュール１において、第１の整流用半導体チップは、図６に示すように抵抗器２５ｂを内蔵している。抵抗器２５ｂを内蔵する第１の整流用半導体チップと、第１のチップコンデンサ２７とは、ブートストラップ回路を構成している。 In the power semiconductor module 1, the first rectifying semiconductor chip includes a resistor 25b as shown in FIG. The first rectifying semiconductor chip incorporating the resistor 25b and the first chip capacitor 27 constitute a bootstrap circuit.
　上記パワー半導体モジュール１において、複数のリード端子は、第３のリード端子１１１と第４のリード端子１１２とを含む。第３のリード端子１１１は、第１のリード端子１１および第２のリード端子１２と離間されている。第４のリード端子１１２は、第３のリード端子１１１から離間されている。上記パワー半導体モジュール１は、第２のチップコンデンサ１２７と第２の電子素子１２５とをさらに備える。第２のチップコンデンサ１２７は、第３の電極１２８ａと第４の電極１２８ｂとを含む。第２の電子素子１２５は、パワー半導体チップ２０、第１および第２のチップコンデンサ２７，１２７および第１の電子素子２５とは異なる素子である。第２のチップコンデンサ１２７の第３の電極１２８ａと第４の電極１２８ｂとは、第２の導電性接着部１３７で、第３のリード端子１１１と第４のリード端子１１２とにそれぞれ接合されている。第３のリード端子１１１には第２の電子素子１２５が搭載されている。第１のチップコンデンサ２７に対する第１の電子素子２５の相対的な配置は、第２のチップコンデンサ１２７に対する第２の電子素子１２５の相対的な配置と同じである。また、第１のチップコンデンサ２７と第１の電子素子２５との間の距離Ｌ２１は、第２のチップコンデンサ１２７と第２の電子素子１２５との間の距離Ｌ２２と同じでもよい。さらに、第３のチップコンデンサ２２７と第３の電子素子２２５とをさらに備える場合、第３のチップコンデンサ２２７と第３の電子素子２２５との間の距離Ｌ２３は、上記距離Ｌ２１と同じであってもよい。 In the power semiconductor module 1, the plurality of lead terminals include a third lead terminal 111 and a fourth lead terminal 112. The third lead terminal 111 is separated from the first lead terminal 11 and the second lead terminal 12. The fourth lead terminal 112 is separated from the third lead terminal 111. The power semiconductor module 1 further includes a second chip capacitor 127 and a second electronic element 125. The second chip capacitor 127 includes a third electrode 128a and a fourth electrode 128b. The second electronic element 125 is an element different from the power semiconductor chip 20, the first and second chip capacitors 27, 127, and the first electronic element 25. The third electrode 128a and the fourth electrode 128b of the second chip capacitor 127 are joined to the third lead terminal 111 and the fourth lead terminal 112 by the second conductive adhesive portion 137, respectively. Yes. A second electronic element 125 is mounted on the third lead terminal 111. The relative arrangement of the first electronic element 25 with respect to the first chip capacitor 27 is the same as the relative arrangement of the second electronic element 125 with respect to the second chip capacitor 127. The distance L21 between the first chip capacitor 27 and the first electronic element 25 may be the same as the distance L22 between the second chip capacitor 127 and the second electronic element 125. Further, when the third chip capacitor 227 and the third electronic element 225 are further provided, the distance L23 between the third chip capacitor 227 and the third electronic element 225 is the same as the distance L21. Also good.
　なお、ここで相対的な配置が同じとは、平面視において、第１のチップコンデンサ２７の中心から第１の電子素子２５の中心に向かう第１のベクトルと、第２のチップコンデンサ１２７の中心から第２の電子素子１２５の中心に向かう第２のベクトルとが実質的に同じことを意味する。より具体的には、上述した相対的な配置が同じとは、第１のチップコンデンサ２７の中心から第１の電子素子２５の中心までの第１の距離と、第２のチップコンデンサ１２７の中心から第２の電子素子１２５の中心までの第２の距離との差が、第１の距離の０％以上１０％以下であり、かつ、上記第１のベクトルの向きと上記第２のベクトルの向きとのなす角度が０°以上１５°以下であることを意味する。また、第１および第２のチップコンデンサ２７，１２７および第１および第２の電子素子２５，１２５の中心について、当該第１及び第２のチップコンデンサ２７，１２７および第１及び第２の電子素子２５，１２５の平面形状が四角形状である場合、当該平面形状の対角線の交点を上記中心としてもよい。また、距離Ｌ２１と距離Ｌ２２または距離Ｌ２３が同じとは、距離Ｌ２２または距離Ｌ２３と距離Ｌ２１との差が、距離Ｌ２１の０%以上１０%以下の場合を意味する。 Here, the same relative arrangement means that the first vector from the center of the first chip capacitor 27 to the center of the first electronic element 25 and the center of the second chip capacitor 127 in plan view. Means substantially the same as the second vector from the center toward the center of the second electronic element 125. More specifically, the above-described relative arrangement is the same as the first distance from the center of the first chip capacitor 27 to the center of the first electronic element 25 and the center of the second chip capacitor 127. And the second distance from the second electronic element 125 to the center of the second electronic element 125 is not less than 0% and not more than 10% of the first distance, and the direction of the first vector and the second vector It means that the angle formed by the direction is 0 ° or more and 15 ° or less. Further, the first and second chip capacitors 27 and 127 and the first and second electronic elements are arranged at the centers of the first and second chip capacitors 27 and 127 and the first and second electronic elements 25 and 125. When the planar shapes of 25 and 125 are quadrangular, the intersection of diagonal lines of the planar shape may be the center. The distance L21 is equal to the distance L22 or the distance L23 when the difference between the distance L22 or the distance L23 and the distance L21 is 0% or more and 10% or less of the distance L21.
　この場合、第１のチップコンデンサ２７と第１の電子素子２５とにより構成される回路の部分の配線抵抗は、第１のリード端子１１における第１のチップコンデンサ２７と第１の電子素子２５との配置により変化する。また、第２のチップコンデンサ１２７と第２の電子素子１２５とにより構成される回路の部分の配線抵抗も、第３のリード端子１１１における第２のチップコンデンサ１２７と第２の電子素子１２５との配置により変化する。そのため、第１のチップコンデンサ２７に対する第１の電子素子２５の相対的な配置と、第２のチップコンデンサ１２７に対する第２の電子素子１２５の相対的な配置とが実質的に同じであれば、上記配線抵抗も実質的に同じにできる。 In this case, the wiring resistance of the portion of the circuit constituted by the first chip capacitor 27 and the first electronic element 25 is the first chip capacitor 27 and the first electronic element 25 in the first lead terminal 11. Varies depending on the arrangement. In addition, the wiring resistance of the circuit portion constituted by the second chip capacitor 127 and the second electronic element 125 is also different between the second chip capacitor 127 and the second electronic element 125 in the third lead terminal 111. It changes with arrangement. Therefore, if the relative arrangement of the first electronic element 25 with respect to the first chip capacitor 27 and the relative arrangement of the second electronic element 125 with respect to the second chip capacitor 127 are substantially the same, The wiring resistance can also be made substantially the same.
　ここで、ブートストラップ回路を構成する第１のチップコンデンサ２７の充放電シーケンスを説明する。図２０は、パワー半導体モジュールのチップコンデンサにおける充放電波形を説明するためのグラフを示す図である。図２０の横軸は時間を示し、縦軸は第１のチップコンデンサ２７の電位を示す。図２０は、時間に対する第１のチップコンデンサ２７の端子間電圧の推移を示している。図２０において実線で示した波形Ａは、破線で示した波形Ｂよりも整流用半導体チップである第１の電子素子２５と第１のチップコンデンサ２７との間の抵抗値が大きいときのものである。当該抵抗値が大きくなると、第１のチップコンデンサ２７に充電するときの波形の傾きが小さくなり、また放電時に低下した電圧の絶対値が小さくなる。そして、３相のそれぞれにおける上記抵抗値がばらつくと、放電期間中、すなわちゲート駆動するために第１から第３のチップコンデンサ２７，１２７，２２７を放電する期間中にパワー半導体チップ２０を駆動する電圧値の下限を下回らないように、充放電シーケンスを各相ごとにチューニングすることが必要になる。つまり、第１から第３のチップコンデンサ２７，１２７，２２７を放電させてパワー半導体チップ２０を駆動させたい期間中に、ゲート駆動に必要な電圧を下回らないように回路設計および充電時間を相ごとに設定する。この場合、下限を下回りそうな相が出た場合には、相ごとに第１から第３のコンデンサ２７，１２７，２２７を充電する時間を変更するなどの操作が必要になる。このようなチューニング操作を不要とするため、ブートストラップ回路を構成する第１から第３の電子素子２５，１２５，２２５と第１から第３のチップコンデンサ２７，１２７，２２７とのそれぞれを繋ぐ経路の抵抗値が相間で均一とすることが好ましい。この場合、インバータ駆動時の回路の安定性が向上する。 Here, a charge / discharge sequence of the first chip capacitor 27 constituting the bootstrap circuit will be described. FIG. 20 is a diagram illustrating a graph for explaining a charge / discharge waveform in the chip capacitor of the power semiconductor module. The horizontal axis of FIG. 20 indicates time, and the vertical axis indicates the potential of the first chip capacitor 27. FIG. 20 shows the transition of the voltage between the terminals of the first chip capacitor 27 with respect to time. A waveform A indicated by a solid line in FIG. 20 is obtained when the resistance value between the first electronic element 25 which is a rectifying semiconductor chip and the first chip capacitor 27 is larger than the waveform B indicated by a broken line. is there. As the resistance value increases, the slope of the waveform when the first chip capacitor 27 is charged decreases, and the absolute value of the voltage that has decreased during discharge decreases. When the resistance value in each of the three phases varies, the power semiconductor chip 20 is driven during the discharge period, that is, during the period during which the first to third chip capacitors 27, 127, and 227 are discharged to drive the gate. It is necessary to tune the charge / discharge sequence for each phase so as not to fall below the lower limit of the voltage value. In other words, the circuit design and the charging time are set phase by phase so that the voltage required for driving the gate does not fall during the period in which the power semiconductor chip 20 is driven by discharging the first to third chip capacitors 27, 127, 227. Set to. In this case, when a phase that is likely to fall below the lower limit appears, an operation such as changing the time for charging the first to third capacitors 27, 127, and 227 for each phase becomes necessary. In order to eliminate the need for such a tuning operation, the paths connecting the first to third electronic elements 25, 125, 225 and the first to third chip capacitors 27, 127, 227 constituting the bootstrap circuit. It is preferable that the resistance value is uniform between the phases. In this case, the stability of the circuit when driving the inverter is improved.
　上記パワー半導体モジュール１において、第１のリード端子１１には、１つ以上の第１の貫通孔１６ａが形成されている。第２のリード端子１２には、１つ以上の第２の貫通孔１６ｂが形成されている。第３のリード端子１１１には、１つ以上の第３の貫通孔１６ｃが形成されている。第４のリード端子１１２には、１つ以上の第４の貫通孔１６ｄが形成されている。１つ以上の第１の貫通孔１６ａ、１つ以上の第２の貫通孔１６ｂ、１つ以上の第３の貫通孔１６ｃ、および１つ以上の第４の貫通孔１６ｄの内部には、それぞれ封止部材４０の一部が配置されている。 In the power semiconductor module 1, the first lead terminal 11 has one or more first through holes 16a. One or more second through holes 16 b are formed in the second lead terminal 12. One or more third through holes 16 c are formed in the third lead terminal 111. The fourth lead terminal 112 is formed with one or more fourth through holes 16d. Each of the one or more first through holes 16a, the one or more second through holes 16b, the one or more third through holes 16c, and the one or more fourth through holes 16d, A part of the sealing member 40 is disposed.
　この場合、１つ以上の第１から第４の貫通孔１６ａ，１６ｂ，１６ｃ，１６ｄの内部にそれぞれ配置された封止部材４０の一部により、第１から第４のリード端子１１，１２，１１１，１１２の上側と下側とに位置する封止部材４０の部分が繋がれた状態となる。このため、第１から第４のリード端子１１，１２，１１１，１１２が封止部材４０により強固に固定された状態となる。したがって、第１から第４のリード端子１１，１２，１１１，１１２に応力が加えられた場合に当該第１から第４のリード端子１１，１２，１１１，１１２の変位を抑制でき、結果的に当該変位に起因する第１から第４のリード端子１１，１２，１１１，１１２からの第１および第２のチップコンデンサ２７，１２７の剥離を抑制できる。 In this case, the first to fourth lead terminals 11, 12, 12 are formed by a part of the sealing member 40 disposed in each of the one or more first to fourth through holes 16 a, 16 b, 16 c, 16 d. The portions of the sealing member 40 located above and below 111 and 112 are connected. Therefore, the first to fourth lead terminals 11, 12, 111, 112 are firmly fixed by the sealing member 40. Therefore, when stress is applied to the first to fourth lead terminals 11, 12, 111, 112, the displacement of the first to fourth lead terminals 11, 12, 111, 112 can be suppressed, and as a result. Separation of the first and second chip capacitors 27, 127 from the first to fourth lead terminals 11, 12, 111, 112 due to the displacement can be suppressed.
　上記パワー半導体モジュール１において、１つ以上の第１の貫通孔１６ａ、１つ以上の第２の貫通孔１６ｂ、１つ以上の第３の貫通孔１６ｃ、および１つ以上の第４の貫通孔１６ｄは、それぞれ複数の貫通孔を含む。 In the power semiconductor module 1, one or more first through holes 16a, one or more second through holes 16b, one or more third through holes 16c, and one or more fourth through holes. Each of 16d includes a plurality of through holes.
　この場合、第１から第４のリード端子１１，１２，１１１，１１２から第１および第２のチップコンデンサ２７，１２７が剥離することをより確実に抑制できる。第１から第４のリード端子１１，１２，１１１，１１２において、複数の貫通孔は図１０に示すように第１または第２のチップコンデンサ２７，１２７を挟む位置に配置されていてもよい。 In this case, separation of the first and second chip capacitors 27 and 127 from the first to fourth lead terminals 11, 12, 111, and 112 can be more reliably suppressed. In the first to fourth lead terminals 11, 12, 111, 112, the plurality of through holes may be arranged at positions where the first or second chip capacitors 27, 127 are sandwiched as shown in FIG. 10.
　上記パワー半導体モジュール１において、第１から第４のリード端子１１，１２，１１１，１１２は、それぞれ封止部材４０における第１の表面から外側に突出した突出部（第１の突出部１１ｃ、第２の突出部１２ｃ、第３の突出部１１１ｃ、第４の突出部１１２ｃ）を含む。第１のチップコンデンサ２７から見て第１のリード端子１１の第１の突出部１１ｃ側に位置するとともに、封止部材４０により封止された第１のリード端子１１の一部分の形状は、第２のチップコンデンサ１２７から見て第３のリード端子１１１の第３の突出部１１１ｃ側に位置するとともに、封止部材４０により封止された第３のリード端子１１１の一部分の形状と同じである。第１のチップコンデンサ２７から見て第２のリード端子１２の第２の突出部１２ｃ側に位置するとともに、封止部材４０により封止された第２のリード端子１２の一部分の形状は、第２のチップコンデンサ１２７から見て第４のリード端子１１２の第４の突出部１１２ｃ側に位置するとともに、封止部材４０により封止された第４のリード端子１１２の一部分の形状と同じである。 In the power semiconductor module 1, the first to fourth lead terminals 11, 12, 111, and 112 are protruding portions (first protruding portion 11 c, first protruding portion) that protrude outward from the first surface of the sealing member 40, respectively. 2 protrusions 12c, third protrusions 111c, and fourth protrusions 112c). The shape of a part of the first lead terminal 11 which is located on the first protruding portion 11c side of the first lead terminal 11 when viewed from the first chip capacitor 27 and is sealed by the sealing member 40 is The third lead terminal 111 is located on the third protruding portion 111c side when viewed from the second chip capacitor 127, and has the same shape as a part of the third lead terminal 111 sealed by the sealing member 40. . The shape of a part of the second lead terminal 12 which is located on the second projecting portion 12c side of the second lead terminal 12 as viewed from the first chip capacitor 27 and sealed by the sealing member 40 is The fourth lead terminal 112 is located on the fourth projecting portion 112 c side when viewed from the second chip capacitor 127 and has the same shape as a part of the fourth lead terminal 112 sealed by the sealing member 40. .
　なお、第１のリード端子１１の上記一部分の形状が第３のリード端子１１１の一部分の形状と同じとは、第１のリード端子１１の上記一部分の外形と第３のリード端子１１１の上記一部分の外形とが実質的に同じであることを意味する。具体的には、第１のリード端子１１の上記一部分の外形線と第３のリード端子１１１の上記一部分の外形線とを重ねたときに、対応する外形線の一部（一辺）の長さの差が、第１のリード端子１１の上記一部分の外形線の当該一部の長さの０％以上１０％以下であり、かつ、対応する外形線の一部（一辺）の延在方向のなす角度が０°以上１５°以下である場合を、第１のリード端子１１の上記一部分の形状が第３のリード端子１１１の一部分の形状と同じであるとする。また、第２のリード端子１２の上記一部分の形状が第４のリード端子１１２の一部分の形状と同じかどうかも、上記第１のおよび第３のリード端子１１，１１１の一部分の形状に関する手法と同様の手法により判断してもよい。 Note that the shape of the part of the first lead terminal 11 is the same as the shape of the part of the third lead terminal 111 means that the shape of the part of the first lead terminal 11 and the part of the third lead terminal 111 are the same. It means that the external shape of is substantially the same. Specifically, when the part of the outline of the first lead terminal 11 and the part of the outline of the third lead terminal 111 overlap, the length of a part (one side) of the corresponding outline Of the first lead terminal 11 is not less than 10% and not more than 10% of the length of the part of the outline of the part, and a part (one side) of the corresponding outline is extended in the extending direction. When the angle formed is 0 ° or more and 15 ° or less, the shape of the part of the first lead terminal 11 is assumed to be the same as the shape of the part of the third lead terminal 111. In addition, whether or not the shape of the part of the second lead terminal 12 is the same as the shape of the part of the fourth lead terminal 112 is also a method related to the shape of the part of the first and third lead terminals 11 and 111. You may judge by the same method.
　この場合、第１および第２のリード端子１１，１２に対する第１のチップコンデンサ２７の接続配置と、第３および第４のリード端子１１１，１１２に対する第２のチップコンデンサ１２７の接続配置とを同様にしておくことで、当該第１または第２のチップコンデンサ２７，１２７の接続位置がずれた場合に、当該ずれを目視により容易に発見できる。 In this case, the connection arrangement of the first chip capacitor 27 to the first and second lead terminals 11 and 12 and the connection arrangement of the second chip capacitor 127 to the third and fourth lead terminals 111 and 112 are the same. Thus, when the connection position of the first or second chip capacitor 27 or 127 is shifted, the shift can be easily found by visual observation.
　上記パワー半導体モジュール１において、第２の電子素子１２５は、第２の整流用半導体チップである。 In the power semiconductor module 1, the second electronic element 125 is a second rectifying semiconductor chip.
　上記パワー半導体モジュール１において、第２の整流用半導体チップは、図６に示した第１の電子素子２５と同様に抵抗器２５ｂを内蔵している。抵抗器２５ｂを内蔵する第２の整流用半導体チップと、第２のチップコンデンサ１２７とは、ブートストラップ回路を構成している。 In the power semiconductor module 1, the second rectifying semiconductor chip includes a resistor 25b as in the first electronic element 25 shown in FIG. The second rectifying semiconductor chip incorporating the resistor 25b and the second chip capacitor 127 constitute a bootstrap circuit.
　上記パワー半導体モジュール１において、複数のリード端子は、第５のリード端子２１１と第６のリード端子２１２とを含む。第５のリード端子２１１は、第１から第４のリード端子１１，１２，１１１，１１２と離間されている。第６のリード端子２１２は、第５のリード端子２１１から離間されている。上記パワー半導体モジュール１は、第３のチップコンデンサ２２７と、第３の電子素子２２５とをさらに備える。第３のチップコンデンサ２２７は、第５の電極２２８ａと第６の電極２２８ｂとを含む。第３の電子素子２２５は、パワー半導体チップ２０と、第１から第３のチップコンデンサ２７，１２７，２２７と、第１および第２の電子素子２５，１２５とは異なる。第３のチップコンデンサ２２７の第５の電極２２８ａと第６の電極２２８ｂとは、第３の導電性接着部２３７で、第５のリード端子２１１と第６のリード端子２１２とにそれぞれ接合されている。第５のリード端子２１１には第３の電子素子２２５が搭載されている。第１から第３のチップコンデンサ２７，１２７，２２７は、図４の上下方向である第１の方向に沿って配置されている。第１から第３のチップコンデンサ２７，１２７，２２７の第１の方向における配置ピッチＰ１は一定である。なお、第１から第３のチップコンデンサ２７，１２７，２２７の第１の方向における配置ピッチＰ１が一定であるとは、以下のような場合である。すなわち、図４に示すように、第１のチップコンデンサ２７において第２のチップコンデンサ１２７が位置する側と反対側の第１の端部と、第２のチップコンデンサ１２７において第１のチップコンデンサ２７側の第２の端部との間の、第１の方向に沿った第１の距離Ｐ１を考える。また、同様に、第２のチップコンデンサ１２７の上記第２の端部と、第３のチップコンデンサ２２７において第２のチップコンデンサ１２７側の第３の端部との間の、第１の方向に沿った第２の距離Ｐ１を考える。本明細書では、上記第１の距離Ｐ１と第２の距離Ｐ１との差が、上記第１の距離Ｐ１の０％以上１０％以下である場合を、上記配置ピッチＰ１が一定である場合とする。 In the power semiconductor module 1, the plurality of lead terminals include a fifth lead terminal 211 and a sixth lead terminal 212. The fifth lead terminal 211 is separated from the first to fourth lead terminals 11, 12, 111, and 112. The sixth lead terminal 212 is separated from the fifth lead terminal 211. The power semiconductor module 1 further includes a third chip capacitor 227 and a third electronic element 225. The third chip capacitor 227 includes a fifth electrode 228a and a sixth electrode 228b. The third electronic element 225 is different from the power semiconductor chip 20, the first to third chip capacitors 27, 127, 227, and the first and second electronic elements 25, 125. The fifth electrode 228a and the sixth electrode 228b of the third chip capacitor 227 are joined to the fifth lead terminal 211 and the sixth lead terminal 212 by the third conductive adhesive portion 237, respectively. Yes. A third electronic element 225 is mounted on the fifth lead terminal 211. The first to third chip capacitors 27, 127, 227 are arranged along a first direction which is the vertical direction of FIG. The arrangement pitch P1 in the first direction of the first to third chip capacitors 27, 127, 227 is constant. The arrangement pitch P1 in the first direction of the first to third chip capacitors 27, 127, 227 is constant in the following cases. That is, as shown in FIG. 4, the first chip capacitor 27 has a first end opposite to the side where the second chip capacitor 127 is located, and the second chip capacitor 127 has the first chip capacitor 27. Consider a first distance P1 along the first direction between the second end of the side. Similarly, in the first direction between the second end portion of the second chip capacitor 127 and the third end portion of the third chip capacitor 227 on the second chip capacitor 127 side. Consider a second distance P1 along. In this specification, the case where the difference between the first distance P1 and the second distance P1 is not less than 0% and not more than 10% of the first distance P1, and the case where the arrangement pitch P1 is constant. To do.
　この場合、第１から第３のチップコンデンサ２７，１２７，２２７を第１から第６のリード端子１１，１２，１１１，１１２，２１１，２１２に実装するときに、第１から第６のリード端子１１，１２，１１１，１１２，２１１，２１２を含むリードフレームを等ピッチで移動させつつ、第１から第３のチップコンデンサ２７，１２７，２２７を移動させる吸着ノズルなどの移動手段の動きを当該移動方向と垂直な方向のみとすることができる。この結果、パワー半導体モジュール１の製造プロセスの作業効率を向上させることができる。 In this case, when the first to third chip capacitors 27, 127, 227 are mounted on the first to sixth lead terminals 11, 12, 111, 112, 211, 212, the first to sixth lead terminals are mounted. The movement of the moving means such as the suction nozzle for moving the first to third chip capacitors 27, 127, 227 is moved while moving the lead frame including 11, 12, 111, 112, 211, 212 at an equal pitch. Only the direction perpendicular to the direction can be used. As a result, the working efficiency of the manufacturing process of the power semiconductor module 1 can be improved.
　上記パワー半導体モジュール１において、第３の電子素子２２５は、第３の整流用半導体チップである。 In the power semiconductor module 1, the third electronic element 225 is a third rectifying semiconductor chip.
　上記パワー半導体モジュール１において、第３の整流用半導体チップは、図６に示す第１の電子素子２５と同様に抵抗器２５ｂを内蔵している。抵抗器２５ｂを内蔵する第３の整流用半導体チップと、第３のチップコンデンサ２２７とは、ブートストラップ回路を構成している。 In the power semiconductor module 1, the third rectifying semiconductor chip includes a resistor 25b as in the first electronic element 25 shown in FIG. The third rectifying semiconductor chip incorporating the resistor 25b and the third chip capacitor 227 constitute a bootstrap circuit.
　実施の形態２．
　＜パワー半導体モジュールの構成および効果＞
　図２１は、実施の形態２に係るパワー半導体モジュールの概略断面図である。図２１を参照して、実施の形態２のパワー半導体モジュール１ｂを説明する。本実施の形態のパワー半導体モジュール１ｂは、実施の形態１のパワー半導体モジュール１と同様の構成を備え、同様の効果を奏するが、以下の点で主に異なる。 Embodiment 2. FIG.
<Configuration and effect of power semiconductor module>
FIG. 21 is a schematic cross-sectional view of a power semiconductor module according to the second embodiment. A power semiconductor module 1b according to the second embodiment will be described with reference to FIG. The power semiconductor module 1b of the present embodiment has the same configuration as that of the power semiconductor module 1 of the first embodiment and has the same effects, but is mainly different in the following points.
　パワー半導体モジュール１ｂでは、複数のリード端子は、封止部材４０から突出する突出部を含む。これら突出部は、ガルウィングの形状に曲げられている。例えば、第１のリード端子１１は、封止部材４０から突出する第１の突出部１１ｃ（図２１に示さず）を含む。第２のリード端子１２は、封止部材４０から突出する第２の突出部１２ｃを含む。第９のリード端子１５は、封止部材４０から突出する第５の突出部１５ｃを含む。第１の突出部１１ｃ、第２の突出部１２ｃ及び第５の突出部１５ｃは、ガルウィングの形状に曲げられている。 In the power semiconductor module 1b, the plurality of lead terminals include protruding portions that protrude from the sealing member 40. These protrusions are bent into a gull wing shape. For example, the first lead terminal 11 includes a first protrusion 11 c (not shown in FIG. 21) that protrudes from the sealing member 40. The second lead terminal 12 includes a second protrusion 12 c that protrudes from the sealing member 40. The ninth lead terminal 15 includes a fifth projecting portion 15 c that projects from the sealing member 40. The first protrusion 11c, the second protrusion 12c, and the fifth protrusion 15c are bent into a gull wing shape.
　複数のリード端子は、複数のパッド（例えば、第１のパッド１１ａ、第２のパッド１２ａ、第７のパッド１４ａ、第８のパッド１５ａ）に沿って延在する複数の端子部を含んでいる。例えば、第１のリード端子１１の第１の突出部１１ｃは、第１突出部分１１ｄ及び第２突出部分１１ｅ（図１を参照）に加えて、第１２突出部分（図示せず）をさらに含む。第１２突出部分は、第２突出部分１１ｅから、第１突出部分１１ｄとは反対方向に、かつ、水平に延在している。第１２突出部分は、第２突出部分１１ｅに対して折り曲げられている。第１２突出部分は、第１のリード端子１１の第１端子部として機能する。第２のリード端子１２の第２の突出部１２ｃは、第３突出部分１２ｄ及び第４突出部分１２ｅに加えて、第１３突出部分１２ｆをさらに含む。第１３突出部分１２ｆは、第４突出部分１２ｅから、第３突出部分１２ｄとは反対方向に、かつ、水平に延在している。第１３突出部分１２ｆは、第４突出部分１２ｅに対して折り曲げられている。第１３突出部分１２ｆは、第２のリード端子１２の第２端子部として機能する。 The plurality of lead terminals include a plurality of terminal portions extending along a plurality of pads (for example, the first pad 11a, the second pad 12a, the seventh pad 14a, and the eighth pad 15a). . For example, the first protrusion 11c of the first lead terminal 11 further includes a twelfth protrusion (not shown) in addition to the first protrusion 11d and the second protrusion 11e (see FIG. 1). . The twelfth projecting portion extends horizontally from the second projecting portion 11e in the direction opposite to the first projecting portion 11d. The twelfth projecting portion is bent with respect to the second projecting portion 11e. The twelfth projecting portion functions as the first terminal portion of the first lead terminal 11. The second projecting portion 12c of the second lead terminal 12 further includes a thirteenth projecting portion 12f in addition to the third projecting portion 12d and the fourth projecting portion 12e. The thirteenth projecting portion 12f extends from the fourth projecting portion 12e in the opposite direction to the third projecting portion 12d and horizontally. The thirteenth protruding portion 12f is bent with respect to the fourth protruding portion 12e. The thirteenth projecting portion 12 f functions as the second terminal portion of the second lead terminal 12.
　第９のリード端子１５の第５の突出部１５ｃは、第９突出部分１５ｄ及び第１０突出部分１５ｅに加えて、第１１突出部分１５ｆをさらに含む。第１１突出部分１５ｆは、第１０突出部分１５ｅから、第９突出部分１５ｄとは反対方向に、かつ、水平に延在している。第１１突出部分１５ｆは、第１０突出部分１５ｅに対して折り曲げられている。第１１突出部分１５ｆは、第９のリード端子１５の第３端子部として機能する。パワー半導体モジュール１ｂでは、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１のチップコンデンサ２７、第１の電子素子２５）はスモールアウトラインパッケージ（ＳＯＰ）方式でパッケージされている。 The fifth protrusion 15c of the ninth lead terminal 15 further includes an eleventh protrusion 15f in addition to the ninth protrusion 15d and the tenth protrusion 15e. The eleventh projecting portion 15f extends from the tenth projecting portion 15e in the direction opposite to the ninth projecting portion 15d and horizontally. The eleventh projecting portion 15f is bent with respect to the tenth projecting portion 15e. The eleventh protruding portion 15 f functions as a third terminal portion of the ninth lead terminal 15. In the power semiconductor module 1b, electronic components (the power semiconductor chip 20, the control semiconductor chip 23, the first chip capacitor 27, and the first electronic element 25) are packaged in a small outline package (SOP) system.
　本実施の形態のパワー半導体モジュール１ｂの製造方法は、実施の形態１のパワー半導体モジュール１の製造方法（図１１を参照）と同様の工程を備えているが、主に以下の点で異なる。パワー半導体モジュール１ｂの製造方法では、リードフレーム１０を加工する工程（Ｓ３）において、複数のリード端子の突出部（例えば、第１の突出部１１ｃ、第２の突出部１２ｃ及び第５の突出部１５ｃ）をガルウィング形状に折り曲げている。複数のリード端子の突出部に、複数の端子部（例えば、第１２突出部分、第１３突出部分１２ｆ及び第１１突出部分１５ｆ）を形成している。複数の端子部は、複数のパッド（例えば、第１のパッド１１ａ、第２のパッド１２ａ、第７のパッド１４ａ、第８のパッド１５ａ）に沿って延在している。こうして、図２１に示されるパワー半導体モジュール１ｂが得られる。 The manufacturing method of the power semiconductor module 1b of the present embodiment includes the same steps as the manufacturing method of the power semiconductor module 1 of the first embodiment (see FIG. 11), but mainly differs in the following points. In the method of manufacturing the power semiconductor module 1b, in the step (S3) of processing the lead frame 10, the protruding portions of the lead terminals (for example, the first protruding portion 11c, the second protruding portion 12c, and the fifth protruding portion) 15c) is bent into a gull wing shape. A plurality of terminal portions (for example, a twelfth protruding portion, a thirteenth protruding portion 12f, and an eleventh protruding portion 15f) are formed on the protruding portions of the plurality of lead terminals. The plurality of terminal portions extend along a plurality of pads (for example, the first pad 11a, the second pad 12a, the seventh pad 14a, and the eighth pad 15a). In this way, the power semiconductor module 1b shown in FIG. 21 is obtained.
　＜半導体装置の構成および効果＞
　図２２は、実施の形態２に係る半導体装置の概略断面図である。図２２を参照して、実施の形態２の半導体装置２ｂを説明する。本実施の形態の半導体装置２ｂは、実施の形態１の半導体装置２と同様の構成を備え、同様の効果を奏するが、以下の点で主に異なる。 <Configuration and effect of semiconductor device>
FIG. 22 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. With reference to FIG. 22, the semiconductor device 2b of the second embodiment will be described. The semiconductor device 2b of the present embodiment has the same configuration as that of the semiconductor device 2 of the first embodiment and has the same effects, but is mainly different in the following points.
　半導体装置２ｂは、パワー半導体モジュール１ｂと、複数の配線（例えば、配線５４，５５）を含む配線基板５１とを備える。複数の配線は、配線基板５１の第１の主面５１ａ上に形成されている。複数のリード端子の端子部が、はんだ接合部で配線に接合される。具体的には、第１のリード端子１１の第１２突出部分（図示せず）は、はんだ接合部（図示せず）で配線（図示せず）に接合される。第２のリード端子１２の第１３突出部分１２ｆは、はんだ接合部５７で配線５４に接合される。第９のリード端子１５の第１１突出部分１５ｆは、はんだ接合部５８で配線５５に接合される。 The semiconductor device 2b includes a power semiconductor module 1b and a wiring board 51 including a plurality of wirings (for example, wirings 54 and 55). The plurality of wirings are formed on the first main surface 51 a of the wiring board 51. Terminal portions of the plurality of lead terminals are joined to the wiring by solder joints. Specifically, a twelfth projecting portion (not shown) of the first lead terminal 11 is joined to a wiring (not shown) by a solder joint (not shown). The thirteenth projecting portion 12 f of the second lead terminal 12 is joined to the wiring 54 by a solder joint portion 57. The eleventh protruding portion 15 f of the ninth lead terminal 15 is joined to the wiring 55 by a solder joint 58.
　本実施の形態の半導体装置２ｂの製造方法を説明する。本実施の形態の半導体装置２ｂの製造方法は、実施の形態１の半導体装置２の製造方法（図１８を参照）と同様の工程を備えているが、主に以下の点で異なる。 A method for manufacturing the semiconductor device 2b of the present embodiment will be described. The manufacturing method of the semiconductor device 2b of the present embodiment includes the same steps as the manufacturing method of the semiconductor device 2 of the first embodiment (see FIG. 18), but mainly differs in the following points.
　パワー半導体モジュール１ｂでは、電子部品（パワー半導体チップ２０、制御用半導体チップ２３、第１から第３のチップコンデンサ２７，１２７，２２７、第１から第３の電子素子２５，１２５，２２５）はスモールアウトラインパッケージ（ＳＯＰ）方式でパッケージされている。そのため、パワー半導体モジュール１ｂを配線基板５１に実装する際に、リフロー式はんだ付けによって、複数のリード端子の複数の端子部（例えば、第１３突出部分１２ｆ及び第１１突出部分１５ｆ）を、配線基板５１の複数の配線（例えば、配線５４，５５）にはんだ接合する。こうして、図２２に示される本実施の形態の半導体装置２ｂが得られる。本実施の形態におけるリフロー式はんだ付けは、実施の形態１におけるフロー式はんだ付けよりも、はんだ付け時のパッケージの到達温度が高く、かつ、はんだ付けに要する時間が長い。そのため、リフロー式はんだ付けによってパワー半導体モジュール１ｂを配線基板５１に実装する際に、より大きな熱応力が、第１の導電性接着部３７に印加される。 In the power semiconductor module 1b, the electronic components (the power semiconductor chip 20, the control semiconductor chip 23, the first to third chip capacitors 27, 127, 227, and the first to third electronic elements 25, 125, 225) are small. It is packaged by the outline package (SOP) method. Therefore, when the power semiconductor module 1b is mounted on the wiring board 51, a plurality of terminal portions (for example, the thirteenth protruding portion 12f and the eleventh protruding portion 15f) of the plurality of lead terminals are connected to the wiring substrate by reflow soldering. The plurality of wirings 51 (for example, the wirings 54 and 55) are soldered. In this way, the semiconductor device 2b of the present embodiment shown in FIG. 22 is obtained. The reflow soldering in the present embodiment has a higher temperature reached by the package at the time of soldering and the time required for soldering than the flow soldering in the first embodiment. Therefore, when the power semiconductor module 1 b is mounted on the wiring substrate 51 by reflow soldering, a larger thermal stress is applied to the first conductive adhesive portion 37.
　＜半導体装置の変形例の構成および効果＞
　図２３は、実施の形態２の変形例に係るパワー半導体モジュールの概略平面図である。図２４は、図２３に示したパワー半導体モジュールの領域ＸＸＩＶの概略部分拡大平面図である。図２５は、図２４の線分ＸＸＶ－ＸＸＶにおける断面模式図である。図２３～図２４に示したパワー半導体モジュール１は、基本的には図２１に示したパワー半導体モジュール１ｂと同様の構成を備え、同様の効果を奏するが、以下の点で主に異なる。なお、図２３および図２４では説明を容易にするため、第１のチップコンデンサ２７（図２７および図１参照）を図示していない。 <Configuration and Effect of Modification of Semiconductor Device>
FIG. 23 is a schematic plan view of a power semiconductor module according to a modification of the second embodiment. 24 is a schematic partial enlarged plan view of a region XXIV of the power semiconductor module shown in FIG. FIG. 25 is a schematic sectional view taken along line XXV-XXV in FIG. The power semiconductor module 1 shown in FIGS. 23 to 24 basically has the same configuration as the power semiconductor module 1b shown in FIG. 21 and provides the same effects, but is mainly different in the following points. Note that the first chip capacitor 27 (see FIGS. 27 and 1) is not shown in FIGS. 23 and 24 for ease of explanation.
　図２３～図２５に示したパワー半導体モジュール１において、第１の電子素子２５は、第１のリード端子１１における第１のパッド１１ａにおいて、第１の貫通孔１６ａと対角線上に配置されることが望ましい。第１のパッド１１ａの平面視における外形はほぼ四角形状となっている。また、言い換えれば、第１のリード端子１１の中央８５から見て、第１の貫通孔１６ａと第１の電子素子２５とは互いに反対側の領域に配置されている。なお、ここで第１のリード端子１１の中央８５とは、実質的には第１のリード端子１１において第１の貫通孔１６ａが形成されるとともに第１の電子素子２５が配置された第１のパッド１１ａの中央８５を意味する。当該中央８５は、第１のパッド１１ａの重心でもよいし、第１のパッド１１ａの外形の角部が接する円の中心としてもよい。また、言い換えれば、第１リード端子１１の第２突出部１１ｅと第１のパッド１１ａとの接続部から第１の貫通孔１６ａまでの距離ｗ３は、当該接続部から第１の電子素子２５までの距離ｗ４より小さくなっている。 In the power semiconductor module 1 shown in FIGS. 23 to 25, the first electronic element 25 is disposed diagonally to the first through hole 16 a in the first pad 11 a of the first lead terminal 11. Is desirable. The outer shape of the first pad 11a in plan view is substantially rectangular. In other words, when viewed from the center 85 of the first lead terminal 11, the first through hole 16a and the first electronic element 25 are disposed in regions opposite to each other. Here, the center 85 of the first lead terminal 11 is substantially the first lead hole 16a formed in the first lead terminal 11 and the first electronic element 25 disposed therein. This means the center 85 of the pad 11a. The center 85 may be the center of gravity of the first pad 11a, or may be the center of a circle in contact with the corner of the outer shape of the first pad 11a. In other words, the distance w3 from the connection portion between the second protrusion 11e of the first lead terminal 11 and the first pad 11a to the first through hole 16a is from the connection portion to the first electronic element 25. Is smaller than the distance w4.
　ここで、上述したパワー半導体モジュール１の特徴的な構成を要約すれば、パワー半導体モジュール１は、第１のリード端子１１を含む複数のリード端子と、パワー半導体チップ２０と、パワー半導体チップ２０とは異なる第１の電子素子２５と、封止部材４０とを備える。封止部材４０は、パワー半導体チップ２０と第１の電子素子２５とを封止する。パワー半導体チップ２０は複数のリード端子の少なくとも１つに接合されている。第１のリード端子１１には第１の電子素子２５が搭載される。第１のリード端子１１には、第１の貫通孔１６ａが形成されている。第１のリード端子１１の中央８５から見て、第１の貫通孔１６ａと第１の電子素子２５とは互いに反対側の領域に配置されている。 Here, to summarize the characteristic configuration of the power semiconductor module 1 described above, the power semiconductor module 1 includes a plurality of lead terminals including the first lead terminal 11, a power semiconductor chip 20, and a power semiconductor chip 20. Includes different first electronic elements 25 and a sealing member 40. The sealing member 40 seals the power semiconductor chip 20 and the first electronic element 25. The power semiconductor chip 20 is bonded to at least one of the plurality of lead terminals. A first electronic element 25 is mounted on the first lead terminal 11. A first through hole 16 a is formed in the first lead terminal 11. When viewed from the center 85 of the first lead terminal 11, the first through hole 16 a and the first electronic element 25 are disposed in regions opposite to each other.
　ここで、第１のリード端子１１の第２突出部分１１ｅには、配線基板５１（図２２参照）にはんだ接合する時にはんだ付け性を向上させるために必要なめっきを施す場合がある。形成されるめっき層はたとえばＳｎを主成分とするめっき層である。この場合、第１の貫通孔１６ａは、第１のリード端子１１の第２突出部分１１ｅを伝って封止部材４０内に侵入してくるめっき液を阻止する機能を有する。たとえばめっき液には強酸性のものがあり、第１の電子素子２５の電極を構成する金属（たとえばＡｌ）が上記めっき液と接触すると当該電極が腐食する。このような電極の腐食は、パワー半導体モジュールを長期間に渡り使用していると当該電極の電気抵抗の増加や破断の原因となり得る。上記のように第１の貫通孔１６ａが第２突出部分１１ｅと第１のパッド１１ａとの接続部の近傍に形成されることにより、上記めっき液や水分の侵入を阻止できる。 Here, the second protruding portion 11e of the first lead terminal 11 may be subjected to plating necessary for improving solderability when soldered to the wiring board 51 (see FIG. 22). The formed plating layer is, for example, a plating layer containing Sn as a main component. In this case, the first through hole 16 a has a function of blocking the plating solution entering the sealing member 40 through the second protruding portion 11 e of the first lead terminal 11. For example, some plating solutions are strongly acidic, and when a metal (for example, Al) constituting the electrode of the first electronic element 25 comes into contact with the plating solution, the electrode corrodes. Such corrosion of the electrode may cause an increase in electrical resistance or breakage of the electrode when the power semiconductor module is used for a long period of time. As described above, the first through hole 16a is formed in the vicinity of the connection portion between the second protruding portion 11e and the first pad 11a, thereby preventing the plating solution and moisture from entering.
　また、上述のように第１の貫通孔１６ａが形成されている場合においても、第２突出部１１ｅを介して少量のめっき液や水分が第１のパッド１１ａの表面に侵入してく可能性がある。しかしながら、侵入してきためっき液などは、第１の貫通孔１６ａに浸透を阻止された後、主に第１のパッド１１ａの辺を伝って広がることが考えられる。そのため、上記のように第１のパッド１１ａ上で第１の貫通孔１６ａと対角に位置する場所に第１の電子素子２５を配置する、あるいは第１リード端子１１の第２突出部１１ｅと第１のパッド１１ａとの接続部から第１の貫通孔１６ａまでの距離ｗ３よりも、当該接続部から第１の電子素子２５までの距離ｗ４を大きくすることにより、めっき液などを第１の電子素子２５に到達しにくくする効果が期待できる。 Further, even when the first through hole 16a is formed as described above, a small amount of plating solution or moisture may enter the surface of the first pad 11a through the second protruding portion 11e. is there. However, it is conceivable that the plating solution or the like that has penetrated spreads mainly along the side of the first pad 11a after being prevented from penetrating into the first through hole 16a. Therefore, as described above, the first electronic element 25 is disposed on the first pad 11a at a position diagonally opposite to the first through hole 16a, or the second protruding portion 11e of the first lead terminal 11 and By making the distance w4 from the connection portion to the first electronic element 25 larger than the distance w3 from the connection portion with the first pad 11a to the first through hole 16a, the plating solution or the like can be removed. The effect of making it difficult to reach the electronic element 25 can be expected.
　また、図２３および図４に示すように第１の電気素子２５が搭載された第１のリード端子１１と、第２の電気素子１２５が搭載された第３のリード端子１１１との間の第４のリード端子１１２に関しても、外側に第４の貫通穴１６ｄを有している。なお、第２の電気素子１２５が搭載された第３のリード端子１１１と、第３の電気素子２２５が搭載された第５のリード端子２１１との間の第６のリード端子２１２に関しても、外側に第６の貫通穴１６ｆを有している。第５のリード端子２１１の第５のパッド２１１ａにも第５の貫通孔１６ｅが形成されている。第３のリード端子１１１および第５のリード端子２１１の構成は基本的に第１のリード端子１１と同様である。 Further, as shown in FIG. 23 and FIG. 4, the first lead terminal 11 on which the first electric element 25 is mounted and the third lead terminal 111 on which the second electric element 125 is mounted. The fourth lead terminal 112 also has a fourth through hole 16d on the outside. Note that the sixth lead terminal 212 between the third lead terminal 111 on which the second electric element 125 is mounted and the fifth lead terminal 211 on which the third electric element 225 is mounted is also outside. Has a sixth through hole 16f. A fifth through hole 16 e is also formed in the fifth pad 211 a of the fifth lead terminal 211. The configurations of the third lead terminal 111 and the fifth lead terminal 211 are basically the same as those of the first lead terminal 11.
　第１のリード端子１１などを構成するリード材料が例えば銅（Ｃｕ）などであっても、当該リード材料がめっき液で腐食する場合がある。このようなリード材料の腐食に起因して、樹脂と第１のリード端子１１などとの間に空間ができる可能性がある。この空間を介して水分などが侵入すると、当該水分により第１の電子素子２５などの寿命が短くなる可能性がある。そのため、第１の電気素子２５が搭載された第１のリード端子１１と、第２の電気素子１２５が搭載された第３のリード端子１１１との間に位置する、電気素子が搭載されていないリード端子である第４のリード端子１１２において、第４の貫通穴１６ｄを設けることで、水分などの侵入を阻止できる。この結果、第１の電気素子２５周辺の樹脂の隙間形成を抑制することができる。 Even if the lead material constituting the first lead terminal 11 is, for example, copper (Cu), the lead material may be corroded by the plating solution. Due to such corrosion of the lead material, there may be a space between the resin and the first lead terminal 11 or the like. If moisture or the like enters through this space, the lifetime of the first electronic element 25 or the like may be shortened by the moisture. Therefore, no electrical element is mounted that is located between the first lead terminal 11 on which the first electrical element 25 is mounted and the third lead terminal 111 on which the second electrical element 125 is mounted. In the fourth lead terminal 112 which is the lead terminal, the fourth through hole 16d is provided, so that intrusion of moisture and the like can be prevented. As a result, the formation of a resin gap around the first electric element 25 can be suppressed.
　図２３～図２５に示したパワー半導体モジュール１では、第１のリード端子１１において第１の電気素子２５と導電ワイヤが接続されるパッドとしてのめっき部１７との間に凹部８１を設けている。なお、第３のリード端子１１１および第５のリード端子２１１においても同様に凹部８１を形成してもよい。異なる観点から言えば、第１のリード端子１１は、中央８５から見て第１の貫通孔１６ａと反対側の領域に位置し、導電ワイヤ２９が接続される内側端子部としてのめっき部１７を含む。第１のリード端子１１において、中央８５から見て内側端子部としてのめっき部１７が位置する側に凹部８１が形成されている。この凹部８１は第１の電気素子２５などを接合する場合に用いる接合材がワイヤーパッドとしての内側端子部であるめっき部１７に到達することを防止する効果がある。なお、上述した第１の貫通孔１６ａと第１の電子素子２５との第１のリード端子１１での配置および凹部８１は実施の形態１に係るパワー半導体モジュール１に適用してもよい。すなわち、図２に示したパワー半導体モジュール１の第１のリード端子１１において第１の電気素子２５と導電ワイヤが接続されるパッドとしてのめっき部１７との間に凹部８１を設けてもよい。また、図２の第２のリード端子１２、第３のリード端子１１１、第４のリード端子１１２、第５のリード端子２１１、第６のリード端子２１２において、それぞれ図２３に示すように凹部８１を設けてもよい。 In the power semiconductor module 1 shown in FIGS. 23 to 25, a recess 81 is provided between the first electrical element 25 and the plating portion 17 as a pad to which a conductive wire is connected in the first lead terminal 11. . Note that the third lead terminal 111 and the fifth lead terminal 211 may be similarly formed with the recess 81. From a different point of view, the first lead terminal 11 is located in a region opposite to the first through hole 16a when viewed from the center 85, and the plated portion 17 as an inner terminal portion to which the conductive wire 29 is connected is provided. Including. In the first lead terminal 11, a concave portion 81 is formed on the side where the plated portion 17 as the inner terminal portion is located when viewed from the center 85. The recess 81 has an effect of preventing the bonding material used when the first electric element 25 or the like is bonded from reaching the plating portion 17 which is an inner terminal portion as a wire pad. The arrangement of the first through-hole 16a and the first electronic element 25 at the first lead terminal 11 and the concave portion 81 may be applied to the power semiconductor module 1 according to the first embodiment. That is, in the first lead terminal 11 of the power semiconductor module 1 shown in FIG. 2, the recess 81 may be provided between the first electric element 25 and the plating part 17 as a pad to which the conductive wire is connected. Further, in each of the second lead terminal 12, the third lead terminal 111, the fourth lead terminal 112, the fifth lead terminal 211, and the sixth lead terminal 212 in FIG. May be provided.
　実施の形態３．
　本実施の形態は、上述した実施の形態１または実施の形態２に係るパワー半導体モジュール１、１ｂを電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態３として、三相のインバータに本発明を適用した場合について説明する。 Embodiment 3 FIG.
In the present embodiment, the power semiconductor modules 1 and 1b according to the first or second embodiment described above are applied to a power conversion device. Although the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a third embodiment.
　図２６は、本実施の形態に係る電力変換装置を適用した電力変換システムの構成を示すブロック図である。図２６に示される電力変換システムは、電源１００、電力変換装置２００、負荷３００から構成される。電源１００は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１００は、特に限定されないが、例えば、直流系統、太陽電池または蓄電池で構成されてもよいし、交流系統に接続された整流回路またはＡＣ／ＤＣコンバータで構成されてもよい。電源１００は、直流系統から出力される直流電力を別の直流電力に変換するＤＣ／ＤＣコンバータによって構成されてもよい。 FIG. 26 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied. The power conversion system shown in FIG. 26 includes a power supply 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. Although the power supply 100 is not specifically limited, For example, it may be comprised with a DC system, a solar cell, or a storage battery, and may be comprised with the rectifier circuit or AC / DC converter connected to the AC system. The power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into another DC power.
　電力変換装置２００は、電源１００と負荷３００の間に接続された三相のインバータであり、電源１００から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図２６に示されるように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１を制御する制御信号を主変換回路２０１に出力する制御回路２０３とを備えている。 The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 26, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. 203.
　負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は、特に限定されるものではないが、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車、電気自動車、鉄道車両、エレベーター、または、空調機器向けの電動機として用いられる。 The load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200. The load 300 is not particularly limited, but is an electric motor mounted on various electric devices, and is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner, for example.
　以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子（図示せず）と還流ダイオード（図示せず）を備えている。スイッチング素子が電源１００から供給される電圧をスイッチングすることによって、主変換回路２０１は、電源１００から供給される直流電力を交流電力に変換して、負荷３００に供給する。主変換回路２０１の具体的な回路構成は種々のものがあるが、本実施の形態に係る主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードとから構成され得る。主変換回路２０１の各スイッチング素子及び各還流ダイオードの少なくともいずれかに、上述した実施の形態１および実施の形態２のいずれかのパワー半導体モジュール１，１ｂを適用する。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相及びＷ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。 Hereinafter, details of the power conversion apparatus 200 will be described. The main conversion circuit 201 includes a switching element (not shown) and a free wheeling diode (not shown). The main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300 by switching the voltage supplied from the power supply 100 by the switching element. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six freewheeling diodes in antiparallel. The power semiconductor modules 1 and 1b according to any one of the first and second embodiments described above are applied to at least one of the switching elements and the free-wheeling diodes of the main conversion circuit 201. Six switching elements are connected in series for every two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase and W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
　また、上述した実施の形態１で説明したように、各スイッチング素子を駆動する駆動回路（例えば、制御用半導体チップ２３）がパワー半導体モジュール２０２に内蔵されているため、主変換回路２０１は駆動回路を備えている。駆動回路は、主変換回路２０１に含まれるスイッチング素子を駆動する駆動信号を生成して、主変換回路２０１のスイッチング素子の制御電極に駆動信号を供給する。具体的には、制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 Further, as described in the first embodiment, since the drive circuit (for example, the control semiconductor chip 23) for driving each switching element is built in the power semiconductor module 202, the main conversion circuit 201 is a drive circuit. It has. The drive circuit generates a drive signal for driving the switching element included in the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When the switching element is kept off, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).
　制御回路２０３は、負荷３００に所望の電力が供給されるよう主変換回路２０１のスイッチング素子を制御する。具体的には、負荷３００に供給すべき電力に基づいて主変換回路２０１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するパルス幅変調（ＰＷＭ）制御によって、主変換回路２０１を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態になるべきスイッチング素子にはオフ信号が出力されるよう、主変換回路２０１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。 The control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
　本実施の形態に係る電力変換装置２００では、主変換回路２０１に含まれるパワー半導体モジュール２０２として、実施の形態１および実施の形態２のいずれかに係るパワー半導体モジュール１，１ｂが適用される。そのため、本実施の形態に係る電力変換装置２００は、小型化が可能である。 In the power conversion device 200 according to the present embodiment, the power semiconductor modules 1 and 1b according to either the first embodiment or the second embodiment are applied as the power semiconductor module 202 included in the main conversion circuit 201. Therefore, power converter 200 according to the present embodiment can be reduced in size.
　本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では２レベルの電力変換装置としたが、３レベルの電力変換装置であってもよいし、マルチレベルの電力変換装置であってもよい。電力変換装置が単相負荷に電力を供給する場合には、単相のインバータに本発明が適用されてもよい。電力変換装置が直流負荷等に電力を供給する場合には、ＤＣ／ＤＣコンバータまたはＡＣ／ＤＣコンバータに本発明が適用されてもよい。 In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described. However, the present invention is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used. However, a three-level power conversion device or a multi-level power conversion device may be used. When the power converter supplies power to a single-phase load, the present invention may be applied to a single-phase inverter. When the power converter supplies power to a DC load or the like, the present invention may be applied to a DC / DC converter or an AC / DC converter.
　本発明が適用された電力変換装置は、負荷が電動機の場合に限定されるものではなく、例えば、放電加工機もしくはレーザー加工機の電源装置、または、誘導加熱調理器もしくは非接触器給電システムの電源装置に組み込まれ得る。本発明が適用された電力変換装置は、太陽光発電システムまたは蓄電システム等のパワーコンディショナーとして用いられ得る。 The power conversion device to which the present invention is applied is not limited to the case where the load is an electric motor. For example, the power supply device of an electric discharge machine or a laser processing machine, or an induction heating cooker or a non-contact power supply system It can be incorporated into a power supply. The power conversion device to which the present invention is applied can be used as a power conditioner such as a solar power generation system or a power storage system.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。矛盾のない限り、今回開示された実施の形態の少なくとも２つを組み合わせてもよい。本発明の範囲は、上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. As long as there is no contradiction, at least two of the embodiments disclosed this time may be combined. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　１，１ｂ，２０２　パワー半導体モジュール、２，２ｂ　半導体装置、１０　リードフレーム、１０ａ　フレーム部、１０ｂ　開口、１１　第１のリード端子、１２　第２のリード端子、１３　第７のリード端子、１４　第８のリード端子、１５　第９のリード端子、１１１　第３のリード端子、１１２　第４のリード端子、１１ａ　第１のパッド、１１ｃ　第１の突出部、１１ｄ　第１突出部分、１１ｅ　第２突出部分、１１ｓ　第１の表面、１２ａ　第２のパッド、１２ｃ　第２の突出部、１２ｄ　第３突出部分、１２ｅ　第４突出部分、１２ｆ　第１３突出部分、１２ｓ　第２の表面、１４ａ　第７のパッド、１５ａ　第８のパッド、１５ｂ　段差部、１５ｃ　第５の突出部、１５ｄ　第９突出部分、１５ｅ　第１０突出部分、１５ｆ　第１１突出部分、５２，５３　貫通孔、１６ａ　第１の貫通孔、１６ｂ　第２の貫通孔、１６ｃ　第３の貫通孔、１６ｄ　第４の貫通孔、１７　めっき部、１８　端子接続部、２０　パワー半導体チップ、２３　制御用半導体チップ、２５　第１の電子素子、１２５　第２の電子素子、２２５　第３の電子素子、２５ａ　ダイオード、２５ｂ　抵抗器、２７　第１のチップコンデンサ、１２７　第２のチップコンデンサ、２２７　第３のチップコンデンサ、２８ａ　第１の電極、２８ｂ　第２の電極、２８ｃ，１２８ｃ，２２８ｃ　セラミック本体部、２９　導電ワイヤ、３０，５７，５８　はんだ接合部、３３　導電接合部、３５　導電性接着部、３７　第１の導電性接着部、４０　封止部材、４１ａ，４１ｂ，４６ａ，４６ｂ　部分、４５　金型、５１　配線基板、５１ａ　第１の主面、５１ｂ　第２の主面、５４，５５　配線、７０，７１　矢印、８１　凹部、８５　中央、１００　電源、１１１ａ　第３のパッド、１１１ｃ　第３の突出部、１１１ｄ　第５突出部分、１１１ｅ　第６突出部分、１１２ａ　第４のパッド、１１２ｃ　第４の突出部、１１２ｄ　第７突出部分、１１２ｅ　第８突出部分、１２１　絶縁性接着剤、１２８ａ　第３の電極、１２８ｂ　第４の電極、１３７　第２の導電性接着部、２００　電力変換装置、２０１　主変換回路、２０３　制御回路、２１１　第５のリード端子、２１２　第６のリード端子、２１１ａ　第５のパッド、２１２ａ　第６のパッド、２２８ａ　第５の電極、２２８ｂ　第６の電極、２３７　第３の導電性接着部、３００　負荷。　 1, 1b, 202 power semiconductor module, 2, 2b semiconductor device, 10 lead frame, 10a frame part, 10b opening, 11 first lead terminal, 12 second lead terminal, 13 seventh lead terminal, 14 eighth Lead terminal, 15 9th lead terminal, 111 3rd lead terminal, 112 4th lead terminal, 11a 1st pad, 11c 1st protruding part, 11d 1st protruding part, 11e 2nd protruding part, 11s 1st surface, 12a 2nd pad, 12c 2nd protrusion, 12d 3rd protrusion, 12e 4th protrusion, 12f 13th protrusion, 12s 2nd surface, 14a 7th pad, 15a 8th pad, 15b Stepped part, 15c 5th projecting part, 15d 9th projecting part, 15e 10th projecting part, 15 11th projecting portion, 52, 53 through hole, 16a first through hole, 16b second through hole, 16c third through hole, 16d fourth through hole, 17 plating part, 18 terminal connection part, 20 power Semiconductor chip, 23 control semiconductor chip, 25 first electronic element, 125 second electronic element, 225 third electronic element, 25a diode, 25b resistor, 27 first chip capacitor, 127 second chip capacitor 227, third chip capacitor, 28a, first electrode, 28b, second electrode, 28c, 128c, 228c, ceramic body, 29 conductive wire, 30, 57, 58 solder joint, 33 conductive joint, 35 conductive Adhesive part, 37 first conductive adhesive part, 40 sealing member, 41a, 41b, 46a, 46b part 45 mold, 51 wiring board, 51a first main surface, 51b second main surface, 54, 55 wiring, 70, 71 arrow, 81 recess, 85 center, 100 power supply, 111a third pad, 111c third 111d, 5th projecting part, 111e, 6th projecting part, 112a, 4th pad, 112c, 4th projecting part, 112d, 7th projecting part, 112e, 8th projecting part, 121, insulating adhesive, 128a, 3rd Electrode, 128b fourth electrode, 137 second conductive adhesive, 200 power conversion device, 201 main conversion circuit, 203 control circuit, 211 fifth lead terminal, 212 sixth lead terminal, 211a fifth Pad, 212a, sixth pad, 228a, fifth electrode, 228b, sixth electrode, 237, third conductive adhesive portion, 300 Load. *

Claims (20)

  1. 　第１のリード端子と、前記第１のリード端子から離間されている第２のリード端子とを含む複数のリード端子と、
    　パワー半導体チップと、
    　第１の電極と第２の電極とを含む第１のチップコンデンサと、
    　前記パワー半導体チップ及び前記第１のチップコンデンサとは異なる第１の電子素子と、
    　前記パワー半導体チップと前記第１のチップコンデンサと前記第１の電子素子とを封止する封止部材とを備え、
    　前記パワー半導体チップは前記複数のリード端子の少なくとも１つに接合されており、
    　前記第１のチップコンデンサの前記第１の電極と前記第２の電極とは、第１の導電性接着部で、前記第１のリード端子と前記第２のリード端子とにそれぞれ接合されており、
    　前記第１のリード端子には前記第１の電子素子が搭載されている、パワー半導体モジュール。     A plurality of lead terminals including a first lead terminal and a second lead terminal spaced from the first lead terminal;
    A power semiconductor chip;
    A first chip capacitor including a first electrode and a second electrode;
    A first electronic element different from the power semiconductor chip and the first chip capacitor;
    A sealing member that seals the power semiconductor chip, the first chip capacitor, and the first electronic element;
    The power semiconductor chip is bonded to at least one of the plurality of lead terminals;
    The first electrode and the second electrode of the first chip capacitor are joined to the first lead terminal and the second lead terminal by a first conductive adhesive portion, respectively. ,
    A power semiconductor module in which the first electronic element is mounted on the first lead terminal.
  2. 　前記第１のチップコンデンサと前記パワー半導体チップとの間の距離より、前記第１のチップコンデンサと前記第１の電子素子との間の距離が短い、請求項１に記載のパワー半導体モジュール。 The power semiconductor module according to claim 1, wherein a distance between the first chip capacitor and the first electronic element is shorter than a distance between the first chip capacitor and the power semiconductor chip.
  3. 　前記第１のリード端子には、１つ以上の第１の貫通孔が形成されており、
    　前記第２のリード端子には、１つ以上の第２の貫通孔が形成されており、
    　前記１つ以上の第１の貫通孔および前記１つ以上の第２の貫通孔の内部には、それぞれ前記封止部材の一部が配置されている、請求項１または請求項２に記載のパワー半導体モジュール。     One or more first through holes are formed in the first lead terminal,
    One or more second through holes are formed in the second lead terminal,
    3. The part of the sealing member is disposed inside the one or more first through holes and the one or more second through holes, respectively. Power semiconductor module.
  4. 　前記１つ以上の第１の貫通孔および前記１つ以上の第２の貫通孔は、それぞれ複数の貫通孔を含む、請求項３に記載のパワー半導体モジュール。 The power semiconductor module according to claim 3, wherein the one or more first through holes and the one or more second through holes each include a plurality of through holes.
  5. 　前記第１のリード端子および前記第２のリード端子は、それぞれ前記封止部材における第１の表面から外側に突出した突出部を含み、
    　前記１つ以上の第１の貫通孔は、前記第１のチップコンデンサから見て前記第１のリード端子の前記突出部側に位置する第１の外側貫通孔を含み、
    　前記１つ以上の第２の貫通孔は、前記第１のチップコンデンサから見て前記第２のリード端子の前記突出部側に位置する第２の外側貫通孔を含み、
    　前記第１のチップコンデンサと前記第１の外側貫通孔との間の第１の距離は、前記第１のチップコンデンサと前記第２の外側貫通孔との間の第２の距離と同じである、請求項３または請求項４に記載のパワー半導体モジュール。     Each of the first lead terminal and the second lead terminal includes a protruding portion protruding outward from a first surface of the sealing member,
    The one or more first through holes include a first outer through hole located on the protruding portion side of the first lead terminal when viewed from the first chip capacitor.
    The one or more second through holes include a second outer through hole located on the protruding portion side of the second lead terminal as viewed from the first chip capacitor.
    The first distance between the first chip capacitor and the first outer through hole is the same as the second distance between the first chip capacitor and the second outer through hole. The power semiconductor module according to claim 3 or 4.
  6. 　前記第１の電子素子は、第１の整流用半導体チップである、請求項１から請求項５のいずれか１項に記載のパワー半導体モジュール。 The power semiconductor module according to any one of claims 1 to 5, wherein the first electronic element is a first rectifying semiconductor chip.
  7. 　前記第１の整流用半導体チップは、抵抗器を内蔵しており、
    　前記抵抗器を内蔵する前記第１の整流用半導体チップと、前記第１のチップコンデンサとは、ブートストラップ回路を構成している、請求項６に記載のパワー半導体モジュール。     The first rectifying semiconductor chip includes a resistor,
    The power semiconductor module according to claim 6, wherein the first rectifying semiconductor chip incorporating the resistor and the first chip capacitor constitute a bootstrap circuit.
  8. 　前記複数のリード端子は、前記第１のリード端子および前記第２のリード端子と離間されている第３のリード端子と、前記第３のリード端子から離間されている第４のリード端子とを含み、
    　第３の電極と第４の電極とを含む第２のチップコンデンサと、
    　前記パワー半導体チップ、前記第１および第２のチップコンデンサおよび前記第１の電子素子とは異なる第２の電子素子と、をさらに備え、
    　前記第２のチップコンデンサの前記第３の電極と前記第４の電極とは、第２の導電性接着部で、前記第３のリード端子と前記第４のリード端子とにそれぞれ接合されており、
    　前記第３のリード端子には前記第２の電子素子が搭載されており、
    　前記第１のチップコンデンサに対する前記第１の電子素子の相対的な配置は、前記第２のチップコンデンサに対する前記第２の電子素子の相対的な配置と同じである、請求項１または請求項２に記載のパワー半導体モジュール。     The plurality of lead terminals include a third lead terminal spaced from the first lead terminal and the second lead terminal, and a fourth lead terminal spaced from the third lead terminal. Including
    A second chip capacitor including a third electrode and a fourth electrode;
    A second electronic element different from the power semiconductor chip, the first and second chip capacitors, and the first electronic element;
    The third electrode and the fourth electrode of the second chip capacitor are joined to the third lead terminal and the fourth lead terminal by a second conductive adhesive portion, respectively. ,
    The second electronic element is mounted on the third lead terminal,
    3. The relative arrangement of the first electronic element with respect to the first chip capacitor is the same as the relative arrangement of the second electronic element with respect to the second chip capacitor. Power semiconductor module as described in 2.
  9. 　前記第１のリード端子には、１つ以上の第１の貫通孔が形成されており、
    　前記第２のリード端子には、１つ以上の第２の貫通孔が形成されており、
    　前記第３のリード端子には、１つ以上の第３の貫通孔が形成されており、
    　前記第４のリード端子には、１つ以上の第４の貫通孔が形成されており、
    　前記１つ以上の第１の貫通孔、前記１つ以上の第２の貫通孔、前記１つ以上の第３の貫通孔、および前記１つ以上の第４の貫通孔の内部には、それぞれ前記封止部材の一部が配置されている、請求項８に記載のパワー半導体モジュール。     One or more first through holes are formed in the first lead terminal,
    One or more second through holes are formed in the second lead terminal,
    The third lead terminal is formed with one or more third through holes,
    One or more fourth through holes are formed in the fourth lead terminal,
    Inside the one or more first through holes, the one or more second through holes, the one or more third through holes, and the one or more fourth through holes, The power semiconductor module according to claim 8, wherein a part of the sealing member is disposed.
  10. 　前記１つ以上の第１の貫通孔、前記１つ以上の第２の貫通孔、前記１つ以上の第３の貫通孔、および前記１つ以上の第４の貫通孔は、それぞれ複数の貫通孔を含む、請求項７に記載のパワー半導体モジュール。 The one or more first through holes, the one or more second through holes, the one or more third through holes, and the one or more fourth through holes each have a plurality of through holes. The power semiconductor module according to claim 7, comprising a hole.
  11. 　前記第１から第４のリード端子は、それぞれ前記封止部材における第１の表面から外側に突出した突出部を含み、
    　前記第１のチップコンデンサから見て前記第１のリード端子の前記突出部側に位置するとともに、前記封止部材により封止された前記第１のリード端子の一部分の形状は、前記第２のチップコンデンサから見て前記第３のリード端子の前記突出部側に位置するとともに、前記封止部材により封止された前記第３のリード端子の一部分の形状と同じであり、
    　前記第１のチップコンデンサから見て前記第２のリード端子の前記突出部側に位置するとともに、前記封止部材により封止された前記第２のリード端子の一部分の形状は、前記第２のチップコンデンサから見て前記第４のリード端子の前記突出部側に位置するとともに、前記封止部材により封止された前記第４のリード端子の一部分の形状と同じである、請求項８から請求項１０のいずれか１項に記載のパワー半導体モジュール。     Each of the first to fourth lead terminals includes a protruding portion protruding outward from the first surface of the sealing member,
    A portion of the first lead terminal that is located on the protruding portion side of the first lead terminal as viewed from the first chip capacitor and is sealed by the sealing member has the second shape. It is located on the protruding portion side of the third lead terminal as viewed from the chip capacitor, and has the same shape as a part of the third lead terminal sealed by the sealing member,
    A portion of the second lead terminal that is located on the protruding portion side of the second lead terminal as viewed from the first chip capacitor and is sealed by the sealing member is 9. The device according to claim 8, wherein the fourth lead terminal is located on the protruding portion side of the fourth capacitor as viewed from the chip capacitor and has the same shape as a part of the fourth lead terminal sealed by the sealing member. Item 11. The power semiconductor module according to any one of Items 10.
  12. 　前記第２の電子素子は、第２の整流用半導体チップである、請求項８から請求項１１のいずれか１項に記載のパワー半導体モジュール。 The power semiconductor module according to any one of claims 8 to 11, wherein the second electronic element is a second rectifying semiconductor chip.
  13. 　前記第２の整流用半導体チップは、抵抗器を内蔵しており、
    　前記抵抗器を内蔵する前記第２の整流用半導体チップと、前記第２のチップコンデンサとは、ブートストラップ回路を構成している、請求項１２に記載のパワー半導体モジュール。     The second rectifying semiconductor chip includes a resistor,
    The power semiconductor module according to claim 12, wherein the second rectifying semiconductor chip incorporating the resistor and the second chip capacitor constitute a bootstrap circuit.
  14. 　前記複数のリード端子は、前記第１から第４のリード端子と離間されている第５のリード端子と、前記第５のリード端子から離間されている第６のリード端子とを含み、
    　第５の電極と第６の電極とを含む第３のチップコンデンサと、
    　前記パワー半導体チップ、前記第１から第３のチップコンデンサ、および前記第１および第２の電子素子とは異なる第３の電子素子と、をさらに備え、
    　前記第３のチップコンデンサの前記第５の電極と前記第６の電極とは、第３の導電性接着部で、前記第５のリード端子と前記第６のリード端子とにそれぞれ接合されており、
    　前記第５のリード端子には前記第３の電子素子が搭載されており、
    　前記第１から第３のチップコンデンサは、第１の方向に沿って配置されており、
    　前記第１から第３のチップコンデンサの前記第１の方向における配置ピッチは一定である、請求項８から請求項１１のいずれか１項に記載のパワー半導体モジュール。     The plurality of lead terminals include a fifth lead terminal spaced from the first to fourth lead terminals, and a sixth lead terminal spaced from the fifth lead terminal,
    A third chip capacitor including a fifth electrode and a sixth electrode;
    The power semiconductor chip, the first to third chip capacitors, and a third electronic element different from the first and second electronic elements, and
    The fifth electrode and the sixth electrode of the third chip capacitor are joined to the fifth lead terminal and the sixth lead terminal by a third conductive adhesive portion, respectively. ,
    The third electronic element is mounted on the fifth lead terminal,
    The first to third chip capacitors are arranged along a first direction;
    The power semiconductor module according to any one of claims 8 to 11, wherein an arrangement pitch of the first to third chip capacitors in the first direction is constant.
  15. 　前記第３の電子素子は、第３の整流用半導体チップである、請求項１４に記載のパワー半導体モジュール。 The power semiconductor module according to claim 14, wherein the third electronic element is a third rectifying semiconductor chip.
  16. 　前記第３の整流用半導体チップは、抵抗器を内蔵しており、
    　前記抵抗器を内蔵する前記第３の整流用半導体チップと、前記第３のチップコンデンサとは、ブートストラップ回路を構成している、請求項１５に記載のパワー半導体モジュール。     The third rectifying semiconductor chip includes a resistor,
    The power semiconductor module according to claim 15, wherein the third rectifying semiconductor chip incorporating the resistor and the third chip capacitor constitute a bootstrap circuit.
  17. 　前記第１のリード端子には、第１の貫通孔が形成されており、
    　前記第１のリード端子の中央から見て、前記第１の貫通孔と前記第１の電子素子とは互いに反対側の領域に配置されている、請求項１または請求項２に記載のパワー半導体モジュール。     A first through hole is formed in the first lead terminal,
    3. The power semiconductor according to claim 1, wherein the first through hole and the first electronic element are disposed in regions opposite to each other when viewed from the center of the first lead terminal. 4. module.
  18. 　第１のリード端子を含む複数のリード端子と、
    　パワー半導体チップと、
    　前記パワー半導体チップとは異なる第１の電子素子と、
    　前記パワー半導体チップと前記第１の電子素子とを封止する封止部材とを備え、
    　前記パワー半導体チップは前記複数のリード端子の少なくとも１つに接合されており、
    　前記第１のリード端子には前記第１の電子素子が搭載され、
    　前記第１のリード端子には、第１の貫通孔が形成されており、
    　前記第１のリード端子の中央から見て、前記第１の貫通孔と前記第１の電子素子とは互いに反対側の領域に配置されている、パワー半導体モジュール。     A plurality of lead terminals including a first lead terminal;
    A power semiconductor chip;
    A first electronic element different from the power semiconductor chip;
    A sealing member for sealing the power semiconductor chip and the first electronic element;
    The power semiconductor chip is bonded to at least one of the plurality of lead terminals;
    The first electronic element is mounted on the first lead terminal,
    A first through hole is formed in the first lead terminal,
    The power semiconductor module, wherein the first through hole and the first electronic element are disposed in regions opposite to each other when viewed from the center of the first lead terminal.
  19. 　前記第１のリード端子は、前記中央から見て前記第１の貫通孔と反対側の領域に位置し、導電ワイヤが接続される内側端子部を含み、
    　前記第１のリード端子において、前記中央から見て前記内側端子部が位置する側に凹部が形成されている、請求項１７または請求項１８に記載のパワー半導体モジュール。     The first lead terminal is located in a region opposite to the first through hole when viewed from the center, and includes an inner terminal portion to which a conductive wire is connected,
    The power semiconductor module according to claim 17 or 18, wherein in the first lead terminal, a recess is formed on a side where the inner terminal portion is located when viewed from the center.
  20. 　請求項１から請求項１９のいずれか１項に記載のパワー半導体モジュールを有し、入力される電力を変換して出力する主変換回路と、
    　前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と、
    　を備えた電力変換装置。     A main conversion circuit that has the power semiconductor module according to any one of claims 1 to 19 and that converts and outputs input power;
    A control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit;
    The power converter provided with.
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