WO2019214266A1 - Dispositif et procédé de calcul d'un code crc - Google Patents

Dispositif et procédé de calcul d'un code crc Download PDF

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WO2019214266A1
WO2019214266A1 PCT/CN2018/125888 CN2018125888W WO2019214266A1 WO 2019214266 A1 WO2019214266 A1 WO 2019214266A1 CN 2018125888 W CN2018125888 W CN 2018125888W WO 2019214266 A1 WO2019214266 A1 WO 2019214266A1
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sequence
polynomial
encoded
crc
calculating
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PCT/CN2018/125888
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English (en)
Chinese (zh)
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林宪正
张进毅
王工艺
沈建强
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华为技术有限公司
中国科学技术大学
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Publication of WO2019214266A1 publication Critical patent/WO2019214266A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the present application relates to the field of information technology and, more particularly, to a method and apparatus for calculating CRC encoding.
  • Cyclic Redundancy Check (CRC) coding is a cyclic code.
  • the CRC coding in the storage system usually uses a primitive polynomial based on the Galois field GF(2) to design a CRC coding scheme. .
  • L-bit information sequence (information value is 0 or 1), a L-1 , a L-2 ,..., a 0 , where the information sequence can be data to be processed, such as to be stored or The transmitted data, the L-bit information sequence can be represented as a polynomial:
  • L-1 is the Most Significant Bit (MSB) of the information sequence
  • a 0 is the Least Significant Bit (LSB) of the information sequence
  • x ⁇ (L-1) is the L- of X. 1 power or X L-1 power.
  • G(x) g m x ⁇ m+g m-1 x ⁇ (m-1)+g m-2 x ⁇ (m-2)+...+g 0
  • CRC(C(x)) C(x)*x ⁇ m mod G(x)
  • the CRC code represents the remainder after C(x)*x ⁇ m divided by another fixed number G(x), where "*" denotes multiplication.
  • the storage system in order to perform error detection on valid data, the storage system CRC-encodes the data, so that after the data is stored or transmitted, the storage system can quickly perform data consistency check, so the CRC code is A must-have feature in the storage system.
  • the present application provides a method for calculating CRC coding, which can reduce the complexity of calculating CRC coding and improve the efficiency and performance of CRC coding.
  • a method for calculating a CRC code comprising: obtaining a first sequence to be encoded; encoding the first sequence to be encoded using at least one polynomial to generate a second sequence; using a primitive polynomial pair The second sequence is encoded to generate a check sequence for the first sequence, each of the at least one polynomial being a multiple of the primitive polynomial, and the number of terms of each polynomial of the at least one polynomial Less than the number of terms of the primitive polynomial.
  • the at least one polynomial includes a first polynomial, and the first polynomial Q 1 (x) satisfies:
  • x a is an adjustment coefficient
  • a is determined according to the capacity of the register, and a is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the first sequence of length 4096 when calculating its CRC encoding, it may first be encoded using the polynomial Q 1 (x) of the primitive polynomial to obtain a second sequence (eg, The length of the second sequence is 394 or 422), and the second sequence is encoded using a primitive polynomial, and finally the CRC code of the first sequence is obtained.
  • a second sequence eg, The length of the second sequence is 394 or 422
  • the second sequence is encoded using a primitive polynomial
  • the CRC code of the first sequence is obtained.
  • the at least one polynomial includes a second polynomial, and the second polynomial Q 2 (x) satisfies:
  • x b is an adjustment coefficient
  • b is determined according to the capacity of the register
  • b is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the first sequence of length 4194304 when calculating its CRC code, it may first encode the original polynomial by using the multiplet Q 2 (x) to obtain the second sequence, and then The second sequence is encoded by using a primitive polynomial, and finally the CRC encoding of the first sequence is obtained, thereby reducing the number of cyclic shift operations and exclusive OR operations when calculating the first sequence, and improving the efficiency and performance of the CRC encoding.
  • the multiple of the primitive polynomial (eg, Q 1 (x) or Q 2 (x)) is adjusted by an adjustment factor (eg, adjusted such that the first sequence is divided according to the ploidy of the primitive polynomial
  • an adjustment factor eg, adjusted such that the first sequence is divided according to the ploidy of the primitive polynomial
  • Each of the obtained data segments can occupy an integer number of registers, so that the hardware resources of the registers can be fully utilized when calculating the CRC encoding of the first sequence by using the multiple of the adjusted primitive polynomial.
  • the first sequence to be encoded is encoded using at least one polynomial
  • the second sequence is generated, including: encoding, by using the second polynomial, the first sequence to be encoded, generating a third sequence; encoding the third sequence using the first polynomial to generate the second sequence.
  • a doubling of the primitive polynomial may be used first (eg, Q 2 (x )) encoding the first sequence to obtain an intermediate sequence (eg, a third sequence), and encoding the third sequence using another multiple of the primitive polynomial (eg, Q 1 (x))
  • Another intermediate sequence for example, the second sequence
  • the CRC encoding of the first sequence is obtained, thereby reducing the cyclic shift operation and the difference when calculating the first sequence.
  • the number of OR operations increases the efficiency and performance of CRC encoding.
  • a primitive polynomial usually has a plurality of multiples of the primitive polynomial, and for the first sequence to be encoded, it is determined from a plurality of multiples of the primitive polynomial for calculating the first A sequence of CRC encoded octaves.
  • a octet for calculating the CRC encoding of the first sequence may be determined from a plurality of multiples of the primitive polynomial based on the length of the first sequence.
  • Q 1 (x) is determined from a plurality of multiples of the primitive polynomial as a ploid for calculating the CRC encoding of the first sequence.
  • the number of items of the valid term of the polynomial of the primitive polynomial is small, and/or the difference between the index of the highest term of the multiplet of the primitive polynomial and the index of the next highest term is larger.
  • apparatus for calculating a CRC code the apparatus for performing the method of any of the first aspect or the first aspect of the first aspect.
  • the apparatus may comprise means for performing the method of the first aspect or any of the possible implementations of the first aspect.
  • an apparatus for calculating a CRC code comprising an interface for storing instructions, the processor for executing the instructions stored by the memory, and to the memory Execution of the instructions stored in the processor causes the processor to perform the method of the first aspect or any of the possible implementations of the first aspect.
  • a chip comprising an interface for storing instructions, the processor for executing the instructions stored by the memory, and instructions stored in the memory Execution of the processor causes the processor to perform the method of the first aspect or any of the possible implementations of the first aspect.
  • a computer readable storage medium stores instructions that, when executed on a computer, cause the computer to perform any of the first aspect or the first aspect The method in the implementation.
  • a computer program product comprising instructions for causing a computer to perform the method of any of the first aspect or the first aspect of the first aspect when the computer program product is run on a computer.
  • FIG. 1 is a schematic diagram of a storage array architecture of an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a controller of a memory array in accordance with an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a distributed block storage system in accordance with an embodiment of the present application.
  • FIG. 4 is a schematic structural block diagram of a server of a distributed block storage system.
  • Figure 5 is a schematic diagram of a prior art CRC encoding.
  • FIG. 6 is a schematic flowchart of a method for calculating CRC coding provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of dividing a first sequence provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the principle of calculating CRC coding provided by an embodiment of the present application.
  • FIG. 9 is another schematic diagram of calculating a CRC code provided by an embodiment of the present application.
  • FIG. 10 is another schematic diagram of dividing a first sequence according to an embodiment of the present application.
  • FIG. 11 is another schematic diagram of calculating a CRC code provided by an embodiment of the present application.
  • FIG. 12 is a schematic block diagram of an apparatus for calculating a CRC code according to an embodiment of the present application.
  • FIG. 13 is another schematic block diagram of an apparatus for calculating a CRC code according to an embodiment of the present application.
  • the storage system in the embodiment of the present application may be a storage array (such as of series, V3 series).
  • the storage array includes a storage controller 101 and a plurality of hard disks, wherein the hard disks include a solid state disk (SSD), a mechanical hard disk, or a hybrid hard disk.
  • Mechanical hard drives such as HDD (Hard Disk Drive).
  • the controller 101 includes a central processing unit (CPU) 201, a memory 202 and an interface 203.
  • the memory 202 stores computer instructions.
  • the CPU 201 executes computer instructions in the memory 202 to manage and store the storage system. Access operation.
  • a Field Programmable Gate Array or other hardware may be used to perform all operations of the CPU 201 in the embodiment of the present application, or the FPGA or other hardware and the CPU 201 respectively use Part of the operation of the CPU 201 of the embodiment of the present application is performed.
  • the embodiment of the present application uniformly refers to a combination of the CPU 201 and the memory 202, and various implementations described above, and the processor communicates with the interface 203.
  • the interface 203 can be a Network Interface Card (NIC), a Host Bus Adaptor (HBA), an antenna, or the like.
  • the controller 101 is configured to acquire data, such as receiving data sent by the host or the client, and calculate a CRC code of the data by using a method for calculating CRC encoding provided by the embodiment of the present application.
  • the storage system of the embodiment of the present application may also be a distributed file storage system (such as of 9000 series), distributed block storage systems (eg of Series) and so on. Take of series.
  • the distributed block storage system includes a plurality of servers, such as a server 1, a server 2, a server 3, a server 4, a server 5, and a server 6, and the servers communicate with each other through InfiniBand or an Ethernet network.
  • the number of servers in the distributed block storage system may be increased according to actual requirements, which is not limited by the embodiment of the present application.
  • the server of the distributed block storage system includes the structure as shown in FIG. As shown in FIG. 4, each server in the distributed block storage system includes a central processing unit (CPU) 401, a memory 402, an interface 403, a hard disk 1, a hard disk 2, and a hard disk 3.
  • the computer 402 stores computer instructions.
  • the CPU 401 executes program instructions in the memory 402 to perform corresponding operations.
  • the interface 403 can be a hardware interface, such as a network interface card (NIC) or a host bus adapter (HBA), or a program interface module.
  • the hard disk contains a Solid State Disk (SSD), a mechanical hard disk, or a hybrid hard disk. Mechanical hard drives such as HDD (Hard Disk Drive).
  • a Field Programmable Gate Array or other hardware may also perform the above-mentioned corresponding operations instead of the CPU 401, or the FPGA or other hardware and the CPU 401 perform the above-mentioned corresponding operations together.
  • the embodiment of the present application collectively refers to the combination of the CPU 401 and the memory 402, the FPGA and other hardware or FPGA replacing the CPU 401 and other hardware replacing the CPU 401 and the CPU 401 as a processor.
  • the interface 403 can be a Network Interface Card (NIC), a Host Bus Adaptor (HBA), an antenna, or the like.
  • the processor of the server is configured to acquire data, such as receiving data sent by the host or the client, and calculate the CRC code of the data by using the method for calculating CRC encoding provided by the embodiment of the present application. .
  • the embodiment of the present application can be applied to a data transmission scenario.
  • data is used in the embodiments of the present application.
  • Calculated data CRC encoding method For example, a computer acquires data, such as data generated by an application on a computer, and calculates a CRC code of the data.
  • CLMUL carry-less multiplication
  • the present application proposes a method for calculating CRC coding, which uses the doubling of the original polynomial to encode the data to obtain an intermediate sequence, and uses the primitive polynomial to calculate the CRC code for the intermediate sequence.
  • the number of shift operations and XOR operations required for CRC encoding can be reduced, thereby reducing the complexity of calculating CRC encoding and improving the efficiency and performance of CRC encoding.
  • the CRC encoding of the K-bit sequence can be generated, and G(x) is called The generator polynomial of this CRC code.
  • the specific generation process of the N-bit check code is as follows: assuming that the data to be stored is called an information sequence, an information sequence can be represented by a polynomial C(X), and C(x) is shifted to the left by N bits (which can be expressed as C(x) *X ⁇ N), so that the right side of C(x) will be N bits, which is the location of the CRC encoding.
  • the embodiment of the present application is based on using C(x)*X ⁇ N and the generator polynomial G(x) to obtain a check code, that is, the remainder obtained by dividing C(x)*X ⁇ N by G(x) as the N-bit CRC code. .
  • a check code that is, the remainder obtained by dividing C(x)*X ⁇ N by G(x) as the N-bit CRC code.
  • any one of the data consisting of binary bit strings can be in one-to-one correspondence with a polynomial whose coefficients are only '0' and '1'.
  • the polynomial corresponding to the data 1010111 is X ⁇ 6+X ⁇ 4+X ⁇ 2+X+1, where X ⁇ 6 represents the 6th power of X or the 6th power of x, x is a pseudo variable, and the power index (also called index) is used to indicate the arrangement position between the people, and "+" means the exclusive OR.
  • the data corresponding to the polynomial X ⁇ 5+X ⁇ 3+X ⁇ 2+X+1 is 101111.
  • the original polynomial of CRC16 developed by the T10 Technical Committee is 0x18BB7, written as binary 0001 1000 1011 1011 0111, and the corresponding polynomial is X ⁇ 16+X ⁇ 15+X ⁇ 11+X ⁇ 9+X ⁇ 8+X ⁇ 7+ X ⁇ 5+X ⁇ 4+X ⁇ 2+X ⁇ 1+1.
  • the information sequence needs to be divided into data segments of size 16 bits, and the data segments divided by the information sequence are the first data segment and the second data segment from the highest bit (from left to right). ..., the Nth data segment. Where N is a natural number not less than 2.
  • the first data segment should be shifted left by 15 bits, left by 11 bits, left by 9 bits, left by 8 bits, left by 7 bits, left by 5 bits, left by 4 bits, left by 2 bits, left. Shift 1 bit, shift 0 bit to the left, XOR the data segment obtained by shifting the first data segment, and XOR the XOR result with the second data segment, and then 3
  • the data segment and the Nth data segment are reconstructed into a data sequence, and then the new data sequence is divided into 16 bits to obtain a new data segment, and then the above shift and XOR operations are performed until the last information sequence length is equal to 16 bits.
  • CRC(C(x)) (xdeg(G(x))C(x))(mod(G(x));
  • CRC(C(x)) represents a sequence of information CRC encoding of C(x);
  • G(x) represents the primitive polynomial, such as the primitive polynomial of CRC16 of T10 is X ⁇ 16+X ⁇ 15+X ⁇ 11+X ⁇ 9+X ⁇ 8+X ⁇ 7+ X ⁇ 5+X ⁇ 4+X ⁇ 2+X ⁇ 1+1;
  • deg(G(x)) represents the index of the highest term of the primitive polynomial, such as the index of the highest term of the primitive polynomial of CRC16 of T10 is 16 , that is, the highest-order index;
  • xdeg(G(x))C(x) represents an exponent bit that shifts the information sequence C(x) to the left of the highest term of the primitive polynomial, and mod denotes modulo.
  • the difference between the index of the effective highest term contained in Q(x) and the index of the effective second highest term is greater than 1, so that the number of cyclic shift operations can be reduced relative to G(x), and further, it can be selected to be effective.
  • Q(x) with a small number of items can further reduce the number of XOR operations, thereby greatly reducing the complexity of CRC coding, for example, selecting the least number of valid terms.
  • the valid term of the polynomial refers to an item having a coefficient of 1, for example, X ⁇ 16, X ⁇ 15, X ⁇ 11, X ⁇ 9, X ⁇ 8, X in the primitive polynomial of CRC16 such as T10.
  • the coefficients of ⁇ 7, X ⁇ 5, X ⁇ 4, X ⁇ 2, X ⁇ 1, and 1 are all 1, which are valid items.
  • FIG. 6 is a schematic flowchart of a method 600 for calculating CRC coding according to an embodiment of the present application.
  • the method 600 can be performed by the controller of Figures 1 and 2 or the processor of the servers of Figures 4 and 5.
  • the method includes at least the following steps.
  • the processor or processor of the server obtains the data to be encoded (eg, the first sequence to be encoded).
  • the processor of the controller or the server receives the first sequence to be encoded sent by the host or the client, and then calculates the CRC code of the first sequence to be encoded.
  • the acquired first sequence to be encoded is encoded using at least one polynomial to generate an intermediate sequence (eg, a second sequence), wherein the at least one polynomial is a multiple of the original polynomial.
  • an intermediate sequence eg, a second sequence
  • the first sequence to be encoded is represented by a polynomial C(x), at least one polynomial is denoted by Q(x), the primitive polynomial is denoted by G(x), and Q(x) is G(x)
  • the doubling, ie Q(x) G(x)T(x), T(x) denotes a polynomial for indicating that Q(x) is a multiple of G(x), ie, by C(x)
  • the second sequence generated in 601 is encoded using a primitive polynomial to generate a check sequence for the first sequence, wherein the number of terms of each polynomial in the at least one polynomial is less than the number of terms of the primitive polynomial .
  • the CRC encoding of the data to be encoded is calculated by at least one multiplication of the primitive polynomial to obtain an intermediate sequence (eg, second Sequence), and then calculating the CRC encoding of the intermediate sequence using the primitive polynomial, thereby avoiding the CRC encoding of the data to be encoded using only the primitive polynomial, since the number of cyclic shift operations and XOR operations is more The resulting computational complexity of CRC coding is high.
  • the following also describes several embodiments for calculating the CRC encoding of the data to be encoded by taking the primitive polynomial of the CRC 16 whose original polynomial is T10 as an example.
  • the at least one polynomial includes a first polynomial, the first polynomial Q 1 (x) satisfying:
  • x ⁇ a is an adjustment coefficient
  • a is determined according to the capacity of the register, and a is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the length of the first sequence is 4096
  • the multiple of the primitive polynomial (eg, the first polynomial) Q 1 (x) satisfies:
  • the method mainly includes the following steps:
  • the first sequence after the "0" is divided into a plurality of data segments. As shown in FIG. 7, the divided data segments start from the highest bit (from left to right): the first data segment and the second data segment respectively.
  • the 53-bit data includes the complemented 16 bits having a value of 0;
  • the first data segment is shifted left by 31 bits and left by 0 bits
  • the data segment obtained by shifting the first data segment to the left by 31 bits is XORed with the data segment obtained by shifting the left bit by 0 bits.
  • the data segment A obtained by the exclusive OR operation is XORed with the second data segment
  • the data segment B and the third data segment to the twelfth data segment obtained by performing an exclusive OR operation on the data segment A and the second data segment are performed.
  • the second sequence may have a length of 394;
  • x a in the formula (2) is an adjustment coefficient.
  • the original value can be used by the adjustment coefficient x a according to the capacity of the register for storing the first sequence.
  • the polynomial is adjusted.
  • the adjustment coefficient x 15 is used to Equation (3) is adjusted, and the adjusted multiplicity of the primitive polynomial satisfies:
  • Adjusting the multiple of the primitive polynomial by adjusting the coefficient for example, adjusting so that each data segment obtained by dividing the first sequence according to the multiple of the primitive polynomial can occupy an integer number of registers, so that the use
  • the multiplier of the adjusted primitive polynomial can fully utilize the hardware resources of the register when calculating the CRC encoding of the first sequence.
  • Embodiment 2 differs from Embodiment 1 in steps c to e.
  • step c is:
  • the first data segment is shifted left by 31 bits and left by 0 bits, and the data segment obtained by shifting the first data segment to the left by 31 bits is XORed with the data segment obtained by shifting the left bit by 0 bits.
  • the data segment obtained by the exclusive OR operation is divided into two parts, namely data segment C and data segment D, data segment C contains the upper 31 bits, and data segment D contains 369 bits beyond the upper 31 bits.
  • the data segment C is shifted to the left by 31 bits and shifted to the left by 0 bits, and the data segment obtained by shifting the left 31 bits is XORed with the data segment obtained by shifting the left bit by 0, and the data segment E obtained by the exclusive OR operation is
  • the data segment F obtained by performing the exclusive OR operation on the data segment D and the second data segment is XORed, and the data segment G obtained by the exclusive OR operation and the third data segment to the twelfth data segment are reconstructed into a new data sequence.
  • step d is:
  • the step b in the first embodiment and the step c in the second embodiment are repeated for the reconstructed data sequence to generate a second sequence.
  • step e is:
  • the CRC encoding is calculated for the second sequence of length 422 using the primitive polynomial of CRC16 of T10, and finally the CRC encoding for the first sequence is obtained.
  • the at least one polynomial includes a second polynomial, the second polynomial Q 2 (x) satisfying:
  • x b is an adjustment coefficient
  • b is determined according to the capacity of the register
  • b is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the length of the first sequence is 4194304, and the multiple of the primitive polynomial (eg, the first polynomial) Q 1 (x) satisfies:
  • the method mainly includes the following steps:
  • the first sequence after the "0" is divided into a plurality of data segments, as shown in FIG. 10, the divided data segments start from the highest bit (from left to right): the first data segment, the second data segment Data segment, third data segment... 64th data segment, 65th data segment, wherein each data segment from the first data segment to the 64th data segment contains 65536 bits of data, and the 65th data segment contains 80 bits of data.
  • the 80-bit data includes the complemented 16 bits having a value of 0;
  • the XOR operation is performed on the first data segment and the second data segment, and the data segment H obtained by the exclusive OR operation and the 65th data segment of the third data segment value are reconstructed into a new data sequence;
  • x b in the equation (5) is an adjustment coefficient.
  • the original value may be used by the adjustment coefficient x b according to the capacity of the register for storing the first sequence.
  • the polynomial is adjusted.
  • the first sequence to be encoded is encoded by using at least one polynomial to generate a second sequence, including: using the second multiple to the first sequence to be encoded. Encoding is performed to generate a third sequence; the third sequence is encoded using the first polynomial to generate the second sequence.
  • two pairs of the primitive polynomial eg, the first polynomial and the second polynomial
  • the first sequence is encoded.
  • a data sequence of length 65615 is generated, and the length is further calculated using the first polynomial (formula 3).
  • the data sequence of 65615 is encoded to generate the second sequence, and finally the CRC encoding is calculated for the second sequence using the primitive polynomial of CRC16 of T10, and finally the CRC encoding for the first sequence is obtained.
  • the first sequence is encoded by using a multiple of the primitive polynomial, and the second sequence is generated as an example.
  • the present application is not limited thereto.
  • the first sequence can also be encoded using a multiple of three or more primitive polynomials to generate a second sequence.
  • the multiples of the primitive polynomials enumerated in Embodiments 1 to 3 are merely illustrative and are not intended to limit the application.
  • the multiple of the primitive polynomial used may be other than the equation (3) enumerated in Embodiment 1, and may be other forms of the primitive polynomial. Double type.
  • the present application also provides a method of determining a ploidy of a primitive polynomial, which is described in detail below.
  • j is an integer greater than or equal to 0, and j ⁇ i.
  • the value of each bit in the sequence of length n is initialized to 0, for example, the value of n can be 524288;
  • n For a sequence of length n, set the index of the index with the index number i and the index number j to 1 and the remaining bits to 0, where 1 ⁇ i ⁇ n-1,0 ⁇ j ⁇ i, for each value of i, j needs to traverse from 0 to i-1;
  • step b using the primitive polynomial (eg, the primitive polynomial of CRC16 of T10) to calculate the CRC encoding of the sequence of length n obtained in step b;
  • the primitive polynomial eg, the primitive polynomial of CRC16 of T10
  • step d if the CRC encoding result of the sequence of length n obtained in step c is 0, the index number i and the index number j in step b are the highest terms of the multiplier (formula 7) of the primitive polynomial, respectively.
  • the index of the index and the second highest item are the highest terms of the multiplier (formula 7) of the primitive polynomial, respectively.
  • the value of the index with the index number of 200 and the index number of 50 in the sequence is set to 1, and the value of the remaining bits is set to 0.
  • the sequence is calculated using the primitive polynomial
  • the result of the CRC encoding is 0, it is indicated that the polynomial corresponding to the sequence of length n is a multiple of the primitive polynomial, and the index number 200 and the index number 50 are respectively the index of the highest term of the doubling and the second highest.
  • the index of the term, that is, the multiple of the primitive polynomial satisfies:
  • a plurality of doublings of the primitive polynomial can be determined according to the above method, and for the first sequence to be encoded, it is required to determine from the multiples of the primitive polynomial for calculating the first sequence The CRC coded multiple.
  • a octade for calculating the CRC encoding of the first sequence may be determined from a plurality of multiples of the primitive polynomial based on the length of the first sequence.
  • Equation 3 is determined from a plurality of multiples of the primitive polynomial as a ploid for calculating the CRC encoding of the first sequence.
  • the number of terms of the effective term of the polynomial of the primitive polynomial is as small as possible, and/or the difference between the index of the highest term of the multiple of the primitive polynomial and the index of the next highest term is as large as possible.
  • Equation 7 the above formula only satisfies Equation 7 as an example of the original polynomial.
  • the present application is not limited thereto.
  • the multiple of the original polynomial can also satisfy:
  • k is an integer greater than or equal to 0, and k ⁇ j ⁇ i.
  • the method for calculating the CRC coding in the present application is described by using the primitive polynomial of the CRC 16 whose original polynomial is T10 as an example.
  • the method for calculating the CRC coding provided by the present application is not limited thereto.
  • the method for calculating CRC coding provided by the present application can also be applied to a method of calculating CRC coding of a sequence to be coded using a primitive polynomial based on other standards.
  • the method for calculating the CRC code provided by the embodiment of the present application is described above with reference to FIG. 6 to FIG. 11.
  • the apparatus for calculating the CRC code provided by the embodiment of the present application is described below with reference to FIG. 12 to FIG.
  • FIG. 12 is a schematic block diagram of an apparatus 700 for calculating CRC coding according to an embodiment of the present disclosure.
  • the apparatus for calculating CRC coding includes an obtaining module 701 and a processing module 702.
  • the obtaining module 701 is configured to obtain a first sequence to be encoded.
  • the processing module 702 is configured to encode the first sequence to be encoded using at least one polynomial to generate a second sequence.
  • the processing module 702 is further configured to: encode the second sequence by using a primitive polynomial to generate a check sequence for the first sequence, where each polynomial of the at least one multiple is a multiple of the primitive polynomial, the at least The number of terms for each polynomial in a polynomial is less than the number of terms of the primitive polynomial.
  • the at least one polynomial comprises a first polynomial, the first polynomial Q 1 (x) satisfying:
  • x a is an adjustment coefficient
  • a is determined according to the capacity of the register, and a is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the at least one polynomial comprises a second polynomial, the second polynomial Q 2 (x) satisfying:
  • x b is an adjustment coefficient
  • b is determined according to the capacity of the register
  • b is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the processing module 702 is further configured to: encode the first sequence to be encoded by using the second polynomial to generate a third sequence, and encode the third sequence by using the first polynomial, This second sequence is generated.
  • processing module 702 is further configured to determine the at least one polynomial according to the length of the first sequence.
  • the first sequence has a length of 4096.
  • the second sequence has a length of 394 or 422.
  • the length of the first sequence is 4194304.
  • FIG. 13 is a schematic block diagram of an apparatus 800 for calculating CRC coding according to an embodiment of the present disclosure.
  • the apparatus for calculating CRC coding includes an interface 801, a memory 802, and a processor 803.
  • the interface 801 is configured to obtain a first sequence to be encoded.
  • the memory 802 is configured to store a program.
  • a processor 803 configured to execute a program stored in the memory, when the program in the memory is executed, the processor 803 is configured to acquire, by using the interface 801, a first sequence to be encoded; using at least one polynomial to treat the Encoding the first sequence to generate a second sequence; encoding the second sequence using a primitive polynomial to generate a check sequence for the first sequence, each polynomial of the at least one polynomial being the primitive polynomial In the doubling, the number of terms of each polynomial in the at least one polynomial is less than the number of terms of the primitive polynomial.
  • the at least one polynomial comprises a first polynomial, the first polynomial Q 1 (x) satisfying:
  • x a is an adjustment coefficient
  • a is determined according to the capacity of the register, and a is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the at least one polynomial comprises a second polynomial, the second polynomial Q 2 (x) satisfying:
  • x b is an adjustment coefficient
  • b is determined according to the capacity of the register
  • b is an integer greater than or equal to 0, and the register is used to store the first sequence.
  • the processor 803 is further configured to: encode the first sequence to be encoded by using the second polynomial to generate a third sequence; and encode the third sequence by using the first polynomial, This second sequence is generated.
  • the processor 803 is further configured to determine the at least one polynomial according to the length of the first sequence.
  • the first sequence has a length of 4096.
  • the second sequence has a length of 394 or 422.
  • the length of the first sequence is 4194304.
  • the present application provides a chip including an interface, a memory, and a processor for storing instructions for executing instructions stored in the memory, and performing execution of instructions stored in the memory such that the processor The method for calculating CRC coding in the embodiment of the present application is performed.
  • the present application provides a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the method of calculating CRC encoding in embodiments of the present application.
  • the present application provides a computer program product comprising instructions for causing a computer to perform the method of calculating CRC encoding in embodiments of the present application when the computer program product is run on a computer.
  • processors mentioned in the embodiment of the present application may be a central processing unit (CPU), and may also be other general-purpose processors, digital signal processors (DSPs), and application specific integrated circuits ( Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory referred to in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM). SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Connection Dynamic Random Access Memory (Synchlink DRAM, SLDRAM) ) and direct memory bus random access memory (DR RAM).
  • processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.
  • memories described herein are intended to comprise, without being limited to, these and any other suitable types of memory.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

La présente invention concerne un procédé de calcul d'un code CRC consistant : à acquérir une première séquence à coder ; à utiliser au moins un polynôme pour coder ladite première séquence, pour générer une seconde séquence ; à utiliser un polynôme primitif pour coder la seconde séquence, pour générer une séquence de vérification pour ladite première séquence, chacun desdits polynômes étant un multiple du polynôme primitif, le nombre de termes de chaque polynôme dudit polynôme étant inférieur au nombre de termes du polynôme primitif. Le procédé peut réduire la complexité de calcul d'un code CRC, et améliorer l'efficacité et la performance du codage CRC.
PCT/CN2018/125888 2018-05-08 2018-12-29 Dispositif et procédé de calcul d'un code crc WO2019214266A1 (fr)

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CN101442313A (zh) * 2007-11-20 2009-05-27 华为技术有限公司 编解码方法以及编码器、解码器、乘积项装置
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