WO2019200835A1 - Cmos型ltps tft基板的制作方法 - Google Patents

Cmos型ltps tft基板的制作方法 Download PDF

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Publication number
WO2019200835A1
WO2019200835A1 PCT/CN2018/106332 CN2018106332W WO2019200835A1 WO 2019200835 A1 WO2019200835 A1 WO 2019200835A1 CN 2018106332 W CN2018106332 W CN 2018106332W WO 2019200835 A1 WO2019200835 A1 WO 2019200835A1
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active layer
polysilicon active
layer
gate
photoresist pattern
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French (fr)
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李立胜
刘广辉
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/309,446 priority Critical patent/US10957721B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a CMOS type LTPS TFT substrate.
  • flat panel display devices such as liquid crystal display (LCD) and active matrix organic light-emitting diode (AMOLED) displays have thin body and high image quality. Power saving, no radiation and many other advantages have been widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens.
  • LCD liquid crystal display
  • AMOLED active matrix organic light-emitting diode
  • Thin Film Transistor (TFT) Array (Array) substrate is the main component of current LCD devices and AMOLED devices. It is directly related to the development direction of high-performance flat panel display devices. It is used to provide driving circuits to displays.
  • the source and drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel electrode, thereby controlling the corresponding pixel region. display.
  • the structure of the thin film transistor on the array substrate further includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, and an insulating protective layer which are stacked on the substrate in this order from bottom to top.
  • LTPS Low Temperature Poly-Silicon
  • A-Si amorphous silicon
  • MOS Metal Oxide Semiconductor
  • LTPS LTPS
  • NMOS Negative Channel Metal Oxide Semiconductor
  • P-type Metal Oxide Semiconductor P-type Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • the main difference between the NMOS transistor and the PMOS transistor is that the source and drain contact regions are respectively heavily doped by N-type ions (phosphorus P+, 1 ⁇ 10) 14 to 1 ⁇ 10 15 ions/cm 2 ) and P-type ions are heavily doped (boron ion B+, 1 ⁇ 10 14 to 1 ⁇ 10 15 ions/cm 2 ), and the NMOS transistor and the PMOS transistor together constitute a CMOS transistor.
  • the hot carrier effect is an important failure mechanism of the device. As the size of the MOS device shrinks, the hot carrier injection effect of the device becomes more and more serious.
  • the existing LTPS NMOS fabrication process usually adopts light doping.
  • a Lightly Doped Drain (LDD) method is to place a low-doped region in the vicinity of the source and drain electrodes in a poly-Poly (Poly-Si) channel, and the low-doped region is also subjected to partial voltage division.
  • LDD processes are MASK (mask) LDD technology and Re-etch (repeated etching) LDD technology, in which MASK LDD technology uses N-type ion heavily doping of polysilicon active layer through photoresist pattern to form source and drain. a contact region, which is then lightly doped with an N-type ion by a gate self-alignment technique to form an LDD region; the Re-etch LDD technique is patterned to form a polysilicon active layer as compared with the MASK LDD technique described above.
  • the polysilicon active layer is not heavily doped by the photoresist pattern, but the gate is formed by two etchings, and the heavily doped source-drain contact region is defined by the first etched metal pattern, and then The second etching results in a gate electrode, and the polysilicon active layer is lightly doped with N-type ions by a gate self-alignment technique to form an LDD region.
  • the main advantage of Re-etch LDD technology is to reduce one lithography process, thereby reducing the production cost of a mask and reducing the processing time of LTPS TFT substrate and increasing production capacity.
  • the number of MASK used is usually 11 to 14 times.
  • Re-etch LDD technology is usually used instead of MASK LDD technology, which usually includes the following steps.
  • Step S10 as shown in FIG. 1, a buffer layer 200 is formed on the substrate 100, and a first polysilicon active layer 310 corresponding to the NMOS and a second polysilicon active layer 320 corresponding to the PMOS are formed in the buffer layer 200.
  • a gate insulating layer 400 covering the first polysilicon active layer 310 and the second polysilicon active layer 320 is formed on the buffer layer 200, and a metal layer 500 is deposited on the gate insulating layer 400,
  • a photoresist is coated on the metal layer 500, and is formed by exposure and development processing through a photomask to form a first photoresist pattern 910 corresponding to a central portion of the first polysilicon active layer 310 and corresponding to a second polysilicon active layer.
  • Step S20 as shown in FIG. 2, the first photoresist pattern 910 and the second photoresist pattern 920 are used as shielding layers, and the metal layer 500 is first etched to be respectively formed in the first polysilicon active region.
  • a first quasi-gate 510' and a second quasi-gate 520' over the layer 310 and over the second polysilicon active layer 320.
  • Step S30 as shown in FIG. 3, the first quasi-gate 510' is used as a shielding layer, and the portion of the first polysilicon active layer 310 that is not covered by the first quasi-gate 510' is N.
  • the type ions are heavily doped (P+, 1 ⁇ 10 14 to 1 ⁇ 10 15 ions/cm 2 ) to form a first source/drain contact region 3101 across the first polysilicon active layer 310.
  • Step S40 as shown in FIG. 4, the metal layer 500 is etched a second time, so that both sides of the first quasi-gate 510' and the second quasi-gate 520' are laterally etched and the width is reduced to form The first gate 510 and the second gate 520 strip and remove the first photoresist pattern 910 and the second photoresist pattern 920.
  • Step S50 as shown in FIG. 5, using the first gate 510 as a shielding layer, performing N-type ion light on a portion of the first polysilicon active layer 310 that is not covered by the first gate 510 Doping (P+, 1 ⁇ 10 12 ⁇ 1 ⁇ 10 13 ions/cm 2 ), obtaining a first channel region 3102 corresponding to the first gate 510 in the middle of the first polysilicon active layer 310 and the source and drain A first LDD region 3103 between the pole contact region 3101 and the first channel region 3102.
  • Step S60 as shown in FIG. 6, a photoresist protective layer 950 covering the first polysilicon active layer 310 is formed on the gate insulating layer 400 and the first gate 510, and the second gate 520 is formed.
  • a portion of the second polysilicon active layer 320 that is not covered by the second gate 520 is heavily doped (B+, 1 ⁇ 10 14 to 1 ⁇ 10 15 ions/cm 2 ) to form a portion of the second polysilicon active layer 320.
  • the second source and drain contact regions 3201 and the second portion of the second polysilicon active layer 320 at the two ends of the second polysilicon active layer 320 are located in the second channel region 3202 below the second gate 520.
  • N-type ion heavily doping is performed on the first polysilicon active layer 310 corresponding to the NMOS.
  • the second polysilicon active layer 320 corresponding to the PMOS is also heavily doped with N-type ions, and subsequently to compensate for the phosphorus ions doped in the second polysilicon active layer 320, so that the second polysilicon has
  • the source layer 320 is converted from an N-type to a P-type semiconductor.
  • a higher dose of boron ions needs to be incorporated, and the process has the following effects on the PMOS:
  • An object of the present invention is to provide a method for fabricating a CMOS type LTPS TFT substrate, wherein a second photoresist pattern is formed over a region of the second polysilicon active layer where P-type ion heavy doping is required by a semi-transmissive mask.
  • the second photoresist segment acts as a protective layer, and when the first polysilicon active layer is heavily doped with N-type ions, the second source of the N-type ion implanted in the second polysilicon active layer can be effectively blocked. Drain contact area.
  • the present invention first provides a method for fabricating a CMOS type LTPS TFT substrate, comprising the following steps:
  • Step S1 providing a substrate, forming a buffer layer on the substrate, forming a first polysilicon active layer and a second polysilicon active layer spaced apart from each other on the buffer layer, forming on the buffer layer Covering a gate insulating layer of the first polysilicon active layer and the second polysilicon active layer, depositing a metal layer on the gate insulating layer, applying a photoresist on the metal layer, and passing through The semi-transmissive reticle exposes and develops the photoresist to form a first photoresist pattern corresponding to a portion above the first polysilicon active layer and completely covers the second poly layer over the second polysilicon active layer a second photoresist pattern of the silicon active layer; the second photoresist pattern has a first photoresist segment in the middle and a second photoresist connected to both sides of the first photoresist segment and having a thickness smaller than that of the first photoresist segment segment;
  • Step S2 using the first photoresist pattern and the second photoresist pattern as a shielding layer, performing the first etching on the metal layer to form a first quasi-gate located above the middle of the first polysilicon active layer and a second quasi-gate that completely covers the second polysilicon active layer over the second polysilicon active layer;
  • Step S3 using the first photoresist pattern as a shielding layer, performing N-type ion heavy doping on a portion of the first polysilicon active layer that is not covered by the first quasi-gate to form a first polycrystal. a first source-drain contact region at both ends of the silicon active layer;
  • Step S4 performing ashing treatment on the first photoresist pattern and the second photoresist pattern, and thinning the thicknesses of the first photoresist pattern and the second photoresist pattern such that the first photoresist pattern and the second light
  • the thickness of the first photoresist segment of the resist pattern is reduced, and the second photoresist segment of the second photoresist pattern is removed to expose both ends of the second polysilicon active layer;
  • Step S5 performing a second etching on the metal layer, so that both sides of the first quasi-gate are laterally etched and the width is reduced, and the first gate is obtained by the first quasi-gate, and the second quasi-gate is obtained.
  • Step S6 performing light-doping of the first polysilicon active layer with N-type ions by using the first gate as a shielding layer, and obtaining a corresponding portion of the first polysilicon active layer at the first gate a first channel region below the pole and a first LDD region between the first source and drain contact regions and the first channel region;
  • Step S7 forming a photoresist protection layer covering the first polysilicon active layer on the gate insulating layer and the first gate, using the second gate as a shielding layer, and the second polysilicon P-type ions are heavily doped at portions of the active layer that are not covered by the second gate, forming a second source-drain contact region at both ends of the second polysilicon active layer and a second portion of the second polysilicon active layer Corresponding to the second channel region under the second gate, the photoresist protection layer is removed.
  • the semi-transmissive reticle used in the step S1 has an opaque region, a semi-transmissive region and a remaining fully transparent region, wherein the opaque region is used to form the first photoresist pattern and the second light. a first photoresist segment of the resist pattern, the semi-transmissive region being used to form a second photoresist segment of the second photoresist pattern.
  • the semi-transmissive reticle used in the step S1 is a gray scale reticle or a halftone reticle.
  • the first photoresist pattern and the second photoresist pattern are subjected to ashing treatment by oxygen.
  • the metal layer is etched a second time by dry etching, and the etching gas for performing the second etching on the metal layer contains oxygen and chlorine.
  • the metal layer is first etched by dry etching, and the etching gas for performing the first etching on the metal layer includes sulfur hexafluoride, pentafluoroethane and carbon tetrafluoride. One or more.
  • the ions doped in the N-type ion heavy doping of the first polysilicon active layer are phosphorus ions, and the doping ion concentration is 1 ⁇ 10 14 -1 ⁇ 10 15 ions/cm 2 .
  • the ions doped when the first polysilicon active layer is lightly doped with N-type ions are phosphorus ions, and the doping ion concentration is 1 ⁇ 10 12 -1 ⁇ 10 13 ions/cm 2 .
  • the ions doped in the P-type ion heavy doping of the second polysilicon active layer are boron ions, and the doping ion concentration is 1 ⁇ 10 14 -1 ⁇ 10 15 ions/cm 2 .
  • the step S1 further includes forming, on the substrate, first and second light blocking blocks respectively under the first polysilicon active layer and below the second polysilicon active layer before forming the buffer layer. Shading block.
  • a method for fabricating a CMOS type LTPS TFT substrate of the present invention when a first polysilicon active layer corresponding to an NMOS and a second polysilicon active layer corresponding to a PMOS are formed, a semi-transmissive light is passed through Shielding a second photoresist layer forming a second photoresist pattern over a region where the second polysilicon active layer is subjected to P-type ion heavy doping as a protective layer, and performing N-type on the first polysilicon active layer
  • the ions are heavily doped, the N-type ions can be effectively blocked from being implanted into the second source-drain contact region of the second polysilicon active layer, and the second polysilicon is subsequently activated compared to the prior art.
  • the layer is heavily doped with P-type ions to form the second source-drain contact region, there is no need to additionally compensate the P-type ions, which reduces the capacity loss of the P-type ion heavy doping process, and the N-type ion heavily doping process cannot be used for the PMOS transistor.
  • the influence is increased, the convergence of the electrical properties of the PMOS transistor is improved, and the number of ion implantations to the active layer of the second polysilicon is reduced, the destruction of the lattice structure of the thin film by ion implantation is reduced, and the device is improved. stability.
  • FIG. 1 is a schematic diagram of a step S10 of fabricating a CMOS type LTPS TFT substrate using the existing Re-etch LDD technology
  • FIG. 2 is a schematic diagram of a step S20 of fabricating a CMOS type LTPS TFT substrate using the existing Re-etch LDD technology
  • FIG. 3 is a schematic diagram of a step S30 of fabricating a CMOS type LTPS TFT substrate by using the existing Re-etch LDD technology;
  • FIG. 4 is a schematic diagram of a step S40 of fabricating a CMOS type LTPS TFT substrate by using the existing Re-etch LDD technology;
  • FIG. 5 is a schematic diagram of a step S50 of fabricating a CMOS type LTPS TFT substrate by using the existing Re-etch LDD technology
  • FIG. 6 is a schematic diagram of a step S60 of fabricating a CMOS type LTPS TFT substrate using the existing Re-etch LDD technology
  • FIG. 7 is a schematic flow chart of a method of fabricating a CMOS type LTPS TFT substrate according to the present invention.
  • step S1 is a schematic diagram of step S1 of a method of fabricating a CMOS type LTPS TFT substrate of the present invention
  • step S2 is a schematic diagram of step S2 of a method of fabricating a CMOS type LTPS TFT substrate of the present invention.
  • FIG. 10 is a schematic diagram of a step S3 of a method of fabricating a CMOS type LTPS TFT substrate according to the present invention.
  • step S4 is a schematic diagram of step S4 of a method of fabricating a CMOS type LTPS TFT substrate of the present invention
  • step S5 is a schematic diagram of step S5 of the method for fabricating a CMOS type LTPS TFT substrate of the present invention
  • FIG. 13 is a schematic diagram showing a step S6 of the method of fabricating the CMOS type LTPS TFT substrate of the present invention.
  • Fig. 14 is a schematic view showing a step S7 of the method of fabricating the CMOS type LTPS TFT substrate of the present invention.
  • the present invention provides a method for fabricating a CMOS type LTPS TFT substrate, which includes the following steps:
  • Step S1 as shown in FIG. 8, a substrate 10 is provided, on which a first light blocking block 61 and a second light blocking block 62 are formed, and a first light shielding block 61 and a first light shielding block 61 are formed on the substrate 10.
  • the buffer layer 20 of the two light blocking blocks 62 forms a first polysilicon active layer 31 and corresponding PMOS of the corresponding NMOS which are respectively spaced above the first light blocking block 61 and the second light blocking block 62 on the buffer layer 20 a second polysilicon active layer 32, on the buffer layer 20, a gate insulating layer 40 covering the first polysilicon active layer 31 and the second polysilicon active layer 32 is formed on the gate
  • a metal layer 50 is deposited on the pole insulating layer 40, a photoresist is coated on the metal layer 50, and the photoresist is exposed and developed through a semi-transmissive mask to form a corresponding active layer on the first polysilicon.
  • first photoresist pattern 91 above the middle portion of the 31 and a second photoresist pattern 92 completely covering the second polysilicon active layer 32 over the second polysilicon active layer 32;
  • the second photoresist pattern 92 has The first photoresist segment 921 located in the middle and the second photoresist having a thickness smaller than the first photoresist segment 921 are smaller than the first photoresist segment 921 922.
  • the semi-transmissive reticle used in the step S1 has an opaque region, a semi-transmissive region and a remaining fully transparent region, wherein the opaque region is used to form the first photoresist pattern 91. And a first photoresist segment 921 of the second photoresist pattern 92, wherein the semi-transmissive region is used to form the second photoresist segment 922 of the second photoresist pattern 92.
  • the semi-transmissive reticle used in the step S1 is a Gray Tone Mask (GTM) or a Half Tone Mask (HTM).
  • GTM Gray Tone Mask
  • HTM Half Tone Mask
  • Step S2 as shown in FIG. 9, the first photoresist pattern 91 and the second photoresist pattern 92 are used as a shielding layer, and the metal layer 50 is first etched to form a first polysilicon active layer.
  • the metal layer 50 is first etched by dry etching, and the etching gas for performing the first etching on the metal layer 50 includes sulfur hexafluoride (SF 6 ), Fluorine (C 2 HF 5 ) and carbon tetrafluoride (CF 4 ).
  • the etching gas for performing the first etching on the metal layer 50 includes sulfur hexafluoride (SF 6 ), Fluorine (C 2 HF 5 ) and carbon tetrafluoride (CF 4 ).
  • Step S3 as shown in FIG. 10, the first photoresist pattern 91 and the first quasi-gate 51' are used as shielding layers, and there is no first quasi-gate on both ends of the first polysilicon active layer 31.
  • the portion covered by 51' is heavily doped with N-type ions to form a first source-drain contact region 311 across the first polysilicon active layer 31.
  • the ions doped by the N-type ion heavy doping of the first polysilicon active layer 31 are phosphorus ions, and the doping ion concentration is 1 ⁇ 10 14 -1 ⁇ 10 15 ions/ Cm 2 .
  • Step S4 as shown in FIG. 11, performing ashing treatment on the first photoresist pattern 91 and the second photoresist pattern 92 to thin the thicknesses of the first photoresist pattern 91 and the second photoresist pattern 92, The thickness of the first photoresist layer 921 of the first photoresist pattern 91 and the second photoresist pattern 92 is reduced, and the second photoresist layer 922 of the second photoresist pattern 92 is removed to expose the second polysilicon. Both ends of the source layer 32.
  • the first photoresist pattern 91 and the second photoresist pattern 92 are subjected to ashing treatment by oxygen.
  • Step S5 as shown in FIG. 12, the metal layer 50 is etched a second time, so that both sides of the first quasi-gate 51' are laterally etched and the width is reduced, and the first quasi-gate 51' is obtained.
  • the first gate 51 is obtained by the second quasi-gate 52' corresponding to the second gate 52 located above the middle of the second polysilicon active layer 32, and the remaining first photoresist pattern 91 and the second photoresist are stripped away. Pattern 92.
  • the metal layer 50 is etched a second time by dry etching, and the etching gas for performing the second etching on the metal layer 50 contains oxygen and chlorine.
  • Step S6 as shown in FIG. 13, using the first gate 51 as a shielding layer, and performing N-type ion light on a portion of the first polysilicon active layer 31 that is not covered by the first gate 51 Doping, a first channel region 312 corresponding to the middle of the first polysilicon active layer 31 corresponding to the first gate 51 and the first source/drain contact region 311 and the first channel region 312 are obtained.
  • the first LDD zone 313 is between.
  • the ions doped are phosphorus ions, and the doping ion concentration is 1 ⁇ 10 12 -1 ⁇ 10 13 ions/ Cm 2 .
  • Step S7 as shown in FIG. 14, a photoresist protective layer 95 covering the first polysilicon active layer 31 is formed on the gate insulating layer 40 and the first gate 51 to be active on the first polysilicon.
  • the layer 31 prevents P-type ions from being implanted into the first polysilicon active layer 31 to affect the NMOS transistor when the P-type ion is heavily doped, and the second gate 52 is used as a shielding layer.
  • a portion of the two polysilicon active layers 32 that is not covered by the second gate 52 is heavily doped with a P-type ion to form a second source/drain contact region 321 and a second portion of the second polysilicon active layer 32.
  • a second channel region 322 located under the second gate 52 is removed from the middle of the second polysilicon active layer 32 to remove the photoresist protection layer 95.
  • the ions doped by the P-type ion heavy doping of the second polysilicon active layer 32 are boron ions, and the doping ion concentration is 1 ⁇ 10 14 -1 ⁇ 10 15 ions/ Cm 2 .
  • the second photoresist pattern 92 is formed over a region of the second polysilicon active layer 32 where P-type ion heavy doping is required by a semi-transmissive mask.
  • the photoresist segment 922 serves as a protective layer, and can effectively block the second source of the N-type ion implantation of the second polysilicon active layer 32 when the first polysilicon active layer 31 is heavily doped with N-type ions.
  • the drain contact region 321 when the second polysilicon active layer 32 is heavily doped with a P-type ion to form the second source/drain contact region 321 , there is no need to additionally compensate the P-type compared to the prior art.
  • Ions reduce the capacity loss of the P-type ion heavy doping process.
  • the N-type ion heavily doping process cannot affect the PMOS transistor, improve the electrical convergence of the PMOS transistor, and reduce the second polysilicon.
  • the number of ion implantations of the active layer 32 reduces the damage of the lattice structure of the thin film by ion implantation, and improves the stability of the device.
  • the CMOS type LTPS TFT substrate of the present invention is fabricated by fabricating a first polysilicon active layer corresponding to an NMOS and a second polysilicon active layer corresponding to a PMOS through a semi-transmissive mask. Forming a second photoresist segment of the second photoresist pattern over the region where the second polysilicon active layer is to be heavily doped with P-type ions as a protective layer, and performing N-type ions on the first polysilicon active layer When heavily doped, the N-type ions can be effectively blocked from being implanted in the second source-drain contact region of the second polysilicon active layer, and the second poly-silicon active layer is subsequently compared to the prior art.
  • the P-type ion When the P-type ion is heavily doped to form the second source-drain contact region, there is no need to additionally compensate the P-type ions, which reduces the capacity loss of the P-type ion heavy doping process, and the N-type ion heavily doping process cannot generate the PMOS transistor.
  • the effect is to improve the electrical convergence of the PMOS transistor, and at the same time reduce the number of ion implantation to the second polysilicon active layer, reduce the damage of the ion implantation on the lattice structure of the thin film, and improve the stability of the device. Sex.

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Abstract

本发明提供一种CMOS型LTPS TFT基板的制作方法，通过一道半透光光罩在第二多晶硅有源层需进行P型离子重掺杂的区域上方形成第二光阻图案的第二光阻段作为保护层，在对第一多晶硅有源层进行N型离子重掺杂时，能够有效阻挡N型离子植入第二多晶硅有源层设置的第二源漏极接触区中，相比于现有技术，后续在对第二多晶硅有源层进行P型离子重掺杂以形成第二源漏极接触区时，无需额外补偿P型离子，降低了P型离子重掺杂制程的产能损失，N型离子重掺杂制程无法对PMOS晶体管产生影响，提高了PMOS晶体管电性的收敛性，同时又因减少了对第二多晶硅有源层的离子植入次数，降低了离子植入对薄膜晶格结构的破坏，提高了器件的稳定性。

Description

CMOS型LTPS TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种CMOS型LTPS TFT基板的制作方法。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光(Active Matrix Organic Light-Emitting Diode，AMOLED)显示器等平板显示装置因具有机身薄、高画质、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本屏幕等。
薄膜晶体管(Thin Film Transistor，TFT)阵列(Array)基板是目前LCD装置和AMOLED装置中的主要组成部件，直接关系到高性能平板显示装置的发展方向，用于向显示器提供驱动电路，通常设置有数条栅极扫描线和数条数据线，该数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅极扫描线相连，当栅极扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。通常阵列基板上薄膜晶体管的结构又包括自下而上依次层叠设置于基板上的栅极、栅极绝缘层、有源层、源漏极、及绝缘保护层。
其中，低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管与
传统非晶硅(A-Si)薄膜晶体管相比，虽然制作工艺复杂，但因其具有更高的载流子迁移率，被广泛用于中小尺寸高分辨率的LCD和AMOLED显示面板的制作，低温多晶硅被视为实现低成本全彩平板显示的重要材料。
目前，金属氧化物半导体(Metal Oxide Semiconductor，MOS)器件通常采用LTPS制作，其主要分为N型金属氧化物半导体(Negative channel Metal Oxide Semiconductor，NMOS)、P型金属氧化物半导体(Positive channel MetalOxide Semiconductor，PMOS)和互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)，其中NMOS晶体管和PMOS晶体管的主要区别在于所设置的源漏极接触区分别由N型离子重 掺杂(磷离子P+，1x10 14～1x10 15ions/cm 2)和P型离子重掺杂(硼离子B+，1x10 14～1x10 15ions/cm 2)所形成，而NMOS晶体管和PMOS管共同组成CMOS晶体管。热载流子效应是器件的一个重要失效机理，随着MOS器件尺寸的日益缩小，器件的热载流子注入效应越来越严重。在LTPS阵列技术中，为了有效抑制LTPS MOS器件的热载流子效应，提高器件工作的稳定性及改善器件在负偏置条件下的漏电流，现有的LTPS NMOS制作工艺通常采取轻掺杂漏区(Lightly Doped Drain，LDD)方式，即是在多晶硅(Poly-Si)沟道中靠近源漏极的附近设置一个低掺杂的区域，让该低掺杂的区域也承受部分分压。目前通常被应用的LDD工艺为MASK(光罩)LDD技术及Re-etch(重复蚀刻)LDD技术，其中MASK LDD技术通过光阻图案对多晶硅有源层进行N型离子重掺杂而形成源漏极接触区，之后通过栅极自对准技术对多晶硅有源层进行N型离子轻掺杂而形成LDD区；Re-etch LDD技术与上述MASK LDD技术相比，在图案化形成多晶硅有源层后，不通过光阻图案对多晶硅有源层进行重掺杂，而是通过两次蚀刻形成栅极，以第一次蚀刻后的金属图案来定义重掺杂的源漏极接触区域，然后进行第二次蚀刻得到栅极，通过栅极自对准技术对多晶硅有源层进行N型离子轻掺杂而形成LDD区。相比于MASK LDD技术，Re-etch LDD技术的主要优点为减少一道光刻制程，从而降低一道光罩的生产成本和减少LTPS TFT基板的制程时间，提高生产产能。CMOS型LTPS TFT基板制作过程中，所使用的MASK数量通常在11～14次。在LTPS CMOS阵列技术中，为了减少光刻制程，通常采用Re-etch LDD技术取代MASK LDD技术，其通常包括如下步骤。
步骤S10、如图1所示，在基板100上形成缓冲层200，在所述缓冲层200形成对应NMOS的第一多晶硅有源层310以及对应PMOS的第二多晶硅有源层320，在所述缓冲层200上形成覆盖第一多晶硅有源层310和第二多晶硅有源层320的栅极绝缘层400，在所述栅极绝缘层400上沉积金属层500，在金属层500涂覆光阻，并通过一道光罩经曝光显影处理形成对应位于第一多晶硅有源层310中部上方的第一光阻图案910和对应位于第二多晶硅有源层320中部上方的第二光阻图案920。
步骤S20、如图2所示，以所述第一光阻图案910和第二光阻图案920为遮蔽层，对所述金属层500进行第一次蚀刻形成分别位于第一多晶硅有源层310上方和第二多晶硅有源层320上方的第一准栅极510’和第二准栅极520’。
步骤S30、如图3所示，以所述第一准栅极510’为遮蔽层，对所述第一 多晶硅有源层310两端没有第一准栅极510’遮盖的部分进行N型离子重掺杂(P+，1x10 14～1x10 15ions/cm 2)，形成第一多晶硅有源层310两端的第一源漏极接触区3101。
步骤S40、如图4所示，对所述金属层500进行第二次蚀刻，使所述第一准栅极510’和第二准栅极520’两侧被横向蚀刻而宽度减小，形成第一栅极510和第二栅极520，剥离去除第一光阻图案910和第二光阻图案920。
步骤S50、如图5所示，以所述第一栅极510为遮蔽层，对所述第一多晶硅有源层310两端没有被第一栅极510遮盖的部分进行N型离子轻掺杂(P+，1x10 12～1x10 13ions/cm 2)，得到第一多晶硅有源层310中部的对应位于所述第一栅极510下方的第一沟道区3102以及所述源漏极接触区3101和第一沟道区3102之间的第一LDD区3103。
步骤S60、如图6所示，在所述栅极绝缘层400和第一栅极510上形成遮盖第一多晶硅有源层310的光阻保护层950，以所述第二栅极520为遮蔽层，对所述第二多晶硅有源层320两端没有被第二栅极520遮盖的部分进行P型离子重掺杂(B+，1x10 14～1x10 15ions/cm 2)，形成第二多晶硅有源层320两端的第二源漏极接触区3201及第二多晶硅有源层320中部的对应位于所述第二栅极520下方的第二沟道区3202。
在上述CMOS Re-etch LDD技术中，因省去了一道N型离子重掺杂用的光罩，在对对应NMOS的第一多晶硅有源层310进行N型离子重掺杂的同时，也会对对应PMOS的第二多晶硅有源层320进行N型离子重掺杂，而后续为了补偿第二多晶硅有源层320中掺入的磷离子，使第二多晶硅有源层320从N型转变成P型半导体，在P型离子重掺杂制程中则需要掺入更高剂量的硼离子，该制程会对PMOS产生如下影响：
1、高剂量的P型离子重掺杂导致牺牲较高的P型离子重掺杂制程的产能；
2、N型离子重掺杂的分布不均和P型离子重掺杂时离子植入深度的不匹配造成PMOS晶体管的电性收敛性变差；
3、PMOS晶体管源漏极接触区经过3次离子掺杂，导致栅极绝缘层400和多晶硅薄膜的晶格结构被严重破坏，器件可靠性降低，负偏置稳定性及击穿电压降低。
发明内容
本发明的目的在于提供一种CMOS型LTPS TFT基板的制作方法，通过一道半透光光罩在第二多晶硅有源层需进行P型离子重掺杂的区域上方 形成第二光阻图案的第二光阻段作为保护层，在对第一多晶硅有源层进行N型离子重掺杂时，能够有效阻挡N型离子植入第二多晶硅有源层设置的第二源漏极接触区。
为实现上述目的，本发明首先提供一种CMOS型LTPS TFT基板的制作方法，包括如下步骤：
步骤S1、提供基板，在所述基板上形成缓冲层，在所述缓冲层上形成相互间隔的第一多晶硅有源层以及第二多晶硅有源层，在所述缓冲层上形成覆盖第一多晶硅有源层和第二多晶硅有源层的栅极绝缘层，在所述栅极绝缘层上沉积金属层，在所述金属层上涂覆光阻，并通过一道半透光光罩对该光阻进行曝光显影处理，形成对应位于第一多晶硅有源层中部上方的第一光阻图案和在第二多晶硅有源层上方完全遮盖第二多晶硅有源层的第二光阻图案；所述第二光阻图案具有位于中间的第一光阻段及与第一光阻段两侧相连的厚度小于第一光阻段的第二光阻段；
步骤S2、以所述第一光阻图案和第二光阻图案为遮蔽层，对所述金属层进行第一次蚀刻形成位于第一多晶硅有源层中部上方的第一准栅极和位于第二多晶硅有源层上方完全遮盖第二多晶硅有源层的第二准栅极；
步骤S3、以所述第一光阻图案为遮蔽层，对所述第一多晶硅有源层两端没有第一准栅极遮盖的部分进行N型离子重掺杂，形成第一多晶硅有源层两端的第一源漏极接触区；
步骤S4、对所述第一光阻图案和第二光阻图案进行灰化处理，减薄所述第一光阻图案和第二光阻图案的厚度，使得第一光阻图案以及第二光阻图案的第一光阻段的厚度减少，而第二光阻图案的第二光阻段被去除掉而露出第二多晶硅有源层的两端；
步骤S5、对所述金属层进行第二次蚀刻，使所述第一准栅极两侧被横向蚀刻而宽度减小，由第一准栅极得到第一栅极，由第二准栅极得到对应位于第二多晶硅有源层中部上方的第二栅极，剥离去除剩余的第一光阻图案和第二光阻图案；
步骤S6、以所述第一栅极为遮蔽层，对所述第一多晶硅有源层进行N型离子轻掺杂，得到第一多晶硅有源层中部的对应位于所述第一栅极下方的第一沟道区以及所述第一源漏极接触区和第一沟道区之间的第一LDD区；
步骤S7、在所述栅极绝缘层和第一栅极上形成遮盖第一多晶硅有源层的光阻保护层，以所述第二栅极为遮蔽层，对所述第二多晶硅有源层两端没有被第二栅极遮盖的部分进行P型离子重掺杂，形成第二多晶硅有源层两端的第二源漏极接触区及第二多晶硅有源层中部的对应位于所述第二栅 极下方的第二沟道区，去除所述光阻保护层。
所述步骤S1中所使用的半透光光罩具有不透光区、半透光区及剩余的全透光区，其中所述不透光区用于形成第一光阻图案以及第二光阻图案的第一光阻段，所述半透光区用于形成第二光阻图案的第二光阻段。
所述步骤S1中所使用的半透光光罩为灰阶光罩或半色调光罩。
所述步骤S4中通过氧气对所述第一光阻图案和第二光阻图案进行灰化处理。
所述步骤S5中，通过干法蚀刻对所述金属层进行第二次蚀刻，对所述金属层进行第二次蚀刻的蚀刻气体包含氧气和氯气。
所述步骤S2中，通过干法蚀刻对所述金属层进行第一次蚀刻，对所述金属层进行第一次蚀刻的蚀刻气体包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种。
所述步骤S3中，对所述第一多晶硅有源层进行N型离子重掺杂时所掺入的离子为磷离子，掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
所述步骤S6中，对所述第一多晶硅有源层进行N型离子轻掺杂时所掺入的离子为磷离子，掺杂离子浓度为1x10 12-1x10 13ions/cm 2。
所述步骤S7中，对所述第二多晶硅有源层进行P型离子重掺杂时所掺入的离子为硼离子，掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
所述步骤S1还包括在形成所述缓冲层之前，在所述基板上形成分别对应位于第一多晶硅有源层下方和第二多晶硅有源层下方的第一遮光块和第二遮光块。
本发明的有益效果：本发明的CMOS型LTPS TFT基板的制作方法，制作对应NMOS的第一多晶硅有源层和对应PMOS的第二多晶硅有源层时，通过一道半透光光罩在第二多晶硅有源层需进行P型离子重掺杂的区域上方形成第二光阻图案的第二光阻段作为保护层，在对第一多晶硅有源层进行N型离子重掺杂时，能够有效阻挡N型离子植入第二多晶硅有源层设置的第二源漏极接触区中，相比于现有技术，后续在对第二多晶硅有源层进行P型离子重掺杂以形成第二源漏极接触区时，无需额外补偿P型离子，降低了P型离子重掺杂制程的产能损失，N型离子重掺杂制程无法对PMOS晶体管产生影响，提高了PMOS晶体管电性的收敛性，同时又因减少了对第二多晶硅有源层的离子植入次数，降低了离子植入对薄膜晶格结构的破坏，提高了器件的稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为采用现有Re-etch LDD技术制作CMOS型LTPS TFT基板的步骤S10的示意图；
图2为采用现有Re-etch LDD技术制作CMOS型LTPS TFT基板的步骤S20的示意图；
图3为采用现有Re-etch LDD技术制作CMOS型LTPS TFT基板的步骤S30的示意图；
图4为采用现有Re-etch LDD技术制作CMOS型LTPS TFT基板的步骤S40的示意图；
图5为采用现有Re-etch LDD技术制作CMOS型LTPS TFT基板的步骤S50的示意图；
图6为采用现有Re-etch LDD技术制作CMOS型LTPS TFT基板的步骤S60的示意图；
图7为本发明的CMOS型LTPS TFT基板的制作方法的流程示意图；
图8为本发明的CMOS型LTPS TFT基板的制作方法的步骤S1的示意图；
图9为本发明的CMOS型LTPS TFT基板的制作方法的步骤S2的示意图；
图10为本发明的CMOS型LTPS TFT基板的制作方法的步骤S3的示意图；
图11为本发明的CMOS型LTPS TFT基板的制作方法的步骤S4的示意图；
图12为本发明的CMOS型LTPS TFT基板的制作方法的步骤S5的示意图；
图13为本发明的CMOS型LTPS TFT基板的制作方法的步骤S6的示意图；
图14为本发明的CMOS型LTPS TFT基板的制作方法的步骤S7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图7，本发明提供一种CMOS型LTPS TFT基板的制作方法，包括如下步骤：
步骤S1、如图8所示，提供基板10，在所述基板10上形成相互间隔的第一遮光块61和第二遮光块62，在所述基板10上形成覆盖第一遮光块61和第二遮光块62的缓冲层20，在所述缓冲层20上形成相互间隔的分别位于第一遮光块61和第二遮光块62上方的对应NMOS的第一多晶硅有源层31以及对应PMOS的第二多晶硅有源层32，在所述缓冲层20上形成覆盖第一多晶硅有源层31和第二多晶硅有源层32的栅极绝缘层40，在所述栅极绝缘层40上沉积金属层50，在所述金属层50上涂覆光阻，并通过一道半透光光罩对该光阻进行曝光显影处理，形成对应位于第一多晶硅有源层31中部上方的第一光阻图案91和在第二多晶硅有源层32上方完全遮盖第二多晶硅有源层32的第二光阻图案92；所述第二光阻图案92具有位于中间的第一光阻段921及与第一光阻段921两侧相连的厚度小于第一光阻段921的第二光阻段922。
具体地，所述步骤S1中所使用的半透光光罩具有不透光区、半透光区及剩余的全透光区，其中所述不透光区用于形成第一光阻图案91以及第二光阻图案92的第一光阻段921，所述半透光区用于形成第二光阻图案92的第二光阻段922。
具体地，所述步骤S1中所使用的半透光光罩为灰阶光罩(Gray Tone Mask，GTM)或半色调光罩(Half Tone Mask，HTM)。
步骤S2、如图9所示，以所述第一光阻图案91和第二光阻图案92为遮蔽层，对所述金属层50进行第一次蚀刻形成位于第一多晶硅有源层31中部上方的第一准栅极51’和位于第二多晶硅有源层32上方完全遮盖第二多晶硅有源层32的第二准栅极52’。
具体地，所述步骤S2中，通过干法蚀刻对所述金属层50进行第一次蚀刻，对所述金属层50进行第一次蚀刻的蚀刻气体包含六氟化硫(SF 6)、五氟乙烷(C 2HF 5)及四氟化碳(CF 4)。
步骤S3、如图10所示，以所述第一光阻图案91及第一准栅极51’为遮蔽层，对所述第一多晶硅有源层31两端没有第一准栅极51’遮盖的部分进行N型离子重掺杂，形成第一多晶硅有源层31两端的第一源漏极接触区311。
具体地，所述步骤S3中，对所述第一多晶硅有源层31进行N型离子重掺杂时所掺入的离子为磷离子，掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
步骤S4、如图11所示，对所述第一光阻图案91和第二光阻图案92进行灰化处理，减薄所述第一光阻图案91和第二光阻图案92的厚度，使得第一光阻图案91以及第二光阻图案92的第一光阻段921的厚度减少，而第二光阻图案92的第二光阻段922被去除掉而露出第二多晶硅有源层32的两端。
具体地，所述步骤S4中通过氧气对所述第一光阻图案91和第二光阻图案92进行灰化处理。
步骤S5、如图12所示，对所述金属层50进行第二次蚀刻，使所述第一准栅极51’两侧被横向蚀刻而宽度减小，由第一准栅极51’得到第一栅极51，由第二准栅极52’得到对应位于第二多晶硅有源层32中部上方的第二栅极52，剥离去除剩余的第一光阻图案91和第二光阻图案92。
具体地，所述步骤S5中，通过干法蚀刻对所述金属层50进行第二次蚀刻，对所述金属层50进行第二次蚀刻的蚀刻气体包含氧气和氯气。
步骤S6、如图13所示，以所述第一栅极51为遮蔽层，对所述第一多晶硅有源层31两端没有被第一栅极51遮盖的部分进行N型离子轻掺杂，得到第一多晶硅有源层31中部的对应位于所述第一栅极51下方的第一沟道区312以及所述第一源漏极接触区311和第一沟道区312之间的第一LDD区313。
具体地，所述步骤S6中，对所述第一多晶硅有源层31进行N型离子轻掺杂时所掺入的离子为磷离子，掺杂离子浓度为1x10 12-1x10 13ions/cm 2。
步骤S7、如图14所示，在所述栅极绝缘层40和第一栅极51上形成遮盖第一多晶硅有源层31的光阻保护层95以对第一多晶硅有源层31，防止后续进行P型离子重掺杂时P型离子植入第一多晶硅有源层31而对NMOS晶体管产生影响，以所述第二栅极52为遮蔽层，对所述第二多晶硅有源层32两端没有被第二栅极52遮盖的部分进行P型离子重掺杂，形成第二多晶硅有源层32两端的第二源漏极接触区321及第二多晶硅有源层32中部的对应位于所述第二栅极52下方的第二沟道区322，去除所述光阻保护层95。
具体地，所述步骤S7中，对所述第二多晶硅有源层32进行P型离子重掺杂时所掺入的离子为硼离子，掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
本发明的CMOS型LTPS TFT基板的制作方法，通过一道半透光光罩在第二多晶硅有源层32需进行P型离子重掺杂的区域上方形成第二光阻图案92的第二光阻段922作为保护层，在对第一多晶硅有源层31进行N型离子重掺杂时，能够有效阻挡N型离子植入第二多晶硅有源层32设置的第二源漏极接触区321中，相比于现有技术，后续在对第二多晶硅有源层32 进行P型离子重掺杂以形成第二源漏极接触区321时，无需额外补偿P型离子，降低了P型离子重掺杂制程的产能损失，N型离子重掺杂制程无法对PMOS晶体管产生影响，提高了PMOS晶体管电性的收敛性，同时又因减少了对第二多晶硅有源层32的离子植入次数，降低了离子植入对薄膜晶格结构的破坏，提高了器件的稳定性。
综上所述，本发明的CMOS型LTPS TFT基板的制作方法，制作对应NMOS的第一多晶硅有源层和对应PMOS的第二多晶硅有源层时，通过一道半透光光罩在第二多晶硅有源层需进行P型离子重掺杂的区域上方形成第二光阻图案的第二光阻段作为保护层，在对第一多晶硅有源层进行N型离子重掺杂时，能够有效阻挡N型离子植入第二多晶硅有源层设置的第二源漏极接触区中，相比于现有技术，后续在对第二多晶硅有源层进行P型离子重掺杂以形成第二源漏极接触区时，无需额外补偿P型离子，降低了P型离子重掺杂制程的产能损失，N型离子重掺杂制程无法对PMOS晶体管产生影响，提高了PMOS晶体管电性的收敛性，同时又因减少了对第二多晶硅有源层的离子植入次数，降低了离子植入对薄膜晶格结构的破坏，提高了器件的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种CMOS型LTPS TFT基板的制作方法，包括如下步骤：
    步骤S1、提供基板，在所述基板上形成缓冲层，在所述缓冲层上形成相互间隔的第一多晶硅有源层以及第二多晶硅有源层，在所述缓冲层上形成覆盖第一多晶硅有源层和第二多晶硅有源层的栅极绝缘层，在所述栅极绝缘层上沉积金属层，在所述金属层上涂覆光阻，并通过一道半透光光罩对该光阻进行曝光显影处理，形成对应位于第一多晶硅有源层中部上方的第一光阻图案和在第二多晶硅有源层上方完全遮盖第二多晶硅有源层的第二光阻图案；所述第二光阻图案具有位于中间的第一光阻段及与第一光阻段两侧相连的厚度小于第一光阻段的第二光阻段；
    步骤S2、以所述第一光阻图案和第二光阻图案为遮蔽层，对所述金属层进行第一次蚀刻形成位于第一多晶硅有源层中部上方的第一准栅极和位于第二多晶硅有源层上方完全遮盖第二多晶硅有源层的第二准栅极；
    步骤S3、以所述第一光阻图案为遮蔽层，对所述第一多晶硅有源层进行N型离子重掺杂，形成第一多晶硅有源层两端的第一源漏极接触区；
    步骤S4、对所述第一光阻图案和第二光阻图案进行灰化处理，减薄所述第一光阻图案和第二光阻图案的厚度，使得第一光阻图案以及第二光阻图案的第一光阻段的厚度减少，而第二光阻图案的第二光阻段被去除掉而露出第二多晶硅有源层的两端；
    步骤S5、对所述金属层进行第二次蚀刻，使所述第一准栅极两侧被横向蚀刻而宽度减小，由第一准栅极得到第一栅极，由第二准栅极得到对应位于第二多晶硅有源层中部上方的第二栅极，剥离去除剩余的第一光阻图案和第二光阻图案；
    步骤S6、以所述第一栅极为遮蔽层，对所述第一多晶硅有源层进行N型离子轻掺杂，得到第一多晶硅有源层中部的对应位于所述第一栅极下方的第一沟道区以及所述第一源漏极接触区和第一沟道区之间的第一LDD区；
    步骤S7、在所述栅极绝缘层和第一栅极上形成遮盖第一多晶硅有源层的光阻保护层，以所述第二栅极为遮蔽层，对所述第二多晶硅有源层两端没有被第二栅极遮盖的部分进行P型离子重掺杂，形成第二多晶硅有源层两端的第二源漏极接触区及第二多晶硅有源层中部的对应位于所述第二栅极下方的第二沟道区，去除所述光阻保护层。
  2. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中， 所述步骤S1中所使用的半透光光罩具有不透光区、半透光区及剩余的全透光区，其中所述不透光区用于形成第一光阻图案以及第二光阻图案的第一光阻段，所述半透光区用于形成第二光阻图案的第二光阻段。
  3. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S1中所使用的半透光光罩为灰阶光罩或半色调光罩。
  4. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S4中通过氧气对所述第一光阻图案和第二光阻图案进行灰化处理。
  5. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S5中，通过干法蚀刻对所述金属层进行第二次蚀刻，对所述金属层进行第二次蚀刻的蚀刻气体包含氧气和氯气。
  6. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S2中，通过干法蚀刻对所述金属层进行第一次蚀刻，对所述金属层进行第一次蚀刻的蚀刻气体包含六氟化硫、五氟乙烷及四氟化碳中的一种或多种。
  7. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S3中，对所述第一多晶硅有源层进行N型离子重掺杂时所掺入的离子为磷离子，掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
  8. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S6中，对所述第一多晶硅有源层进行N型离子轻掺杂时所掺入的离子为磷离子，掺杂离子浓度为1x10 12-1x10 13ions/cm 2。
  9. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S7中，对所述第二多晶硅有源层进行P型离子重掺杂时所掺入的离子为硼离子，掺杂离子浓度为1x10 14-1x10 15ions/cm 2。
  10. 如权利要求1所述的CMOS型LTPS TFT基板的制作方法，其中，所述步骤S1还包括在形成所述缓冲层之前，在所述基板上形成分别对应位于第一多晶硅有源层下方和第二多晶硅有源层下方的第一遮光块和第二遮光块。
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