WO2019182197A1 - Rf chip package - Google Patents

Rf chip package Download PDF

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Publication number
WO2019182197A1
WO2019182197A1 PCT/KR2018/006378 KR2018006378W WO2019182197A1 WO 2019182197 A1 WO2019182197 A1 WO 2019182197A1 KR 2018006378 W KR2018006378 W KR 2018006378W WO 2019182197 A1 WO2019182197 A1 WO 2019182197A1
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Prior art keywords
die
peripheral circuit
substrate
circuit chip
chip
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PCT/KR2018/006378
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French (fr)
Korean (ko)
Inventor
김선국
이상훈
김수빈
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김선국
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Publication of WO2019182197A1 publication Critical patent/WO2019182197A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00

Definitions

  • the present invention relates to an RF chip package, and more particularly, in advance in the package substrate when there is a step between the RF die and the peripheral circuit chip.
  • the step of the shape To form a cavity of the shape,
  • the step of the shape The present invention relates to an RF chip package capable of effectively suppressing side effects caused by a step between an RF die and a peripheral circuit chip by mounting an RF die in a shape cavity.
  • an RF product requires that an RF die and a peripheral circuit chip including a matching circuit or a passive element are disposed and bonded in one package.
  • peripheral circuit chip and the RF die including the matching circuit or the passive element have different thicknesses and there are steps, the peripheral circuit chip and the RF die including the matching circuit or the passive element are bonded in one package. Due to the above step, there is a problem that the wire bonding process is complicated or the frequency characteristic is reduced.
  • the present invention has been made to solve the problems of the prior art, and the technical problem to be achieved by the present invention is in advance in the package substrate when there is a step between the RF die and the peripheral circuit chip.
  • the step of the shape To form a cavity of the shape, The step of the shape By mounting the RF die in the cavity of the shape, it is to provide an RF chip package that can effectively suppress the side effects caused by the step between the RF die and the peripheral circuit chip.
  • the RF chip package includes a peripheral circuit chip including a matching circuit or a passive element, an RF die, and a substrate on which the peripheral circuit chip and the RF die are mounted.
  • a portion of the substrate The step of the shape is formed, the RF die is mounted on top of the step of the substrate, the peripheral circuit chip is mounted on the substrate of the region where the step is not formed, the pad of the peripheral circuit chip And the pads of the RF die are electrically connected by wire bonding.
  • the sum of the thickness of the step and the thickness of the RF die is about 1 to about 1.3 times the thickness of the peripheral circuit chip.
  • the RF chip package includes a peripheral circuit chip including a matching circuit or a passive element, an RF die, and a substrate on which the peripheral circuit chip and the RF die are mounted.
  • a portion of the substrate The cavity of the shape is formed, the RF die is mounted in the cavity of the substrate, the peripheral circuit chip is mounted on the substrate of the region where the cavity is not formed, the pad of the peripheral circuit chip and the The pads of the RF dies are arranged to overlap and are electrically connected through interconnection pins of the conductor material.
  • the depth of the cavity is preferably about 1 times to about 1.3 times the thickness of the RF die.
  • the RF chip package according to the embodiments of the present invention is preliminary to the package substrate when there is a step between the RF die and the peripheral circuit chip.
  • the step of the shape To form a cavity of the shape, The step of the shape By mounting the RF die in the cavity of the shape, side effects caused by the step between the RF die and the peripheral circuit chip can be effectively suppressed.
  • FIG. 1 is a plan view of an RF chip package according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of an RF chip package according to an embodiment of the present invention.
  • FIG 3 is a cross-sectional view of an RF chip package according to another embodiment of the present invention.
  • an RF chip package may include peripheral circuit chips 210 and 220, an RF die 300, and the peripheral circuit chip (including a matching circuit or a passive element). 210 and 220 and the substrate 100 on which the RF die 300 is mounted.
  • the substrate 100 may be composed of a silicon substrate or a copper substrate, and in some regions of the substrate 100, as shown in FIG. 2,
  • the step 110 of the shape is formed by an etching process or a grinding process.
  • the RF die 300 is mounted on the step 110 of the substrate 100, and the peripheral circuit chip (top) of the substrate 100 in the region where the step 110 is not formed.
  • 210 and 220 are mounted, the pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226 of the peripheral circuit chip 210, 220 and the RF die 300.
  • Pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326 are wire bonded and electrically connected.
  • the sum of the thickness of the step 110 and the thickness of the RF die 300 may be maintained at about 1 to 1.3 times the thickness of the peripheral circuit chips 210 and 220. As a result, the step difference between the RF die 300 and the peripheral circuit chips 210 and 220 may be reduced.
  • RF chip package in advance to the substrate (100)
  • step 110 By forming the step 110 of the shape and mounting the RF die 300 on top of the step 110, to reduce the step existing between the RF die 300 and the peripheral circuit chip (210, 220). Therefore, the problem that the wire bonding process becomes complicated or the frequency characteristic is reduced can be effectively suppressed.
  • an RF chip package may include peripheral circuit chips 210 and 220, an RF die 300, and the peripheral circuit chips 210 and 220 including a matching circuit or a passive element, as shown in FIG. 3. ) And the substrate 100 on which the RF die 300 is mounted.
  • the substrate 100 may be formed of a silicon substrate or a copper substrate, and in some regions of the substrate 100, as shown in FIG. 3,
  • the cavity 120 of the shape is formed by an etching process or a grinding process.
  • the RF die 300 is mounted in the cavity 120 of the substrate 100, and the peripheral circuit chip 210 is formed on the substrate 100 in an area where the cavity 120 is not formed.
  • 220 is mounted and pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, and 226 of the peripheral circuit chips 210 and 220 and the die die 300.
  • the pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326 are arranged to overlap and are electrically connected through the interconnect pins 401 of the conductor material.
  • the interconnection pin 401 is formed in a cylindrical shape with a conductive material such as Au, Ag, Cu, or Al, and pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226 and pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, of the die die 300.
  • the interconnection pins 401 are disposed between the 325 and 326 and pressed to form pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, of the peripheral circuit chip 210, 220.
  • 225, 226 and pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326 of the RF die 300 are electrically connected through an interconnect pin 401. do.
  • the cavity 120 is formed such that the depth of the cavity 120 may be maintained at about 1 to 1.3 times the thickness of the RF die 300, thereby forming the RF die 300 and the peripheral circuit chip.
  • the step difference between 210 and 220 can be reduced.
  • the pads 211, 212, 213, 214, 215, 216, of the peripheral circuit chip 210, 220 are formed. 221, 222, 223, 224, 225, 226 and pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226 of the RF die 300 are interconnection pins.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention provides an RF chip package comprising: a peripheral circuit chip including a matching circuit or a passive element; an RF die; and a substrate on which the peripheral circuit chip and the RF die are mounted, wherein a convex step is formed in a partial region of the substrate, the RF die is mounted on the upper part of the step on the substrate, the peripheral circuit chip is mounted on the upper part of the substrate in a region in which the step is not formed, and a pad of the peripheral circuit chip and a pad of the RF die are wire-bonded and electrically connected.

Description

알에프 칩 패키지RF chip package
본 발명은 알에프 칩 패키지에 관한 것으로서, 보다 상세하게는 알에프 다이와 주변 회로 칩 사이에 단차가 존재하는 경우에 패키지 서브스트레이트에 미리
Figure PCTKR2018006378-appb-I000001
형상의 스텝이나
Figure PCTKR2018006378-appb-I000002
형상의 캐비티를 형성하고,
Figure PCTKR2018006378-appb-I000003
형상의 스텝이나
Figure PCTKR2018006378-appb-I000004
형상의 캐비티에 알에프 다이를 실장함으로써, 알에프 다이와 주변 회로 칩 사이에 단차로 인해서 발생되는 부작용을 효과적으로 억제할 수 있는 알에프 칩 패키지에 관한 것이다.The present invention relates to an RF chip package, and more particularly, in advance in the package substrate when there is a step between the RF die and the peripheral circuit chip.
Figure PCTKR2018006378-appb-I000001
The step of the shape
Figure PCTKR2018006378-appb-I000002
To form a cavity of the shape,
Figure PCTKR2018006378-appb-I000003
The step of the shape
Figure PCTKR2018006378-appb-I000004
The present invention relates to an RF chip package capable of effectively suppressing side effects caused by a step between an RF die and a peripheral circuit chip by mounting an RF die in a shape cavity.
ICT(Information and Communications Technologies) 기술의 확산으로 인해 실외공간에서 이루어지던 다양한 활동들이 점차 실내에서 진행되고 있다. 이로 인해, 일상생활에서 실내공간이 차지하는 비율은 점차 높아지고 있으며, 더불어 내비게이션 등과 같이 실외공간을 대상으로 제공되어 오던 서비스들이 점차 실내공간을 대상으로 확장되어 가고 있다.Due to the proliferation of ICT (Information and Communications Technologies) technology, various activities in the outdoor space are gradually progressing indoors. As a result, the proportion of indoor space in everyday life is gradually increasing, and services that have been provided for outdoor spaces such as navigation are gradually expanding to indoor spaces.
이러한 서비스 수요를 만족시키기 위해서, 고성능을 제공하는 알에프(RF; Radio Frequency) 제품이 제안되고 있다.In order to satisfy such service demand, RF (Radio Frequency) products that provide high performance have been proposed.
상술한 것처럼, 고성능을 제공하기 위해서는 알에프 제품은 하나의 패키지 내에 매칭 회로나 수동 소자를 포함하는 주변 회로 칩과 알에프 다이가 배치되어 본딩되는 것이 필요하다.As described above, in order to provide high performance, an RF product requires that an RF die and a peripheral circuit chip including a matching circuit or a passive element are disposed and bonded in one package.
한편, 매칭 회로나 수동 소자를 포함하는 주변 회로 칩과 알에프 다이는 두께가 서로 달라, 단차가 존재하므로, 하나의 패키지 내에 매칭 회로나 수동 소자를 포함하는 주변 회로 칩과 알에프 다이가 본딩되는 경우에 상술한 단차로 인하여, 와이어 본딩 공정이 복잡해지거나 주파수 특성이 감소되는 문제점이 있었다. Meanwhile, since the peripheral circuit chip and the RF die including the matching circuit or the passive element have different thicknesses and there are steps, the peripheral circuit chip and the RF die including the matching circuit or the passive element are bonded in one package. Due to the above step, there is a problem that the wire bonding process is complicated or the frequency characteristic is reduced.
본 발명의 배경기술은 대한민국 등록특허공보 10-1191075호에 게시되어 있다.Background art of the present invention is published in Republic of Korea Patent Publication No. 10-1191075.
본 발명은 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명이 이루고자 하는 기술적 과제는, 알에프 다이와 주변 회로 칩 사이에 단차가 존재하는 경우에 패키지 서브스트레이트에 미리
Figure PCTKR2018006378-appb-I000005
형상의 스텝이나
Figure PCTKR2018006378-appb-I000006
형상의 캐비티를 형성하고,
Figure PCTKR2018006378-appb-I000007
형상의 스텝이나
Figure PCTKR2018006378-appb-I000008
형상의 캐비티에 알에프 다이를 실장함으로써, 알에프 다이와 주변 회로 칩 사이에 단차로 인해서 발생되는 부작용을 효과적으로 억제할 수 있는 알에프 칩 패키지를 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and the technical problem to be achieved by the present invention is in advance in the package substrate when there is a step between the RF die and the peripheral circuit chip.
Figure PCTKR2018006378-appb-I000005
The step of the shape
Figure PCTKR2018006378-appb-I000006
To form a cavity of the shape,
Figure PCTKR2018006378-appb-I000007
The step of the shape
Figure PCTKR2018006378-appb-I000008
By mounting the RF die in the cavity of the shape, it is to provide an RF chip package that can effectively suppress the side effects caused by the step between the RF die and the peripheral circuit chip.
본 발명이 이루고자 하는 기술적 과제들은 이상에서 언급한 기술적 과제들로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 아래의 기재로부터 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 명확하게 이해될 수 있을 것이다.Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.
상기와 같은 목적을 달성하기 위하여 본 발명의 일 실시예에 따른 알에프 칩 패키지는 매칭 회로나 수동 소자를 포함하는 주변 회로 칩, 알에프 다이 및 상기 주변 회로 칩과 상기 알에프 다이가 실장되는 서브스트레이트로 구성되는 알에프 칩 패키지에 있어서, 상기 서브스트레이트의 일부 영역에
Figure PCTKR2018006378-appb-I000009
형상의 스텝이 형성되어 있고, 상기 서브스트레이트의 스텝의 상부에 상기 알에프 다이가 실장되며, 상기 스텝이 형성되지 않은 영역의 서브스트레이트의 상부에 상기 주변 회로 칩이 실장되고, 상기 주변 회로 칩의 패드와 상기 알에프 다이의 패드가 와이어 본딩되어 전기적으로 연결되는 것을 특징으로 한다.In order to achieve the above object, the RF chip package according to an embodiment of the present invention includes a peripheral circuit chip including a matching circuit or a passive element, an RF die, and a substrate on which the peripheral circuit chip and the RF die are mounted. In an RF chip package, a portion of the substrate
Figure PCTKR2018006378-appb-I000009
The step of the shape is formed, the RF die is mounted on top of the step of the substrate, the peripheral circuit chip is mounted on the substrate of the region where the step is not formed, the pad of the peripheral circuit chip And the pads of the RF die are electrically connected by wire bonding.
본 발명의 일 실시예에 따른 알에프 칩 패키지는, 상기 스텝의 두께와 상기 알에프 다이의 두께의 합이 상기 주변 회로 칩의 두께의 1 배 ~ 1.3 배 정도인 것이 바람직하다.In the RF chip package according to the embodiment of the present invention, it is preferable that the sum of the thickness of the step and the thickness of the RF die is about 1 to about 1.3 times the thickness of the peripheral circuit chip.
상기와 같은 목적을 달성하기 위하여 본 발명의 다른 실시예에 따른 알에프 칩 패키지는 매칭 회로나 수동 소자를 포함하는 주변 회로 칩, 알에프 다이 및 상기 주변 회로 칩과 상기 알에프 다이가 실장되는 서브스트레이트로 구성되는 알에프 칩 패키지에 있어서, 상기 서브스트레이트의 일부 영역에
Figure PCTKR2018006378-appb-I000010
형상의 캐비티가 형성되어 있고, 상기 서브스트레이트의 캐비티에 상기 알에프 다이가 실장되며, 상기 캐비티가 형성되지 않은 영역의 서브스트레이트의 상부에 상기 주변 회로 칩이 실장되고, 상기 주변 회로 칩의 패드와 상기 알에프 다이의 패드가 오버랩되도록 배치되어, 도전체 물질의 인터커넥션 핀을 통해서 전기적으로 연결되는 것을 특징으로 한다.In order to achieve the above object, the RF chip package according to another embodiment of the present invention includes a peripheral circuit chip including a matching circuit or a passive element, an RF die, and a substrate on which the peripheral circuit chip and the RF die are mounted. In an RF chip package, a portion of the substrate
Figure PCTKR2018006378-appb-I000010
The cavity of the shape is formed, the RF die is mounted in the cavity of the substrate, the peripheral circuit chip is mounted on the substrate of the region where the cavity is not formed, the pad of the peripheral circuit chip and the The pads of the RF dies are arranged to overlap and are electrically connected through interconnection pins of the conductor material.
본 발명의 다른 실시예에 따른 알에프 칩 패키지는, 상기 캐비티의 깊이는 상기 알에프 다이의 두께의 1 배 ~ 1.3 배 정도인 것이 바람직하다.In the RF chip package according to another embodiment of the present invention, the depth of the cavity is preferably about 1 times to about 1.3 times the thickness of the RF die.
본 발명의 실시예들에 따른 알에프 칩 패키지는 알에프 다이와 주변 회로 칩 사이에 단차가 존재하는 경우에 패키지 서브스트레이트에 미리
Figure PCTKR2018006378-appb-I000011
형상의 스텝이나
Figure PCTKR2018006378-appb-I000012
형상의 캐비티를 형성하고,
Figure PCTKR2018006378-appb-I000013
형상의 스텝이나
Figure PCTKR2018006378-appb-I000014
형상의 캐비티에 알에프 다이를 실장함으로써, 알에프 다이와 주변 회로 칩 사이에 단차로 인해서 발생되는 부작용을 효과적으로 억제할 수 있다.The RF chip package according to the embodiments of the present invention is preliminary to the package substrate when there is a step between the RF die and the peripheral circuit chip.
Figure PCTKR2018006378-appb-I000011
The step of the shape
Figure PCTKR2018006378-appb-I000012
To form a cavity of the shape,
Figure PCTKR2018006378-appb-I000013
The step of the shape
Figure PCTKR2018006378-appb-I000014
By mounting the RF die in the cavity of the shape, side effects caused by the step between the RF die and the peripheral circuit chip can be effectively suppressed.
도 1은 본 발명의 일 실시예에 따른 알에프 칩 패키지의 평면도.1 is a plan view of an RF chip package according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따른 알에프 칩 패키지의 단면도.2 is a cross-sectional view of an RF chip package according to an embodiment of the present invention.
도 3은 본 발명의 다른 실시예에 따른 알에프 칩 패키지의 단면도.3 is a cross-sectional view of an RF chip package according to another embodiment of the present invention.
후술하는 본 발명에 대한 상세한 설명은, 본 발명이 실시될 수 있는 특정 실시예를 예시로서 도시하는 첨부 도면을 참조한다. 이들 실시예는 당업자가 본 발명을 실시할 수 있기에 충분하도록 상세히 설명된다. 본 발명의 다양한 실시예는 서로 다르지만 상호 배타적일 필요는 없음이 이해되어야 한다. 예를 들어, 여기에 기재되어 있는 특정 형상, 구조 및 특성은 일 실시예에 관련하여 본 발명의 정신 및 범위를 벗어나지 않으면서 다른 실시예로 구현될 수 있다. 또한, 각각의 개시된 실시예 내의 개별 구성요소의 위치 또는 배치는 본 발명의 정신 및 범위를 벗어나지 않으면서 변경될 수 있음이 이해되어야 한다. DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention.
따라서, 후술하는 상세한 설명은 한정적인 의미로서 취하려는 것이 아니며, 본 발명의 범위는, 적절하게 설명된다면, 그 청구항들이 주장하는 것과 균등한 모든 범위와 더불어 첨부된 청구항에 의해서만 한정된다. 도면에서 유사한 참조부호는 여러 측면에 걸쳐서 동일하거나 유사한 기능을 지칭하며, 길이 및 면적, 두께 등과 그 형태는 편의를 위하여 과장되어 표현될 수도 있다.The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.
본 발명의 일 실시예에 따른 알에프 칩 패키지는 도 1 및 도 2에 도시된 것처럼, 매칭 회로나 수동 소자를 포함하는 주변 회로 칩(210, 220), 알에프 다이(300) 및 상기 주변 회로 칩(210, 220)과 상기 알에프 다이(300)가 실장되는 서브스트레이트(100)를 포함하여 구성된다.As illustrated in FIGS. 1 and 2, an RF chip package according to an exemplary embodiment of the present invention may include peripheral circuit chips 210 and 220, an RF die 300, and the peripheral circuit chip (including a matching circuit or a passive element). 210 and 220 and the substrate 100 on which the RF die 300 is mounted.
여기에서, 상기 서브스트레이트(100)는 실리콘 서브스트레이트나 구리 서브스트레이트로 구성될 수 있으며, 상기 서브스트레이트(100)의 일부 영역에는 도 2에 도시된 것처럼,
Figure PCTKR2018006378-appb-I000015
형상의 스텝(110)이 식각 공정이나 그라인딩 공정으로 형성되어 있다.Here, the substrate 100 may be composed of a silicon substrate or a copper substrate, and in some regions of the substrate 100, as shown in FIG. 2,
Figure PCTKR2018006378-appb-I000015
The step 110 of the shape is formed by an etching process or a grinding process.
한편, 상기 서브스트레이트(100)의 스텝(110)의 상부에는 상기 알에프 다이(300)가 실장되며, 상기 스텝(110)이 형성되지 않은 영역의 서브스트레이트(100)의 상부에는 상기 주변 회로 칩(210, 220)이 실장되고, 상기 주변 회로 칩(210, 220)의 패드(211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226)와 상기 알에프 다이(300)의 패드(311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326)가 와이어 본딩되어 전기적으로 연결된다.On the other hand, the RF die 300 is mounted on the step 110 of the substrate 100, and the peripheral circuit chip (top) of the substrate 100 in the region where the step 110 is not formed. 210 and 220 are mounted, the pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226 of the peripheral circuit chip 210, 220 and the RF die 300. Pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326 are wire bonded and electrically connected.
여기에서, 상기 스텝(110)의 두께와 상기 알에프 다이(300)의 두께의 합은 상기 주변 회로 칩(210, 220)의 두께의 1 배 ~ 1.3 배 정도로 유지될 수 있도록 상기 스텝(110)이 형성됨으로써, 상기 알에프 다이(300)와 상기 주변 회로 칩(210, 220) 사이에 존재하는 단차를 줄일 수 있다.Here, the sum of the thickness of the step 110 and the thickness of the RF die 300 may be maintained at about 1 to 1.3 times the thickness of the peripheral circuit chips 210 and 220. As a result, the step difference between the RF die 300 and the peripheral circuit chips 210 and 220 may be reduced.
본 발명의 일 실시예에 따른 알에프 칩 패키지는 상기 서브스트레이트(100)에 미리
Figure PCTKR2018006378-appb-I000016
형상의 스텝(110)을 형성하고, 상기 스텝(110)의 상부에 알에프 다이(300)를 실장함으로써, 상기 알에프 다이(300)와 상기 주변 회로 칩(210, 220) 사이에 존재하는 단차를 줄일 수 있으므로, 와이어 본딩 공정이 복잡해지거나 주파수 특성이 감소되는 문제점을 효과적으로 억제할 수 있다.RF chip package according to an embodiment of the present invention in advance to the substrate (100)
Figure PCTKR2018006378-appb-I000016
By forming the step 110 of the shape and mounting the RF die 300 on top of the step 110, to reduce the step existing between the RF die 300 and the peripheral circuit chip (210, 220). Therefore, the problem that the wire bonding process becomes complicated or the frequency characteristic is reduced can be effectively suppressed.
본 발명의 다른 실시예에 따른 알에프 칩 패키지는 도 3에 도시된 것처럼, 매칭 회로나 수동 소자를 포함하는 주변 회로 칩(210, 220), 알에프 다이(300) 및 상기 주변 회로 칩(210, 220)과 상기 알에프 다이(300)가 실장되는 서브스트레이트(100)를 포함하여 구성된다.According to another embodiment of the present invention, an RF chip package may include peripheral circuit chips 210 and 220, an RF die 300, and the peripheral circuit chips 210 and 220 including a matching circuit or a passive element, as shown in FIG. 3. ) And the substrate 100 on which the RF die 300 is mounted.
여기에서, 상기 서브스트레이트(100)는 실리콘 서브스트레이트나 구리 서브스트레이트로 구성될 수 있으며, 상기 서브스트레이트(100)의 일부 영역에는 도 3에 도시된 것처럼,
Figure PCTKR2018006378-appb-I000017
형상의 캐비티(120)가 식각 공정이나 그라인딩 공정으로 형성되어 있다.Here, the substrate 100 may be formed of a silicon substrate or a copper substrate, and in some regions of the substrate 100, as shown in FIG. 3,
Figure PCTKR2018006378-appb-I000017
The cavity 120 of the shape is formed by an etching process or a grinding process.
한편, 상기 서브스트레이트(100)의 캐비티(120)에는 상기 알에프 다이(300)가 실장되며, 상기 캐비티(120)가 형성되지 않은 영역의 서브스트레이트(100)의 상부에는 상기 주변 회로 칩(210, 220)이 실장되고, 상기 주변 회로 칩(210, 220)의 패드(211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226)와 상기 알에프 다이(300)의 패드(311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326)가 오버랩되도록 배치되어, 도전체 물질의 인터커넥션 핀(401)을 통해서 전기적으로 연결된다. Meanwhile, the RF die 300 is mounted in the cavity 120 of the substrate 100, and the peripheral circuit chip 210 is formed on the substrate 100 in an area where the cavity 120 is not formed. 220 is mounted and pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, and 226 of the peripheral circuit chips 210 and 220 and the die die 300. The pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326 are arranged to overlap and are electrically connected through the interconnect pins 401 of the conductor material.
상기 인터커넥션 핀(401)은 도 3에 도시된 것처럼, Au, Ag, Cu 또는 Al과 같은 도정성 물질로 원기둥 형상으로 형성되며, 상기 주변 회로 칩(210, 220)의 패드(211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226)와 상기 알에프 다이(300)의 패드(311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326) 사이에 인터커넥션 핀(401)을 배치하고 압착하여, 상기 주변 회로 칩(210, 220)의 패드(211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226)와 상기 알에프 다이(300)의 패드(311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326)가 인터커넥션 핀(401)을 통해서 전기적으로 연결된다.As shown in FIG. 3, the interconnection pin 401 is formed in a cylindrical shape with a conductive material such as Au, Ag, Cu, or Al, and pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226 and pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, of the die die 300. The interconnection pins 401 are disposed between the 325 and 326 and pressed to form pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, of the peripheral circuit chip 210, 220. 225, 226 and pads 311, 312, 313, 314, 315, 316, 321, 322, 323, 324, 325, 326 of the RF die 300 are electrically connected through an interconnect pin 401. do.
여기에서, 상기 캐비티(120)의 깊이는 상기 알에프 다이(300)의 두께의 1 배 ~ 1.3 배 정도로 유지될 수 있도록 상기 캐비티(120)가 형성됨으로써, 상기 알에프 다이(300)와 상기 주변 회로 칩(210, 220) 사이에 존재하는 단차를 줄일 수 있다.Here, the cavity 120 is formed such that the depth of the cavity 120 may be maintained at about 1 to 1.3 times the thickness of the RF die 300, thereby forming the RF die 300 and the peripheral circuit chip. The step difference between 210 and 220 can be reduced.
본 발명의 다른 실시예에 따른 알에프 칩 패키지는 상기 서브스트레이트(100)에 미리
Figure PCTKR2018006378-appb-I000018
형상의 캐비티(120)를 형성하고, 상기 캐비티(120)에 알에프 다이(300)를 실장한 후에, 상기 주변 회로 칩(210, 220)의 패드(211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226)와 상기 알에프 다이(300)의 패드(211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226)가 인터커넥션 핀(401)을 통해서 전기적으로 연결함으로써, 상기 알에프 다이(300)와 상기 주변 회로 칩(210, 220) 사이에 존재하는 단차를 줄일 수 있으므로, 와이어 본딩 공정이 복잡해지거나 주파수 특성이 감소되는 문제점을 효과적으로 억제할 수 있다.RF chip package according to another embodiment of the present invention in advance to the substrate (100)
Figure PCTKR2018006378-appb-I000018
After the cavity 120 having a shape is formed and the RF die 300 is mounted in the cavity 120, the pads 211, 212, 213, 214, 215, 216, of the peripheral circuit chip 210, 220 are formed. 221, 222, 223, 224, 225, 226 and pads 211, 212, 213, 214, 215, 216, 221, 222, 223, 224, 225, 226 of the RF die 300 are interconnection pins. By electrically connecting through the 401, the step difference between the RF die 300 and the peripheral circuit chips 210 and 220 may be reduced, thereby effectively complicating the problem of complicated wire bonding process or reduced frequency characteristics. It can be suppressed.
이상, 본 발명을 본 발명의 원리를 예시하기 위한 바람직한 실시예와 관련하여 설명하고 도시하였지만, 본 발명은 그와 같이 도시되고 설명된 그대로의 구성 및 작용으로 한정되는 것이 아니다.While the invention has been described and illustrated in connection with a preferred embodiment for illustrating the principles of the invention, the invention is not limited to the configuration and operation as such is shown and described.
오히려, 첨부된 청구범위의 사상 및 범주를 일탈함이 없이 본 발명에 대한 다수의 변경 및 수정이 가능함을 당업자들은 잘 이해할 수 있을 것이다.Rather, it will be apparent to those skilled in the art that many changes and modifications to the present invention are possible without departing from the spirit and scope of the appended claims.
따라서, 그러한 모든 적절한 변경 및 수정과 균등물들도 본 발명의 범위에 속하는 것으로 간주되어야 할 것이다.Accordingly, all such suitable changes and modifications and equivalents should be considered to be within the scope of the present invention.

Claims (4)

  1. 매칭 회로나 수동 소자를 포함하는 주변 회로 칩, 알에프 다이 및 상기 주변 회로 칩과 상기 알에프 다이가 실장되는 서브스트레이트로 구성되는 알에프 칩 패키지에 있어서,An RF chip package comprising a peripheral circuit chip, an RF die including a matching circuit or a passive element, and a substrate on which the peripheral circuit chip and the RF die are mounted.
    상기 서브스트레이트의 일부 영역에
    Figure PCTKR2018006378-appb-I000019
    형상의 스텝이 형성되어 있고,    In some areas of the substrate
    Figure PCTKR2018006378-appb-I000019
    The step of the shape is formed,
    상기 서브스트레이트의 스텝의 상부에 상기 알에프 다이가 실장되며, 상기 스텝이 형성되지 않은 영역의 서브스트레이트의 상부에 상기 주변 회로 칩이 실장되고,The RF die is mounted on the step of the substrate, and the peripheral circuit chip is mounted on the substrate of the region where the step is not formed.
    상기 주변 회로 칩의 패드와 상기 알에프 다이의 패드가 와이어 본딩되어 전기적으로 연결되는 것을 특징으로 하는 알에프 칩 패키지.And the pad of the peripheral circuit chip and the pad of the RF die are wire-bonded and electrically connected.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 스텝의 두께와 상기 알에프 다이의 두께의 합은 상기 주변 회로 칩의 두께의 1 배 ~ 1.3 배 정도인 것을 특징으로 하는 알에프 칩 패키지.And the sum of the thickness of the step and the thickness of the RF die is about 1 to about 1.3 times the thickness of the peripheral circuit chip.
  3. 매칭 회로나 수동 소자를 포함하는 주변 회로 칩, 알에프 다이 및 상기 주변 회로 칩과 상기 알에프 다이가 실장되는 서브스트레이트로 구성되는 알에프 칩 패키지에 있어서,An RF chip package comprising a peripheral circuit chip, an RF die including a matching circuit or a passive element, and a substrate on which the peripheral circuit chip and the RF die are mounted.
    상기 서브스트레이트의 일부 영역에
    Figure PCTKR2018006378-appb-I000020
    형상의 캐비티가 형성되어 있고,    In some areas of the substrate
    Figure PCTKR2018006378-appb-I000020
    The cavity of the shape is formed,
    상기 서브스트레이트의 캐비티에 상기 알에프 다이가 실장되며, 상기 캐비티가 형성되지 않은 영역의 서브스트레이트의 상부에 상기 주변 회로 칩이 실장되고,The RF die is mounted in the cavity of the substrate, and the peripheral circuit chip is mounted on the substrate in the region where the cavity is not formed.
    상기 주변 회로 칩의 패드와 상기 알에프 다이의 패드가 오버랩되도록 배치되어, 도전체 물질의 인터커넥션 핀을 통해서 전기적으로 연결되는 것을 특징으로 하는 알에프 칩 패키지.And the pads of the peripheral circuit chip and the pads of the RF die overlap each other to be electrically connected through interconnection pins of a conductor material.
  4. 청구항 3에 있어서,The method according to claim 3,
    상기 캐비티의 깊이는 상기 알에프 다이의 두께의 1 배 ~ 1.3 배 정도인 것을 특징으로 하는 알에프 칩 패키지.And the depth of the cavity is about 1 times to about 1.3 times the thickness of the RF die package.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990055508A (en) * 1997-12-27 1999-07-15 구본준 Area array package and its manufacturing method
JP3395918B2 (en) * 1994-01-20 2003-04-14 新光電気工業株式会社 Semiconductor device, semiconductor device formed body, and method of manufacturing the formed body
KR100665332B1 (en) * 2005-12-21 2007-01-09 삼성전기주식회사 Wireless communication module
KR20160101502A (en) * 2015-02-17 2016-08-25 한국전자통신연구원 Rf package and manufacturing method thereof
JP6288879B2 (en) * 2016-09-05 2018-03-07 日本電信電話株式会社 High frequency semiconductor module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3395918B2 (en) * 1994-01-20 2003-04-14 新光電気工業株式会社 Semiconductor device, semiconductor device formed body, and method of manufacturing the formed body
KR19990055508A (en) * 1997-12-27 1999-07-15 구본준 Area array package and its manufacturing method
KR100665332B1 (en) * 2005-12-21 2007-01-09 삼성전기주식회사 Wireless communication module
KR20160101502A (en) * 2015-02-17 2016-08-25 한국전자통신연구원 Rf package and manufacturing method thereof
JP6288879B2 (en) * 2016-09-05 2018-03-07 日本電信電話株式会社 High frequency semiconductor module

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