WO2019174206A1 - 一种存储设备的数据读取方法、装置、终端设备和存储介质 - Google Patents

一种存储设备的数据读取方法、装置、终端设备和存储介质 Download PDF

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Publication number
WO2019174206A1
WO2019174206A1 PCT/CN2018/105308 CN2018105308W WO2019174206A1 WO 2019174206 A1 WO2019174206 A1 WO 2019174206A1 CN 2018105308 W CN2018105308 W CN 2018105308W WO 2019174206 A1 WO2019174206 A1 WO 2019174206A1
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Prior art keywords
data read
flash
read command
address
controller
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PCT/CN2018/105308
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English (en)
French (fr)
Inventor
唐江
梁小庆
李志雄
邓恩华
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中山市江波龙电子有限公司
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Publication of WO2019174206A1 publication Critical patent/WO2019174206A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling

Definitions

  • the present invention relates to the field of storage device technologies, and in particular, to a data reading method, device, terminal device, and computer storage medium for a storage device.
  • the memory chip In current storage devices such as SSDs, the memory chip generally uses flash.
  • the host computer When reading data, since the flash read data is an asynchronous operation process, the host computer first sends a data read command to the flash, and then needs to wait for the flash. The data is ready for the host computer to start receiving data.
  • Interleaving is usually used to improve the data reading efficiency, that is, the interleaving technology is used to offset the data preparation time of the flash between multiple channels of flash and multiple chip select storage areas. .
  • embodiments of the present invention provide a data reading method, apparatus, terminal device, and computer storage medium for a storage device, which can significantly improve data reading efficiency of the storage device.
  • a first aspect of the embodiments of the present invention provides a data reading method for a storage device, including:
  • a second aspect of the embodiments of the present invention provides a data reading apparatus for a storage device, including:
  • a data read command acquisition module configured to acquire a plurality of data read commands sent by the host computer
  • a data read command parsing module configured to parse the plurality of data read commands to obtain a physical address corresponding to each of the data read commands, where the physical address includes a chip select address and a storage unit address of the flash ;
  • a data read command submitting module configured to submit the data read command to the controller of the flash according to an order of traversing the chip select address first and then traversing the storage unit address, so that the controller sequentially The received data read command is executed.
  • a third aspect of an embodiment of the present invention provides a terminal device including a memory, a processor, and a computer program stored in the memory and operable on the processor, when the processor executes the computer program A step of implementing a data reading method of a storage device as provided by the first aspect of the embodiments of the present invention.
  • a fourth aspect of the embodiments of the present invention provides a computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the first aspect of the embodiment of the present invention The steps of the data reading method of the storage device.
  • the data reading method of the storage device includes: acquiring a plurality of data read commands sent by the upper computer; parsing the plurality of data read commands, respectively obtaining each of the data read commands Corresponding physical address, the physical address includes a chip select address and a storage unit address of the flash; and the data read command is submitted to the flash according to an order of traversing the chip select address and traversing the storage unit address a controller to cause the controller to sequentially execute the received data read command.
  • the data read command sent by the host computer is sorted in the order of traversing the chip select address and then traversing the memory unit address, so that the adjacent data read commands after the sorting are respectively applied to different chip select storage areas of the flash.
  • each chip selection storage area of the flash can start data preparation work in time.
  • other chip select storage areas are preparing data; when the chip select storage area transfers data, data preparation work of other chip select storage areas is basically completed, and The data transmission is started, thereby effectively avoiding the waste of time resources and significantly improving the data reading efficiency of the storage device.
  • FIG. 1 is a flowchart of a first embodiment of a data reading method of a storage device according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a second embodiment of a data reading method of a storage device according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a third embodiment of a data reading method of a storage device according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of an embodiment of a data reading apparatus of a storage device according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention.
  • Embodiments of the present invention provide a data reading method, device, terminal device, and computer storage medium for a storage device, which can significantly improve data reading efficiency of the storage device.
  • a first embodiment of a data reading method for a storage device in an embodiment of the present invention includes:
  • the storage device refers to various storage devices including a flash storage device, such as an SSD.
  • a flash storage device such as an SSD.
  • the master chip of the storage device can obtain the data read command, and submit the data read command to the flash chip of the storage device to read the flash. The data stored in the chip.
  • Step 102 Parse the plurality of data read commands, and obtain a physical address corresponding to each of the data read commands, where the physical address includes a chip select address and a storage unit address of the flash;
  • the master control chip of the storage device parses the data read commands to obtain physical addresses corresponding to each of the data read commands, the physical address. Includes the chip select address and memory location of the flash.
  • the flash of the storage device is generally divided into multiple channels, each channel includes a plurality of chip select storage areas, and each chip select storage area includes a plurality of storage units.
  • Each data read command will point to a certain storage unit, and the logical address in the data read command can be converted into the physical address of the flash by looking up the mapping table.
  • the main control chip parses the data read command sent by the host computer, the parsed data read command including the physical address information may be referred to as a flash command.
  • the data read command (ie, each flash command) is submitted to the device in the order of traversing the chip select address and traversing the memory unit address.
  • the controller of the flash is configured to cause the controller to sequentially execute the received data read command. It should be noted that this embodiment is mainly directed to a series of data read commands whose physical addresses point to the same channel of the flash.
  • the conventional storage device data reading mode is: the main control chip submits the acquired data read command to the flash controller, and the flash controller sequentially executes the received data read command, that is, the order in which the flash executes the command and the upper position.
  • the order in which the commands are sent by the machine is the same.
  • the sorting is performed again, that is, the data read command is submitted to the order of traversing the chip select address and then traversing the storage unit address.
  • the controller of the flash the order in which the flash executes the commands is the sorted order.
  • the master chip sequentially acquires 10 data read commands, which are A, B, C, D, E, F, G, H, I, and J.
  • the physical addresses of these commands all point to the same channel of the flash.
  • the channel includes four chip select storage areas of CE0, CE1, CE2 and CE3, and each chip select storage area includes 8 storage units of die0 to die7.
  • A corresponds to CE0-die3
  • B corresponds to CE3-die0
  • C corresponds to CE0-die1
  • D corresponds to CE1-die0
  • E corresponds to CE2-die2
  • F corresponds to CE1-die1
  • G corresponds to CE3-die6
  • H corresponds to CE2-die3
  • I corresponds to CE1-die5
  • J corresponds to CE2-die0.
  • the sorting process first traverse the chip select addresses CE0 to CE3, and then traverse the memory cell addresses die0 to die7, that is, according to the physical addresses CE0-die0, CE1-die0, CE2-die0, CE3-die0, CE0-die1, CE1-die1 , the order of CE2-die1, CE3-die1, CE0-die2... is sorted.
  • the data read command corresponding to the next die of the CE is extracted in order, for example, if CE2-die0 is empty, Sorted in the order of CE0-die0, CE1-die0, CE2-die1, CE3-die0, CE0-die1, CE1-die1, CE2-die2, CE3-die1, CE0-die2.
  • the above commands A, B, C, D, E, F, G, H, I, and J are sorted: C, D, J, B, A, F, E, G, I, and H. .
  • a channel of flash can only transmit data of one chip select storage area at the same time, and data preparation work can be performed simultaneously between each chip select storage area.
  • the flash executes a data read command corresponding to any one of the memory cells in a certain chip select memory area
  • the chip select memory area starts data preparation work. It can be seen that the data read command sent by the host computer is sorted according to the above rules and executed, which ensures that each chip selection storage area of the flash can start data preparation in time, so that when a current chip select storage area is transmitting data, A chip select storage area is preparing data; when the current chip select storage area is finished transmitting data, the data preparation work of the latter chip select storage area is also basically completed, and the data transfer can be directly performed, thereby significantly improving the data reading efficiency.
  • the data reading method of the storage device includes: acquiring a plurality of data read commands sent by the upper computer; parsing the plurality of data read commands, respectively obtaining each of the data read commands Corresponding physical address, the physical address includes a chip select address and a storage unit address of the flash; and the data read command is submitted to the flash according to an order of traversing the chip select address and traversing the storage unit address a controller to cause the controller to sequentially execute the received data read command.
  • the data read command sent by the host computer is sorted in the order of traversing the chip select address and then traversing the memory unit address, so that the adjacent data read commands after the sorting are respectively applied to different chip select storage areas of the flash.
  • each chip selection storage area of the flash can start data preparation work in time.
  • other chip select storage areas are preparing data; when the chip select storage area transfers data, data preparation work of other chip select storage areas is basically completed.
  • the ability to start transmitting data thereby effectively avoiding the waste of time resources, and significantly improving the data reading efficiency of the storage device.
  • a second embodiment of a data reading method for a storage device in an embodiment of the present invention includes:
  • Step 201 is the same as step 101. For details, refer to the related description of step 101.
  • step 202 The difference between step 202 and step 102 is that the physical address corresponding to the parsed data read command further includes the channel address of the flash.
  • a series of data read commands directed to each channel of the flash address are reordered after the command sent by the host computer is obtained, that is, the channel address is traversed first, then the chip select address is traversed, and finally The data read command is submitted to the controller of the flash by traversing the order of the storage unit addresses, and the order in which the flash executes the commands is the sorted order.
  • flash has 4 channels, which are ch0, ch1, ch2, and ch3, and each channel includes four chip select storage areas of CE0, CE1, CE2, and CE3, and each chip select storage area includes 8 die0 to die7 respectively. Storage unit.
  • the channel addresses ch0 to ch3 are first traversed, then the chip select addresses CE0 to CE3 are traversed, and finally the memory cell addresses die0 to die7 are traversed, that is, according to the physical addresses ch0-CE0-die0, ch1-CE0-die0, ch2-CE0.
  • the data read command corresponding to the next CE of the corresponding channel is extracted in order, in the process of traversing CE0 to CE3. If there is a data read command corresponding to a certain die, the data read command corresponding to the next die of the CE is extracted in order.
  • the flash channels work independently, that is, they can transmit data at the same time, but one channel can only transmit data of one chip select storage area at the same time, and data preparation work can be performed simultaneously between each chip select storage area. It can be seen that the data read command issued by the main control chip is sorted according to the above rules and executed, which ensures that each channel of the flash can start data transmission in time, and the chip selection storage area of each channel can start data preparation work in time.
  • each channel can start data transmission work in time, and for any channel of flash, when one chip selection storage area is transmitting data, the latter chip selection storage area is preparing data;
  • the data preparation work of the latter chip selection storage area is basically completed, and the data transmission can be directly performed, thereby significantly improving the data reading efficiency.
  • the data reading method of the storage device includes: acquiring a plurality of data read commands sent by the upper computer; parsing the plurality of data read commands, respectively obtaining each of the data read commands Corresponding physical address, the physical address includes a channel address, a chip select address, and a storage unit address of the flash; the order of traversing the channel address, then traversing the chip select address, and finally traversing the memory unit address
  • the data read command is submitted to the controller of the flash to cause the controller to sequentially execute the received data read command.
  • the data reading method of the embodiment can ensure that each channel of the flash starts data transmission in time, and the chip selection storage area of each channel can start data preparation work in time, which greatly improves the data reading efficiency of the multi-channel flash.
  • a third embodiment of a data reading method for a storage device in an embodiment of the present invention includes:
  • Steps 301-302 are the same as steps 101-102. For details, refer to the related description of steps 101-102.
  • the multiple data read commands are sequentially discharged into the vacant nodes in the preset command queue, and each vacant node is configured with a data read command.
  • the parsed data read command (ie, the flash command) is sequentially discharged into the vacant nodes in the preset command queue (ie, the nodes that are not logged into the command), and each vacant node is discharged with a data read command.
  • the order here refers to the order in which the data read command is acquired and parsed according to the master chip.
  • command queue can be preset by the following steps:
  • the specified memory space is selected by the main control chip of the storage device.
  • the memory space is divided into N nodes to form the command queue, and each node is used to store a data read command, and N is an integer greater than 1.
  • the number N of nodes of the command queue is more than twice the number of storage units of the flash.
  • each CPU can execute the command, and the CPU of the master chip can simultaneously parse the commands sent by the host computer, thereby achieving the effect of parallel processing and further improving the processing. effectiveness.
  • Step 304 The data read command in the command queue is sequentially cached in a linked list of each storage unit of the flash according to a corresponding physical address;
  • the data read command in the command queue is sequentially cached in the linked list of the storage units of the flash according to the corresponding physical address. It should be noted that all data read commands can be first queued into the command queue, and the data read commands in the command queue are cached to the linked list of each storage unit according to the corresponding physical address; or several data can be read first.
  • the command is queued to the command queue, and then the data read command in the command queue is cached to the linked list of each storage unit, thereby implementing the command output and the command cache simultaneously, which can improve the processing efficiency.
  • a linked list is created for each storage unit of the flash, and the linked list is mainly used for the cache data read command, thereby facilitating the sorting of the data read commands.
  • A is buffered into the linked list of the channel ch0, the memory cell die3 of the chip select CE1, and so on.
  • a linked list of a storage unit has multiple nodes, and multiple data read commands can be cached, that is, if multiple data read commands correspond to the same storage unit, the data read commands are sequentially cached to the storage unit.
  • the list of storage units is if multiple data read commands correspond to the same storage unit, the data read commands are sequentially cached to the storage unit.
  • a linked list header may be separately created for each storage unit, and the linked list header is used to manage each node of the storage unit linked list, such as allocation and recycling of each node.
  • a link header for managing the vacant node may be created to manage allocation and collection of the vacant nodes of the task queue.
  • the specific node management process is as follows: the link header is set with two pointers, one header pointer points to the head node, one tail pointer points to the tail node, each node has a pointer, and the relationship between two adjacent nodes is the previous node pointer Next node. Each time a node is fetched from the tail pointer, the next node pointed to by the node is found first, and then the tail pointer of the list header is pointed to the node. When each node enters the linked list, it first points the pointer of the node to the node pointed to by the head pointer in the list header, and then points the head pointer in the linked list to the incoming node.
  • step 305 can include:
  • step (1) it is determined whether the total number of data read commands cached in the linked list of all the storage units of the flash is greater than a first threshold.
  • the first threshold is set, the better the sorting effect of the task is, but at the same time, the parallel processing effect of the flash execution command and the main control chip parsing command is deteriorated, so the first threshold cannot be set too large. It can generally be set to N/2, which is half the number of nodes in the command queue.
  • the first data read command cached in the linked list of the target storage unit is submitted to the controller of the flash; the target storage unit is The traversal order determines a storage unit that should currently submit a data read command. For example, if ch3-CE1-die0 is currently submitted in accordance with the traversal order and the data read command should be submitted, the first data read command cached in the linked list of the storage unit ch3-CE1-die0 (ie, the first The data read command stored in the linked list is submitted to the controller of the flash.
  • step 301 it may return to step 301 to wait for more data read commands to be cached to the linked list of the respective storage units of the flash.
  • the parallel processing of buffering the new command to the linked list and submitting the cached command to the flash controller is achieved, which effectively improves the processing efficiency.
  • step 305 can include:
  • step (1) it is determined whether a new data read command is acquired within the preset time period, that is, whether the host computer issues a new data read command to the flash master chip within the preset time period.
  • step (2) if a new data read command is not acquired within the preset time period, all the data read commands cached in the linked list of the respective storage units are submitted to the controller of the flash. Similarly, the traversal order is followed when the data read command is submitted.
  • the new data read command is discharged into a vacant node in the command queue, and the new one is corresponding according to the corresponding physical address.
  • the data read command is cached in a linked list of memory locations of the flash. That is, if a new data read command is received, the new data read command is preferentially cached to the linked list of the storage unit until a new data read command is not received. Then, all data read commands cached in the storage unit linked list are submitted to the controller of the flash in the traversal order. After all data read commands are submitted to the flash controller, the data read commands in the command queue can be emptied to free up more vacant nodes.
  • the number of caches in the linked list of each storage unit of the flash is compared with the new data.
  • a data read command having the same read command is submitted to the controller of the flash, and a data read command submitted to the controller of the flash is cleared in the command queue to form a new data that can be discharged Read the free node of the command.
  • the linked list of ch0-CE0-die0 is submitted.
  • a data read command in the buffer is sent to the flash controller, and then the data read command is cleared in the command queue to free a free node to the new data read command.
  • the data read command that is the earliest cached to the linked list is submitted; if there is no cached data read command in the linked list of ch0-CE0-die0, Then submit a data read command cached in the linked list of ch0-CE0-die1.
  • the data reading method of the storage device includes: acquiring a plurality of data read commands sent by the upper computer; parsing the plurality of data read commands, respectively obtaining each of the data read commands Corresponding physical address; the plurality of data read commands are sequentially discharged into the vacant nodes in the preset command queue, and each vacant node is arranged with a data read command; the data read command in the command queue is And sequentially buffering to the linked list of the respective storage units of the flash according to the corresponding physical address; and submitting the data read command cached in the linked list of the respective storage units to the controller of the flash.
  • the sorting of the data read commands can be conveniently implemented.
  • the above describes mainly a data reading method of a storage device, and a data reading device of a storage device will be described below.
  • an embodiment of a data reading apparatus for a storage device in an embodiment of the present invention includes:
  • the data read command obtaining module 401 is configured to acquire a plurality of data read commands sent by the host computer;
  • the data read command parsing module 402 is configured to parse the plurality of data read commands to obtain a physical address corresponding to each of the data read commands, where the physical address includes a chip select address and a storage unit of the flash. address;
  • the data read command submitting module 403 is configured to submit the data read command to the controller of the flash according to the order of traversing the chip select address and then traversing the storage unit address, so that the controller The received data read command is sequentially executed.
  • the physical address further includes a channel address of the flash
  • the data read command submitting module 403 may be specifically configured to:
  • the data read command is submitted to the controller of the flash in the order of traversing the channel address, then traversing the chip select address, and finally traversing the memory cell address.
  • An embodiment of the present invention further provides a terminal device, including a memory, a processor, and a computer program stored in the memory and operable on the processor, where the processor implements the computer program as shown in FIG. 1
  • a terminal device including a memory, a processor, and a computer program stored in the memory and operable on the processor, where the processor implements the computer program as shown in FIG. 1
  • the embodiment of the present invention further provides a computer readable storage medium, where the computer readable storage medium stores a computer program, and when the computer program is executed by the processor, implements any storage device as shown in FIG. 1 to FIG. The steps of the data reading method.
  • FIG. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention.
  • the terminal device 5 of this embodiment includes a processor 50, a memory 51, and a computer program 52 stored in the memory 51 and operable on the processor 50.
  • the processor 50 executes the computer program 52 to implement the steps in the embodiment of the data reading method of each of the above storage devices, such as steps 101 to 103 shown in FIG.
  • the processor 50 executes the computer program 52
  • the functions of the modules/units in the foregoing device embodiments are implemented, such as the functions of the modules 401 to 403 shown in FIG.
  • the computer program 52 can be partitioned into one or more modules/units that are stored in the memory 51 and executed by the processor 50 to complete the present invention.
  • the one or more modules/units may be a series of computer program instruction segments capable of performing a particular function, the instruction segments being used to describe the execution of the computer program 52 in the terminal device 5.
  • the terminal device 5 may be a computing device such as various types of mobile phones, desktop computers, notebooks, palmtop computers, and cloud servers.
  • the terminal device may include, but is not limited to, a processor 50 and a memory 51. It will be understood by those skilled in the art that FIG. 5 is only an example of the terminal device 5, does not constitute a limitation of the terminal device 5, may include more or less components than the illustrated, or combine some components, or different components.
  • the terminal device 5 may further include an input/output device, a network access device, a bus, and the like.
  • the processor 50 may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5.
  • the memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk equipped on the terminal device 5, a smart memory card (SMC), and a secure digital (SD). Card, flash card, etc. Further, the memory 51 may also include both an internal storage unit of the terminal device 5 and an external storage device.
  • the memory 51 is used to store the computer program and other programs and data required by the terminal device.
  • the memory 51 can also be used to temporarily store data that has been output or is about to be output.
  • each functional unit and module described above is exemplified. In practical applications, the above functions may be assigned to different functional units as needed.
  • the module is completed by dividing the internal structure of the device into different functional units or modules to perform all or part of the functions described above.
  • Each functional unit and module in the embodiment may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit, and the integrated unit may be hardware.
  • Formal implementation can also be implemented in the form of software functional units.
  • the specific names of the respective functional units and modules are only for the purpose of facilitating mutual differentiation, and are not intended to limit the scope of protection of the present application.
  • the disclosed apparatus and method may be implemented in other manners.
  • the system embodiment described above is merely illustrative.
  • the division of the module or unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the present invention implements all or part of the processes in the foregoing embodiments, and may also be completed by a computer program to instruct related hardware.
  • the computer program may be stored in a computer readable storage medium. The steps of the various method embodiments described above may be implemented when the program is executed by the processor.
  • the computer program comprises computer program code, which may be in the form of source code, object code form, executable file or some intermediate form.
  • the computer readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a removable hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM). , random access memory (RAM, Random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. It should be noted that the content contained in the computer readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in a jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, computer readable media It does not include electrical carrier signals and telecommunication signals.

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Abstract

本发明涉及存储设备技术领域，提出一种存储设备的数据读取方法、装置、终端设备和计算机存储介质。所述数据读取方法包括：获取上位机下发的多条数据读取命令；对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。本发明通过将数据读取命令按照先遍历片选地址、后遍历存储单元地址的顺序排序，使得flash的每个片选存储区域都能及时开始数据准备工作，显著提高了存储设备的数据读取效率。

Description

一种存储设备的数据读取方法、装置、终端设备和存储介质 【技术领域】
本发明涉及存储设备技术领域，尤其涉及一种存储设备的数据读取方法、装置、终端设备和计算机存储介质。
【背景技术】
在目前的存储设备比如SSD中，存储芯片一般采用flash，当读取数据时，由于flash读数据是一个异步操作的过程，即首先由上位机给flash发送数据读取命令，然后需要等flash把数据准备好上位机才能开始接收数据。针对这个特性，目前通常采用交叉存取技术(Interleaving)来提高数据的读取效率，即在flash的多个通道和多个片选存储区域之间采用交叉存取技术来抵消flash的数据准备时间。
然而，由于上位机发送的一连串数据读取命令所对应的存储单元地址是随机乱序的，即很可能出现连续的多条数据读取命令作用在flash的同一个片选存储区域，这就导致flash的其它片选存储区域无法及时开始数据准备工作，产生时间资源的浪费。因此，采用传统的交叉存取技术对于存储设备的数据读取效率的提高效果并不显著。
【发明内容】
有鉴于此，本发明实施例提供了一种存储设备的数据读取方法、装置、终端设备和计算机存储介质，能够显著提高存储设备的数据读取效率。
本发明实施例的第一方面提供了一种存储设备的数据读取方法，包括：
获取上位机下发的多条数据读取命令；
对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；
按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。
本发明实施例的第二方面提供了一种存储设备的数据读取装置，包括：
数据读取命令获取模块，用于获取上位机下发的多条数据读取命令；
数据读取命令解析模块，用于对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；
数据读取命令提交模块，用于按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。
本发明实施例的第三方面提供了一种终端设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行 所述计算机程序时实现如本发明实施例的第一方面提供的存储设备的数据读取方法的步骤。
本发明实施例的第四方面提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现如本发明实施例的第一方面提供的存储设备的数据读取方法的步骤。
本发明实施例提出的存储设备的数据读取方法包括：获取上位机下发的多条数据读取命令；对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。上述过程通过将上位机下发的数据读取命令按照先遍历片选地址、后遍历存储单元地址的顺序排序，能够保证排序后相邻的数据读取命令分别作用在flash的不同片选存储区域，从而使得flash的每个片选存储区域都能及时开始数据准备工作。通过这样设置，当某个片选存储区域在传输数据时，其它片选存储区域在准备数据；当该片选存储区域传输完数据时，其它片选存储区域的数据准备工作也基本完成，能够开始传输数据，从而有效避免时间资源的浪费，显著提高了存储设备的数据读取效率。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种存储设备的数据读取方法的第一个实施例的流程图；
图2是本发明实施例提供的一种存储设备的数据读取方法的第二个实施例的流程图；
图3是本发明实施例提供的一种存储设备的数据读取方法的第三个实施例的流程图；
图4是本发明实施例提供的一种存储设备的数据读取装置的一个实施例的结构图；
图5是本发明实施例提供的一种终端设备的示意图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本发明实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本发明。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本发明的描述。
本发明实施例提供了一种存储设备的数据读取方法、装置、终端设备和计算机存储介质，能够显著提高存储设备的数据读取效率。
请参阅图1，本发明实施例中一种存储设备的数据读取方法的第一个实施例包括：
101、获取上位机下发的多条数据读取命令；
在本发明实施例中，所述存储设备指包含flash存储器件的各种存储设备，比如SSD。当上位机下发数据读取命令给存储设备后，该存储设备的主控芯片能够获取到这些数据读取命令，并将这些数据读取命令提交给该存储设备的flash芯片，以读取flash芯片中保存的数据。
102、对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；
在获取到上位机下发的多条数据读取命令之后，存储设备的主控芯片对这些数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址。存储设备的flash一般分为多个通道，每个通道包括多个片选存储区域，每个片选存储区域包括多个存储单元。每条数据读取命令都会指向某个存储单元，可以通过查找映射表的方式将数据读取命令中的逻辑地址转换为flash的物理地址。在主控芯片对上位机下发的数据读取命令进行解析后，可以将解析得到的包含物理地址信息的数据读取命令称作flash命令。
103、按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。
在得到每条所述数据读取命令对应的物理地址之后，按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令(即各个flash命令)提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。需要指出的是，本实施例主要针对物理地址指向flash同一个通道的一连串数据读取命令。
传统的存储设备数据读取方式为：主控芯片将获取到的数据读取命令提交给flash的控制器，flash的控制器依次执行接收到的数据读取命令，即flash执行命令的顺序与上位机下发命令的顺序相同。
而在本实施例中，在获取到上位机下发的命令后会重新进行排序，即按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，flash执行命令的顺序为排序后的顺序。假设主控芯片依次获取到10条数据读取命令，分别为A、B、C、D、E、F、G、H、I和J，这些命令的物理地址都指向flash的同一个通道，该通道共包括CE0、CE1、CE2和CE3四个片选存储区域，每个片选存储区域分别包括die0至die7共8个存储单元。其中A对应于CE0-die3，B对应于CE3-die0，C对应于CE0-die1，D对应于CE1-die0，E对应于CE2-die2，F对应于CE1-die1，G对应于CE3-die6，H对应于CE2-die3，I对应于CE1-die5，J对应于CE2-die0。在排序过程中，首 先遍历片选地址CE0至CE3，然后遍历存储单元地址die0至die7，即按照物理地址CE0-die0、CE1-die0、CE2-die0、CE3-die0、CE0-die1、CE1-die1、CE2-die1、CE3-die1、CE0-die2…的顺序排序。另外，若在遍历CE0至CE3的过程中存在某个die对应的数据读取命令为空，则按顺序提取该CE的下一个die对应的数据读取命令，比如若CE2-die0为空，则按照CE0-die0、CE1-die0、CE2-die1、CE3-die0、CE0-die1、CE1-die1、CE2-die2、CE3-die1、CE0-die2…的顺序排序。按照这个规则，上述命令A、B、C、D、E、F、G、H、I和J在排序后即为：C、D、J、B、A、F、E、G、I和H。
flash的一个通道在同一时间只能传输一个片选存储区域的数据，而各个片选存储区域之间是可以同时进行数据准备工作的。当flash执行对应于某个片选存储区域内任意一个存储单元的数据读取命令时，该片选存储区域即开始数据准备工作。可见，将上位机下发的数据读取命令按照上述规则排序后再执行，能够确保flash的各个片选存储区域都能及时开始数据准备工作，这样当前一个片选存储区域在传输数据时，后一个片选存储区域在准备数据；当前一个片选存储区域传输数据完毕时，后一个片选存储区域的数据准备工作也基本完成，可以直接进行数据传输，从而显著提高了数据的读取效率。
本发明实施例提出的存储设备的数据读取方法包括：获取上位机下发的多条数据读取命令；对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。上述过程通过将上位机下发的数据读取命令按照先遍历片选地址、后遍历存储单元地址的顺序排序，能够保证排序后相邻的数据读取命令分别作用在flash的不同片选存储区域，从而使得flash的每个片选存储区域都能及时开始数据准备工作。通过这样设置，当某个片选存储区域在传输数据时，其它的片选存储区域在准备数据；当该片选存储区域传输完数据时，其它片选存储区域的数据准备工作也基本完成，能够开始传输数据，从而有效避免时间资源的浪费，显著提高了存储设备的数据读取效率。
请参阅图2，本发明实施例中一种存储设备的数据读取方法的第二个实施例包括：
201、获取上位机下发的多条数据读取命令；
步骤201与步骤101相同，具体可参照步骤101的相关说明。
202、对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的通道地址、片选地址和存储单元地址；
步骤202与步骤102的区别在于，解析得到的数据读取命令对应的物理地址还包括flash的通道地址。
203、按照先遍历所述通道地址、然后遍历所述片选地址、最后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控 制器依次执行接收到的所述数据读取命令。
本实施例针对物理地址指向flash各个通道的一连串数据读取命令，在获取到上位机下发的命令后会重新进行排序，即按照先遍历所述通道地址、然后遍历所述片选地址、最后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，flash执行命令的顺序为排序后的顺序。假设flash有4个通道，分别为ch0、ch1、ch2和ch3，每个通道分别包括CE0、CE1、CE2和CE3四个片选存储区域，每个片选存储区域分别包括die0至die7共8个存储单元。在排序过程中，首先遍历通道地址ch0至ch3，然后遍历片选地址CE0至CE3，最后遍历存储单元地址die0至die7，即按照物理地址ch0-CE0-die0、ch1-CE0-die0、ch2-CE0-die0、ch3-CE0-die0、ch0-CE1-die0、ch1-CE1-die0、ch2-CE1-die0、ch3-CE1-die0、ch0-CE2-die0、ch1-CE2-die0、ch2-CE2-die0、ch3-CE2-die0…ch3-CE3-die0、ch0-CE0-die1、ch1-CE0-die1、ch2-CE0-die1、ch3-CE0-die1、ch0-CE1-die1…的顺序排序。另外，若在遍历ch0至ch3的过程中存在某个CE对应的数据读取命令为空，则按顺序提取对应通道的下一个CE对应的数据读取命令，若在遍历CE0至CE3的过程中存在某个die对应的数据读取命令为空，则按顺序提取该CE的下一个die对应的数据读取命令。比如，若ch2-CE0对应的数据读取命令为空(即ch2-CE0-die0、ch2-CE0-die1…ch2-CE0-die7都为空)，则按照ch0-CE0-die0、ch1-CE0-die0、ch2-CE1-die0、ch3-CE0-die0、ch0-CE1-die0…的顺序排序。
flash的各个通道之间是独立工作的，即能够同时传输数据，但一个通道在同一时间只能传输一个片选存储区域的数据，而各个片选存储区域之间可以同时进行数据准备工作。可见，将主控芯片下发的数据读取命令按照上述规则排序后再执行，能够确保flash的各个通道能够及时开始数据传输工作，而且各个通道的片选存储区域都能及时开始数据准备工作。具体的，对于flash来说，各个通道能够及时开始数据传输工作，而对于flash的任意一个通道来说，当前一个片选存储区域在传输数据时，后一个片选存储区域在准备数据；当前一个片选存储区域传输数据完毕时，后一个片选存储区域的数据准备工作也基本完成，可以直接进行数据传输，从而显著提高了数据的读取效率。
本发明实施例提出的存储设备的数据读取方法包括：获取上位机下发的多条数据读取命令；对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的通道地址、片选地址和存储单元地址；按照先遍历所述通道地址、然后遍历所述片选地址、最后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。采用本实施例的数据读取方法能够确保flash的各个通道及时开始数据传输工作，而且各个通道的片选存储区域都能及时开始数据准备工作，极大地提升了多通道flash的数据读取效率。
请参阅图3，本发明实施例中一种存储设备的数据读取方法的第三个实施例包括：
301、获取上位机下发的多条数据读取命令；
302、对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址；
步骤301-302与步骤101-102相同，具体可参照步骤101-102的相关说明。
303、将所述多条数据读取命令依次排入预设的命令队列中的空余节点，每个空余节点排入一条数据读取命令；
也即，将解析后的数据读取命令(即flash命令)依次排入预设的命令队列中的空余节点(即未排入命令的节点)，每个空余节点排入一条数据读取命令。需要说明的是，这里的依次指按照主控芯片获取并解析数据读取命令的次序。
具体的，该命令队列可以通过以下步骤预先设置：
由存储设备的主控芯片选取指定的内存空间；
将所述内存空间划分成N个节点，形成所述命令队列，每个节点用于存储一条数据读取命令，N为大于1的整数。
优选的，所述命令队列的节点数量N为flash的存储单元数量的2倍以上。
通过将N设置为存储单元数量的2倍以上，每个存储单元在执行命令时，主控芯片的CPU还能同时对上位机下发的命令进行解析，从而达到并行处理的效果，进一步提高处理效率。
304、将所述命令队列中的数据读取命令依次按照对应的物理地址缓存到所述flash的各个存储单元的链表中；
将所述命令队列中的数据读取命令依次按照对应的物理地址缓存到所述flash的各个存储单元的链表中。需要说明的是，可以先将所有数据读取命令排入命令队列，再将命令队列中的数据读取命令按照对应的物理地址缓存到各个存储单元的链表；也可以先将若干个数据读取命令排入命令队列，然后即开始将命令队列中的数据读取命令缓存到各个存储单元的链表，从而实现命令排入与命令缓存的同时进行，能够提高处理效率。
在flash的初始化过程中，会给flash的每个存储单元分别创建一个链表，链表主要用于缓存数据读取命令，从而给数据读取命令的排序提供便利。假设数据读取命令A对应的物理地址为ch0-CE1-die3，则将A缓存到通道ch0、片选CE1的存储单元die3的链表中，以此类推。需要说明的是，一个存储单元的链表具有多个节点，可以缓存多条数据读取命令，即若有多条数据读取命令对应同一个存储单元，则依次将这些数据读取命令缓存到该存储单元的链表中。
具体的，可以为每个存储单元分别创建一个链表头，该链表头用于管理存储单元链表的各个节点，比如各个节点的分配和回收。
具体的，还可以创建一个管理空余节点的链表头，用于管理所述任务队列的空余节点的分配和回收。
具体的节点管理过程如下：链表头设置有两个指针，一个头指针指向头节点，一个尾指针指向尾节点，每个节点会有一个指针，两个相邻节点的关系是上一个节点指针指向下一个节点。当每次从尾指针中取出一个节点时，会先找到这个节点指向的下一个节点，然后把链表头的尾指针指向这个节点。当每个节点进入链表时，首先把该节点的指针指向链表头中头指针指向的节点，然后 把链表中的头指针指向这个进入的节点。
305、将所述各个存储单元的链表中缓存的数据读取命令提交至所述flash的控制器。
需要指出的是，在将各个存储单元的链表中缓存的数据读取命令提交至flash的控制器时，按照先遍历片选地址、后遍历存储单元地址的顺序；或者按照先遍历通道地址、然后遍历片选地址、最后遍历存储单元地址的顺序(具体可参照第一个实施例和第二个实施例中的相关说明)。
可选的，步骤305可以包括：
(1)判断所述flash的所有存储单元的链表中缓存的数据读取命令的总数量是否大于第一阈值；
(2)若所述总数量大于第一阈值，则将目标存储单元的链表中缓存的第一条数据读取命令提交至所述flash的控制器；所述目标存储单元为按照所述遍历顺序确定的当前应当提交数据读取命令的存储单元。
对于上述步骤(1)，判断所述flash的所有存储单元的链表中缓存的数据读取命令的总数量是否大于第一阈值。这里的第一阈值设置得越大，则任务的排序效果越好，但与此同时flash执行命令和主控芯片解析命令的并行处理效果会变差，因此第一阈值也不能设置得太大，一般可设为N/2，即所述命令队列的节点数量的一半。
对于上述步骤(2)，若所述总数量大于第一阈值，则将目标存储单元的链表中缓存的第一条数据读取命令提交至所述flash的控制器；所述目标存储单元为按照所述遍历顺序确定的当前应当提交数据读取命令的存储单元。比如，若按照所述遍历顺序确定的当前应当提交数据读取命令的是ch3-CE1-die0，则将存储单元ch3-CE1-die0的链表中缓存的第一条数据读取命令(即最先存入该链表的数据读取命令)提交至所述flash的控制器。
另外，若所述总数量小于或等于第一阈值，则可以返回步骤301，等待更多的数据读取命令缓存到所述flash的各个存储单元的链表。通过这样设置，达到了将新命令缓存到链表、将链表中缓存的命令提交至flash控制器的并行处理，有效提高了处理效率。
可选的，步骤305可以包括：
(1)判断在预设时长内是否获取到新的数据读取命令；
(2)若在预设时长内没有获取到新的数据读取命令，则将所述各个存储单元的链表中缓存的数据读取命令全部提交至所述flash的控制器。
对于上述步骤(1)，判断在预设时长内是否获取到新的数据读取命令，即上位机在预设时长内是否下发新的数据读取命令给flash的主控芯片。
对于上述步骤(2)，若在预设时长内没有获取到新的数据读取命令，则将所述各个存储单元的链表中缓存的数据读取命令全部提交至所述flash的控制器。同样的，在提交数据读取命令时按照所述遍历顺序。
进一步的，若在预设时长内获取到新的数据读取命令，则将所述新的数据读取命令排入所述命令队列中的空余节点，并且按照对应的物理地址将所述新 的数据读取命令缓存到所述flash的存储单元的链表中。即若接收到新的数据读取命令，优先将新的数据读取命令缓存到存储单元的链表，直至接收不到新的数据读取命令。然后，将存储单元链表中缓存的所有数据读取命令按照所述遍历顺序提交给flash的控制器执行。在将所有数据读取命令提交给flash的控制器之后，可以清空所述命令队列中的数据读取命令，以腾出更多的空余节点。
更进一步的，若所述命令队列中没有足够的空余节点(即无法排入所有新的数据读取命令)，则将所述flash的各个存储单元的链表中缓存的数量与所述新的数据读取命令相同的数据读取命令提交至所述flash的控制器，并且在所述命令队列中清除提交至所述flash的控制器的数据读取命令，以形成能够排入所述新的数据读取命令的空余节点。
由于所述命令队列的节点数量是有限的，因此可能出现队列中没有足够的空余节点缓存新命令的问题。此时先将一部分数据读取命令提交给flash的控制器，然后在命令队列中清除这些数据读取命令，以腾出空余节点给新的数据读取命令。需要说明的是，提交命令至flash的控制器时需要按照先遍历片选地址、后遍历存储单元地址的顺序，或者按照先遍历通道地址、然后遍历片选地址、最后遍历存储单元地址的顺序。比如，若当前有一条新的数据读取命令，而命令队列中没有空余节点，且当前按顺序应当提交物理地址为ch0-CE0-die0的数据读取命令，则提交ch0-CE0-die0的链表中缓存的一条数据读取命令至flash的控制器，然后在命令队列中清除这条数据读取命令，以腾出一个空余节点给新的数据读取命令。另外，若ch0-CE0-die0的链表中缓存有多条数据读取命令，则提交最早缓存到链表的那条数据读取命令；若ch0-CE0-die0的链表中没有缓存数据读取命令，则提交ch0-CE0-die1的链表中缓存的一条数据读取命令。
本发明实施例提出的存储设备的数据读取方法包括：获取上位机下发的多条数据读取命令；对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址；将所述多条数据读取命令依次排入预设的命令队列中的空余节点，每个空余节点排入一条数据读取命令；将所述命令队列中的数据读取命令依次按照对应的物理地址缓存到所述flash的各个存储单元的链表中；将所述各个存储单元的链表中缓存的数据读取命令提交至所述flash的控制器。本实施例通过在flash的每个存储单元创建链表，并且将获取到的数据读取命令都缓存到对应的存储单元的链表中，能够方便地实现数据读取命令的排序。
应理解，上述各个实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
上面主要描述了一种存储设备的数据读取方法，下面将对一种存储设备的数据读取装置进行描述。
请参阅图4，本发明实施例中一种存储设备的数据读取装置的一个实施例包括：
数据读取命令获取模块401，用于获取上位机下发的多条数据读取命令；
数据读取命令解析模块402，用于对所述多条数据读取命令进行解析，分 别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；
数据读取命令提交模块403，用于按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。
进一步的，所述物理地址还包括flash的通道地址，所述数据读取命令提交模块403具体可以用于：
按照先遍历所述通道地址、然后遍历所述片选地址、最后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器。
本发明实施例还提供一种终端设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如图1至图3表示的任意一种存储设备的数据读取方法的步骤。
本发明实施例还提供一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现如图1至图3表示的任意一种存储设备的数据读取方法的步骤。
图5是本发明一实施例提供的终端设备的示意图。如图5所示，该实施例的终端设备5包括：处理器50、存储器51以及存储在所述存储器51中并可在所述处理器50上运行的计算机程序52。所述处理器50执行所述计算机程序52时实现上述各个存储设备的数据读取方法的实施例中的步骤，例如图1所示的步骤101至103。或者，所述处理器50执行所述计算机程序52时实现上述各装置实施例中各模块/单元的功能，例如图4所示模块401至403的功能。
所述计算机程序52可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器51中，并由所述处理器50执行，以完成本发明。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序52在所述终端设备5中的执行过程。
所述终端设备5可以是各种类型的手机、桌上型计算机、笔记本、掌上电脑及云端服务器等计算设备。所述终端设备可包括，但不仅限于，处理器50、存储器51。本领域技术人员可以理解，图5仅仅是终端设备5的示例，并不构成对终端设备5的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如所述终端设备5还可以包括输入输出设备、网络接入设备、总线等。
所述处理器50可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器51可以是所述终端设备5的内部存储单元，例如终端设备5的硬盘或内存。所述存储器51也可以是所述终端设备5的外部存储设备，例如 所述终端设备5上配备的插接式硬盘，智能存储卡(Smart Media Card,SMC)，安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)等。进一步地，所述存储器51还可以既包括所述终端设备5的内部存储单元也包括外部存储设备。所述存储器51用于存储所述计算机程序以及所述终端设备所需的其他程序和数据。所述存储器51还可以用于暂时地存储已经输出或者将要输出的数据。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
在本发明所提供的实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的系统实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或 使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实现上述实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括是电载波信号和电信信号。
以上所述实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种存储设备的数据读取方法，其中，包括：
    获取上位机下发的多条数据读取命令；
    对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；
    按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。
  2. 如权利要求1所述的存储设备的数据读取方法，其中，所述物理地址还包括flash的通道地址，所述按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器具体为：
    按照先遍历所述通道地址、然后遍历所述片选地址、最后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器。
  3. 如权利要求1或2所述的存储设备的数据读取方法，其中，在对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址之后，还包括：
    将所述多条数据读取命令依次排入预设的命令队列中的空余节点，每个空余节点排入一条数据读取命令；
    将所述命令队列中的数据读取命令依次按照对应的物理地址缓存到所述flash的各个存储单元的链表中，所述flash的各个存储单元的链表在flash的初始化过程中创建；
    所述将所述数据读取命令提交至所述flash的控制器具体为：
    将所述各个存储单元的链表中缓存的数据读取命令提交至所述flash的控制器。
  4. 如权利要求3所述的存储设备的数据读取方法，其中，所述将所述各个存储单元的链表中缓存的数据读取命令提交至所述flash的控制器包括：
    判断所述flash的所有存储单元的链表中缓存的数据读取命令的总数量是否大于第一阈值；
    若所述总数量大于第一阈值，则将目标存储单元的链表中缓存的第一条数据读取命令提交至所述flash的控制器，所述目标存储单元为按照所述遍历顺序确定的当前应当提交数据读取命令的存储单元。
  5. 如权利要求3所述的存储设备的数据读取方法，其中，所述将所述各个存储单元的链表中缓存的数据读取命令提交至所述flash的控制器包括：
    判断在预设时长内是否获取到新的数据读取命令；
    若在预设时长内没有获取到新的数据读取命令，则将所述各个存储单元的链表中缓存的数据读取命令全部提交至所述flash的控制器。
  6. 如权利要求5所述的存储设备的数据读取方法，其中，还包括：
    若在预设时长内获取到新的数据读取命令，则将所述新的数据读取命令排 入所述命令队列中的空余节点，并且按照对应的物理地址将所述新的数据读取命令缓存到所述flash的存储单元的链表中。
  7. 如权利要求6所述的存储设备的数据读取方法，其中，还包括：
    若所述命令队列中没有足够的空余节点，则将所述flash的各个存储单元的链表中缓存的数量与所述新的数据读取命令相同的数据读取命令提交至所述flash的控制器，并且在所述命令队列中清除提交至所述flash的控制器的数据读取命令，以形成能够排入所述新的数据读取命令的空余节点。
  8. 一种存储设备的数据读取装置，其中，包括：
    数据读取命令获取模块，用于获取上位机下发的多条数据读取命令；
    数据读取命令解析模块，用于对所述多条数据读取命令进行解析，分别得到每条所述数据读取命令对应的物理地址，所述物理地址包括flash的片选地址和存储单元地址；
    数据读取命令提交模块，用于按照先遍历所述片选地址、后遍历所述存储单元地址的顺序将所述数据读取命令提交至所述flash的控制器，以使所述控制器依次执行接收到的所述数据读取命令。
  9. 一种终端设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，其中，所述处理器执行所述计算机程序时实现如权利要求1至7中任一项所述的存储设备的数据读取方法的步骤。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其中，所述计算机程序被处理器执行时实现如权利要求1至7中任一项所述的存储设备的数据读取方法的步骤。
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