WO2019165786A1 - 数据传输方法、装置及系统、显示装置 - Google Patents

数据传输方法、装置及系统、显示装置 Download PDF

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Publication number
WO2019165786A1
WO2019165786A1 PCT/CN2018/111104 CN2018111104W WO2019165786A1 WO 2019165786 A1 WO2019165786 A1 WO 2019165786A1 CN 2018111104 W CN2018111104 W CN 2018111104W WO 2019165786 A1 WO2019165786 A1 WO 2019165786A1
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WIPO (PCT)
Prior art keywords
data
chip
identity
signal line
driving
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Application number
PCT/CN2018/111104
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English (en)
French (fr)
Inventor
段欣
罗信忠
陈明
邵喜斌
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/487,484 priority Critical patent/US11393418B2/en
Priority to EP18904495.1A priority patent/EP3761297A4/en
Publication of WO2019165786A1 publication Critical patent/WO2019165786A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes

Definitions

  • the present application relates to a data transmission method, device and system, and display device.
  • the display device may generally include a display panel and a panel driving circuit for driving the display panel, and the panel driving circuit may include a timing controller (T/CON), a gate driving circuit, and a source driving circuit.
  • the gate driving circuit includes a plurality of gate driving chips
  • the source driving circuit includes a plurality of source driver chips.
  • two types of signal lines are generally included, and the two types of signal lines include: a first signal line and a second signal line.
  • the signal transmission rate of the first signal line is smaller than the signal transmission rate of the second signal line.
  • the first signal line can be referred to as a low speed signal line, typically used to identify a level state; the second signal line can be referred to as a high speed signal line, typically used to transmit high speed differential signals.
  • a point-to-point high-speed signal transmission technology is generally used for signal transmission, which is characterized in that a pair is established between two chips of the panel driving circuit (for example, a timing controller and a source driving chip).
  • the timing controller is further provided with an additional first signal line, a plurality of source driving chips are connected in parallel, and are connected to the line, the first signal line is used to identify the level state to match the second
  • the signal line performs clock synchronization between the timing controller and the source driver chip.
  • the embodiment of the present application provides a data transmission method, device, system, and display device.
  • the technical solution is as follows:
  • a data transmission method which is applied to a controller, wherein the controller is connected to a plurality of parallel driving chips through a first signal line, and the plurality of driving chips are sorted according to a preset response feedback order.
  • the method includes:
  • the data request instruction includes an identity of an initial driver chip, and the initial driver chip is a driver chip of the plurality of driver chips;
  • the instructions transmitted on the first signal line each include a preamble, a start identifier, a data bit, and an end identifier that are sequentially arranged;
  • the preamble is used to instruct the receiving end to perform clock and phase calibration, the start identifier is used to indicate the start of data transmission, the data bit is used to carry target data, and the end identifier is used to indicate the end of data transmission.
  • the target data carried by the data bit of the data request instruction includes: a transmission mode of the first signal line, an identity of the initial driver chip, and a register to be configured on the plurality of driver chips. Address, and data checksum;
  • the target data carried by the data bit of each of the data response instructions includes: a transmission mode of the first signal line, an identity of a corresponding driver chip, an address of a register to be configured on the plurality of driver chips, and a corresponding Drive chip data, as well as data checksum.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • the initial driving chip is different from the last one of the plurality of driving chips
  • the data requesting instruction further includes an identity identifier of the termination driving chip, where the termination driving chip is a driving chip located behind the initial driving chip among the plurality of driving chips,
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of the response feedback.
  • the identifiers of the plurality of driver chips are characters with sequential features.
  • the response feedback order is an order obtained by sorting the sequential features of the identity.
  • the identifiers of the plurality of driving chips are different numbers.
  • the response feedback order is an order in which the identity identifiers are arranged from small to large.
  • the preamble is obtained by Manchester encoding from consecutive 0 bits of binary 0;
  • the starting identifier includes consecutive zeros of at least 2 bits of binary
  • the target data carried by the data bits is data obtained by Manchester coding
  • the end identifier includes a continuous one of at least 2 bits of binary.
  • the method further includes:
  • a clock calibration operation is performed upon detecting that the signal on the first signal line is pulled low.
  • a data transmission method is provided, which is applied to a first driving chip, where the first driving chip is any one of a plurality of driving chips, and the plurality of driving chips are connected in parallel, and pass through a first
  • the signal line is connected to the controller, and the plurality of driving chips are sorted according to a preset response feedback order, and the method includes:
  • a data response instruction includes an identity of the first driver chip and data of the first driver chip
  • the first data response instruction is used to trigger the plurality of driving chips to sequentially send data response commands according to the response feedback order from the first driving chip after the first driving chip, and each data response instruction
  • the identity of the corresponding driver chip and the data of the corresponding driver chip are included.
  • the instructions transmitted on the first signal line include a preamble, a start identifier, a data bit, and an end identifier that are sequentially arranged;
  • the preamble is used to instruct the receiving end to perform clock and phase calibration, the start identifier is used to indicate the start of data transmission, the data bit is used to carry target data, and the end identifier is used to indicate the end of data transmission.
  • the target data carried by the data bit of the data request instruction includes: a transmission mode of the first signal line, an identity of the initial driver chip, and a register to be configured on the plurality of driver chips. Address, and data checksum;
  • the target data carried by the data bit of each of the data response instructions includes: a transmission mode of the first signal line, an identity of a corresponding driver chip, an address of a register to be configured on the plurality of driver chips, and a corresponding Drive chip data, as well as data checksum.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • the initial driving chip is different from the last one of the plurality of driving chips, and the method further includes:
  • the third data response instruction includes an identity of the first driver chip and data of the first driver chip
  • the third data response instruction is used to trigger the plurality of driving chips to sequentially send data response instructions according to the response feedback order from the first driving chip after the first driving chip, and each data response instruction
  • the identity of the corresponding driver chip and the data of the corresponding driver chip are included.
  • the data requesting instruction further includes: ending the driving chip, wherein the terminating driving chip is a driving chip located after the initial driving chip of the plurality of driving chips, the method further comprising:
  • the identity identifier carried in the second data response instruction is the identity identifier of the previous driver chip
  • the response instruction includes an identity of the first driver chip and data of the first driver chip
  • the third data response instruction is used to trigger the plurality of driving chips to sequentially send data response instructions according to the response feedback order from the first driving chip after the first driving chip, and each data response instruction
  • the identity of the corresponding driver chip and the data of the corresponding driver chip are included.
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of the response feedback.
  • the identifiers of the plurality of driver chips are characters with sequential features.
  • the response feedback order is an order obtained by sorting the sequential features of the identity.
  • the identifiers of the plurality of driving chips are different numbers.
  • the response feedback order is an order in which the identity identifiers are arranged from small to large.
  • the preamble is obtained by Manchester encoding from consecutive 0 bits of binary 0;
  • the starting identifier includes consecutive zeros of at least 2 bits of binary
  • the target data carried by the data bits is data obtained by Manchester coding
  • the end identifier includes a continuous one of at least 2 bits of binary.
  • the method further includes:
  • a data transmission system including a timing controller and a plurality of source driving chips connected in parallel, wherein the timing controller is connected to a plurality of source driving chips connected in parallel through a first signal line, The plurality of source driver chips are sorted according to a preset response feedback order.
  • the timing controller is configured to generate a data request instruction, and send the data request instruction by using the first signal line, where the data request instruction includes an identity of a starting source driver chip, the starting source The driving chip is different from the last one of the plurality of source driving chips;
  • the initial source driving chip is configured to send a first data response instruction to the timing controller and the remaining source driving chips through the first signal line when receiving the data request instruction, the first
  • the data response instruction includes an identity of the starting source driver chip and data of the starting source driver chip;
  • Each of the source driving chips after the starting source driving chip is configured to detect the second data when receiving a second data response instruction sent by another source driving chip through the first signal line Whether the identity identifier carried in the response instruction is the identity of the previous source driver chip of the source driver chip; and the identity identifier carried in the second data response command is detected as the previous source driver chip And transmitting, by the first signal line, a third data response instruction to the timing controller and the remaining source driving chips by using the first signal line, where the third data response instruction includes an identity identifier and a location of the source driving chip Describe the data of the source driver chip.
  • the starting source driving chip is a first source driving chip that is arranged by the plurality of source driving chips in the response feedback order.
  • a data transmission apparatus which is applied to a controller, wherein the controller is connected to a plurality of parallel driving chips through a first signal line, and the plurality of driving chips are sorted according to a preset response feedback order.
  • the data transmission device includes:
  • One or more processors are One or more processors.
  • the memory stores one or more programs, the one or more programs being configured to be executed by the one or more processors, the one or more programs including instructions for:
  • the data request instruction includes an identity of an initial driver chip, and the initial driver chip is a driver chip of the plurality of driver chips;
  • the instructions transmitted on the first signal line each include a preamble, a start identifier, a data bit, and an end identifier that are sequentially arranged;
  • the preamble is used to instruct the receiving end to perform clock and phase calibration, the start identifier is used to indicate the start of data transmission, the data bit is used to carry target data, and the end identifier is used to indicate the end of data transmission.
  • the target data carried by the data bit of the data request instruction includes: a transmission mode of the first signal line, an identity of the initial driver chip, and a register to be configured on the plurality of driver chips. Address, and data checksum;
  • the target data carried by the data bit of each of the data response instructions includes: a transmission mode of the first signal line, an identity of a corresponding driver chip, an address of a register to be configured on the plurality of driver chips, and a corresponding Drive chip data, as well as data checksum.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • the initial driving chip is different from the last one of the plurality of driving chips
  • the one or more programs also include instructions for performing the following operations:
  • the data requesting instruction further includes an identity identifier of the termination driving chip, where the termination driving chip is a driving chip located behind the initial driving chip among the plurality of driving chips,
  • the one or more programs also include instructions for performing the following operations:
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of the response feedback.
  • the identifiers of the plurality of driver chips are characters with sequential features.
  • the response feedback order is an order obtained by sorting the sequential features of the identity.
  • the response feedback order is an order in which the identity identifiers are arranged from small to large.
  • the preamble is obtained by Manchester encoding by consecutive at least 8 bits of binary 0;
  • the starting identifier includes consecutive zeros of at least 2 bits of binary
  • the end identifier includes a continuous one of at least 2 bits of binary.
  • the one or more programs further include instructions for:
  • a clock calibration operation is performed upon detecting that the signal on the first signal line is pulled low.
  • One or more processors are One or more processors.
  • a data response instruction includes an identity of the first driver chip and data of the first driver chip
  • the first data response instruction is used to trigger the plurality of driving chips to sequentially send data response commands according to the response feedback order from the first driving chip after the first driving chip, and each data response instruction
  • the identity of the corresponding driver chip and the data of the corresponding driver chip are included.
  • the instructions transmitted on the first signal line each include a preamble, a start identifier, a data bit, and an end identifier that are sequentially arranged;
  • the preamble is used to instruct the receiving end to perform clock and phase calibration, the start identifier is used to indicate the start of data transmission, the data bit is used to carry target data, and the end identifier is used to indicate the end of data transmission.
  • the target data carried by the data bit of each of the data response instructions includes: a transmission mode of the first signal line, an identity of a corresponding driver chip, an address of a register to be configured on the plurality of driver chips, and a corresponding Drive chip data, as well as data checksum.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • the initial driver chip is different from the last one of the plurality of driver chips
  • the one or more programs further include instructions for:
  • the third data response instruction includes an identity of the first driver chip and data of the first driver chip
  • the third data response instruction is used to trigger the plurality of driving chips to sequentially send data response instructions according to the response feedback order from the first driving chip after the first driving chip, and each data response instruction
  • the identity of the corresponding driver chip and the data of the corresponding driver chip are included.
  • the data requesting instruction further includes terminating an identity of the driving chip, where the termination driving chip is a driving chip located behind the initial driving chip among the plurality of driving chips, the one or more programs It also contains instructions for doing the following:
  • the identity identifier carried in the second data response instruction is the identity identifier of the previous driver chip
  • the response instruction includes an identity of the first driver chip and data of the first driver chip
  • the third data response instruction is used to trigger the plurality of driving chips to sequentially send data response instructions according to the response feedback order from the first driving chip after the first driving chip, and each data response instruction
  • the identity of the corresponding driver chip and the data of the corresponding driver chip are included.
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of the response feedback.
  • the identifiers of the plurality of driver chips are characters with sequential features.
  • the response feedback order is an order obtained by sorting the sequential features of the identity.
  • the identifiers of the plurality of driving chips are different numbers.
  • the response feedback order is an order in which the identity identifiers are arranged from small to large.
  • the preamble is obtained by Manchester encoding from consecutive 0 bits of binary 0;
  • the starting identifier includes consecutive zeros of at least 2 bits of binary
  • the target data carried by the data bits is data obtained by Manchester coding
  • the end identifier includes a continuous one of at least 2 bits of binary.
  • the one or more programs further include instructions for:
  • a display device includes a controller and a plurality of driving chips
  • the controller includes the data transmission device of the fourth aspect
  • the plurality of driving chips include the data transmission device of the fifth aspect.
  • a data transmission apparatus including a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor implementing the computer program to implement the first The data transmission method described in the aspect.
  • a data transmission apparatus comprising: a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor implementing the second The data transmission method described in the aspect.
  • a computer readable storage medium storing a computer program that, when executed by a processor, implements the data transmission method of the first aspect.
  • a computer readable storage medium storing a computer program that, when executed by a processor, implements the data transmission method of the second aspect.
  • a computer program product comprising instructions, when executed on a computer, causes the computer to perform the data transfer method of the first aspect.
  • a computer program product comprising instructions which, when run on a computer, cause the computer to perform the data transfer method of the second aspect.
  • FIG. 1A is a schematic diagram of an application environment involved in various embodiments of the present application.
  • FIG. 1B is a schematic diagram of another application environment involved in various embodiments of the present application.
  • FIG. 2 is a schematic flowchart of a data transmission method according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of another data transmission method provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a format of an instruction transmitted on a first signal line according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of target data carried by data bits of a data request instruction according to an embodiment of the present application
  • FIG. 7 is a schematic diagram of target data carried by data bits of a data response command according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of target data carried by data bits of another data response instruction according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a data transmission system according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a data transmission apparatus according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another data transmission apparatus according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of still another data transmission apparatus according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of still another data transmission apparatus according to an embodiment of the present application.
  • FIG. 14 is a structural block diagram of another display device according to an embodiment of the present application.
  • FIG. 1A is a schematic diagram of an application environment of a data transmission method according to an embodiment of the present application.
  • the data transmission method is applied to a display device, where the display device includes a controller 01 and multiple The driving chip 02 is connected to the controller 01. At least one of the plurality of driving chips 02 is further connected to the display panel.
  • the plurality of driving chips 02 have a transmission function of returning data.
  • the display panel can be an in-cell touch display panel, and the in-cell touch display panel is a display panel integrated with a touch function layer (referred to as a touch layer), that is,
  • the OLED (Organic Light-Emitting Diode) display panel or the LCD (Liquid Crystal Display) display panel can be an OLED (Organic Light-Emitting Diode) display panel.
  • the plurality of driving chips may be respectively connected to the plurality of touch signal output terminals of the in-cell touch display panel.
  • the controller 01 is connected to the plurality of driving chips 02 through a plurality of second signal lines H.
  • the plurality of second signal lines H of the controller are connected to the plurality of driving chips one by one.
  • the signal in the second signal line is unidirectionally transmitted.
  • the controller is further connected to a first signal line L.
  • the plurality of driving chips are connected in parallel and connected to the first signal line L.
  • the The first signal line L has a bidirectional transmission function, and the plurality of driver chips are usually arranged in a pre-configured response feedback order.
  • the controller may send a data request instruction to the plurality of driving chips through the first signal line, and receive, by using the first signal line, a data response instruction that is sequentially sent by the plurality of driving chips from the initial driving chip according to the response feedback order to obtain the driving chip.
  • the data The response feedback sequence is used to identify the sequence in which the plurality of driver chips send data response instructions.
  • each driver chip has an identity
  • the identity of the multiple driver chips may be characters with sequential features
  • the response feedback order is an order sorted according to the sequential features of the identity.
  • the characters can be letters, numbers or words.
  • the IDs of the 4 driver chips can be: a, b, c, and d, or: 4, 3, 2, and 1, or: A, B, C, and D.
  • the identifiers of the multiple driver chips may be different numbers, and the response feedback order may be in the order of the identifiers being arranged from small to large.
  • the response feedback order can be The order of the four IDs from small to large, because X4 has the smallest identity, X1 has the largest identity, so after sorting, you can get: X4, X3, X2, and X1.
  • the order of the response feedback may also be in the order of the identifiers being arranged from the largest to the smallest, which is not limited by the embodiment of the present application.
  • the driving chip may be a source driving chip or a gate driving chip; the controller may be a timing controller, a system chip (English: System on Chip; SOC), and a micro control unit integrated in the timing controller (English: Any of the Microcontroller Units; MCUs.
  • FIG. 1B illustrates an example in which the controller is the timing controller 011 and the driving chip is the source driving chip 021.
  • the timing controller 011 is connected to the plurality of source driving chips 021 in a one-to-one correspondence by a plurality of second signal lines H, respectively.
  • the timing controller 011 is further connected to a first signal line L.
  • the plurality of source driving chips 021 are connected in parallel and connected to the first signal line L.
  • the first signal line L can be identified by a level state, for example, by the The first signal line L sets the pin of the source driving chip to a high level or a low level.
  • the second signal line may be a high speed signal line
  • the first signal line may be a low speed signal line.
  • the third signal line may also be a high-speed signal line, that is, the signal transmission rate of the second signal line and the The signal transmission rate of the three signal lines is greater than the signal transmission rate of the first signal line.
  • the second signal line and the third signal line are differential signal lines
  • the first signal line is a normal signal line.
  • the first signal line L can only be marked with a level state, for example, the pin of the source driving chip is set to a high level or a low level through the first signal line L. .
  • the first signal line has a single function and a low utilization rate.
  • the timing controller cannot obtain the data of the source driving chip through the first signal line L, which limits the implementation of certain functions, such as the touch function and the OLED compensation function.
  • the touch function requires scanning the position of the touch coordinate point at a higher frequency, that is, the source driving chip is required to send data to the timing controller in real time to notify the timing controller whether the touch operation and the touch coordinate point are detected.
  • the source driver chip When this function is implemented, the source driver chip is used for touch driving and display driving; the OLED compensation function requires real-time adjustment of the color and brightness of a certain position picture during the display process to avoid color cast or color. Uniform phenomenon, in order to achieve this function, the current position current, voltage and other relevant state data need to be used as the original data on which the compensation operation is based, which requires the source driver chip to send the source driver chip to the timing controller in real time. Display Data.
  • the first signal line L can perform data transmission in addition to the identification of the level state.
  • the timing controller can acquire the data of the source driving chip through the first signal line L, thereby implementing various functions. For example, when the touch function is implemented, the timing controller can obtain the data of the source driving chip in real time through the first signal line L, and then scan the position of the touch coordinate point at a higher frequency; in implementing the OLED compensation function, The timing controller can obtain the display data of the source driving chip in real time through the first signal line L, use the display data as the original data on which the compensation operation is based, and then perform a compensation operation, thereby real-time adjusting the color and brightness of the current position picture. To avoid color cast or uneven color.
  • FIG. 2 is a schematic flowchart diagram of a data transmission method according to an embodiment of the present application.
  • the data transmission method can be applied to the controller in FIG. 1A, and the controller is connected to a plurality of parallel driving chips through a first signal line, as shown in FIG. 2, the method includes:
  • a data request instruction is generated, the data request instruction including an identity of the initial driver chip, and the initial driver chip is a driver chip of the plurality of driver chips.
  • step 202 a data request instruction is sent to the plurality of driver chips through the first signal line.
  • step 203 a data response instruction that is sequentially sent by the plurality of driving chips from the initial driving chip in the order of response feedback is received by the first signal line, and each data response instruction includes an identifier of the corresponding driving chip and a corresponding driving chip. The data.
  • the controller receives, by using the first signal line, a data response instruction that is sent by the plurality of driving chips in order from the initial driving chip in order from the front to the back.
  • the response feedback sequence indicates that the plurality of driving chips themselves are sorted, and the arrangement positions of the plurality of driving chips can also be arranged in a sorting order.
  • FIG. 3 is a schematic flowchart of a data transmission method according to an embodiment of the present application.
  • the data transmission method can be applied to the first driving chip in FIG. 1A, the first driving chip is any one of the plurality of driving chips, the plurality of driving chips are connected in parallel, and is connected to the controller through a first signal line.
  • the plurality of driver chips are sorted according to a preset response feedback order. As shown in FIG. 3, the method includes:
  • step 301 when receiving the data request instruction sent by the controller through the first signal line, it is detected whether the identity of the initial driver chip carried in the data request instruction is the identity of the first driver chip.
  • step 302 after detecting that the identity of the initial driving chip is the identity of the first driving chip, sending a first data response instruction to the controller and the remaining driving chips through the first signal line, the first data response instruction
  • the identity of the first driver chip and the data of the first driver chip are included.
  • the first data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • the data transmission method after detecting that the identity of the initial driver chip carried in the data request instruction is the identity identifier of the first driver chip, the first driver chip can Transmitting, by the first signal line, a first data response instruction to the controller and the remaining driving chip, where the first data response instruction includes an identity of the first driving chip and data of the first driving chip, and the driving chip passes the first A signal line can transmit data of the driving chip to the controller, thereby enriching the function of the first signal line and improving the utilization of the first signal line.
  • FIG. 4 is a schematic flowchart diagram of a data transmission method according to an embodiment of the present application.
  • the data transmission method can be applied to the application environment shown in FIG. 1A.
  • the controller is connected to a plurality of parallel driving chips through a first signal line, and the plurality of driving chips are sorted according to a preset response feedback order.
  • the method may include:
  • step 401 the controller generates a data request instruction.
  • the data request instruction includes an identity of the initial driver chip, and the initial driver chip is a driver chip of the plurality of driver chips.
  • the controller may perform basic configuration on the plurality of driving chips in a broadcast manner based on the first signal line in advance, so that the driving chip has the function of returning data, and then performing step 401.
  • the controller can configure the identity of each driver chip in advance.
  • the controller may configure the identifier of the driving chip by setting the pin of the driving chip to a high level or a low level, or may use a method of writing an instruction to the internal driving chip to the driving chip. Identity is configured.
  • step 402 the controller transmits a data request instruction to the plurality of driver chips through the first signal line.
  • the controller may simultaneously send a data request instruction to the plurality of driver chips through the first signal line according to the preset frequency.
  • the preset frequency may be 500 kHz (kilohertz).
  • step 403 when receiving the data request instruction sent by the controller through the first signal line, the first driver chip detects whether the identity of the initial driver chip carried in the data request instruction is the identity of the first driver chip.
  • the first driving chip is any one of a plurality of driving chips.
  • the first driver chip detects whether the identity of the initial driver chip carried in the data request instruction is an identity of the first driver chip, so as to determine whether the first driver chip is the initial driver chip.
  • step 404 after detecting that the identity of the initial driver chip is the identity of the first driver chip, the first driver chip sends the first data response command to the controller and the remaining driver chips through the first signal line.
  • the remaining driving chips refer to the driving chips except the first driving chip among the plurality of driving chips connected in parallel with the first signal line.
  • the first driving chip When detecting that the identity of the initial driving chip is the identity of the first driving chip, indicating that the first driving chip is the initial driving chip, the first driving chip sends the first signal to the controller and the remaining driving chips through the first signal line.
  • a data response instruction, the first data response instruction including an identity of the first driver chip and data of the first driver chip.
  • the first data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • three driving chips are connected in parallel and connected to the controller through a first signal line.
  • the three driver chips are: X1, X2 and X3, and the IDs of the three driver chips are X1, X2 and X3, respectively, and the three driver chips are sorted according to the preset response feedback order: X1, X2 and X3.
  • the first driver chip is X1
  • the identity of the initial driver chip carried in the data request command sent by the controller through the first signal line is X1
  • X1 detects that the identity of the initial driver chip carried in the data request command is The identity of the first driver chip, X1 sends a first data response command to the controller, X2 and X3 through the first signal line.
  • each instruction transmitted on the first signal line includes a preamble (English: preamble) and a start ( English: start) identification, data bits (also known as: transmission body, English: transaction body) and end (English: stop) identification.
  • the preamble is used to indicate the clock and phase calibration of the receiving end, and the receiving end (the timing controller or the source driving chip) performs the clock transmission according to the content of the preamble when detecting the preamble transmission on the first signal line.
  • Phase adjustment means that the clock is kept in line with the clock at the transmitting end, and the phase is the same as the transmitting end.
  • the receiving end adjusts the clock and phase during the process of receiving the preamble, and after the preamble transmission ends, the clock and phase are adjusted.
  • the start identifier is used to indicate the start of data transmission, the data bit is used to carry the target data, and the end identifier is used to indicate the end of the data transmission.
  • the preamble can be obtained by successive Manchester encoding of at least 8 bits of binary 0.
  • FIG. 5 schematically illustrates that the preamble is obtained by Manchester coding from consecutive 8-bit binary 0; the start identifier can hold a low level signal and no Manchester coding is performed, and the start identifier can include Continuous at least 2 bits of binary 0,
  • FIG. 5 is schematically illustrated by the start identifier being a continuous 2-bit binary 0; the target data carried by the data bits is data obtained by Manchester coding; the end marker can be kept high
  • the signal is not Manchester coded, the end marker may comprise a continuous at least 2 bit binary 1 and FIG. 5 is schematically illustrated with the end 2 identified as a continuous 2 bit binary.
  • the Manchester coding can be used to make the data generate a significant transition edge and facilitate the detection of the data. Therefore, the data to be encoded in the embodiment of the present application can be Manchester coded. However, in actual applications, other coding methods may be used or not. coding.
  • the first bit of the target data in the data bit may generate a hop edge with the start identifier ( That is, the first bit of the target data in the data bit is different from the last bit value of the start identifier, for example, the first bit of the target data in the data bit is 1, the last bit of the start identifier is 0), and the target data in the data bit
  • the last bit can generate a transition edge with the end marker (ie, the last digit of the target data in the data bit is different from the first digit of the end identifier, for example, the last digit of the target data in the data bit is 0, and the first digit of the end identifier is 1 ).
  • the above transition edge facilitates effective identification of data at the receiving end.
  • the target data carried by the data bit of the data request instruction generated by the controller may include: a transmission mode of the first signal line, an identity of the initial driver chip, and an address of a register to be configured on the plurality of driver chips. And the data checksum.
  • the transmission mode of the first signal line is a group read mode (English: Bust Read Mode) mode, and the group read mode indicates that the controller receives data sequentially sent by the plurality of driver chips from the start driver chip according to the response feedback sequence.
  • the signal of the transmission mode of the first signal line can occupy 2 bits of the data bits.
  • the data checksum in the data bits is used to ensure the accuracy of the data received at the receiving end.
  • the first driving chip may be the last one of the plurality of driving chips, or may not be the last one of the plurality of driving chips.
  • the controller passes the first signal line.
  • the data response command sent by the first driving chip can be received, enriching the function of the first signal line, and improving the utilization of the first signal line.
  • the controller passes the first signal line.
  • the data sent by the plurality of driving chips can be received through the first signal line, and the data of the plurality of driving chips is read at one time, and in the process, the number of times the data request instruction is sent is small, and more The time required for the driver chip to return data is shorter, and the efficiency of returning data is higher.
  • the controller passes The first signal line receives the data response command sequentially sent by the plurality of driving chips from the initial driving chip according to the response feedback sequence, and may include: the controller receives the plurality of driving chips through the first signal line according to the response feedback sequence, and starts from the initial driving.
  • the last driver chip is the last driver chip of the plurality of driver chips sorted according to the preset response feedback order.
  • the first driving chip may perform the following steps 405 to 406.
  • step 405 after detecting that the identity of the initial driver chip is not the identity of the first driver chip, when the first driver chip receives the second data response command sent by the other driver chip through the first signal line.
  • the first driver chip detects whether the identity carried in the second data response command is an identity of a previous driver chip of the first driver chip.
  • the driver chip whose identity identifier is the same as the identity of the initial driver chip is based on the data request command sent by the controller.
  • the remaining driver chip sends a data response command, and if the data response command is the second data response command, the first driver chip receives another driver chip (ie, the driver chip whose identity is the same as the identity of the initial driver chip).
  • the second data response command sent by the first signal line.
  • the first driver chip detects whether the identity identifier carried in the second data response command is an identity of a previous driver chip of the first driver chip, so as to determine whether the first signal is passed.
  • the line sends the corresponding data response command.
  • step 406 after detecting that the identity carried in the second data response command is the identity of the previous driver chip, the first driver chip sends the third data response command to the controller and the remaining driver chips through the first signal line. .
  • the third data response instruction includes an identity of the first driver chip and data of the first driver chip.
  • the third data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of response feedback.
  • the three driver chips are sorted according to the preset response feedback order: X1, X2 and X3, that is, the first drivers of the three driver chips arranged in response feedback order.
  • the chip is X1, then the starting driver chip is X1.
  • Step 401 to step 406, X1 detects that the identity of the initial driver chip carried in the data request command sent by the controller through the first signal line is an identity of X1, and X1 passes the first signal line to the controller and the remaining drivers.
  • the chip sends a data response command, where the data response command includes the identity of X1 and the data of X1; X2 detects the identity of X1, which is the previous driver chip whose identity is X2 carried in the data response command sent by X1, and X2 passes the A signal line sends a data response command to the controller and the remaining driver chips, the data response command includes the X2 identity and the X2 data; and the X3 detects the previous driver chip with the identity X3 carried in the data response command sent by the X2. That is, the identity of X2, X3 sends a data response command to the controller and the remaining driver chips through the first signal line, the data response command includes the identity of X3 and the data of X3.
  • the controller may sequentially receive multiple drivers.
  • the data sent by the chip realizes reading data of a plurality of driving chips at one time.
  • the controller can sequentially receive the data sent by all the driving chips, thereby realizing reading the data of all the driving chips at one time.
  • the data request instruction sent by the controller may further include terminating the identity of the driving chip, and terminating the driving chip into a driving chip located after the initial driving chip among the plurality of driving chips.
  • the controller can receive the data response command sent by the specified plurality of driver chips through the first signal line.
  • FIG. 8 exemplarily shows a schematic diagram of a data request instruction including an identity of a termination driver chip.
  • the location of the identity of the terminating driver chip can be located after the identity of the originating driver chip in the data request instruction.
  • the controller receives, by using the first signal line, a data response instruction that is sequentially sent by the plurality of driving chips from the initial driving chip according to the response feedback sequence, and may include: the controller receives the plurality of driving chips through the first signal line according to the response feedback order, The data response command is sent from the start driver chip to the termination drive chip.
  • the first driver chip when the data request instruction further includes terminating the identity of the driver chip, the first driver chip may further perform the following steps 407 to 411.
  • step 407 after detecting that the identity of the initial driver chip is not the identity of the first driver chip, the first driver chip records the identity of the termination driver chip.
  • step 408 when receiving a second data response instruction sent by another driving chip through the first signal line, the first driving chip detects whether the identity identifier carried in the second data response instruction is the previous one of the first driving chip. The identity of the driver chip.
  • step 409 after detecting that the identity identifier carried in the second data response instruction is the identity of the previous driver chip, the first driver chip detects whether the identity of the previous driver chip is the identity of the termination driver chip.
  • step 410 when the identity of the current driver chip is not to terminate the identity of the driver chip, the first driver chip sends a third data response command to the controller and the remaining driver chips through the first signal line.
  • the third data response instruction includes an identity of the first driver chip and data of the first driver chip.
  • step 411 when the identity of the current one of the driving chips is to terminate the identity of the driving chip, the first driving chip ends the action.
  • the third data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of response feedback.
  • the three driver chips are sorted according to the preset response feedback order: X1, X2 and X3, that is, the first drivers of the three driver chips arranged in response feedback order.
  • the chip is X1, then the starting driver chip is X1.
  • the termination driver chip is the driver chip X2 located after the start driver chip. X1, by performing step 403 to step 404, detecting that the identity of the initial driver chip carried in the data request command sent by the controller through the first signal line is an identity of X1, and X1 passes the first signal line to the controller and the rest.
  • the driving chip sends a data response command, where the data response command includes the identifier of X1 and the data of X1; X2 performs step 407 to step 410 to record the identity of the terminating driver chip X2, and detects that the data response command sent by X1 is carried.
  • the identity is the identity of the previous driver chip of X2, and the identity of the previous driver chip is not the identity of the termination driver chip, and X2 sends a data response command to the controller and the remaining driver chips through the first signal line, the data
  • the response command includes the identity of X2 and the data of X2;
  • X3 records the identity of the termination driver chip X2 by performing steps 407 to 410, and detects the previous driver chip of the identity identifier X3 carried in the data response instruction sent by X2.
  • Identity, and the identity of the previous driver chip is the identity of the termination driver chip.
  • X3 operation is terminated, i.e., not transmitting a data X3 identity X3 and X3 in response to an instruction of the controller and the rest through the first signal line driver chip.
  • the controller may sequentially receive data sent by the specified plurality of driving chips according to actual requirements, so as to read data of the specified plurality of driving chips at one time, thereby avoiding Get unwanted data.
  • the designated plurality of driving chips are driving chips whose identity belongs to the range of the identity of the initial driving chip to the identity of the termination driving chip. For example, if there are 12 driver chips in total, the controller can only receive data sent by the first 4 driver chips.
  • the data bit of the data response instruction may carry a terminator for indicating that the data response instruction is currently sent to the controller.
  • the driver chip is the termination driver chip.
  • the terminator may be a preset symbol such as "*", "#", or the like.
  • the controller may also filter out data required from all the driving chips after receiving data transmitted from all the driving chips.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • the preset duration can be 10 microseconds.
  • step 412 in the process of signal transmission through the first signal line, when an abnormality occurs in the first driving chip, the first driving chip pulls down the signal on the first signal line.
  • step 412 the controller performs a clock calibration operation upon detecting that the signal on the first signal line is pulled low.
  • the signal transmitted through the first signal line includes a data request instruction and a data response instruction.
  • the driving chip in the process that the driving chip returns data to the controller in real time, the driving chip may not be based on the second signal line due to some external factors (the second signal line may be referred to as a high-speed signal line, and is generally used.
  • the second signal line may be referred to as a high-speed signal line, and is generally used.
  • the clock is out of lock, and the controller cannot transmit the high-speed differential signal to the driver chip through the second signal line.
  • the clock state feedback can be performed through the first signal line transmitted bidirectionally.
  • the controller Since the controller is connected to the plurality of driving chips connected in parallel through the first signal line, when any of the driving chips is abnormal, the driving chip pulls the signal on the first signal line low, and at this time, the first signal line No other data is transmitted to the controller, then the controller can receive a low level signal for a period of time, and determine that there is a clock unlocked state of the current driver chip, and then the controller performs a clock calibration operation, thereby avoiding the clock loss. The failure caused by the lock cannot be restored, and the basic application of the point-to-point interface architecture is avoided.
  • the controller can generate a data request instruction, and then send a data request instruction through the first signal line, and then receive multiple driving chips from the initial driving chip through the first signal line.
  • the data response command is sequentially sent in accordance with the response feedback sequence.
  • the controller can acquire the data of the driving chip through the first signal line, thereby enriching the function of the first signal line and improving the utilization of the first signal line. rate.
  • the embodiment of the present application further provides a data transmission system.
  • a timing controller and a plurality of source driving chips connected in parallel are provided.
  • the timing controller is connected to a plurality of driving chips connected in parallel through a first signal line.
  • the source driver chips are sorted according to a preset response feedback order.
  • the timing controller is configured to generate a data request instruction, and send a data request instruction by using a first signal line, where the data request instruction includes an identity of the starting source driving chip, the starting source driving chip and the plurality of sources The last source driver chip in the pole driver chip is different.
  • a start source driver chip configured to send a first data response instruction to the timing controller and the remaining source driver chips through the first signal line when receiving the data request instruction, where the first data response instruction includes a start source driver The identity of the chip and the data of the starting source driver chip.
  • each of the source driving chips after the source driving chip is configured to detect the identity carried in the second data response instruction when receiving the second data response command sent by the other source driving chip through the first signal line Identifying whether the identity of the previous source driver chip of the source driver chip is the first signal line timing after detecting that the identity carried in the second data response command is the identity of the previous source driver chip
  • the controller and the remaining source driver chips send a third data response command including an identity of the source driver chip and data of the source driver chip.
  • the starting source driving chip is a first source driving chip arranged by the plurality of source driving chips in the order of response feedback.
  • X1, X2, X3, X4, X5, and X6 the identity of X1 is 1, the identity of X2 is 2, and the identity of X3 is 3.
  • X4 has an identity of 4
  • X5 has an identity of 5
  • X6 has an identity of 6.
  • the response feedback order may be in the order of the six identity identifiers, since X1 has the smallest identity and the identity of X6.
  • the logo is the largest, so after sorting you can get: X1, X2, X3, X4, X5 and X6.
  • the starting source driver chip is X1.
  • the timing controller is configured to generate a data request instruction and send a data request instruction through the first signal line, the data request instruction including an identity of X1: 1.
  • X1 is a starting source driving chip, and X1 is configured to send a data response instruction to the timing controller and the remaining source driving chips through the first signal line when receiving the data request instruction sent by the timing controller, the data response instruction includes X1's identity and X1's data.
  • X2, X3, X4, X5, and X6 are configured to detect, when receiving the data response instruction sent by X1, whether the identity carried in the data response instruction is the identity of the previous source driver chip. Since X2 detects that the identity carried in the data response instruction is the identity of its previous source driver chip, X2 sends a data response command to the timing controller and the remaining source driver chips through the first signal line, the data The response command includes the identity of X2 and the data of X2.
  • X3, X4, X5 and X6 are used to detect whether the identity carried in the data response instruction is the identity of the previous source driver chip when the data response command sent by the X2 is received, and the data is detected by X3.
  • the identity carried in the response command is the identity of the previous source driver chip of the user, so X3 sends a data response command to the timing controller and the remaining source driver chips through the first signal line, the data response command including the identity of X3. Identification and X3 data.
  • X4, X5, and X6 also sequentially send data response commands to the timing controller and the remaining source driver chips through the first signal line, the data response instructions including the identity of the corresponding source driver chip and the corresponding source. Drive the data of the chip.
  • the timing controller sequentially receives the data response commands sent by X1, X3, X4, X5, and X6 through the first signal line.
  • FIG. 9 only schematically shows a schematic diagram of the next source driver chip of the source driver chip receiving a data response command and detecting an identity identifier carried in the data response command.
  • the timing controller generates a data request instruction, and sends a data request instruction through the first signal line, where the data request instruction includes an identity of the starting source driver chip, and the start
  • the source driver chip is different from the last source driver chip of the plurality of source driver chips, and the initial source driver chip can drive the chip to the timing controller and the remaining source through the first signal line when receiving the data request command.
  • each of the driving chips after the starting source driving chip detects the second data response instruction when receiving the second data response instruction sent by the other source driving chip through the first signal line
  • the third data response command is sent to the timing controller and the remaining source driver chips through the first signal line, and the timing controller passes the first
  • a signal line can acquire data of the source driving chip, and realize reading data of the plurality of source driving chips at one time.
  • Fu is the function of the first signal line, to improve the utilization of the first signal line, it is possible to realize a variety of functions can be applied to real-time source driving chips required return data to the timing controller scene.
  • the embodiment of the present application provides a data transmission device, which is applied to a controller.
  • the controller is connected to a plurality of parallel driving chips through a first signal line, and the plurality of driving chips are sorted according to a preset response feedback order.
  • the data transmission device 1000 includes:
  • the generating module 1001 is configured to generate a data request instruction, where the data request instruction includes an identifier of the initial driving chip, and the initial driving chip is a driving chip of the plurality of driving chips.
  • the sending module 1002 is configured to send a data request instruction to the plurality of driving chips by using the first signal line.
  • the receiving module 1003 is configured to receive, by using the first signal line, data response commands sequentially sent by the plurality of driving chips from the initial driving chip according to the response feedback sequence, where each data response instruction includes an identifier of the corresponding driving chip and a corresponding driving Chip data.
  • the generating module generates a data request instruction
  • the sending module sends the data request instruction through the first signal line
  • the receiving module receives the plurality of driving chips through the first signal line, and starts to respond according to the starting driving chip.
  • the feedback response sequence sequentially sends the data response command.
  • the controller can acquire the data of the driving chip through the first signal line, thereby enriching the function of the first signal line and improving the utilization of the first signal line.
  • the instructions transmitted on the first signal line each include a preamble, a start identifier, a data bit, and an end identifier that are sequentially arranged;
  • the preamble is used to instruct the receiving end to perform clock and phase calibration, the initial identifier is used to indicate the start of data transmission, the data bit is used to carry the target data, and the end identifier is used to indicate the end of the data transmission.
  • the target data carried by the data bit of the data request instruction includes: a transmission mode of the first signal line, an identity of the initial driver chip, an address of a register to be configured on the plurality of driver chips, and a data checksum.
  • the transmission mode of the first signal line is a group read mode.
  • the target data carried by the data bits of each data response instruction includes: a transmission mode of the first signal line, an identity of the corresponding driver chip, an address of a register to be configured on the plurality of driver chips, a data of the corresponding driver chip, and Data checksum.
  • the transmission mode of the first signal line is a reply transmission mode.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • the initial driving chip is different from the last one of the plurality of driving chips
  • the receiving module 1003 is specifically configured to:
  • the data requesting instruction may further include: terminating the identity of the driving chip, and terminating the driving chip into a driving chip located after the initial driving chip among the plurality of driving chips, and correspondingly, the receiving module 1003, specifically for:
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of response feedback.
  • the identifiers of the plurality of driver chips are characters having sequential features
  • the response feedback order is an order obtained by sorting the sequential features of the identity identifiers.
  • the identifiers of the plurality of driver chips are different numbers, and the response feedback order is an order in which the identifiers are arranged from small to large.
  • the preamble is obtained by Manchester encoding from at least 8 consecutive binary 0's; the initial identifier includes consecutive at least 2 bits of binary 0; the target data carried by the data bits is data obtained by Manchester encoding; the end identifier includes Continuous at least 2 bits of binary ones.
  • FIG. 11 is a schematic structural diagram of another data transmission apparatus provided on the basis of FIG. 10 according to an embodiment of the present application. Further, as shown in FIG. 11, the data transmission device 1000 may further include:
  • the processing module 1004 is configured to perform a clock calibration operation when detecting that the signal on the first signal line is pulled low during signal transmission through the first signal line.
  • the generating module generates a data request instruction, and the sending module sends a data request instruction through the first signal line, and then the receiving module receives the plurality of driving chips from the first signal line from the start.
  • the driving chip starts to send the data response command in sequence according to the response feedback sequence.
  • the controller can acquire the data of the driving chip through the first signal line, thereby enriching the function of the first signal line and improving the first signal line. Utilization.
  • the embodiment of the present application provides another data transmission device, which is applied to a first driving chip.
  • the first driving chip is any one of a plurality of driving chips, and the plurality of driving chips are connected in parallel, and A signal line is connected to the controller, and the plurality of driver chips are sorted according to a preset response feedback order.
  • the data transmission device 1200 includes:
  • the first detecting module 1201 is configured to: when receiving the data request instruction sent by the controller by using the first signal line, detecting whether the identity of the initial driving chip carried in the data requesting instruction is an identity of the first driving chip.
  • the first sending module 1202 is configured to: after detecting that the identity of the initial driving chip is the identity of the first driving chip, send a first data response instruction to the controller and the remaining driving chips by using the first signal line, where the first The data response instruction includes an identity of the first driver chip and data of the first driver chip.
  • the first data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • the first sending module can pass the first signal line to the controller and The remaining driving chip sends a first data response instruction, where the first data response instruction includes an identifier of the first driving chip and data of the first driving chip, and the driving chip can send data to the controller through the first signal line compared to the related technology. Therefore, the function of the first signal line is enriched, and the utilization rate of the first signal line is improved.
  • the instructions transmitted on the first signal line each include a preamble, a start identifier, a data bit, and an end identifier that are sequentially arranged;
  • the preamble is used to instruct the receiving end to perform clock and phase calibration, the initial identifier is used to indicate the start of data transmission, the data bit is used to carry the target data, and the end identifier is used to indicate the end of the data transmission.
  • the target data carried by the data bit of the data request instruction includes: a transmission mode of the first signal line, an identity of the initial driver chip, an address of a register to be configured on the plurality of driver chips, and a data checksum.
  • the transmission mode of the first signal line is a group read mode.
  • the target data carried by the data bits of each data response instruction includes: a transmission mode of the first signal line, an identity of the corresponding driver chip, an address of a register to be configured on the plurality of driver chips, a data of the corresponding driver chip, and Data checksum.
  • the transmission mode of the first signal line is a reply transmission mode.
  • the time intervals between two adjacent instructions transmitted on the first signal line are equal, and are all preset durations.
  • FIG. 13 is a schematic structural diagram of another data transmission device provided on the basis of FIG. 12 in the embodiment of the present application. Further, as shown in FIG. 13, the data transmission device 1200 may further include:
  • the second detecting module 1203 is configured to: after detecting that the identity of the initial driving chip is not the identity of the first driving chip, when receiving the second data response instruction sent by the other driving chip through the first signal line, Detecting whether the identity carried in the second data response instruction is an identity of a previous driver chip of the first driver chip.
  • the second sending module 1204 is configured to: after detecting that the identity identifier carried in the second data response command is the identity of the previous driver chip, send the third data response command to the controller and the remaining driver chips through the first signal line,
  • the third data response instruction includes an identity of the first driver chip and data of the first driver chip.
  • the third data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • the data requesting instruction may further include: terminating the identity of the driving chip, and terminating the driving chip into a driving chip located after the initial driving chip among the plurality of driving chips.
  • the data transmission device 1200 may further include:
  • the recording module 1205 is configured to record the identity of the termination driver chip after detecting that the identity of the initial driver chip is not the identity of the first driver chip.
  • the third detecting module 1026 is configured to: when receiving the second data response instruction sent by the other driving chip through the first signal line, detecting whether the identity identifier carried in the second data response instruction is the previous driving of the first driving chip The identity of the chip.
  • the fourth detecting module 1207 is configured to detect, after detecting that the identity identifier carried in the second data response command is the identity of the previous driving chip, whether the identity of the previous driving chip is the identity of the terminating driving chip.
  • the third sending module 1208 is configured to: when the identity of the current one of the driving chips is not to terminate the identity of the driving chip, send a third data response instruction to the controller and the remaining driving chips through the first signal line, the third data response instruction The identity of the first driver chip and the data of the first driver chip are included.
  • the processing module 1209 is configured to end the action when the identity of the current one of the driver chips is to terminate the identity of the driver chip.
  • the third data response instruction is configured to trigger the plurality of driving chips to sequentially send the data response instructions according to the response feedback sequence from the first driving chip after the first driving chip, where each data response instruction includes an identifier of the corresponding driving chip. And the corresponding driver chip data.
  • the initial driving chip is a first driving chip that is arranged by the plurality of driving chips in the order of response feedback.
  • the identifiers of the plurality of driver chips are characters having sequential features
  • the response feedback order is an order obtained by sorting the sequential features of the identity identifiers.
  • the identifiers of the plurality of driver chips are different numbers, and the response feedback order is an order in which the identifiers are arranged from small to large.
  • the preamble is obtained by Manchester encoding from at least 8 consecutive binary 0's; the initial identifier includes consecutive at least 2 bits of binary 0; the target data carried by the data bits is data obtained by Manchester encoding; the end identifier includes Continuous at least 2 bits of binary ones.
  • the data transmission device 1200 may further include:
  • the first sending module can pass the first signal after detecting that the identity of the initial driving chip carried in the data requesting instruction is the identity of the first driving chip.
  • the line sends a first data response instruction to the controller and the remaining driver chip, where the first data response instruction includes the identity of the first driver chip and the data of the first driver chip, and the driver chip can pass the first signal line compared to the related technology.
  • Sending data to the controller enriches the function of the first signal line and improves the utilization of the first signal line.
  • the embodiment of the present application provides a display device, including a controller and a plurality of driving chips, the plurality of driving chips including the first driving chip, and a connection manner of the controller and each driving chip may refer to FIG. 1A above;
  • the data transmission device shown in FIG. 10 or FIG. 11 is included;
  • the plurality of drive chips include the data transmission device shown in FIG. 12 or FIG.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 14 is a block diagram showing the structure of a display device 1400 provided by an exemplary embodiment of the present application.
  • the device 1400 can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the apparatus 1400 includes a processor 1401 and a memory 1402.
  • Processor 1401 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like.
  • the processor 1401 may be configured by at least one of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). achieve.
  • the processor 1401 may also include a main processor and a coprocessor.
  • the main processor is a processor for processing data in an awake state, which is also called a CPU (Central Processing Unit); the coprocessor is A low-power processor for processing data in standby.
  • the processor 1401 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and rendering of the content that the display needs to display.
  • the processor 1401 may further include an AI (Artificial Intelligence) processor for processing computational operations related to machine learning.
  • AI Artificial Intelligence
  • Memory 1402 can include one or more computer readable storage media, which can be non-transitory.
  • the memory 1402 may also include high speed random access memory, as well as non-volatile memory such as one or more magnetic disk storage devices, flash memory storage devices.
  • the non-transitory computer readable storage medium in the memory 1402 is configured to store at least one instruction for execution by the processor 1401 to implement data transmission provided by the method embodiments of the present application. method.
  • the apparatus 1400 can also optionally include a peripheral device interface 1403 and at least one peripheral device.
  • the processor 1401, the memory 1402, and the peripheral device interface 1403 may be connected by a bus or a signal line.
  • Each peripheral device can be connected to the peripheral device interface 1403 via a bus, a signal line, or a circuit board.
  • the peripheral device includes at least one of a radio frequency circuit 1404, a display screen 1405, a camera 1406, an audio circuit 1407, a positioning component 1408, and a power source 1409.
  • the RF circuit 1404 is configured to receive and transmit an RF (Radio Frequency) signal, also referred to as an electromagnetic signal.
  • Radio frequency circuit 1404 communicates with the communication network and other communication devices via electromagnetic signals.
  • the RF circuit 1404 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal.
  • the radio frequency circuit 1404 includes an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a subscriber identity module card, and the like.
  • Radio frequency circuitry 1404 can communicate with other devices via at least one wireless communication protocol.
  • the wireless communication protocol includes, but is not limited to, a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G, and 5G), a wireless local area network, and/or a WiFi (Wireless Fidelity) network.
  • the RF circuit 1404 may also include NFC (Near Field Communication) related circuitry, which is not limited in this application.
  • the display 1405 is used to display a UI (User Interface).
  • the UI can include graphics, text, icons, video, and any combination thereof.
  • the display 1405 also has the ability to capture touch signals over the surface or surface of the display 1405.
  • the touch signal can be input to the processor 1401 as a control signal for processing.
  • the display 1405 can also be used to provide virtual buttons and/or virtual keyboards, also referred to as soft buttons and/or soft keyboards.
  • the display screen 1405 can be one, setting the front panel of the device 1400; in other embodiments, the display screen 1405 can be at least two, respectively disposed on different surfaces of the device 1400 or in a folded design; In still other embodiments, display screen 1405 can be a flexible display screen disposed on a curved surface or folded surface of device 1400. Even the display screen 1405 can be set to a non-rectangular irregular pattern, that is, a profiled screen. Display screen 1405 can include an LCD display panel or an OLED display panel.
  • Camera component 1406 is used to capture images or video.
  • camera assembly 1406 includes a front camera and a rear camera.
  • the front camera is placed on the front panel of the unit and the rear camera is placed on the back of the unit.
  • the rear camera is at least two, which are respectively a main camera, a depth camera, a wide-angle camera, and a telephoto camera, so as to realize the background blur function of the main camera and the depth camera, and the main camera Combine with a wide-angle camera for panoramic shooting and VR (Virtual Reality) shooting or other integrated shooting functions.
  • camera assembly 1406 can also include a flash.
  • the flash can be a monochrome temperature flash or a two-color temperature flash.
  • the two-color temperature flash is a combination of a warm flash and a cool flash that can be used for light compensation at different color temperatures.
  • the audio circuit 1407 can include a microphone and a speaker.
  • the microphone is used to collect sound waves of the user and the environment, and convert the sound waves into electrical signals for processing to the processor 1401 for processing, or input to the RF circuit 1404 for voice communication.
  • the microphones may be multiple, respectively disposed at different locations of the device 1400.
  • the microphone can also be an array microphone or an omnidirectional acquisition microphone.
  • the speaker is then used to convert electrical signals from the processor 1401 or the RF circuit 1404 into sound waves.
  • the speaker can be a conventional film speaker or a piezoelectric ceramic speaker.
  • the audio circuit 1407 can also include a headphone jack.
  • the positioning component 1408 is used to locate the current geographic location of the device 1400 to implement navigation or LBS (Location Based Service).
  • the positioning component 1408 can be a positioning component based on a US-based GPS (Global Positioning System), a Chinese Beidou system, or a Russian Greiner system or the European Union's Galileo system.
  • Power source 1409 is used to power various components in device 1400.
  • the power source 1409 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery.
  • the rechargeable battery can support wired charging or wireless charging.
  • the rechargeable battery can also be used to support fast charging technology.
  • device 1400 also includes one or more sensors 1410.
  • the one or more sensors 1410 include, but are not limited to, an acceleration sensor 1411, a gyro sensor 1412, a pressure sensor 1413, a fingerprint sensor 1414, an optical sensor 1415, and a proximity sensor 1416.
  • the acceleration sensor 1411 can detect the magnitude of the acceleration on the three coordinate axes of the coordinate system established by the device 1400.
  • the acceleration sensor 1411 can be used to detect components of gravity acceleration on three coordinate axes.
  • the processor 1401 can control the touch display screen 1405 to display the user interface in a landscape view or a portrait view according to the gravity acceleration signal collected by the acceleration sensor 1411.
  • the acceleration sensor 1411 can also be used for the acquisition of game or user motion data.
  • the gyro sensor 1412 can detect the body direction and the rotation angle of the device 1400, and the gyro sensor 1412 can cooperate with the acceleration sensor 1411 to collect the user's 3D motion on the device 1400. Based on the data collected by the gyro sensor 1412, the processor 1401 can implement functions such as motion sensing (such as changing the UI according to the user's tilting operation), image stabilization at the time of shooting, game control, and inertial navigation.
  • functions such as motion sensing (such as changing the UI according to the user's tilting operation), image stabilization at the time of shooting, game control, and inertial navigation.
  • Pressure sensor 1413 can be disposed on a side frame of device 1400 and/or a lower layer of touch display screen 1405.
  • the processor 1401 performs left and right hand recognition or shortcut operation according to the holding signal collected by the pressure sensor 1413.
  • the processor 1401 controls the operability control on the UI interface according to the user's pressure operation on the touch display screen 1405.
  • the operability control includes at least one of a button control, a scroll bar control, an icon control, and a menu control.
  • the fingerprint sensor 1414 is configured to collect the fingerprint of the user, and the processor 1401 identifies the identity of the user according to the fingerprint collected by the fingerprint sensor 1414, or the fingerprint sensor 1414 identifies the identity of the user according to the collected fingerprint. Upon identifying that the user's identity is a trusted identity, the processor 1401 authorizes the user to perform related sensitive operations including unlocking the screen, viewing encrypted information, downloading software, paying and changing settings, and the like. Fingerprint sensor 1414 can be placed on the front, back or side of device 1400. When the device 1400 is provided with a physical button or vendor logo, the fingerprint sensor 1414 can be integrated with a physical button or vendor logo.
  • Optical sensor 1415 is used to collect ambient light intensity.
  • the processor 1401 can control the display brightness of the touch display 1405 based on the ambient light intensity acquired by the optical sensor 1415. Specifically, when the ambient light intensity is high, the display brightness of the touch display screen 1405 is raised; when the ambient light intensity is low, the display brightness of the touch display screen 1405 is lowered.
  • the processor 1401 can also dynamically adjust the shooting parameters of the camera assembly 1406 based on the ambient light intensity acquired by the optical sensor 1415.
  • Proximity sensor 1416 also referred to as a distance sensor, is typically disposed on the front panel of device 1400. Proximity sensor 1416 is used to capture the distance between the user and the front of device 1400. In one embodiment, when the proximity sensor 1416 detects that the distance between the user and the front side of the device 1400 is gradually decreasing, the touch screen 1405 is controlled by the processor 1401 to switch from the bright screen state to the touch screen state; when the proximity sensor 1416 detects When the distance between the user and the front side of the device 1400 gradually becomes larger, the processor 1401 controls the touch display screen 1405 to switch from the state of the screen to the bright state.
  • FIG. 14 does not constitute a limitation to device 1400, may include more or fewer components than illustrated, or may be combined with certain components, or with different component arrangements.
  • the embodiment of the present application further provides a data transmission device, which is applied to a controller.
  • the controller is connected to a plurality of parallel driving chips through a first signal line, and the plurality of driving chips are sorted according to a preset response feedback order.
  • the data transmission device includes:
  • One or more processors are One or more processors.
  • the memory stores one or more programs, the one or more programs configured to be executed by the one or more processors, and configured to be executed by the one or more processors by executing the program
  • the data transmission method performed by the controller in the above embodiment.
  • the embodiment of the present application further provides a data transmission device, which is applied to a first driving chip, where the first driving chip is any one of a plurality of driving chips, and the plurality of driving chips are connected in parallel and pass through a first signal line.
  • the plurality of driver chips are sorted according to a preset response feedback order, and the data transmission device includes:
  • One or more processors are One or more processors.
  • the memory stores one or more programs, the one or more programs configured to be executed by the one or more processors, and configured to be executed by the one or more processors by executing the program
  • the data transmission method performed by the first driving chip in the above embodiment.
  • the embodiment of the present application provides a data transmission apparatus, including a memory, a processor, and a computer program stored on the memory and operable on the processor, and the data transmission shown in FIG. 2 or FIG. 4 is implemented when the processor executes the computer program. method.
  • the embodiment of the present application provides a data transmission apparatus, including a memory, a processor, and a computer program stored on the memory and operable on the processor, and the data transmission shown in FIG. 3 or FIG. 4 is implemented when the processor executes the computer program. method.
  • the embodiment of the present application provides a chip, which includes programmable logic circuits and/or program instructions, and is used to implement the data transmission method shown in FIG. 2 or FIG. 4 when the chip is running.
  • the embodiment of the present application provides a chip, which includes programmable logic circuits and/or program instructions, and is used to implement the data transmission method shown in FIG. 3 or FIG. 4 when the chip is running.
  • the embodiment of the present application provides a computer readable storage medium, which is a non-volatile readable storage medium, which stores a computer program.
  • a computer program When the computer program is executed by the processor, the implementation shown in FIG. 2 or FIG. 4 is implemented. Data transmission method.
  • the embodiment of the present application provides another computer readable storage medium, which is a non-volatile readable storage medium, which stores a computer program.
  • a computer program When the computer program is executed by the processor, the implementation of FIG. 3 or FIG. 4 is implemented. Data transfer method.
  • the embodiment of the present application further provides a computer program product comprising instructions, which when executed on a computer, causes the computer to execute the data transmission method shown in FIG. 2 or FIG.
  • the embodiment of the present application further provides another computer program product comprising instructions, which when executed on a computer, causes the computer to execute the data transmission method shown in FIG. 3 or FIG.

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Abstract

公开了一种数据传输方法、装置及系统、显示装置，属于液晶面板制造领域。该方法应用于控制器，控制器通过一第一信号线与并联的多个驱动芯片连接，多个驱动芯片按照预设的响应反馈顺序排序，该方法包括：生成数据请求指令，数据请求指令包括起始驱动芯片的身份标识，起始驱动芯片为多个驱动芯片中的驱动芯片(201)；通过第一信号线发送数据请求指令(202)；通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据(203)。该数据传输方法解决了相关技术中第一信号线的功能单一，利用率较低的问题，丰富了第一信号线的功能，提高了利用率，用于显示装置。

Description

数据传输方法、装置及系统、显示装置
本申请要求于2018年03月01日提交的申请号为201810172079.4、发明名称为“数据传输方法、组件及系统、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种数据传输方法、装置及系统、显示装置。
背景技术
显示装置一般可以包括显示面板以及用于驱动该显示面板的面板驱动电路，该面板驱动电路可以包括时序控制器(timer controller，T/CON)、栅极驱动电路和源极驱动电路。其中，栅极驱动电路包括多个栅极驱动芯片，源极驱动电路包括多个源极驱动(英文：source driver)芯片。在面板驱动电路中，通常包括两种信号线，该两种信号线包括：第一信号线和第二信号线。第一信号线的信号传输速率小于第二信号线的信号传输速率。该第一信号线可称为低速信号线，通常用于标识电平状态；第二信号线可称为高速信号线，通常用于传输高速差分信号。
具体的，在面板驱动过程中，一般采用点对点的高速信号传输技术来进行信号传输，其特点是在面板驱动电路的两个芯片之间(例如，时序控制器和源极驱动芯片)建立一对一的第二信号线，以传输高速差分信号。其中，时序控制器还设置有额外的一根第一信号线，多个源极驱动芯片并联，且都连接到这根线上，该第一信号线用于标识电平状态，以配合第二信号线进行时序控制器和源极驱动芯片之间的时钟同步。
发明内容
本申请实施例提供了一种数据传输方法、装置及系统、显示装置，所述技术方案如下：
第一方面，提供了一种数据传输方法，应用于控制器，所述控制器通过一第一信号线与并联的多个驱动芯片连接，所述多个驱动芯片按照预设的响应反 馈顺序排序，所述方法包括：
生成数据请求指令，所述数据请求指令包括起始驱动芯片的身份标识，所述起始驱动芯片为所述多个驱动芯片中的驱动芯片；
通过所述第一信号线向所述多个驱动芯片发送所述数据请求指令；
通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，每个所述数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
可选地，所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
可选地，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
可选地，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，
所述通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，包括：
通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述最后一个驱动芯片依次发送的数据响应指令。
可选地，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，
所述通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，包括：
通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所 述起始驱动芯片至所述终止驱动芯片依次发送的数据响应指令。
可选地，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
可选地，所述多个驱动芯片的身份标识为具有顺序特征的字符，
所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
可选地，所述多个驱动芯片的身份标识为不同的数字，
所述响应反馈顺序为按照身份标识从小到大排列的顺序。
可选地，所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
所述起始标识包括连续的至少2比特二进制的0；
所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
所述结束标识包括连续的至少2比特二进制的1。
可选地，所述方法还包括：
在通过所述第一信号线进行信号传输的过程中，在检测到所述第一信号线上的信号被拉低时，执行时钟校准操作。
第二方面，提供了一种数据传输方法，应用于第一驱动芯片，所述第一驱动芯片为多个驱动芯片中的任一驱动芯片，所述多个驱动芯片并联，且通过一第一信号线与控制器连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述方法包括：
当接收到所述控制器通过所述第一信号线发送的数据请求指令时，检测所述数据请求指令中携带的起始驱动芯片的身份标识是否为所述第一驱动芯片的身份标识；
在检测到所述起始驱动芯片的身份标识为所述第一驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第一数据响应指令，所述第一数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
其中，所述第一数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述第一信号线上传输的指令均包括依次排列的前导码、起始标 识、数据位和结束标识；
其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
可选地，所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
可选地，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
可选地，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，所述方法还包括：
在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，所述方法还包括：
在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，记录所述终止驱动芯片的身份标识；
当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，检测所述前一个驱动芯片的身份标识是否为所述终止驱动芯片的身份标识；
当所述前一个驱动芯片的身份标识不为所述终止驱动芯片的身份标识时，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
当所述前一个驱动芯片的身份标识为所述终止驱动芯片的身份标识时，结束动作；
其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
可选地，所述多个驱动芯片的身份标识为具有顺序特征的字符，
所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
可选地，所述多个驱动芯片的身份标识为不同的数字，
所述响应反馈顺序为按照身份标识从小到大排列的顺序。
可选地，所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
所述起始标识包括连续的至少2比特二进制的0；
所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
所述结束标识包括连续的至少2比特二进制的1。
可选地，所述方法还包括：
在通过所述第一信号线进行信号传输的过程中，当所述第一驱动芯片出现异常时，将所述第一信号线上的信号拉低，使得所述控制器根据拉低后的信号执行时钟校准操作。
第三方面，提供了一种数据传输系统，包括时序控制器和并联的多个源极驱动芯片，所述时序控制器通过一第一信号线与并联的多个源极驱动芯片连接，所述多个源极驱动芯片按照预设的响应反馈顺序排序，
所述时序控制器，用于生成数据请求指令，并通过所述第一信号线发送所述数据请求指令，所述数据请求指令包括起始源极驱动芯片的身份标识，所述起始源极驱动芯片与所述多个源极驱动芯片中的最后一个源极驱动芯片不同；
所述起始源极驱动芯片，用于在接收到所述数据请求指令时通过所述第一信号线向所述时序控制器和其余源极驱动芯片发送第一数据响应指令，所述第一数据响应指令包括所述起始源极驱动芯片的身份标识和所述起始源极驱动芯片的数据；
所述起始源极驱动芯片之后的每一个源极驱动芯片，用于在接收到另一源极驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述源极驱动芯片的前一个源极驱动芯片的身份标识；在检测到所述第二数据响应指令中携带的身份标识为所述前一个源极驱动芯片的身份标识后，通过所述第一信号线向所述时序控制器和其余源极驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述源极驱动芯片的身份标识和所述源极驱动芯片的数据。
可选地，所述起始源极驱动芯片为所述多个源极驱动芯片按照所述响应反馈顺序排列得到的首个源极驱动芯片。
第四方面，提供了一种数据传输装置，应用于控制器，所述控制器通过一第一信号线与并联的多个驱动芯片连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述数据传输装置包括：
一个或多个处理器；和
存储器；
所述存储器存储有一个或多个程序，所述一个或多个程序被配置成由所述一个或多个处理器执行，所述一个或多个程序包含用于进行以下操作的指令：
生成数据请求指令，所述数据请求指令包括起始驱动芯片的身份标识，所述起始驱动芯片为所述多个驱动芯片中的驱动芯片；
通过所述第一信号线向所述多个驱动芯片发送所述数据请求指令；
通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，每个所述数据响应指令包括对应 的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
可选地，所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
可选地，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
可选地，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，
所述一个或多个程序还包含用于进行以下操作的指令：
通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述最后一个驱动芯片依次发送的数据响应指令。
可选地，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，
所述一个或多个程序还包含用于进行以下操作的指令：
通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述终止驱动芯片依次发送的数据响应指令。
可选地，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
可选地，所述多个驱动芯片的身份标识为具有顺序特征的字符，
所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
可选地，所述多个驱动芯片的身份标识为不同的数字，
所述响应反馈顺序为按照身份标识从小到大排列的顺序。
可选地，所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得 到；
所述起始标识包括连续的至少2比特二进制的0；
所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
所述结束标识包括连续的至少2比特二进制的1。
可选地，所述一个或多个程序还包含用于进行以下操作的指令：
在通过所述第一信号线进行信号传输的过程中，在检测到所述第一信号线上的信号被拉低时，执行时钟校准操作。
第五方面，提供了一种数据传输装置，应用于第一驱动芯片，所述第一驱动芯片为多个驱动芯片中的任一驱动芯片，所述多个驱动芯片并联，且通过一第一信号线与控制器连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述数据传输装置包括：
一个或多个处理器；和
存储器；
所述存储器存储有一个或多个程序，所述一个或多个程序被配置成由所述一个或多个处理器执行，所述一个或多个程序包含用于进行以下操作的指令：
当接收到所述控制器通过所述第一信号线发送的数据请求指令时，检测所述数据请求指令中携带的起始驱动芯片的身份标识是否为所述第一驱动芯片的身份标识；
在检测到所述起始驱动芯片的身份标识为所述第一驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第一数据响应指令，所述第一数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
其中，所述第一数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
可选地，所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
可选地，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
可选地，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，所述一个或多个程序还包含用于进行以下操作的指令：
在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，所述一个或多个程序还包含用于进行以下操作的指令：
在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，记录所述终止驱动芯片的身份标识；
当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片 的身份标识后，检测所述前一个驱动芯片的身份标识是否为所述终止驱动芯片的身份标识；
当所述前一个驱动芯片的身份标识不为所述终止驱动芯片的身份标识时，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
当所述前一个驱动芯片的身份标识为所述终止驱动芯片的身份标识时，结束动作；
其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
可选地，所述多个驱动芯片的身份标识为具有顺序特征的字符，
所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
可选地，所述多个驱动芯片的身份标识为不同的数字，
所述响应反馈顺序为按照身份标识从小到大排列的顺序。
可选地，所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
所述起始标识包括连续的至少2比特二进制的0；
所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
所述结束标识包括连续的至少2比特二进制的1。
可选地，所述一个或多个程序还包含用于进行以下操作的指令：
在通过所述第一信号线进行信号传输的过程中，当所述第一驱动芯片出现异常时，将所述第一信号线上的信号拉低，使得所述控制器根据拉低后的信号执行时钟校准操作。
第六方面，提供了一种显示装置，包括控制器和多个驱动芯片，
所述控制器包括第四方面所述的数据传输装置；
所述多个驱动芯片包括第五方面所述的数据传输装置。
第七方面，提供了一种数据传输装置，包括存储器，处理器及存储在所述 存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现第一方面所述的数据传输方法。
第八方面，提供了一种数据传输装置，包括存储器，处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现第二方面所述的数据传输方法。
第九方面，提供了一种计算机可读存储介质，该存储介质存储有计算机程序，计算机程序被处理器执行时，实现如第一方面所述的数据传输方法。
第十方面，提供了一种计算机可读存储介质，该存储介质存储有计算机程序，计算机程序被处理器执行时，实现如第二方面所述的数据传输方法。
第十一方面，提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行如第一方面所述的数据传输方法。
第十二方面，提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行如第二方面所述的数据传输方法。
附图说明
图1A是本申请各个实施例所涉及的一种应用环境示意图；
图1B是本申请各个实施例所涉及的另一种应用环境示意图；
图2是本申请实施例提供的一种数据传输方法的流程示意图；
图3是本申请实施例提供的另一种数据传输方法的流程示意图；
图4是本申请实施例提供的又一种数据传输方法的流程示意图；
图5是本申请实施例提供的一种第一信号线上传输的指令的格式示意图；
图6是本申请实施例提供的一种数据请求指令的数据位携带的目标数据的示意图；
图7是本申请实施例提供的一种数据响应指令的数据位携带的目标数据的示意图；
图8是本申请实施例提供的另一种数据响应指令的数据位携带的目标数据的示意图；
图9是本申请实施例示例性提供的一种数据传输系统的结构示意图；
图10是本申请实施例提供的一种数据传输装置的结构示意图；
图11是本申请实施例提供的另一种数据传输装置的结构示意图；
图12是本申请实施例提供的又一种数据传输装置的结构示意图；
图13是本申请实施例提供的再一种数据传输装置的结构示意图；
图14是本申请实施例提供的另外一种显示装置的结构框图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
请参考图1A，图1A是本申请实施例提供的一种数据传输方法的应用环境示意图，如图1A所示，该数据传输方法应用于显示装置中，该显示装置包括控制器01和多个驱动芯片02，该多个驱动芯片02均与控制器01连接，该多个驱动芯片02中的至少一个驱动芯片02还与显示面板连接，多个驱动芯片02具有回传数据的传输功能。示例的，该显示面板可以为内嵌式(in-cell)触控显示面板，该内嵌式触控显示面板为集成有触控功能层(简称：触控层)的显示面板，也即是将触控功能层嵌入显示面板的像素中的结构，该显示面板可以为OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板或LCD(Liquid Crystal Display，液晶显示阵列)显示面板。当具有回传数据的传输功能的驱动芯片有多个时，该多个驱动芯片可以分别与内嵌式触控显示面板的多个触控信号输出端子连接。
如图1A所示，控制器01通过多个第二信号线H分别与多个驱动芯片02连接，通常的，该控制器的多个第二信号线H与多个驱动芯片一一对应连接，其中，第二信号线中的信号是单向传输的，该控制器还连接有一第一信号线L，多个驱动芯片并联，且与第一信号线L连接，在本申请实施例中，该第一信号线L具有双向传输的功能，多个驱动芯片通常按照预先配置的响应反馈顺序排列。控制器可以通过第一信号线向多个驱动芯片发送数据请求指令，并通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，以获取驱动芯片的数据。该响应反馈顺序用于标识该多个驱动芯片发送数据响应指令的先后顺序。
示例的，每个驱动芯片具有一个身份标识，多个驱动芯片的身份标识可以为具有顺序特征的字符，响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。比如字符可以为字母、数字或文字等。假设有4个驱动芯片，4个驱动芯片的身份标识可以依次为：a、b、c和d，或者为：4、3、2和1，或者为：甲、乙、丙和丁。
示例的，多个驱动芯片的身份标识可以为不同的数字，响应反馈顺序可以为按照身份标识从小到大排列的顺序。假设有4个驱动芯片：X1、X2、X3和X4，X1的身份标识为4，X2的身份标识为3，X3的身份标识为2，X4的身份标识为1，那么响应反馈顺序可以为按照这4个身份标识从小到大排列的顺序，由于X4的身份标识最小，X1的身份标识最大，所以排序后可以得到：X4、X3、X2和X1。此外，当多个驱动芯片的身份标识为不同的数字时，响应反馈顺序也可以为按照身份标识从大到小排列的顺序，本申请实施例对此不作限定。
上述驱动芯片可以为源极驱动芯片或栅极驱动芯片；控制器可以为时序控制器，系统芯片(英文：System on Chip；简称：SOC)以及集成在时序控制器中的微控制单元(英文：Microcontroller Unit；MCU)中的任一种。图1B以控制器为时序控制器011，驱动芯片为源极驱动芯片021为例进行说明。如图1B所示，该时序控制器011通过多个第二信号线H分别与多个源极驱动芯片021一一对应连接。该时序控制器011还连接有一第一信号线L，该多个源极驱动芯片021并联，且与第一信号线L连接，该第一信号线L可以进行电平状态的标识，例如通过该第一信号线L将源极驱动芯片的引脚设置为高电平或低电平。
图1B假设该多个源极驱动芯片021并联且均通过第一信号线和第二信号线与时序控制器011连接，并且该多个源极驱动芯片021均与显示面板03连接，但本申请实施例并不对此进行限制。
其中，第二信号线可以为高速信号线，第一信号线可以为低速信号线。需要说明的是，假设用于连接上述显示面板与驱动芯片的信号线为第三信号线，则该第三信号线也可以为高速信号线，也即是第二信号线的信号传输速率和第三信号线的信号传输速率均大于第一信号线的信号传输速率。例如，该第二信号线和第三信号线为差分信号线，第一信号线为普通信号线。
传统的显示装置的面板驱动电路中，该第一信号线L只能进行电平状态的标识，例如通过该第一信号线L将源极驱动芯片的引脚设置为高电平或低电平。第一信号线的功能单一，利用率较低。传统的显示装置的面板驱动电路中，时序控制器通过第一信号线L无法获取源极驱动芯片的数据，这样就限制了某些功能的实现，比如触控功能、OLED补偿功能等。其中，触控功能要求以较高的频率对触摸坐标点的位置进行扫描，即要求源极驱动芯片实时向时序控制器发送数据，以通知时序控制器是否检测到触摸操作和触摸坐标点，在实现该功能时，源极驱动芯片用于进行触控驱动和显示驱动；OLED补偿功能则要求在显示 画面的过程中对某一位置画面的颜色和亮度进行实时调整，避免出现偏色或者色彩不均匀的现象，为了实现该功能，需要将当前位置的电流、电压和其他相关状态数据作为补偿运算所依据的原始数据，这就要求源极驱动芯片实时向时序控制器发送源极驱动芯片当前的显示数据。
而在本申请实施例中，该第一信号线L除了可以进行电平状态的标识，还可以进行数据传输。时序控制器通过第一信号线L可以获取源极驱动芯片的数据，进而实现多种功能。比如，在实现触控功能时，时序控制器通过第一信号线L可以实时获取源极驱动芯片的数据，进而以较高的频率对触摸坐标点的位置进行扫描；在实现OLED补偿功能中，时序控制器通过第一信号线L可以实时获取源极驱动芯片的显示数据，将该显示数据作为补偿运算所依据的原始数据，然后进行补偿运算，进而对当前位置画面的颜色和亮度进行实时调整，避免出现偏色或者色彩不均匀的现象。
请参考图2，图2是本申请实施例提供的一种数据传输方法的流程示意图。该数据传输方法可以应用于图1A中的控制器，该控制器通过一第一信号线与并联的多个驱动芯片连接，如图2所示，该方法包括：
在步骤201中，生成数据请求指令，该数据请求指令包括起始驱动芯片的身份标识，该起始驱动芯片为多个驱动芯片中的驱动芯片。
在步骤202中，通过第一信号线向多个驱动芯片发送数据请求指令。
在步骤203中，通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
在本申请实施例中，控制器通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序，从前至后依次发送的数据响应指令。响应反馈顺序指示多个驱动芯片本身进行了排序，多个驱动芯片的排布位置也可以按照排序顺序来进行排布。
综上所述，本申请实施例提供的数据传输方法，控制器能够生成数据请求指令，再通过第一信号线发送数据请求指令，之后通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，相较于相关技术，控制器通过第一信号线可以获取驱动芯片的数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
请参考图3，图3是本申请实施例提供的一种数据传输方法的流程示意图。该数据传输方法可以应用于图1A中的第一驱动芯片，该第一驱动芯片为多个驱动芯片中的任一驱动芯片，多个驱动芯片并联，且通过一第一信号线与控制器连接，多个驱动芯片按照预设的响应反馈顺序排序。如图3所示，该方法包括：
在步骤301中，当接收到控制器通过第一信号线发送的数据请求指令时，检测数据请求指令中携带的起始驱动芯片的身份标识是否为第一驱动芯片的身份标识。
在步骤302中，在检测到起始驱动芯片的身份标识为第一驱动芯片的身份标识后，通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令，该第一数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
其中，第一数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
综上所述，本申请实施例提供的数据传输方法，第一驱动芯片在检测到数据请求指令中携带的起始驱动芯片的身份标识为第一驱动芯片的身份标识后，能够根据数据请求指令通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令，第一数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据，相较于相关技术，驱动芯片通过第一信号线可以向控制器发送驱动芯片的数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
请参考图4，图4是本申请实施例提供的一种数据传输方法的流程示意图。该数据传输方法可以应用于图1A所示的应用环境，参见图1A，控制器通过一第一信号线与并联的多个驱动芯片连接，多个驱动芯片按照预设的响应反馈顺序排序。如图4所示，该方法可以包括：
在步骤401中，控制器生成数据请求指令。
该数据请求指令包括起始驱动芯片的身份标识，该起始驱动芯片为多个驱动芯片中的驱动芯片。
在本申请实施例中，控制器可以事先基于第一信号线对该多个驱动芯片以广播的形式同步进行基本配置，使驱动芯片具备回传数据的功能，然后再执行步骤401。比如控制器可以事先对每个驱动芯片的身份标识进行配置。示例的， 控制器可以采用将驱动芯片的引脚设置为高电平或低电平的方式对驱动芯片的身份标识进行配置，或者，可以采用向驱动芯片内部写入指令的方式对驱动芯片的身份标识进行配置。
在步骤402中，控制器通过第一信号线向多个驱动芯片发送数据请求指令。
示例的，控制器可以按照预设频率通过第一信号线，向多个驱动芯片同时发送数据请求指令。其中，预设频率可以为500KHz(千赫兹)。
在步骤403中，当接收到控制器通过第一信号线发送的数据请求指令时，第一驱动芯片检测数据请求指令中携带的起始驱动芯片的身份标识是否为第一驱动芯片的身份标识。
假设第一驱动芯片为多个驱动芯片中的任一驱动芯片。第一驱动芯片检测数据请求指令中携带的起始驱动芯片的身份标识是否为第一驱动芯片的身份标识，以便于确定第一驱动芯片是否为起始驱动芯片。
在步骤404中，在检测到起始驱动芯片的身份标识为第一驱动芯片的身份标识后，第一驱动芯片通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令。
其中，其余驱动芯片指的是前述与第一信号线连接，且并联的多个驱动芯片中除第一驱动芯片之外的驱动芯片。
在检测到起始驱动芯片的身份标识为第一驱动芯片的身份标识时，表明第一驱动芯片为起始驱动芯片，则第一驱动芯片通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令，该第一数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
其中，第一数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
示例的，3个驱动芯片并联，且通过一第一信号线与控制器连接。3个驱动芯片分别为：X1、X2和X3，3个驱动芯片的身份标识分别为X1、X2和X3，且3个驱动芯片按照预设的响应反馈顺序排序为：X1、X2和X3。假设第一驱动芯片为X1，控制器通过第一信号线发送的数据请求指令中携带的起始驱动芯片的身份标识为X1，X1检测到数据请求指令中携带的起始驱动芯片的身份标识为第一驱动芯片的身份标识，X1则通过第一信号线向控制器、X2和X3发送第一数据响应指令。
可选地，本申请实施例中，控制器和驱动芯片之间传输的指令的格式相同，第一信号线上传输的每个指令均包括依次排列的前导码(英文：preamble)、起始(英文：start)标识、数据位(也称：传输主体，英文：transaction body)和结束(英文：stop)标识。
其中，前导码用于指示接收端进行时钟和相位校准，接收端(时序控制器或源极驱动芯片)在检测到第一信号线上有前导码传输时，便根据前导码的内容进行时钟和相位调整。其中，时钟和相位校准是指保持时钟与发送端的时钟一致，相位与发送端相同。接收端在接收前导码的过程中调整时钟和相位，在前导码传输结束后，时钟和相位调整完毕。起始标识用于指示数据传输开始，数据位用于携带目标数据，结束标识用于指示数据传输结束。
示例的，前导码可以由连续的至少8比特二进制的0采用曼彻斯特(Manchester)编码得到。如图5所示，图5以该前导码由连续的8比特二进制的0采用曼彻斯特编码得到来进行示意性说明；起始标识可以保持低电平信号且不进行曼彻斯特编码，起始标识可以包括连续的至少2比特二进制的0，图5以该起始标识为连续的2比特二进制的0进行示意性说明；数据位携带的目标数据为采用曼彻斯特编码得到的数据；结束标识可以保持高电平信号且不进行曼彻斯特编码，结束标识可以包括连续的至少2比特二进制的1，图5以该结束标识为连续的2比特二进制的1进行示意性说明。
由于采用曼彻斯特编码可以使数据产生明显的跳变沿，便于数据的检测，因此，本申请实施例中需要编码的数据均可以采用曼彻斯特编码，但是实际应用中，也可以采用其他编码方式或者不进行编码。
示例的，在本申请实施例中，为了保证数据位携带的目标数据在解码端能够有效识别，请参考图5，在数据位中的目标数据的首位可以与起始标识产生一跳变沿(即数据位中的目标数据的首位与起始标识的末位数值不同，例如，数据位中的目标数据的首位为1，起始标识的末位为0)，在数据位中的目标数据的末位可以与结束标识产生一跳变沿(即数据位中的目标数据的末位与结束标识的首位数值不同，例如，数据位中的目标数据的末位为0，结束标识的首位为1)。上述跳变沿便于接收端进行数据的有效识别。
如图6所示，控制器生成的数据请求指令的数据位携带的目标数据可以包括：第一信号线的传输模式，起始驱动芯片的身份标识，多个驱动芯片上需要配置的寄存器的地址，以及数据校验和。其中，第一信号线的传输模式为成组 读取(英文：Bust Read Mode)模式，成组读取模式指示控制器接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据。示例的，第一信号线的传输模式的信号可以占用数据位中的2比特。数据位中的数据校验和用于确保接收端接收到的数据的准确性。
如图7所示，每个数据响应指令的数据位携带的目标数据包括：第一信号线的传输模式，对应的驱动芯片的身份标识，多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。其中，第一信号线的传输模式为回复传输模式，回复传输模式指示驱动芯片对控制器进行指令的回复。
在本申请实施例中，第一驱动芯片可以为多个驱动芯片中的最后一个驱动芯片，也可以不为多个驱动芯片中的最后一个驱动芯片。当该第一驱动芯片为多个驱动芯片中的最后一个驱动芯片时，在数据请求指令中起始驱动芯片的身份标识为第一驱动芯片的身份标识的情况下，控制器通过第一信号线可以接收该第一驱动芯片发送的数据响应指令，丰富了第一信号线的功能，提高了第一信号线的利用率。当第一驱动芯片不为多个驱动芯片中的最后一个驱动芯片时，在数据请求指令中起始驱动芯片的身份标识为第一驱动芯片的身份标识的情况下，控制器通过第一信号线发送一次数据请求指令，可以通过第一信号线接收到多个驱动芯片发送的数据，实现一次性读取多个驱动芯片的数据，在该过程中，发送数据请求指令的次数较少，且多个驱动芯片回传数据的时间较短，回传数据的效率较高。
在本申请实施例中，当起始驱动芯片与多个驱动芯片中的最后一个驱动芯片不同(也即是起始驱动芯片不是该多个驱动芯片中的最后一个驱动芯片)时，控制器通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，可以包括：控制器通过第一信号线接收多个驱动芯片按照响应反馈顺序，从起始驱动芯片至最后一个驱动芯片依次发送的数据响应指令。其中，最后一个驱动芯片为按照预设的响应反馈顺序排序的多个驱动芯片的最后一名驱动芯片。当第一驱动芯片不为起始驱动芯片时，第一驱动芯片可以执行下述步骤405至步骤406。
在步骤405中，在检测到起始驱动芯片的身份标识不为第一驱动芯片的身份标识后，当第一驱动芯片接收到另一驱动芯片通过第一信号线发送的第二数据响应指令时，第一驱动芯片检测第二数据响应指令中携带的身份标识是否为第一驱动芯片的前一个驱动芯片的身份标识。
比如当数据请求指令中携带的起始驱动芯片的身份标识不为第一驱动芯片的身份标识时，身份标识与起始驱动芯片的身份标识相同的驱动芯片会根据控制器发送的数据请求指令向其余驱动芯片发送数据响应指令，假设该数据响应指令为第二数据响应指令，那么第一驱动芯片会接收到另一驱动芯片(即身份标识与起始驱动芯片的身份标识相同的驱动芯片)通过第一信号线发送的第二数据响应指令。在接收到该第二数据响应指令时，第一驱动芯片检测该第二数据响应指令中携带的身份标识是否为第一驱动芯片的前一个驱动芯片的身份标识，以便于确定是否通过第一信号线发送相应的数据响应指令。
在步骤406中，在检测到第二数据响应指令中携带的身份标识为前一个驱动芯片的身份标识后，第一驱动芯片通过第一信号线向控制器和其余驱动芯片发送第三数据响应指令。
该第三数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
其中，第三数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，起始驱动芯片为多个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片。假设一共有3个驱动芯片：X1、X2和X3，3个驱动芯片按照预设的响应反馈顺序排序为：X1、X2和X3，即这3个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片是X1，那么起始驱动芯片则为X1。通过步骤401至步骤406，X1检测到控制器通过第一信号线发送的数据请求指令中携带的起始驱动芯片的身份标识为X1的身份标识，X1通过第一信号线向控制器和其余驱动芯片发送数据响应指令，该数据响应指令包括X1的身份标识和X1的数据；X2检测到X1发送的数据响应指令中携带的身份标识为X2的前一个驱动芯片即X1的身份标识，X2通过第一信号线向控制器和其余驱动芯片发送数据响应指令，该数据响应指令包括X2的身份标识和X2的数据；X3检测到X2发送的数据响应指令中携带的身份标识为X3的前一个驱动芯片即X2的身份标识，X3通过第一信号线向控制器和其余驱动芯片发送数据响应指令，该数据响应指令包括X3的身份标识和X3的数据。
在本申请实施例中，当第一驱动芯片不为起始驱动芯片且不为多个驱动芯片中的最后一个驱动芯片时，通过执行步骤401至步骤406，控制器可以依次接 收到多个驱动芯片发送的数据，实现一次性读取多个驱动芯片的数据。且当起始驱动芯片为多个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片时，控制器可以依次接收到所有驱动芯片发送的数据，实现一次性读取所有驱动芯片的数据。
可选的，控制器发送的数据请求指令还可以包括终止驱动芯片的身份标识，终止驱动芯片为多个驱动芯片中位于起始驱动芯片之后的驱动芯片。在这种情况下，控制器通过第一信号线可以接收到指定的多个驱动芯片发送的数据响应指令。图8示例性示出了包括终止驱动芯片的身份标识的数据请求指令的示意图。示例的，终止驱动芯片的身份标识的位置可以位于数据请求指令中的起始驱动芯片的身份标识之后。控制器通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，可以包括：控制器通过第一信号线接收多个驱动芯片按照响应反馈顺序，从起始驱动芯片至终止驱动芯片依次发送的数据响应指令。对于第一驱动芯片来说，当数据请求指令还包括终止驱动芯片的身份标识时，第一驱动芯片还可以执行下述步骤407至步骤411。
在步骤407中，在检测到起始驱动芯片的身份标识不为第一驱动芯片的身份标识后，第一驱动芯片记录终止驱动芯片的身份标识。
在步骤408中，当接收到另一驱动芯片通过第一信号线发送的第二数据响应指令时，第一驱动芯片检测第二数据响应指令中携带的身份标识是否为第一驱动芯片的前一个驱动芯片的身份标识。
在步骤409中，在检测到第二数据响应指令中携带的身份标识为前一个驱动芯片的身份标识后，第一驱动芯片检测前一个驱动芯片的身份标识是否为终止驱动芯片的身份标识。
在步骤410中，当前一个驱动芯片的身份标识不为终止驱动芯片的身份标识时，第一驱动芯片通过第一信号线向控制器和其余驱动芯片发送第三数据响应指令。
该第三数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
在步骤411中，当前一个驱动芯片的身份标识为终止驱动芯片的身份标识时，第一驱动芯片结束动作。
其中，第三数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第 一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，起始驱动芯片为多个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片。假设一共有3个驱动芯片：X1、X2和X3，3个驱动芯片按照预设的响应反馈顺序排序为：X1、X2和X3，即这3个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片是X1，那么起始驱动芯片则为X1。终止驱动芯片为位于起始驱动芯片之后的驱动芯片X2。X1通过执行步骤403至步骤404，检测到控制器通过第一信号线发送的数据请求指令中携带的起始驱动芯片的身份标识为X1的身份标识，X1通过第一信号线向控制器和其余驱动芯片发送数据响应指令，该数据响应指令包括X1的身份标识和X1的数据；X2通过执行步骤407至步骤410，记录终止驱动芯片X2的身份标识，检测到X1发送的数据响应指令中携带的身份标识为X2的前一个驱动芯片的身份标识，且前一个驱动芯片的身份标识不为终止驱动芯片的身份标识，X2通过第一信号线向控制器和其余驱动芯片发送数据响应指令，该数据响应指令包括X2的身份标识和X2的数据；X3通过执行步骤407至步骤410，记录终止驱动芯片X2的身份标识，检测到X2发送的数据响应指令中携带的身份标识为X3的前一个驱动芯片的身份标识，且前一个驱动芯片的身份标识为终止驱动芯片的身份标识，X3结束动作，即X3不再通过第一信号线向控制器和其余驱动芯片发送包括X3的身份标识和X3的数据的数据响应指令。
在本申请实施例中，通过执行步骤407至步骤411，控制器可以根据实际需求，依次接收到指定的多个驱动芯片发送的数据，实现一次性读取指定的多个驱动芯片的数据，避免得到不需要的数据。其中，指定的多个驱动芯片为身份标识属于起始驱动芯片的身份标识至终止驱动芯片的身份标识的范围的驱动芯片。比如，一共有12个驱动芯片，控制器可以仅接收前4个驱动芯片发送的数据。
此外，在本申请实施例中，当终止驱动芯片向控制器发送数据响应指令时，可以在数据响应指令的数据位携带一终止符，该终止符用于指示当前向控制器发送数据响应指令的驱动芯片为终止驱动芯片。这样一来，后一个驱动芯片在接收到该数据响应指令时，检测到该数据响应指令的数据位携带有终止符，则结束动作。示例的，该终止符可以为预设的符号比如“*”、“#”等。另外，为了获取到指定的多个驱动芯片的数据，控制器也可以在接收到所有驱动芯片发 送的数据后，从所有驱动芯片发送的数据中筛选出需要的数据。
为了保证数据的有效传输，第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。示例的，该预设时长可以为10微秒。
在步骤412中，在通过第一信号线进行信号传输的过程中，当第一驱动芯片出现异常时，第一驱动芯片将第一信号线上的信号拉低。
在步骤412中，控制器在检测到第一信号线上的信号被拉低时，执行时钟校准操作。其中，通过第一信号线传输的信号包括数据请求指令和数据响应指令。
在本申请实施例中，在驱动芯片实时向控制器回传数据的过程中，可能会因为一些外界因素导致驱动芯片无法基于第二信号线(第二信号线可称为高速信号线，通常用于传输高速差分信号)正常工作，造成时钟失锁，控制器无法通过第二信号线向驱动芯片传输高速差分信号，此时可以通过双向传输的第一信号线进行时钟状态反馈。由于控制器通过第一信号线与并联的多个驱动芯片连接，因此，当任一驱动芯片出现异常时，该驱动芯片将第一信号线上的信号拉低，此时，第一信号线上不会有其他数据传输至控制器，那么控制器可以接收到一段时长的低电平信号，并确定当前有驱动芯片出现了时钟失锁状态，然后控制器执行时钟校准操作，进而可以避免时钟失锁造成的无法还原现象，避免影响点对点接口架构的基本应用。
综上所述，本申请实施例提供的数据传输方法，控制器能够生成数据请求指令，再通过第一信号线发送数据请求指令，之后通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，相较于相关技术，控制器通过第一信号线可以获取驱动芯片的数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
需要说明的是，本申请实施例提供的数据传输方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
本申请实施例还提供了一种数据传输系统，参考图1B，包括时序控制器和并联的多个源极驱动芯片，时序控制器通过一第一信号线与并联的多个驱动芯片连接，多个源极驱动芯片按照预设的响应反馈顺序排序。
其中，时序控制器，用于生成数据请求指令，并通过第一信号线发送数据请求指令，该数据请求指令包括起始源极驱动芯片的身份标识，该起始源极驱动芯片与多个源极驱动芯片中的最后一个源极驱动芯片不同。
起始源极驱动芯片，用于在接收到数据请求指令时通过第一信号线向时序控制器和其余源极驱动芯片发送第一数据响应指令，该第一数据响应指令包括起始源极驱动芯片的身份标识和起始源极驱动芯片的数据。
起始源极驱动芯片之后的每一个源极驱动芯片，用于在接收到另一源极驱动芯片通过第一信号线发送的第二数据响应指令时，检测第二数据响应指令中携带的身份标识是否为本源极驱动芯片的前一个源极驱动芯片的身份标识；在检测到第二数据响应指令中携带的身份标识为前一个源极驱动芯片的身份标识后，通过第一信号线向时序控制器和其余源极驱动芯片发送第三数据响应指令，第三数据响应指令包括该源极驱动芯片的身份标识和该源极驱动芯片的数据。
可选地，起始源极驱动芯片为多个源极驱动芯片按照响应反馈顺序排列得到的首个源极驱动芯片。
示例的，参考图9，假设一共有6个源极驱动芯片：X1、X2、X3、X4、X5和X6，X1的身份标识为1，X2的身份标识为2，X3的身份标识为3，X4的身份标识为4，X5的身份标识为5，X6的身份标识为6，那么响应反馈顺序可以为按照这6个身份标识从小到大排列的顺序，由于X1的身份标识最小，X6的身份标识最大，所以排序后可以得到：X1、X2、X3、X4、X5和X6。起始源极驱动芯片为X1。
参见图9，时序控制器用于生成数据请求指令，并通过第一信号线发送数据请求指令，该数据请求指令包括X1的身份标识：1。
X1为起始源极驱动芯片，X1用于在接收到时序控制器发送的数据请求指令时，通过第一信号线向时序控制器和其余源极驱动芯片发送数据响应指令，该数据响应指令包括X1的身份标识和X1的数据。X2、X3、X4、X5和X6用于在接收到X1发送的数据响应指令时，检测该数据响应指令中携带的身份标识是否为自身的前一个源极驱动芯片的身份标识。由于X2检测到该数据响应指令中携带的身份标识为自身的前一个源极驱动芯片的身份标识，所以X2通过第一信号线向时序控制器和其余源极驱动芯片发送数据响应指令，该数据响应指令包括X2的身份标识和X2的数据。X3、X4、X5和X6用于在接收到X2发送的数据响应指令时，检测该数据响应指令中携带的身份标识是否为自身的前一个 源极驱动芯片的身份标识，由于X3检测到该数据响应指令中携带的身份标识为自身的前一个源极驱动芯片的身份标识，所以X3通过第一信号线向时序控制器和其余源极驱动芯片发送数据响应指令，该数据响应指令包括X3的身份标识和X3的数据。同样的，X4、X5和X6也会依次通过第一信号线向时序控制器和其余源极驱动芯片发送数据响应指令，该数据响应指令包括对应的源极驱动芯片的身份标识和对应的源极驱动芯片的数据。最终，时序控制器通过第一信号线依次接收到X1、X3、X4、X5和X6发送的数据响应指令。
需要补充说明的是，在图9中，当某一源极驱动芯片通过第一信号线发送数据响应指令，其余源极驱动芯片都会接收到该数据响应指令。图9仅示意性示出了该源极驱动芯片的下一个源极驱动芯片接收数据响应指令，并检测该数据响应指令中携带的身份标识的示意图。
综上所述，本申请实施例提供的数据传输系统，时序控制器生成数据请求指令，并通过第一信号线发送数据请求指令，数据请求指令包括起始源极驱动芯片的身份标识，起始源极驱动芯片与多个源极驱动芯片中的最后一个源极驱动芯片不同，起始源极驱动芯片能够在接收到数据请求指令时通过第一信号线向时序控制器和其余源极驱动芯片发送第一数据响应指令，起始源极驱动芯片之后的每一个驱动芯片在接收到另一源极驱动芯片通过第一信号线发送的第二数据响应指令时，在检测到第二数据响应指令中携带的身份标识为前一个源极驱动芯片的身份标识后，通过第一信号线向时序控制器和其余源极驱动芯片发送第三数据响应指令，相较于相关技术，时序控制器通过第一信号线可以获取源极驱动芯片的数据，实现一次性读取多个源极驱动芯片的数据，丰富了第一信号线的功能，提高了第一信号线的利用率，能够实现多种功能，可以适用于需要源极驱动芯片实时向时序控制器回传数据的场景。
本申请实施例提供一种数据传输装置，应用于控制器，请参考图1A，控制器通过一第一信号线与并联的多个驱动芯片连接，多个驱动芯片按照预设的响应反馈顺序排序，如图10所示，该数据传输装置1000包括：
生成模块1001，用于生成数据请求指令，该数据请求指令包括起始驱动芯片的身份标识，起始驱动芯片为多个驱动芯片中的驱动芯片。
发送模块1002，用于通过第一信号线向多个驱动芯片发送数据请求指令。
接收模块1003，用于通过第一信号线接收多个驱动芯片从起始驱动芯片开 始按照响应反馈顺序依次发送的数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
本申请实施例提供的数据传输装置，生成模块生成数据请求指令，发送模块通过第一信号线发送数据请求指令，之后接收模块通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，相较于相关技术，控制器通过第一信号线可以获取驱动芯片的数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
可选地，第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
其中，前导码用于指示接收端进行时钟和相位校准，起始标识用于指示数据传输开始，数据位用于携带目标数据，结束标识用于指示数据传输结束。
其中，数据请求指令的数据位携带的目标数据包括：第一信号线的传输模式，起始驱动芯片的身份标识，多个驱动芯片上需要配置的寄存器的地址，以及数据校验和。其中，第一信号线的传输模式为成组读取模式。
每个数据响应指令的数据位携带的目标数据包括：第一信号线的传输模式，对应的驱动芯片的身份标识，多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。其中，第一信号线的传输模式为回复传输模式。
可选地，第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
可选地，起始驱动芯片与多个驱动芯片中的最后一个驱动芯片不同，接收模块1003，具体用于：
通过第一信号线接收多个驱动芯片按照响应反馈顺序，从起始驱动芯片至最后一个驱动芯片依次发送的数据响应指令。
进一步的，数据请求指令还可以包括终止驱动芯片的身份标识，终止驱动芯片为多个驱动芯片中位于起始驱动芯片之后的驱动芯片，相应的，接收模块1003，具体用于：
通过第一信号线接收多个驱动芯片按照响应反馈顺序，从起始驱动芯片至终止驱动芯片依次发送的数据响应指令。
可选地，起始驱动芯片为多个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片。
可选地，多个驱动芯片的身份标识为具有顺序特征的字符，响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
可选地，多个驱动芯片的身份标识为不同的数字，响应反馈顺序为按照身份标识从小到大排列的顺序。
可选地，前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；起始标识包括连续的至少2比特二进制的0；数据位携带的目标数据为采用曼彻斯特编码得到的数据；结束标识包括连续的至少2比特二进制的1。
图11是本申请实施例在图10的基础上提供的另一种数据传输装置的结构示意图。进一步的，如图11所示，该数据传输装置1000还可以包括：
处理模块1004，用于在通过第一信号线进行信号传输的过程中，在检测到第一信号线上的信号被拉低时，执行时钟校准操作。
综上所述，本申请实施例提供的数据传输装置，生成模块生成数据请求指令，发送模块通过第一信号线发送数据请求指令，之后接收模块通过第一信号线接收多个驱动芯片从起始驱动芯片开始按照响应反馈顺序依次发送的数据响应指令，相较于相关技术，控制器通过第一信号线可以获取驱动芯片的数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
本申请实施例提供另一种数据传输装置，应用于第一驱动芯片，请参考图1A，第一驱动芯片为多个驱动芯片中的任一驱动芯片，多个驱动芯片并联，且通过一第一信号线与控制器连接，多个驱动芯片按照预设的响应反馈顺序排序，如图12所示，该数据传输装置1200包括：
第一检测模块1201，用于当接收到控制器通过第一信号线发送的数据请求指令时，检测数据请求指令中携带的起始驱动芯片的身份标识是否为第一驱动芯片的身份标识。
第一发送模块1202，用于在检测到起始驱动芯片的身份标识为第一驱动芯片的身份标识后，通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令，该第一数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
其中，第一数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
本申请实施例提供的数据传输装置，第一发送模块在检测到数据请求指令中携带的起始驱动芯片的身份标识为第一驱动芯片的身份标识后，能够通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令，第一数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据，相较于相关技术，驱动芯片通过第一信号线可以向控制器发送数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
可选地，第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
其中，前导码用于指示接收端进行时钟和相位校准，起始标识用于指示数据传输开始，数据位用于携带目标数据，结束标识用于指示数据传输结束。
可选地，数据请求指令的数据位携带的目标数据包括：第一信号线的传输模式，起始驱动芯片的身份标识，多个驱动芯片上需要配置的寄存器的地址，以及数据校验和。其中，第一信号线的传输模式为成组读取模式。
每个数据响应指令的数据位携带的目标数据包括：第一信号线的传输模式，对应的驱动芯片的身份标识，多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。其中，第一信号线的传输模式为回复传输模式。
可选地，第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
可选地，起始驱动芯片与多个驱动芯片中的最后一个驱动芯片不同，图13是本申请实施例在图12的基础上提供的另一种数据传输装置的结构示意图。进一步的，如图13所示，该数据传输装置1200还可以包括：
第二检测模块1203，用于在检测到起始驱动芯片的身份标识不为第一驱动芯片的身份标识后，当接收到另一驱动芯片通过第一信号线发送的第二数据响应指令时，检测第二数据响应指令中携带的身份标识是否为第一驱动芯片的前一个驱动芯片的身份标识。
第二发送模块1204，用于在检测到第二数据响应指令中携带的身份标识为前一个驱动芯片的身份标识后，通过第一信号线向控制器和其余驱动芯片发送第三数据响应指令，该第三数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
其中，第三数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第 一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
进一步的，数据请求指令还可以包括终止驱动芯片的身份标识，终止驱动芯片为多个驱动芯片中位于起始驱动芯片之后的驱动芯片，如图13所示，该数据传输装置1200还可以包括：
记录模块1205，用于在检测到起始驱动芯片的身份标识不为第一驱动芯片的身份标识后，记录终止驱动芯片的身份标识。
第三检测模块1026，用于当接收到另一驱动芯片通过第一信号线发送的第二数据响应指令时，检测第二数据响应指令中携带的身份标识是否为第一驱动芯片的前一个驱动芯片的身份标识。
第四检测模块1207，用于在检测到第二数据响应指令中携带的身份标识为前一个驱动芯片的身份标识后，检测前一个驱动芯片的身份标识是否为终止驱动芯片的身份标识。
第三发送模块1208，用于当前一个驱动芯片的身份标识不为终止驱动芯片的身份标识时，通过第一信号线向控制器和其余驱动芯片发送第三数据响应指令，该第三数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据。
处理模块1209，用于当前一个驱动芯片的身份标识为终止驱动芯片的身份标识时，结束动作。
其中，第三数据响应指令用于触发多个驱动芯片从第一驱动芯片之后的第一个驱动芯片开始按照响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
可选地，起始驱动芯片为多个驱动芯片按照响应反馈顺序排列得到的首个驱动芯片。
可选地，多个驱动芯片的身份标识为具有顺序特征的字符，响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
可选地，多个驱动芯片的身份标识为不同的数字，响应反馈顺序为按照身份标识从小到大排列的顺序。
可选地，前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；起始标识包括连续的至少2比特二进制的0；数据位携带的目标数据为采用曼彻斯特编码得到的数据；结束标识包括连续的至少2比特二进制的1。
进一步的，如图13所示，该数据传输装置1200还可以包括：
拉低模块1210，用于在通过第一信号线进行信号传输的过程中，当第一驱动芯片出现异常时，将第一信号线上的信号拉低，使得控制器根据拉低后的信号执行时钟校准操作。
综上所述，本申请实施例提供的数据传输装置，第一发送模块在检测到数据请求指令中携带的起始驱动芯片的身份标识为第一驱动芯片的身份标识后，能够通过第一信号线向控制器和其余驱动芯片发送第一数据响应指令，第一数据响应指令包括第一驱动芯片的身份标识和第一驱动芯片的数据，相较于相关技术，驱动芯片通过第一信号线可以向控制器发送数据，所以丰富了第一信号线的功能，提高了第一信号线的利用率。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本申请实施例提供一种显示装置，包括控制器和多个驱动芯片，该多个驱动芯片包括上述第一驱动芯片，控制器和每个驱动芯片的连接方式可以参考上图1A；该控制器包括图10或图11所示的数据传输装置；多个驱动芯片包括图12或图13所示的数据传输装置。
示例的，该显示装置可以为液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图14示出了本申请一个示例性实施例提供的显示装置1400的结构框图。该装置1400可以是液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。通常，该装置1400包括有：处理器1401和存储器1402。
处理器1401可以包括一个或多个处理核心，比如4核心处理器、8核心处理器等。处理器1401可以采用DSP(Digital Signal Processing，数字信号处理)、FPGA(Field－Programmable Gate Array，现场可编程门阵列)、PLA(Programmable Logic Array，可编程逻辑阵列)中的至少一种硬件形式来实现。处理器1401也可以包括主处理器和协处理器，主处理器是用于对在唤醒状态下的数据进行处理的处理器，也称CPU(Central Processing Unit，中央处理器)；协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施 例中，处理器1401可以在集成有GPU(Graphics Processing Unit，图像处理器)，GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中，处理器1401还可以包括AI(Artificial Intelligence，人工智能)处理器，该AI处理器用于处理有关机器学习的计算操作。
存储器1402可以包括一个或多个计算机可读存储介质，该计算机可读存储介质可以是非暂态的。存储器1402还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。在一些实施例中，存储器1402中的非暂态的计算机可读存储介质用于存储至少一个指令，该至少一个指令用于被处理器1401所执行以实现本申请中方法实施例提供的数据传输方法。
在一些实施例中，装置1400还可选包括有：外围设备接口1403和至少一个外围设备。处理器1401、存储器1402和外围设备接口1403之间可以通过总线或信号线相连。各个外围设备可以通过总线、信号线或电路板与外围设备接口1403相连。具体地，外围设备包括：射频电路1404、显示屏1405、摄像头1406、音频电路1407、定位组件1408和电源1409中的至少一种。
外围设备接口1403可被用于将I/O(Input/Output，输入/输出)相关的至少一个外围设备连接到处理器1401和存储器1402。在一些实施例中，处理器1401、存储器1402和外围设备接口1403被集成在同一芯片或电路板上；在一些其他实施例中，处理器1401、存储器1402和外围设备接口1403中的任意一个或两个可以在单独的芯片或电路板上实现，本实施例对此不加以限定。
射频电路1404用于接收和发射RF(Radio Frequency，射频)信号，也称电磁信号。射频电路1404通过电磁信号与通信网络以及其他通信设备进行通信。射频电路1404将电信号转换为电磁信号进行发送，或者，将接收到的电磁信号转换为电信号。可选地，射频电路1404包括：天线系统、RF收发器、一个或多个放大器、调谐器、振荡器、数字信号处理器、编解码芯片组、用户身份模块卡等等。射频电路1404可以通过至少一种无线通信协议来与其它装置进行通信。该无线通信协议包括但不限于：城域网、各代移动通信网络(2G、3G、4G及5G)、无线局域网和/或WiFi(Wireless Fidelity，无线保真)网络。在一些实施例中，射频电路1404还可以包括NFC(Near Field Communication，近距离无线通信)有关的电路，本申请对此不加以限定。
显示屏1405用于显示UI(User Interface，用户界面)。该UI可以包括图形、 文本、图标、视频及其它们的任意组合。当显示屏1405是触摸显示屏时，显示屏1405还具有采集在显示屏1405的表面或表面上方的触摸信号的能力。该触摸信号可以作为控制信号输入至处理器1401进行处理。此时，显示屏1405还可以用于提供虚拟按钮和/或虚拟键盘，也称软按钮和/或软键盘。在一些实施例中，显示屏1405可以为一个，设置装置1400的前面板；在另一些实施例中，显示屏1405可以为至少两个，分别设置在装置1400的不同表面或呈折叠设计；在再一些实施例中，显示屏1405可以是柔性显示屏，设置在装置1400的弯曲表面上或折叠面上。甚至，显示屏1405还可以设置成非矩形的不规则图形，也即异形屏。显示屏1405可以包括LCD显示面板或OLED显示面板。
摄像头组件1406用于采集图像或视频。可选地，摄像头组件1406包括前置摄像头和后置摄像头。通常，前置摄像头设置在装置的前面板，后置摄像头设置在装置的背面。在一些实施例中，后置摄像头为至少两个，分别为主摄像头、景深摄像头、广角摄像头、长焦摄像头中的任意一种，以实现主摄像头和景深摄像头融合实现背景虚化功能、主摄像头和广角摄像头融合实现全景拍摄以及VR(Virtual Reality，虚拟现实)拍摄功能或者其它融合拍摄功能。在一些实施例中，摄像头组件1406还可以包括闪光灯。闪光灯可以是单色温闪光灯，也可以是双色温闪光灯。双色温闪光灯是指暖光闪光灯和冷光闪光灯的组合，可以用于不同色温下的光线补偿。
音频电路1407可以包括麦克风和扬声器。麦克风用于采集用户及环境的声波，并将声波转换为电信号输入至处理器1401进行处理，或者输入至射频电路1404以实现语音通信。出于立体声采集或降噪的目的，麦克风可以为多个，分别设置在装置1400的不同部位。麦克风还可以是阵列麦克风或全向采集型麦克风。扬声器则用于将来自处理器1401或射频电路1404的电信号转换为声波。扬声器可以是传统的薄膜扬声器，也可以是压电陶瓷扬声器。当扬声器是压电陶瓷扬声器时，不仅可以将电信号转换为人类可听见的声波，也可以将电信号转换为人类听不见的声波以进行测距等用途。在一些实施例中，音频电路1407还可以包括耳机插孔。
定位组件1408用于定位装置1400的当前地理位置，以实现导航或LBS(Location Based Service，基于位置的服务)。定位组件1408可以是基于美国的GPS(Global Positioning System，全球定位系统)、中国的北斗系统或俄罗斯的格雷纳斯系统或欧盟的伽利略系统的定位组件。
电源1409用于为装置1400中的各个组件进行供电。电源1409可以是交流电、直流电、一次性电池或可充电电池。当电源1409包括可充电电池时，该可充电电池可以支持有线充电或无线充电。该可充电电池还可以用于支持快充技术。
在一些实施例中，装置1400还包括有一个或多个传感器1410。该一个或多个传感器1410包括但不限于：加速度传感器1411、陀螺仪传感器1412、压力传感器1413、指纹传感器1414、光学传感器1415以及接近传感器1416。
加速度传感器1411可以检测以装置1400建立的坐标系的三个坐标轴上的加速度大小。比如，加速度传感器1411可以用于检测重力加速度在三个坐标轴上的分量。处理器1401可以根据加速度传感器1411采集的重力加速度信号，控制触摸显示屏1405以横向视图或纵向视图进行用户界面的显示。加速度传感器1411还可以用于游戏或者用户的运动数据的采集。
陀螺仪传感器1412可以检测装置1400的机体方向及转动角度，陀螺仪传感器1412可以与加速度传感器1411协同采集用户对装置1400的3D动作。处理器1401根据陀螺仪传感器1412采集的数据，可以实现如下功能：动作感应(比如根据用户的倾斜操作来改变UI)、拍摄时的图像稳定、游戏控制以及惯性导航。
压力传感器1413可以设置在装置1400的侧边框和/或触摸显示屏1405的下层。当压力传感器1413设置在装置1400的侧边框时，可以检测用户对装置1400的握持信号，由处理器1401根据压力传感器1413采集的握持信号进行左右手识别或快捷操作。当压力传感器1413设置在触摸显示屏1405的下层时，由处理器1401根据用户对触摸显示屏1405的压力操作，实现对UI界面上的可操作性控件进行控制。可操作性控件包括按钮控件、滚动条控件、图标控件、菜单控件中的至少一种。
指纹传感器1414用于采集用户的指纹，由处理器1401根据指纹传感器1414采集到的指纹识别用户的身份，或者，由指纹传感器1414根据采集到的指纹识别用户的身份。在识别出用户的身份为可信身份时，由处理器1401授权该用户执行相关的敏感操作，该敏感操作包括解锁屏幕、查看加密信息、下载软件、支付及更改设置等。指纹传感器1414可以被设置装置1400的正面、背面或侧面。当装置1400上设置有物理按键或厂商Logo时，指纹传感器1414可以与物理按键或厂商Logo集成在一起。
光学传感器1415用于采集环境光强度。在一个实施例中，处理器1401可以根据光学传感器1415采集的环境光强度，控制触摸显示屏1405的显示亮度。具体地，当环境光强度较高时，调高触摸显示屏1405的显示亮度；当环境光强度较低时，调低触摸显示屏1405的显示亮度。在另一个实施例中，处理器1401还可以根据光学传感器1415采集的环境光强度，动态调整摄像头组件1406的拍摄参数。
接近传感器1416，也称距离传感器，通常设置在装置1400的前面板。接近传感器1416用于采集用户与装置1400的正面之间的距离。在一个实施例中，当接近传感器1416检测到用户与装置1400的正面之间的距离逐渐变小时，由处理器1401控制触摸显示屏1405从亮屏状态切换为息屏状态；当接近传感器1416检测到用户与装置1400的正面之间的距离逐渐变大时，由处理器1401控制触摸显示屏1405从息屏状态切换为亮屏状态。
本领域技术人员可以理解，图14中示出的结构并不构成对装置1400的限定，可以包括比图示更多或更少的组件，或者组合某些组件，或者采用不同的组件布置。
本申请实施例还提供了一种数据传输装置，应用于控制器，该控制器通过一第一信号线与并联的多个驱动芯片连接，多个驱动芯片按照预设的响应反馈顺序排序，该数据传输装置包括：
一个或多个处理器；和
存储器；
所述存储器存储有一个或多个程序，所述一个或多个程序被配置成由所述一个或多个处理器执行，且经配置由所述一个或多个处理器通过执行上述程序来执行上述实施例中控制器所执行的数据传输方法。
本申请实施例还提供了一种数据传输装置，应用于第一驱动芯片，该第一驱动芯片为多个驱动芯片中的任一驱动芯片，多个驱动芯片并联，且通过一第一信号线与控制器连接，多个驱动芯片按照预设的响应反馈顺序排序，该数据传输装置包括：
一个或多个处理器；和
存储器；
所述存储器存储有一个或多个程序，所述一个或多个程序被配置成由所述 一个或多个处理器执行，且经配置由所述一个或多个处理器通过执行上述程序来执行上述实施例中第一驱动芯片所执行的数据传输方法。
本申请实施例提供了一种数据传输装置，包括存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行计算机程序时实现图2或图4所示的数据传输方法。
本申请实施例提供了一种数据传输装置，包括存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行计算机程序时实现图3或图4所示的数据传输方法。
本申请实施例提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时用于实现图2或图4所示的数据传输方法。
本申请实施例提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时用于实现图3或图4所示的数据传输方法。
本申请实施例提供了一种计算机可读存储介质，该存储介质为非易失性可读存储介质，其存储有计算机程序，计算机程序被处理器执行时，实现图2或图4所示的数据传输方法。
本申请实施例提供了另一种计算机可读存储介质，该存储介质为非易失性可读存储介质，其存储有计算机程序，计算机程序被处理器执行时，实现图3或图4所示的数据传输方法。
本申请实施例还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行图2或图4所示的数据传输方法。
本申请实施例还提供另一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行图3或图4所示的数据传输方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的 权利要求来限制。

Claims (51)

  1. 一种数据传输方法，应用于控制器，所述控制器通过一第一信号线与并联的多个驱动芯片连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述方法包括：
    生成数据请求指令，所述数据请求指令包括起始驱动芯片的身份标识，所述起始驱动芯片为所述多个驱动芯片中的驱动芯片；
    通过所述第一信号线向所述多个驱动芯片发送所述数据请求指令；
    通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，每个所述数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  2. 根据权利要求1所述的方法，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
    其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
  3. 根据权利要求2所述的方法，
    所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
    每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
  4. 根据权利要求1所述的方法，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
  5. 根据权利要求1至4任一所述的方法，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，
    所述通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，包括：
    通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述最后一个驱动芯片依次发送的数据响应指令。
  6. 根据权利要求1至4任一所述的方法，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，
    所述通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，包括：
    通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述终止驱动芯片依次发送的数据响应指令。
  7. 根据权利要求5或6所述的方法，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
  8. 根据权利要求1所述的方法，所述多个驱动芯片的身份标识为具有顺序特征的字符，
    所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
  9. 根据权利要求8所述的方法，所述多个驱动芯片的身份标识为不同的数字，
    所述响应反馈顺序为按照身份标识从小到大排列的顺序。
  10. 根据权利要求2所述的方法，
    所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
    所述起始标识包括连续的至少2比特二进制的0；
    所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
    所述结束标识包括连续的至少2比特二进制的1。
  11. 根据权利要求1所述的方法，所述方法还包括：
    在通过所述第一信号线进行信号传输的过程中，在检测到所述第一信号线上的信号被拉低时，执行时钟校准操作。
  12. 一种数据传输方法，应用于第一驱动芯片，所述第一驱动芯片为多个驱动芯片中的任一驱动芯片，所述多个驱动芯片并联，且通过一第一信号线与控制器连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述方法包括：
    当接收到所述控制器通过所述第一信号线发送的数据请求指令时，检测所述数据请求指令中携带的起始驱动芯片的身份标识是否为所述第一驱动芯片的身份标识；
    在检测到所述起始驱动芯片的身份标识为所述第一驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第一数据响应指令，所述第一数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
    其中，所述第一数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  13. 根据权利要求12所述的方法，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
    其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
  14. 根据权利要求13所述的方法，
    所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
    每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
  15. 根据权利要求12所述的方法，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
  16. 根据权利要求12至15任一所述的方法，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，所述方法还包括：
    在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
    在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
    其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  17. 根据权利要求12至15任一所述的方法，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，所述方法还包括：
    在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，记录所述终止驱动芯片的身份标识；
    当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
    在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，检测所述前一个驱动芯片的身份标识是否为所述终止驱动芯片的身份标识；
    当所述前一个驱动芯片的身份标识不为所述终止驱动芯片的身份标识时， 通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
    当所述前一个驱动芯片的身份标识为所述终止驱动芯片的身份标识时，结束动作；
    其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  18. 根据权利要求16或17所述的方法，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
  19. 根据权利要求12所述的方法，所述多个驱动芯片的身份标识为具有顺序特征的字符，
    所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
  20. 根据权利要求19所述的方法，所述多个驱动芯片的身份标识为不同的数字，
    所述响应反馈顺序为按照身份标识从小到大排列的顺序。
  21. 根据权利要求13所述的方法，
    所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
    所述起始标识包括连续的至少2比特二进制的0；
    所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
    所述结束标识包括连续的至少2比特二进制的1。
  22. 根据权利要求12所述的方法，所述方法还包括：
    在通过所述第一信号线进行信号传输的过程中，当所述第一驱动芯片出现异常时，将所述第一信号线上的信号拉低，使得所述控制器根据拉低后的信号执行时钟校准操作。
  23. 一种数据传输系统，包括时序控制器和并联的多个源极驱动芯片，所述时序控制器通过一第一信号线与并联的多个源极驱动芯片连接，所述多个源极驱动芯片按照预设的响应反馈顺序排序，
    所述时序控制器，用于生成数据请求指令，并通过所述第一信号线发送所述数据请求指令，所述数据请求指令包括起始源极驱动芯片的身份标识，所述起始源极驱动芯片与所述多个源极驱动芯片中的最后一个源极驱动芯片不同；
    所述起始源极驱动芯片，用于在接收到所述数据请求指令时通过所述第一信号线向所述时序控制器和其余源极驱动芯片发送第一数据响应指令，所述第一数据响应指令包括所述起始源极驱动芯片的身份标识和所述起始源极驱动芯片的数据；
    所述起始源极驱动芯片之后的每一个源极驱动芯片，用于在接收到另一源极驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述源极驱动芯片的前一个源极驱动芯片的身份标识；在检测到所述第二数据响应指令中携带的身份标识为所述前一个源极驱动芯片的身份标识后，通过所述第一信号线向所述时序控制器和其余源极驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述源极驱动芯片的身份标识和所述源极驱动芯片的数据。
  24. 根据权利要求23所述的系统，所述起始源极驱动芯片为所述多个源极驱动芯片按照所述响应反馈顺序排列得到的首个源极驱动芯片。
  25. 一种数据传输装置，应用于控制器，所述控制器通过一第一信号线与并联的多个驱动芯片连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述数据传输装置包括：
    一个或多个处理器；和
    存储器；
    所述存储器存储有一个或多个程序，所述一个或多个程序被配置成由所述一个或多个处理器执行，所述一个或多个程序包含用于进行以下操作的指令：
    生成数据请求指令，所述数据请求指令包括起始驱动芯片的身份标识，所述起始驱动芯片为所述多个驱动芯片中的驱动芯片；
    通过所述第一信号线向所述多个驱动芯片发送所述数据请求指令；
    通过所述第一信号线接收所述多个驱动芯片从所述起始驱动芯片开始按照所述响应反馈顺序依次发送的数据响应指令，每个所述数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  26. 根据权利要求25所述的数据传输装置，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
    其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
  27. 根据权利要求26所述的数据传输装置，
    所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
    每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
  28. 根据权利要求25所述的数据传输装置，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
  29. 根据权利要求25至28任一所述的数据传输装置，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，
    所述一个或多个程序还包含用于进行以下操作的指令：
    通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述最后一个驱动芯片依次发送的数据响应指令。
  30. 根据权利要求25至28任一所述的数据传输装置，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，
    所述一个或多个程序还包含用于进行以下操作的指令：
    通过所述第一信号线接收所述多个驱动芯片按照所述响应反馈顺序，从所述起始驱动芯片至所述终止驱动芯片依次发送的数据响应指令。
  31. 根据权利要求29或30所述的数据传输装置，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
  32. 根据权利要求25所述的数据传输装置，所述多个驱动芯片的身份标识为具有顺序特征的字符，
    所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
  33. 根据权利要求32所述的数据传输装置，所述多个驱动芯片的身份标识为不同的数字，
    所述响应反馈顺序为按照身份标识从小到大排列的顺序。
  34. 根据权利要求26所述的数据传输装置，
    所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
    所述起始标识包括连续的至少2比特二进制的0；
    所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
    所述结束标识包括连续的至少2比特二进制的1。
  35. 根据权利要求25所述的数据传输装置，所述一个或多个程序还包含用于进行以下操作的指令：
    在通过所述第一信号线进行信号传输的过程中，在检测到所述第一信号线上的信号被拉低时，执行时钟校准操作。
  36. 一种数据传输装置，应用于第一驱动芯片，所述第一驱动芯片为多个驱动芯片中的任一驱动芯片，所述多个驱动芯片并联，且通过一第一信号线与控制器连接，所述多个驱动芯片按照预设的响应反馈顺序排序，所述数据传输装置包括：
    一个或多个处理器；和
    存储器；
    所述存储器存储有一个或多个程序，所述一个或多个程序被配置成由所述一个或多个处理器执行，所述一个或多个程序包含用于进行以下操作的指令：
    当接收到所述控制器通过所述第一信号线发送的数据请求指令时，检测所述数据请求指令中携带的起始驱动芯片的身份标识是否为所述第一驱动芯片的身份标识；
    在检测到所述起始驱动芯片的身份标识为所述第一驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第一数据响应指令，所述第一数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
    其中，所述第一数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  37. 根据权利要求36所述的数据传输装置，所述第一信号线上传输的指令均包括依次排列的前导码、起始标识、数据位和结束标识；
    其中，所述前导码用于指示接收端进行时钟和相位校准，所述起始标识用于指示数据传输开始，所述数据位用于携带目标数据，所述结束标识用于指示数据传输结束。
  38. 根据权利要求37所述的数据传输装置，
    所述数据请求指令的数据位携带的目标数据包括：所述第一信号线的传输模式，所述起始驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，以及数据校验和；
    每个所述数据响应指令的数据位携带的目标数据包括：所述第一信号线的传输模式，对应的驱动芯片的身份标识，所述多个驱动芯片上需要配置的寄存器的地址，对应的驱动芯片的数据，以及数据校验和。
  39. 根据权利要求36所述的数据传输装置，所述第一信号线上传输的相邻两个指令之间的时间间隔相等，且均为预设时长。
  40. 根据权利要求36至39任一所述的数据传输装置，所述起始驱动芯片与所述多个驱动芯片中的最后一个驱动芯片不同，所述一个或多个程序还包含用于进行以下操作的指令：
    在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
    在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
    其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  41. 根据权利要求36至39任一所述的数据传输装置，所述数据请求指令还包括终止驱动芯片的身份标识，所述终止驱动芯片为所述多个驱动芯片中位于所述起始驱动芯片之后的驱动芯片，所述一个或多个程序还包含用于进行以下操作的指令：
    在检测到所述起始驱动芯片的身份标识不为所述第一驱动芯片的身份标识后，记录所述终止驱动芯片的身份标识；
    当接收到另一驱动芯片通过所述第一信号线发送的第二数据响应指令时，检测所述第二数据响应指令中携带的身份标识是否为所述第一驱动芯片的前一个驱动芯片的身份标识；
    在检测到所述第二数据响应指令中携带的身份标识为所述前一个驱动芯片的身份标识后，检测所述前一个驱动芯片的身份标识是否为所述终止驱动芯片的身份标识；
    当所述前一个驱动芯片的身份标识不为所述终止驱动芯片的身份标识时，通过所述第一信号线向所述控制器和其余驱动芯片发送第三数据响应指令，所 述第三数据响应指令包括所述第一驱动芯片的身份标识和所述第一驱动芯片的数据；
    当所述前一个驱动芯片的身份标识为所述终止驱动芯片的身份标识时，结束动作；
    其中，所述第三数据响应指令用于触发所述多个驱动芯片从所述第一驱动芯片之后的第一个驱动芯片开始按照所述响应反馈顺序依次发送数据响应指令，每个数据响应指令包括对应的驱动芯片的身份标识和对应的驱动芯片的数据。
  42. 根据权利要求40或41所述的数据传输装置，所述起始驱动芯片为所述多个驱动芯片按照所述响应反馈顺序排列得到的首个驱动芯片。
  43. 根据权利要求36所述的数据传输装置，所述多个驱动芯片的身份标识为具有顺序特征的字符，
    所述响应反馈顺序为按照身份标识的顺序特征排序得到的顺序。
  44. 根据权利要求43所述的数据传输装置，所述多个驱动芯片的身份标识为不同的数字，
    所述响应反馈顺序为按照身份标识从小到大排列的顺序。
  45. 根据权利要求37所述的数据传输装置，
    所述前导码由连续的至少8比特二进制的0采用曼彻斯特编码得到；
    所述起始标识包括连续的至少2比特二进制的0；
    所述数据位携带的目标数据为采用曼彻斯特编码得到的数据；
    所述结束标识包括连续的至少2比特二进制的1。
  46. 根据权利要求36所述的数据传输装置，所述一个或多个程序还包含用于进行以下操作的指令：
    在通过所述第一信号线进行信号传输的过程中，当所述第一驱动芯片出现异常时，将所述第一信号线上的信号拉低，使得所述控制器根据拉低后的信号执行时钟校准操作。
  47. 一种显示装置，包括控制器和多个驱动芯片，
    所述控制器包括权利要求25至35任一所述的数据传输装置；
    所述多个驱动芯片包括权利要求36至46任一所述的数据传输装置。
  48. 一种数据传输装置，包括存储器，处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现权利要求1至11任一所述的数据传输方法。
  49. 一种数据传输装置，包括存储器，处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现权利要求12至22任一所述的数据传输方法。
  50. 一种计算机可读存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时，实现权利要求1至11任一所述的数据传输方法。
  51. 一种计算机可读存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时，实现权利要求12至22任一所述的数据传输方法。
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