WO2019160015A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2019160015A1
WO2019160015A1 PCT/JP2019/005281 JP2019005281W WO2019160015A1 WO 2019160015 A1 WO2019160015 A1 WO 2019160015A1 JP 2019005281 W JP2019005281 W JP 2019005281W WO 2019160015 A1 WO2019160015 A1 WO 2019160015A1
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WO
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Prior art keywords
transistor
voltage
type mos
signal line
signal
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PCT/JP2019/005281
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French (fr)
Japanese (ja)
Inventor
春敏 長友
Original Assignee
株式会社吉川システック
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Application filed by 株式会社吉川システック filed Critical 株式会社吉川システック
Priority to CN201980012774.7A priority Critical patent/CN111712911A/en
Publication of WO2019160015A1 publication Critical patent/WO2019160015A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a technology for protecting a semiconductor device from reverse engineering.
  • Patent Documents 1 to 9 Various methods for preventing reverse engineering have been proposed (see, for example, Patent Documents 1 to 9).
  • In order to prevent reverse engineering for example, by modifying the transistor characteristics and connection information by devising the wiring layer or using a diffusion layer or bulk below the wiring layer, just reading the wiring layer Proposals have been made to prevent functions from being reproduced.
  • Patent Document 1 a semiconductor device is reproduced by reverse engineering by using a transistor with a gate in a floating state and generating a signal using a difference in output voltage due to variation in transistor characteristics. Techniques that make this difficult are proposed.
  • Patent Document 1 Since the gate is in a floating state, a wasteful consumption current flows from the power supply voltage to the ground, and when noise occurs due to crosstalk or the like, voltage fluctuation occurs and the operation and current consumption are not stable.
  • the output voltage generated by a plurality of transistors is not a binarized voltage but a continuous analog amount, a comparator that receives the output requires high-precision analog characteristics, which increases current consumption and size. . Due to such current consumption and size restrictions, there are restrictions on the number of chips that can be mounted on one chip. Another method for preventing reverse engineering requires a special process, which increases the process development period and cost.
  • An object of the present invention is to provide a semiconductor device that makes it difficult to reproduce the semiconductor device by reverse engineering.
  • the semiconductor device is connected in series between a signal line for supplying a first voltage and a signal line for supplying a second voltage lower than the first voltage, and each gate has a predetermined value.
  • a plurality of first signal output circuits that output a voltage at a connection point of the first transistor and the second transistor;
  • a third transistor and a fourth transistor are connected in series between a signal line supplying a first voltage and a signal line supplying the second voltage, and a predetermined voltage is supplied to each gate.
  • the third transistor has different characteristics with the same layout as the first transistor
  • the fourth transistor has different characteristics with the same layout as the second transistor
  • Serial and outputs the third transistor and the voltage at the connection point of said fourth transistor characterized in that it comprises a plurality of second signal output circuit.
  • FIG. 1A is a diagram illustrating an example of a semiconductor device according to the first embodiment.
  • FIG. 1B is a diagram illustrating an example of the semiconductor device according to the first embodiment.
  • FIG. 2A is a diagram illustrating an example of a semiconductor device according to the second embodiment.
  • FIG. 2B is a diagram illustrating an example of a semiconductor device according to the second embodiment.
  • FIG. 3A is a diagram illustrating an example of a semiconductor device according to the third embodiment.
  • FIG. 3B is a diagram illustrating an example of a semiconductor device according to the third embodiment.
  • FIG. 4A is a diagram illustrating an example of a semiconductor device according to the fourth embodiment.
  • FIG. 4B is a diagram illustrating an example of a semiconductor device according to the fourth embodiment.
  • FIG. 4A is a diagram illustrating an example of a semiconductor device according to the fourth embodiment.
  • FIG. 5A is a diagram illustrating an example of a semiconductor device according to the fifth embodiment.
  • FIG. 5B is a diagram illustrating an example of a semiconductor device according to the fifth embodiment.
  • FIG. 6A is a diagram illustrating an example of a semiconductor device according to the sixth embodiment.
  • FIG. 6B is a diagram illustrating an example of a semiconductor device according to the sixth embodiment.
  • FIG. 7A is a diagram illustrating an example of a semiconductor device according to the seventh embodiment.
  • FIG. 7B is a diagram illustrating an example of a semiconductor device according to the seventh embodiment.
  • FIG. 8 is a diagram illustrating an application example of the semiconductor device according to the present embodiment.
  • the semiconductor device according to the first embodiment includes a plurality of signal output circuits as shown in FIGS. 1A and 1B.
  • 1A and 1B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to the first embodiment.
  • the first signal output circuit shown in FIG. 1A includes N-type MOS transistors MN101, MN102, MN103, MN104, and an amplifier unit 11.
  • Two N-type MOS transistors MN101 and MN102 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the two N-type MOS transistors MN101 and MN102 is output as the signal SINA.
  • the N-type MOS transistors MN101 and MN102 have gates connected to a signal line that supplies the power supply voltage VDD, and back gates connected to a signal line that supplies the reference voltage GND.
  • Two N-type MOS transistors MN103 and MN104 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point between the two N-type MOS transistors MN103 and MN104 is output as the signal SINB.
  • the N-type MOS transistors MN103 and MN104 have their gates connected to a signal line that supplies the power supply voltage VDD, and their back gates connected to a signal line that supplies the reference voltage GND.
  • the signal SINA is input to the input terminal INA, and the signal SINB is input to the input terminal INB. Based on the input signal SINA and the voltage of the signal SINB, the amplifying unit 11 outputs a signal “1” at the power supply voltage VDD level or a signal “0” at the reference voltage GND level as the output signal SOUT from the output terminal OUT. Output.
  • the function of the amplifying unit 11 is realized by a level shifter (level shift circuit) having P-type MOS transistors MP11 and MP12 and N-type MOS transistors MN11 and MN12. By using a level shifter (level shift circuit) as the amplifying unit 11, it is possible to prevent an excessive through current from flowing, and to reduce current consumption.
  • the P-type MOS transistor MP11 and the N-type MOS transistor MN11 are connected in series in this order from the signal line supplying the power supply voltage VDD. Connected to.
  • the P-type MOS transistor MP12 and the N-type MOS transistor MN12 are arranged in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. Connected in series.
  • the signal SINA is input to the gate of the N-type MOS transistor MN11, and the signal SINB is input to the gate of the N-type MOS transistor MN12.
  • the gate of the P-type MOS transistor MP11 is connected to the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12, and the gate of the P-type MOS transistor MP12 is connected to the P-type MOS transistor MP11 and the N-type MOS transistor MN11. Connected to the connection point.
  • the voltage at the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12 is output as the output signal SOUT.
  • the threshold voltages of the N-type MOS transistors MN101 and MN104 are the same voltage and are higher than the power supply voltage VDD.
  • the threshold voltages of the N-type MOS transistors MN102 and MN103 are the same voltage, which is a general (standard) threshold voltage (for example, about +0.5 V).
  • Transistor threshold voltage control is realized by channel implant doping control that changes the doping amount for the channel, gate oxide film thickness control that changes the gate oxide thickness, and back gate voltage control that uses the back gate effect. Is possible. Note that in the drawing, (HVT) is added to indicate that the transistor has a high threshold voltage (the same applies to the following embodiments).
  • the layout of the two N-type MOS transistors MN101 and MN102 and the layout of the two N-type MOS transistors MN103 and MN104 have the same shape including the wirings related to them. That is, the layout and wiring shape of the N-type MOS transistors MN101 and MN103 are the same, and the layout and wiring shape of the N-type MOS transistors MN102 and MN104 are the same.
  • the gate lengths and gate widths of the N-type MOS transistors MN101 and MN103 are the same, and the gate lengths and gate widths of the N-type MOS transistors MN102 and MN104 are the same.
  • the layouts and wiring shapes of the N-type MOS transistors MN101 and MN103 are the same, it is indistinguishable in terms of which transistor has a threshold higher than the power supply voltage VDD.
  • the layouts and wiring shapes of the N-type MOS transistors MN102 and MN104 are the same, it cannot be distinguished in terms of which transistor has a threshold value higher than the power supply voltage VDD.
  • the N-type MOS transistors MN101 and MN104 having a threshold voltage higher than the power supply voltage VDD are turned off, and the N-type having a general (standard) threshold voltage is set.
  • the MOS transistors MN102 and MN103 are turned on. Therefore, the voltage at the connection point of the N-type MOS transistors MN101 and MN102 (signal SINA) is substantially the reference voltage GND, and the voltage at the connection point of the N-type MOS transistors MN103 and MN104 (signal SINB) is N from the power supply voltage VDD.
  • the threshold voltage VTH of the type MOS transistor MN103 is lower (VDD ⁇ VTH).
  • the circuit shown in FIG. 1A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
  • the second signal output circuit shown in FIG. 1B includes N-type MOS transistors MN105, MN106, MN107, MN108, and an amplifying unit 11.
  • the same components as those shown in FIG. 1A are denoted by the same reference numerals, and redundant description is omitted.
  • Two N-type MOS transistors MN105 and MN106 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the two N-type MOS transistors MN105 and MN106 is output as the signal SINA.
  • the N-type MOS transistors MN105 and MN106 have gates connected to a signal line that supplies the power supply voltage VDD, and back gates connected to a signal line that supplies the reference voltage GND.
  • Two N-type MOS transistors MN107 and MN108 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point between the two N-type MOS transistors MN107 and MN108 is output as the signal SINB.
  • the N-type MOS transistors MN107 and MN108 have gates connected to a signal line that supplies a power supply voltage VDD, and back gates connected to a signal line that supplies a reference voltage GND.
  • the threshold voltages of the N-type MOS transistors MN106 and MN107 are the same voltage and are higher than the power supply voltage VDD.
  • the threshold voltages of the N-type MOS transistors MN105 and MN108 are the same voltage and are general (standard) threshold voltages. That is, for each of the two N-type MOS transistors that output the signal SINA and the two N-type MOS transistors that output the signal SINB, the arrangement of the transistors is changed, and a circuit configuration that outputs the signals SINA and SINB is obtained. This is the reverse of that shown in FIG. 1A.
  • the layout of the two N-type MOS transistors MN105 and MN106 and the layout of the two N-type MOS transistors MN107 and MN108 have the same shape including the wirings related to them.
  • N-type MOS transistors MN105 and MN107 have the same layout and wiring shapes, and N-type MOS transistors MN106 and MN108 have the same layout and wiring shapes. Therefore, in the N-type MOS transistors MN105 and MN107, it is not apparent from the outside whether the transistor having a threshold value higher than the power supply voltage VDD is present. It is indistinguishable in terms of which transistor has a high threshold.
  • the N-type MOS transistors MN106 and MN107 having a threshold voltage higher than the power supply voltage VDD are turned off, and the N-type having a general (standard) threshold voltage is applied.
  • the MOS transistors MN105 and MN108 are turned on. Accordingly, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN105 and MN106 is lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN105 (VDD ⁇ VTH), and the N-type MOS transistors MN107,
  • the voltage (signal SINB) at the connection point of the MN 108 is substantially the reference voltage GND.
  • the circuit shown in FIG. 1B outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
  • transistors having different characteristics are used, the layout and wiring shape are the same, but two signal output circuits that realize different functions are used, and output signals are output in accordance with signals from the two signal output circuits.
  • the level of is determined. As a result, the operation cannot be reproduced simply by reading the circuit diagram from the layout, and the reproduction of the semiconductor device by reverse engineering can be made difficult.
  • the size can be realized by 8 transistors equivalent to a 4-input NAND, and a large number of signal output circuits are mounted in an automatic placement and wiring area on a semiconductor chip. be able to.
  • a large number of signal output circuits in this embodiment are mounted on a semiconductor chip, it is necessary to identify all functions (output states) of these signal output circuits when performing reverse engineering. In the method used, it is very difficult and unrealistic to analyze all the signal output circuits mounted.
  • the semiconductor device includes two N-type MOS transistors connected in series between the signal line that supplies the power supply voltage VDD and the signal line that supplies the reference voltage GND in the first embodiment. Two P-type MOS transistors are provided.
  • the semiconductor device according to the second embodiment has a plurality of signal output circuits as shown in FIGS. 2A and 2B.
  • 2A and 2B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the second embodiment.
  • the first signal output circuit shown in FIG. 2A includes P-type MOS transistors MP201, MP202, MP203, MP204, and an amplifying unit 21.
  • Two P-type MOS transistors MP201 and MP202 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the two P-type MOS transistors MP201 and MP202 is output as the signal SINA.
  • the gate is connected to a signal line that supplies a reference voltage GND, and the back gate is connected to a signal line that supplies a power supply voltage VDD.
  • Two P-type MOS transistors MP203 and MP204 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point between the two P-type MOS transistors MP203 and MP204 is output as the signal SINB.
  • the gate is connected to a signal line that supplies the reference voltage GND, and the back gate is connected to a signal line that supplies the power supply voltage VDD.
  • the signal SINA is input to the input terminal INA
  • the signal SINB is input to the input terminal INB.
  • the amplifying unit 21 Based on the input signal SINA and the voltage of the signal SINB, the amplifying unit 21 outputs a signal “1” at the power supply voltage VDD level or a signal “0” at the reference voltage GND level as the output signal SOUT from the output terminal OUT. Output.
  • the function of the amplifying unit 21 is realized by a level shifter (level shift circuit) having P-type MOS transistors MP21 and MP22 and N-type MOS transistors MN21 and MN22.
  • the P-type MOS transistor MP21 and the N-type MOS transistor MN21 are connected in series in this order from the signal line supplying the power supply voltage VDD. Connected to.
  • the P-type MOS transistor MP22 and the N-type MOS transistor MN22 are arranged in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. Connected in series.
  • the signal SINA is input to the gate of the P-type MOS transistor MP21, and the signal SINB is input to the gate of the P-type MOS transistor MP22.
  • the gate of the N-type MOS transistor MN21 is connected to the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22, and the gate of the N-type MOS transistor MN22 is connected between the P-type MOS transistor MP21 and the N-type MOS transistor MN21. Connected to the connection point.
  • the voltage at the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22 is output as the output signal SOUT.
  • the threshold voltages of the P-type MOS transistors MP201 and MP204 are the same voltage, which is lower than the value of (reference voltage GND ⁇ power supply voltage VDD). Further, the threshold voltages of the P-type MOS transistors MP202 and MP203 are the same voltage, and are general (standard) threshold voltages. Control of the threshold voltage of the transistor can be realized by channel implant doping control, gate oxide film thickness control, back gate voltage control, and the like, as in the first embodiment.
  • the layout of the two P-type MOS transistors MP201 and MP202 and the layout of the two P-type MOS transistors MP203 and MP204 have the same shape including the wirings related to them. That is, the layout and wiring shape of the P-type MOS transistors MP201 and MP203 are the same, and the layout and wiring shape of the P-type MOS transistors MP202 and MP204 are the same.
  • the P-type MOS transistors MP201 and MP203 have the same gate length and gate width
  • the P-type MOS transistors MP202 and MP204 have the same gate length and gate width.
  • the P-type MOS transistors MP201 and MP204 having a threshold voltage lower than the value of (reference voltage GND ⁇ power supply voltage VDD) are turned off, and the general (standard) ) P-type MOS transistors MP202 and MP203 having a threshold voltage are turned on. Therefore, the voltage (signal SINA) at the connection point between the P-type MOS transistors MP201 and MP202 becomes (GND +
  • the voltage (signal SINB) at the connection point of the transistors MP203 and MP204 is substantially the power supply voltage VDD.
  • the circuit shown in FIG. 2A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
  • the second signal output circuit shown in FIG. 2B includes P-type MOS transistors MP205, MP206, MP207, MP208, and an amplifying unit 21.
  • the same components as those shown in FIG. 2A are denoted by the same reference numerals, and redundant description is omitted.
  • Two P-type MOS transistors MP205 and MP206 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point between the two P-type MOS transistors MP205 and MP206 is output as the signal SINA.
  • the gates are connected to a signal line that supplies the reference voltage GND, and the back gates are connected to a signal line that supplies the power supply voltage VDD.
  • Two P-type MOS transistors MP207 and MP208 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point between the two P-type MOS transistors MP207 and MP208 is output as the signal SINB.
  • the gates are connected to a signal line that supplies the reference voltage GND, and the back gates are connected to the signal line that supplies the power supply voltage VDD.
  • the threshold voltages of the P-type MOS transistors MP206 and MP207 are the same voltage, and are lower than the value of (reference voltage GND ⁇ power supply voltage VDD). Further, the threshold voltages of the P-type MOS transistors MP205 and MP208 are the same voltage, and are general (standard) threshold voltages. That is, for each of the two P-type MOS transistors that output the signal SINA and the two P-type MOS transistors that output the signal SINB, the arrangement of the transistors is changed, and a circuit configuration that outputs the signals SINA and SINB is obtained. This is the reverse of that shown in FIG. 2A.
  • the layout of the two P-type MOS transistors MP205 and MP206 and the layout of the two P-type MOS transistors MP207 and MP208 have the same shape including the wirings related to them.
  • the layout and wiring shape of the P-type MOS transistors MP205 and MP207 are the same, and the layout and wiring shape of the P-type MOS transistors MP206 and MP208 are the same.
  • the P-type MOS transistors MP206 and MP207 having a threshold voltage lower than the value of (reference voltage GND ⁇ power supply voltage VDD) are turned off.
  • P-type MOS transistors MP205 and MP208 having a threshold voltage are turned on. Therefore, the voltage at the connection point of the P-type MOS transistors MP205 and MP206 (signal SINA) is substantially the power supply voltage VDD, and the voltage at the connection point of the P-type MOS transistors MP207 and MP208 (signal SINB) is P from the reference voltage GND. (GND +
  • the circuit shown in FIG. 2B outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
  • the semiconductor device according to the third embodiment has a plurality of signal output circuits as shown in FIGS. 3A and 3B.
  • 3A and 3B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the third embodiment.
  • the first signal output circuit shown in FIG. 3A includes N-type MOS transistors MN301, MN302, MN303, MN304, MN305, and an amplifier unit 11.
  • the N-type transistor MN305 is a transistor having a general (standard) threshold voltage, and is connected between a signal line that supplies the power supply voltage VDD and a signal line that supplies a voltage lower than the power supply voltage VDD. At the same time, the gate is connected to a signal line for supplying the power supply voltage VDD. That is, the N-type transistor MN305 is diode-connected to the signal line that supplies the power supply voltage VDD. Therefore, the voltage of the signal line that supplies a voltage lower than the power supply voltage VDD is lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN305 (VDD ⁇ VTH).
  • the N-type MOS transistors MN301, MN302, MN303, MN304 and the amplification unit 11 are the same as the N-type MOS transistors MN101, MN102, MN103, MN104 and the amplification unit 11 shown in FIG. 1A, respectively.
  • the two N-type MOS transistors MN301 and MN302 are connected in series between a signal line that supplies a voltage (VDD-VTH) and a signal line that supplies a reference voltage GND.
  • the two N-type MOS transistors MN303 and MN304 are connected in series between a signal line that supplies a voltage (VDD ⁇ VTH) and a signal line that supplies a reference voltage GND.
  • the gates of the N-type MOS transistors MN301, MN302, MN303, and MN304 are connected to a signal line that supplies a voltage (VDD-VTH).
  • the N-type MOS transistors MN301 and MN304 are turned off, and the N-type MOS transistors MN302 and MN303 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN301 and MN302 is substantially the reference voltage GND, and the voltage (signal SINB) at the connection point of the N-type MOS transistors MN303 and MN304 is the voltage (VDD ⁇ VTH). ) Lower than the threshold voltage VTH of the N-type MOS transistor MN303 (VDD ⁇ 2VTH). Therefore, the circuit shown in FIG. 3A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
  • the second signal output circuit shown in FIG. 3B includes N-type MOS transistors MN306, MN307, MN308, MN309, MN310, and the amplifying unit 11.
  • the N-type transistor MN310 is a transistor having a general (standard) threshold voltage, and is connected between a signal line that supplies the power supply voltage VDD and a signal line that supplies a voltage lower than the power supply voltage VDD. At the same time, the gate is connected to a signal line for supplying the power supply voltage VDD. That is, the N-type transistor MN310 is diode-connected to the signal line that supplies the power supply voltage VDD. Accordingly, the voltage of the signal line that supplies a voltage lower than the power supply voltage VDD is lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN310 (VDD ⁇ VTH).
  • the N-type MOS transistors MN306, MN307, MN308, and MN309 and the amplifying unit 11 are the same as the N-type MOS transistors MN105, MN106, MN107, MN108, and the amplifying unit 11 shown in FIG. 1B, respectively.
  • the two N-type MOS transistors MN306 and MN307 are connected in series between a signal line that supplies a voltage (VDD-VTH) and a signal line that supplies a reference voltage GND.
  • the two N-type MOS transistors MN308 and MN309 are connected in series between a signal line that supplies a voltage (VDD ⁇ VTH) and a signal line that supplies a reference voltage GND.
  • the gates of the N-type MOS transistors MN306, MN307, MN308, and MN309 are connected to a signal line that supplies a voltage (VDD-VTH).
  • the N-type MOS transistors MN307 and MN308 are turned off, and the N-type MOS transistors MN306 and MN309 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN306 and MN307 is lower than the voltage (VDD ⁇ VTH) by the threshold VTH of the N-type MOS transistor MN306 (VDD ⁇ 2VTH), and the N-type MOS
  • the voltage (signal SINB) at the connection point of the transistors MN308 and MN309 is substantially the reference voltage GND. Therefore, the circuit shown in FIG. 3B outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
  • a diode-connected N-type MOS transistor is provided on the power supply voltage VDD side, and a signal line for supplying a voltage lower than the power supply voltage VDD obtained by the N-type MOS transistor and a signal line for supplying the reference voltage GND are provided.
  • the third embodiment in which two N-type MOS transistors are connected in series with each other, the same effect as in the first embodiment can be obtained, and the reproduction of the semiconductor device by reverse engineering can be made difficult. .
  • the third embodiment is equivalent to lowering the power supply voltage in the first embodiment, power consumption can be reduced.
  • the semiconductor device according to the fourth embodiment has a plurality of signal output circuits as shown in FIGS. 4A and 4B.
  • 4A and 4B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the fourth embodiment.
  • the first signal output circuit shown in FIG. 4A includes N-type MOS transistors MN401, MN402, MN403, and MN404, and an amplifier unit 11.
  • the N-type MOS transistors MN401, MN402, MN403, and MN404 and the amplification unit 11 are the same as the N-type MOS transistors MN101, MN102, MN103, MN104, and the amplification unit 11 shown in FIG. 1A, respectively.
  • the gate of the N-type MOS transistor MN401 is connected to the signal line that supplies the voltage VDD
  • the gate of the N-type MOS transistor MN402 is connected to the connection point of the two N-type MOS transistors MN401 and MN402.
  • the gate of the N-type MOS transistor MN403 is connected to a signal line that supplies the voltage VDD
  • the gate of the N-type MOS transistor MN404 is connected to the connection point of the two N-type MOS transistors MN403 and MN404. That is, each of the N-type MOS transistors MN401, MN402, MN403, and MN404 is diode-connected.
  • the N-type MOS transistors MN401 and MN404 are turned off, and the N-type MOS transistors MN402 and MN403 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN401 and MN402 is higher than the reference voltage GND by the threshold VTH of the N-type MOS transistor MN402 (GND + VTH), and the N-type MOS transistors MN403 and MN404
  • the voltage at the connection point (signal SINB) is lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN403 (VDD ⁇ VTH). Therefore, the circuit shown in FIG. 4A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
  • the second signal output circuit shown in FIG. 4B includes N-type MOS transistors MN405, MN406, MN407, MN408, and an amplifying unit 11.
  • the N-type MOS transistors MN405, MN406, MN407, MN408 and the amplifying unit 11 are the same as the N-type MOS transistors MN105, MN106, MN107, MN108 and the amplifying unit 11 shown in FIG. 1B, respectively.
  • the gate of the N-type MOS transistor MN405 is connected to the signal line that supplies the voltage VDD
  • the gate of the N-type MOS transistor MN406 is connected to the connection point of the two N-type MOS transistors MN405 and MN406.
  • the gate of the N-type MOS transistor MN407 is connected to a signal line that supplies the voltage VDD
  • the gate of the N-type MOS transistor MN408 is connected to a connection point between the two N-type MOS transistors MN407 and MN408. That is, each of the N-type MOS transistors MN405, MN406, MN407, and MN408 is diode-connected.
  • the N-type MOS transistors MN406 and MN407 are turned off, and the N-type MOS transistors MN405 and MN408 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN405 and MN406 is lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN405 (VDD ⁇ VTH), and the N-type MOS transistors MN407,
  • the voltage at the connection point of MN408 (signal SINB) is higher than the reference voltage GND by the threshold value VTH of the N-type MOS transistor MN408 (GND + VTH). Therefore, the circuit shown in FIG. 4B outputs a “1” signal at the power supply voltage VDD level as the output signal SOUT.
  • the same effects as those of the first embodiment can be obtained, making it difficult to reproduce the semiconductor device by reverse engineering and reducing the power consumption.
  • the semiconductor device according to the fifth embodiment has a plurality of signal output circuits as shown in FIGS. 5A and 5B.
  • 5A and 5B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the fifth embodiment.
  • the first signal output circuit shown in FIG. 5A includes a depletion type N-type MOS transistor MN501 and an enhancement type N-type MOS transistor MN502.
  • N-type MOS transistors MN501 and MN502 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the type MOS transistors MN501 and MN502 is output as the output signal SOUT.
  • the gate of the N-type MOS transistor MN501 is connected to the connection point of the N-type MOS transistors MN501 and MN502, and the gate of the N-type MOS transistor MN502 is connected to a signal line that supplies the reference voltage GND. That is, the N-type MOS transistors MN501 and MN502 are diode-connected. Further, the back gates of the N-type MOS transistors MN501 and MN502 are connected to a signal line for supplying the reference voltage GND.
  • the depletion type N-type MOS transistor MN501 is turned on, and the enhancement type N-type MOS transistor MN502 is turned off. Therefore, the circuit shown in FIG. 5A outputs a signal “1” at the power supply voltage VDD level as the output signal SOUT.
  • the second signal output circuit shown in FIG. 5B includes an enhancement type N-type MOS transistor MN503 and a depletion type N-type MOS transistor MN504.
  • the N-type MOS transistor MN503 has the same layout and wiring shape as the N-type MOS transistor MN501
  • the N-type MOS transistor MN504 has the same layout and wiring shape as the N-type MOS transistor MN502.
  • N-type MOS transistors MN503 and MN504 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the type MOS transistors MN503 and MN504 is output as the output signal SOUT.
  • the gate of the N-type MOS transistor MN503 is connected to the connection point of the N-type MOS transistors MN503 and MN504, and the gate of the N-type MOS transistor MN504 is connected to a signal line that supplies the reference voltage GND. That is, the N-type MOS transistors MN503 and MN504 are diode-connected. Further, the back gates of the N-type MOS transistors MN503 and MN504 are connected to a signal line that supplies the reference voltage GND.
  • the depletion type N-type MOS transistor MN504 is turned on, and the enhancement type N-type MOS transistor MN503 is turned off. Therefore, the circuit shown in FIG. 5B outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
  • the voltage at the connection point of the N-type MOS transistors MN501 and MN502 and the voltage at the connection point of the N-type MOS transistors MN503 and MN504 are the power supply voltage VDD level or Since it becomes the reference voltage GND level, an amplifying unit is unnecessary.
  • the signal output circuit included in the semiconductor device according to the fifth embodiment has fewer transistors than the signal output circuit shown in FIGS. 1A and 1B, and does not require an amplifier. The required area can be reduced, and a larger number of signal output circuits can be mounted in the automatic placement and wiring area on the semiconductor chip. Therefore, the reproduction of the semiconductor device by reverse engineering can be made more difficult. In addition, since almost no current flows, power consumption can be reduced.
  • the semiconductor device according to the sixth embodiment has a plurality of signal output circuits as shown in FIGS. 6A and 6B.
  • 6A and 6B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the sixth embodiment.
  • the first signal output circuit shown in FIG. 6A includes a depletion type P-type MOS transistor MP601 and an enhancement type P-type MOS transistor MP602.
  • P-type MOS transistors MP601 and MP602 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the type MOS transistors MP601 and MP602 is output as the output signal SOUT.
  • the gate of the P-type MOS transistor MP601 is connected to the signal line that supplies the power supply voltage VDD
  • the gate of the P-type MOS transistor MP602 is connected to the connection point of the P-type MOS transistors MP601 and MP602. That is, the P-type MOS transistors MP601 and MP602 are diode-connected.
  • the back gates of the P-type MOS transistors MP601 and MP602 are connected to a signal line that supplies the power supply voltage VDD.
  • the depletion type P-type MOS transistor MP601 is turned on, and the enhancement type P-type MOS transistor MP602 is turned off. Therefore, the circuit shown in FIG. 6A outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
  • the second signal output circuit shown in FIG. 6B includes an enhancement type P-type MOS transistor MP603 and a depletion type P-type MOS transistor MP604.
  • the P-type MOS transistor MP603 has the same layout and wiring shape as the P-type MOS transistor MP601
  • the P-type MOS transistor MP604 has the same layout and wiring shape as the P-type MOS transistor MP602.
  • P-type MOS transistors MP603 and MP604 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND.
  • the voltage at the connection point of the type MOS transistors MP603 and MP604 is output as the output signal SOUT.
  • the gate of the P-type MOS transistor MP603 is connected to the signal line that supplies the power supply voltage VDD
  • the gate of the P-type MOS transistor MP604 is connected to the connection point of the P-type MOS transistors MP603 and MP604. That is, the P-type MOS transistors MP603 and MP604 are diode-connected.
  • the back gates of the P-type MOS transistors MP603 and MP604 are connected to a signal line that supplies the power supply voltage VDD.
  • the depletion type P-type MOS transistor MP604 is turned on, and the enhancement type P-type MOS transistor MP603 is turned off. Therefore, the circuit shown in FIG. 6B outputs a signal of “0” at the reference voltage GND level as the output signal SOUT. Also in the sixth embodiment, the voltage at the connection point of the P-type MOS transistors MP601 and MP602 and the voltage at the connection point of the P-type MOS transistors MP603 and MP604 are at the power supply voltage VDD level or the reference voltage GND level. An amplifying unit is unnecessary.
  • the same effect as that of the fifth embodiment can be obtained, and it is difficult to reproduce a semiconductor device by reverse engineering. And power consumption can be reduced.
  • the semiconductor device according to the seventh embodiment has a plurality of signal output circuits as shown in FIGS. 7A and 7B.
  • 7A and 7B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the seventh embodiment.
  • the first signal output circuit shown in FIG. 7A includes a P-type MOS transistor MP701 and an N-type MOS transistor MN701.
  • the P-type MOS transistor MP701 and the N-type MOS transistor MN701 have different withstand voltages, and in the example shown in FIG. 7A, the N-type MOS transistor MN701 is a high withstand voltage transistor.
  • the P-type MOS transistor MP701 and the N-type MOS transistor MN701 are connected in series in this order from the signal line supplying the power supply voltage VDD. And a voltage at a connection point between the P-type MOS transistor MP701 and the N-type MOS transistor MN701 is output as the output signal SOUT.
  • the gate is connected to the signal line that supplies the reference voltage GND, and the back gate is connected to the signal line that supplies the power supply voltage VDD.
  • the N-type MOS transistor MN701 has a gate connected to a signal line that supplies the power supply voltage VDD, and a back gate connected to a signal line that supplies the reference voltage GND.
  • the circuit shown in FIG. 7A outputs a signal having a high voltage VH close to the power supply voltage VDD as the output signal SOUT.
  • the second signal output circuit shown in FIG. 7B includes a P-type MOS transistor MP702 and an N-type MOS transistor MN702.
  • the P-type MOS transistor MP702 and the N-type MOS transistor MN702 have different withstand voltages.
  • the P-type MOS transistor MP702 is a high withstand voltage transistor.
  • the P-type MOS transistor MP702 has the same layout and wiring shape as the P-type MOS transistor MP701
  • the N-type MOS transistor MN702 has the same layout and wiring shape as the N-type MOS transistor MN701.
  • the P-type MOS transistor MP702 and the N-type MOS transistor MN702 are connected in series in this order from the signal line side supplying the power supply voltage VDD. And a voltage at a connection point between the P-type MOS transistor MP702 and the N-type MOS transistor MN702 is output as the output signal SOUT.
  • the P-type MOS transistor MP702 has a gate connected to a signal line that supplies the reference voltage GND, and a back gate connected to a signal line that supplies the power supply voltage VDD.
  • the N-type MOS transistor MN702 has a gate connected to a signal line that supplies the power supply voltage VDD, and a back gate connected to a signal line that supplies the reference voltage GND.
  • the circuit shown in FIG. 7B outputs a signal having a low voltage VL close to the reference voltage GND as the output signal SOUT.
  • the signal output circuit according to the seventh embodiment has a small number of transistors, and a larger number of signal output circuits can be mounted in the automatic placement and wiring area on the semiconductor chip. Therefore, the reproduction of the semiconductor device by reverse engineering can be made more difficult.
  • FIG. 8 is a diagram illustrating an application example of the semiconductor device in the present embodiment.
  • reference numeral 100 denotes a semiconductor chip including the semiconductor device according to the present embodiment.
  • outputs of a plurality of signal output circuits 120 are connected to a logic processing circuit unit 110 that performs various logic processes.
  • the logic processing circuit unit 110 performs a part or all of the logic processing using the output of the signal output circuit 120, so that the relationship between the input and output in the logic processing circuit unit 110 is the output state of the signal output circuit 120. Also depends.

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Abstract

This semiconductor device includes: a plurality of first signal output circuits that each have a first transistor (MN101, MN105) and a second transistor (MN102, MN106) each having a gate to which a predetermined voltage is supplied, the first transistor and the second transistor being connected in series between a signal line for supplying a power supply voltage and a signal line for supplying a reference voltage, and that output a voltage at a connection point between the two transistors; and a plurality of second signal output terminals that each have a third transistor (MN103, MN107) and a fourth transistor (MN104, MN108) each having a gate to which a predetermined voltage is supplied, the third transistor and the fourth transistor being connected in series between a signal line for supplying a power supply voltage and a signal line for supplying a reference voltage, and that output a voltage at a connection point between the two transistors, wherein the third transistor and the first transistor are the same in layout and different in properties, and the fourth transistor and the second transistor are the same in layout and different in properties.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関し、詳しくはリバースエンジニアリングからの半導体装置の保護技術に関する。 The present invention relates to a semiconductor device, and more particularly to a technology for protecting a semiconductor device from reverse engineering.
　近年、半導体装置の不当なリバースエンジニアリングが増えてきている。リバースエンジニアリングの手法として、半導体装置が実装されたチップ表面からの光学的解析だけでなく、配線層を１層ずつ剥離して撮影し、得られた画像を重ね合わせ、ソフトウェアツールで配線情報を抽出し回路図を再現する技術も用いられている。 In recent years, unjust reverse engineering of semiconductor devices has increased. As a reverse engineering technique, not only optical analysis from the chip surface on which the semiconductor device is mounted, but also by separating and shooting the wiring layers one by one, overlaying the obtained images, and extracting wiring information with a software tool A technique for reproducing the circuit diagram is also used.
　リバースエンジニアリングを防止するための様々な方法が提案されている（例えば、特許文献１～９参照）。リバースエンジニアリングを防ぐために、例えば配線層に工夫を施したり、配線層よりも下層にある拡散層やバルクを利用したりすることにより、トランジスタの特性や接続情報を変えて、配線層を読み取るだけでは機能を再現できないようにする方法が提案されている。また、例えば、特許文献１には、ゲートをフローティング状態にしてトランジスタを使用し、トランジスタの特性ばらつきによる出力電圧の差を利用して信号を生成することで、リバースエンジニアリングによって半導体装置を再現することを困難にする技術が提案されている。 Various methods for preventing reverse engineering have been proposed (see, for example, Patent Documents 1 to 9). In order to prevent reverse engineering, for example, by modifying the transistor characteristics and connection information by devising the wiring layer or using a diffusion layer or bulk below the wiring layer, just reading the wiring layer Proposals have been made to prevent functions from being reproduced. Further, for example, in Patent Document 1, a semiconductor device is reproduced by reverse engineering by using a transistor with a gate in a floating state and generating a signal using a difference in output voltage due to variation in transistor characteristics. Techniques that make this difficult are proposed.
　しかしながら、前述した特許文献１に記載の技術では、以下のような問題がある。ゲートがフローティング状態であるために、電源電圧からグランドへ無駄な消費電流が流れるとともに、クロストーク等でノイズが入ると電圧変動が起こって動作や消費電流が安定しない。また、複数のトランジスタによって発生する出力電圧は、２値化された電圧ではなく連続したアナログ量になるため、それを受けるコンパレータには高精度のアナログ特性が要求され、消費電流やサイズが大きくなる。このような消費電流やサイズの制約によって、１チップ上に搭載できる個数に制約が発生する。また、リバースエンジニアリングを防止する他の方法においては、特殊なプロセスが必要になり、プロセス開発期間やコストが増加するといった問題がある。 However, the technique described in Patent Document 1 described above has the following problems. Since the gate is in a floating state, a wasteful consumption current flows from the power supply voltage to the ground, and when noise occurs due to crosstalk or the like, voltage fluctuation occurs and the operation and current consumption are not stable. In addition, since the output voltage generated by a plurality of transistors is not a binarized voltage but a continuous analog amount, a comparator that receives the output requires high-precision analog characteristics, which increases current consumption and size. . Due to such current consumption and size restrictions, there are restrictions on the number of chips that can be mounted on one chip. Another method for preventing reverse engineering requires a special process, which increases the process development period and cost.
米国特許第９４３７５５５号明細書U.S. Pat. No. 9433755 特開平６－１６３５３９号公報JP-A-6-163539 特開平９－９２７２７号公報JP-A-9-92727 米国特許第６１１７７６２号明細書US Pat. No. 6,117,762 米国特許第６９７９６０６号明細書US Pat. No. 6,796,606 米国特許第７１２８２７１号明細書US Pat. No. 7,128,271 米国特許第９３３７１５６号明細書U.S. Pat. No. 9,337,156 特表２００４－５１８２７３号公報JP-T-2004-518273 特開２０１４－１３５３８６号公報JP 2014-135386 A
　本発明の目的は、リバースエンジニアリングによる半導体装置の再現を困難にする半導体装置を提供することである。 An object of the present invention is to provide a semiconductor device that makes it difficult to reproduce the semiconductor device by reverse engineering.
　本発明に係る半導体装置は、第１の電圧を供給する信号線と前記第１の電圧より低い第２の電圧を供給する信号線との間に直列に接続されるとともに、それぞれのゲートに所定の電圧が供給される第１のトランジスタ及び第２のトランジスタを有し、前記第１のトランジスタと前記第２のトランジスタの接続点の電圧を出力する、複数の第１の信号出力回路と、前記第１の電圧を供給する信号線と前記第２の電圧を供給する信号線との間に直列に接続されるとともに、それぞれのゲートに所定の電圧が供給される第３のトランジスタ及び第４のトランジスタを有し、前記第３のトランジスタは前記第１のトランジスタと同じレイアウトで特性が異なり、前記第４のトランジスタは前記第２のトランジスタと同じレイアウトで特性が異なり、前記第３のトランジスタと前記第４のトランジスタの接続点の電圧を出力する、複数の第２の信号出力回路とを含むことを特徴とする。 The semiconductor device according to the present invention is connected in series between a signal line for supplying a first voltage and a signal line for supplying a second voltage lower than the first voltage, and each gate has a predetermined value. A plurality of first signal output circuits that output a voltage at a connection point of the first transistor and the second transistor; A third transistor and a fourth transistor are connected in series between a signal line supplying a first voltage and a signal line supplying the second voltage, and a predetermined voltage is supplied to each gate. The third transistor has different characteristics with the same layout as the first transistor, the fourth transistor has different characteristics with the same layout as the second transistor, Serial and outputs the third transistor and the voltage at the connection point of said fourth transistor, characterized in that it comprises a plurality of second signal output circuit.
　本発明によれば、リバースエンジニアリングによる半導体装置の再現を困難にする半導体装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device that makes it difficult to reproduce the semiconductor device by reverse engineering.
図１Ａは、第１の実施形態における半導体装置の例を示す図である。FIG. 1A is a diagram illustrating an example of a semiconductor device according to the first embodiment. 図１Ｂは、第１の実施形態における半導体装置の例を示す図である。FIG. 1B is a diagram illustrating an example of the semiconductor device according to the first embodiment. 図２Ａは、第２の実施形態における半導体装置の例を示す図である。FIG. 2A is a diagram illustrating an example of a semiconductor device according to the second embodiment. 図２Ｂは、第２の実施形態における半導体装置の例を示す図である。FIG. 2B is a diagram illustrating an example of a semiconductor device according to the second embodiment. 図３Ａは、第３の実施形態における半導体装置の例を示す図である。FIG. 3A is a diagram illustrating an example of a semiconductor device according to the third embodiment. 図３Ｂは、第３の実施形態における半導体装置の例を示す図である。FIG. 3B is a diagram illustrating an example of a semiconductor device according to the third embodiment. 図４Ａは、第４の実施形態における半導体装置の例を示す図である。FIG. 4A is a diagram illustrating an example of a semiconductor device according to the fourth embodiment. 図４Ｂは、第４の実施形態における半導体装置の例を示す図である。FIG. 4B is a diagram illustrating an example of a semiconductor device according to the fourth embodiment. 図５Ａは、第５の実施形態における半導体装置の例を示す図である。FIG. 5A is a diagram illustrating an example of a semiconductor device according to the fifth embodiment. 図５Ｂは、第５の実施形態における半導体装置の例を示す図である。FIG. 5B is a diagram illustrating an example of a semiconductor device according to the fifth embodiment. 図６Ａは、第６の実施形態における半導体装置の例を示す図である。FIG. 6A is a diagram illustrating an example of a semiconductor device according to the sixth embodiment. 図６Ｂは、第６の実施形態における半導体装置の例を示す図である。FIG. 6B is a diagram illustrating an example of a semiconductor device according to the sixth embodiment. 図７Ａは、第７の実施形態における半導体装置の例を示す図である。FIG. 7A is a diagram illustrating an example of a semiconductor device according to the seventh embodiment. 図７Ｂは、第７の実施形態における半導体装置の例を示す図である。FIG. 7B is a diagram illustrating an example of a semiconductor device according to the seventh embodiment. 図８は、本実施形態における半導体装置の適用例を示す図である。FIG. 8 is a diagram illustrating an application example of the semiconductor device according to the present embodiment.
　以下、本発明の実施形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
（第１の実施形態）
　本発明の第１の実施形態について説明する。第１の実施形態における半導体装置は、図１Ａ及び図１Ｂに示すような信号出力回路を複数有する。図１Ａ及び図１Ｂは、第１の実施形態における半導体装置が有する信号出力回路の例を示す図である。図１Ａに示す第１の信号出力回路は、Ｎ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２、ＭＮ１０３、ＭＮ１０４、及び増幅部１１を有する。 (First embodiment)
A first embodiment of the present invention will be described. The semiconductor device according to the first embodiment includes a plurality of signal output circuits as shown in FIGS. 1A and 1B. 1A and 1B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to the first embodiment. The first signal output circuit shown in FIG. 1A includes N-type MOS transistors MN101, MN102, MN103, MN104, and an amplifier unit 11.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２が、この順で直列に接続され、２つのＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２の接続点の電圧が信号ＳＩＮＡとして出力される。Ｎ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２は、ゲートが電源電圧ＶＤＤを供給する信号線に接続され、バックゲートが基準電圧ＧＮＤを供給する信号線に接続される。 Two N-type MOS transistors MN101 and MN102 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the two N-type MOS transistors MN101 and MN102 is output as the signal SINA. The N-type MOS transistors MN101 and MN102 have gates connected to a signal line that supplies the power supply voltage VDD, and back gates connected to a signal line that supplies the reference voltage GND.
　また、電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＮ型ＭＯＳトランジスタＭＮ１０３、ＭＮ１０４が、この順で直列に接続され、２つのＮ型ＭＯＳトランジスタＭＮ１０３、ＭＮ１０４の接続点の電圧が信号ＳＩＮＢとして出力される。Ｎ型ＭＯＳトランジスタＭＮ１０３、ＭＮ１０４は、ゲートが電源電圧ＶＤＤを供給する信号線に接続され、バックゲートが基準電圧ＧＮＤを供給する信号線に接続される。 Two N-type MOS transistors MN103 and MN104 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point between the two N-type MOS transistors MN103 and MN104 is output as the signal SINB. The N-type MOS transistors MN103 and MN104 have their gates connected to a signal line that supplies the power supply voltage VDD, and their back gates connected to a signal line that supplies the reference voltage GND.
　増幅部１１は、入力端子ＩＮＡに信号ＳＩＮＡが入力されるとともに、入力端子ＩＮＢに信号ＳＩＮＢが入力される。増幅部１１は、入力される信号ＳＩＮＡ及び信号ＳＩＮＢの電圧に基づいて、出力端子ＯＵＴから出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号又は基準電圧ＧＮＤレベルの‘０’の信号を出力する。本実施形態では一例として、Ｐ型ＭＯＳトランジスタＭＰ１１、ＭＰ１２及びＮ型ＭＯＳトランジスタＭＮ１１、ＭＮ１２を有するレベルシフタ（レベルシフト回路）により増幅部１１の機能を実現する。増幅部１１としてレベルシフタ（レベルシフト回路）を用いることで余計な貫通電流が流れることを防止することができ、消費電流を低減することができる。 In the amplifying unit 11, the signal SINA is input to the input terminal INA, and the signal SINB is input to the input terminal INB. Based on the input signal SINA and the voltage of the signal SINB, the amplifying unit 11 outputs a signal “1” at the power supply voltage VDD level or a signal “0” at the reference voltage GND level as the output signal SOUT from the output terminal OUT. Output. In this embodiment, as an example, the function of the amplifying unit 11 is realized by a level shifter (level shift circuit) having P-type MOS transistors MP11 and MP12 and N-type MOS transistors MN11 and MN12. By using a level shifter (level shift circuit) as the amplifying unit 11, it is possible to prevent an excessive through current from flowing, and to reduce current consumption.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ１１とＮ型ＭＯＳトランジスタＭＮ１１とが、この順で直列に接続される。また、電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ１２とＮ型ＭＯＳトランジスタＭＮ１２とが、この順で直列に接続される。 Between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND, the P-type MOS transistor MP11 and the N-type MOS transistor MN11 are connected in series in this order from the signal line supplying the power supply voltage VDD. Connected to. The P-type MOS transistor MP12 and the N-type MOS transistor MN12 are arranged in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. Connected in series.
　Ｎ型ＭＯＳトランジスタＭＮ１１のゲートには信号ＳＩＮＡが入力され、Ｎ型ＭＯＳトランジスタＭＮ１２のゲートには信号ＳＩＮＢが入力される。また、Ｐ型ＭＯＳトランジスタＭＰ１１のゲートがＰ型ＭＯＳトランジスタＭＰ１２とＮ型ＭＯＳトランジスタＭＮ１２との接続点に接続され、Ｐ型ＭＯＳトランジスタＭＰ１２のゲートがＰ型ＭＯＳトランジスタＭＰ１１とＮ型ＭＯＳトランジスタＭＮ１１との接続点に接続される。Ｐ型ＭＯＳトランジスタＭＰ１２とＮ型ＭＯＳトランジスタＭＮ１２との接続点の電圧が出力信号ＳＯＵＴとして出力される。 The signal SINA is input to the gate of the N-type MOS transistor MN11, and the signal SINB is input to the gate of the N-type MOS transistor MN12. The gate of the P-type MOS transistor MP11 is connected to the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12, and the gate of the P-type MOS transistor MP12 is connected to the P-type MOS transistor MP11 and the N-type MOS transistor MN11. Connected to the connection point. The voltage at the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12 is output as the output signal SOUT.
　ここで、Ｎ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０４のしきい値電圧は、同じ電圧とし、電源電圧ＶＤＤよりも高い値である。また、Ｎ型ＭＯＳトランジスタＭＮ１０２、ＭＮ１０３のしきい値電圧は、同じ電圧とし、一般的（標準的）なしきい値電圧（例えば＋０．５Ｖ程度）である。トランジスタのしきい値電圧の制御は、チャネルに対するドープ量を変えるチャネルインプラントドーピング制御、ゲート酸化膜の厚さを変えるゲート酸化膜厚制御、バックゲート効果を利用するためのバックゲート電圧制御等により実現することが可能である。なお、図示において、（ＨＶＴ）を付記して記載したものが高いしきい値電圧を持つトランジスタであることを示す（以下の実施形態においても同様）。 Here, the threshold voltages of the N-type MOS transistors MN101 and MN104 are the same voltage and are higher than the power supply voltage VDD. In addition, the threshold voltages of the N-type MOS transistors MN102 and MN103 are the same voltage, which is a general (standard) threshold voltage (for example, about +0.5 V). Transistor threshold voltage control is realized by channel implant doping control that changes the doping amount for the channel, gate oxide film thickness control that changes the gate oxide thickness, and back gate voltage control that uses the back gate effect. Is possible. Note that in the drawing, (HVT) is added to indicate that the transistor has a high threshold voltage (the same applies to the following embodiments).
　また、２つのＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２のレイアウトと、２つのＮ型ＭＯＳトランジスタＭＮ１０３、ＭＮ１０４のレイアウトとは、それらに係る配線も含めて同じ形状になっている。すなわち、Ｎ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０３のレイアウト及び配線の形状が同じであり、Ｎ型ＭＯＳトランジスタＭＮ１０２、ＭＮ１０４のレイアウト及び配線の形状が同じである。例えば、Ｎ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０３のゲート長及びゲート幅は同じであり、Ｎ型ＭＯＳトランジスタＭＮ１０２、ＭＮ１０４のゲート長及びゲート幅は同じである。 Further, the layout of the two N-type MOS transistors MN101 and MN102 and the layout of the two N-type MOS transistors MN103 and MN104 have the same shape including the wirings related to them. That is, the layout and wiring shape of the N-type MOS transistors MN101 and MN103 are the same, and the layout and wiring shape of the N-type MOS transistors MN102 and MN104 are the same. For example, the gate lengths and gate widths of the N-type MOS transistors MN101 and MN103 are the same, and the gate lengths and gate widths of the N-type MOS transistors MN102 and MN104 are the same.
　このようにＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０３のレイアウト及び配線の形状を同じにしているため、電源電圧ＶＤＤよりも高いしきい値のトランジスタがどちらであるかは外見上では区別がつかない。同様に、Ｎ型ＭＯＳトランジスタＭＮ１０２、ＭＮ１０４のレイアウト及び配線の形状を同じにしているため、電源電圧ＶＤＤよりも高いしきい値のトランジスタがどちらであるかは外見上では区別がつかない。 As described above, since the layouts and wiring shapes of the N-type MOS transistors MN101 and MN103 are the same, it is indistinguishable in terms of which transistor has a threshold higher than the power supply voltage VDD. Similarly, since the layouts and wiring shapes of the N-type MOS transistors MN102 and MN104 are the same, it cannot be distinguished in terms of which transistor has a threshold value higher than the power supply voltage VDD.
　図１Ａに示したように接続された回路では、電源電圧ＶＤＤよりも高いしきい値電圧のＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０４はオフ状態になり、一般的（標準的）なしきい値電圧のＮ型ＭＯＳトランジスタＭＮ１０２、ＭＮ１０３はオン状態になる。したがって、Ｎ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２の接続点の電圧（信号ＳＩＮＡ）は、ほぼ基準電圧ＧＮＤになり、Ｎ型ＭＯＳトランジスタＭＮ１０３、ＭＮ１０４の接続点の電圧（信号ＳＩＮＢ）は、電源電圧ＶＤＤよりＮ型ＭＯＳトランジスタＭＮ１０３のしきい値ＶＴＨ分低い（ＶＤＤ－ＶＴＨ）になる。 In the circuit connected as shown in FIG. 1A, the N-type MOS transistors MN101 and MN104 having a threshold voltage higher than the power supply voltage VDD are turned off, and the N-type having a general (standard) threshold voltage is set. The MOS transistors MN102 and MN103 are turned on. Therefore, the voltage at the connection point of the N-type MOS transistors MN101 and MN102 (signal SINA) is substantially the reference voltage GND, and the voltage at the connection point of the N-type MOS transistors MN103 and MN104 (signal SINB) is N from the power supply voltage VDD. The threshold voltage VTH of the type MOS transistor MN103 is lower (VDD−VTH).
　このとき、増幅部（レベルシフタ）１１では、Ｐ型ＭＯＳトランジスタＭＰ１１及びＮ型ＭＯＳトランジスタＭＮ１２はオン状態になり、Ｐ型ＭＯＳトランジスタＭＰ１２及びＮ型ＭＯＳトランジスタＭＮ１１はオフ状態になる。したがって、図１Ａに示した回路は、出力信号ＳＯＵＴとして、基準電圧ＧＮＤレベルの‘０’の信号を出力する。 At this time, in the amplification unit (level shifter) 11, the P-type MOS transistor MP11 and the N-type MOS transistor MN12 are turned on, and the P-type MOS transistor MP12 and the N-type MOS transistor MN11 are turned off. Accordingly, the circuit shown in FIG. 1A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
　次に、図１Ｂに示す第２の信号出力回路は、Ｎ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６、ＭＮ１０７、ＭＮ１０８、及び増幅部１１を有する。なお、図１Ｂにおいて、図１Ａに示した構成要素と同一の構成要素には同一の符号を付し、重複する説明は省略する。 Next, the second signal output circuit shown in FIG. 1B includes N-type MOS transistors MN105, MN106, MN107, MN108, and an amplifying unit 11. In FIG. 1B, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and redundant description is omitted.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＮ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６が、この順で直列に接続され、２つのＮ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６の接続点の電圧が信号ＳＩＮＡとして出力される。Ｎ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６は、ゲートが電源電圧ＶＤＤを供給する信号線に接続され、バックゲートが基準電圧ＧＮＤを供給する信号線に接続される。 Two N-type MOS transistors MN105 and MN106 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the two N-type MOS transistors MN105 and MN106 is output as the signal SINA. The N-type MOS transistors MN105 and MN106 have gates connected to a signal line that supplies the power supply voltage VDD, and back gates connected to a signal line that supplies the reference voltage GND.
　また、電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＮ型ＭＯＳトランジスタＭＮ１０７、ＭＮ１０８が、この順で直列に接続され、２つのＮ型ＭＯＳトランジスタＭＮ１０７、ＭＮ１０８の接続点の電圧が信号ＳＩＮＢとして出力される。Ｎ型ＭＯＳトランジスタＭＮ１０７、ＭＮ１０８は、ゲートが電源電圧ＶＤＤを供給する信号線に接続され、バックゲートが基準電圧ＧＮＤを供給する信号線に接続される。 Two N-type MOS transistors MN107 and MN108 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point between the two N-type MOS transistors MN107 and MN108 is output as the signal SINB. The N-type MOS transistors MN107 and MN108 have gates connected to a signal line that supplies a power supply voltage VDD, and back gates connected to a signal line that supplies a reference voltage GND.
　ここで、Ｎ型ＭＯＳトランジスタＭＮ１０６、ＭＮ１０７のしきい値電圧は、同じ電圧とし、電源電圧ＶＤＤよりも高い値である。また、Ｎ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０８のしきい値電圧は、同じ電圧とし、一般的（標準的）なしきい値電圧である。すなわち、信号ＳＩＮＡを出力する２つのＮ型ＭＯＳトランジスタ、及び信号ＳＩＮＢを出力する２つのＮ型ＭＯＳトランジスタのそれぞれについて、トランジスタの配置を入れ替えたものであり、信号ＳＩＮＡ、ＳＩＮＢを出力する回路構成が、図１Ａに示したものとは逆になっている。 Here, the threshold voltages of the N-type MOS transistors MN106 and MN107 are the same voltage and are higher than the power supply voltage VDD. In addition, the threshold voltages of the N-type MOS transistors MN105 and MN108 are the same voltage and are general (standard) threshold voltages. That is, for each of the two N-type MOS transistors that output the signal SINA and the two N-type MOS transistors that output the signal SINB, the arrangement of the transistors is changed, and a circuit configuration that outputs the signals SINA and SINB is obtained. This is the reverse of that shown in FIG. 1A.
　なお、２つのＮ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６のレイアウトと、２つのＮ型ＭＯＳトランジスタＭＮ１０７、ＭＮ１０８のレイアウトとは、それらに係る配線も含めて同じ形状になっている。Ｎ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０７のレイアウト及び配線の形状が同じであり、Ｎ型ＭＯＳトランジスタＭＮ１０６、ＭＮ１０８のレイアウト及び配線の形状が同じである。したがって、Ｎ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０７において、電源電圧ＶＤＤよりも高いしきい値のトランジスタがどちらであるかは外見上では区別がつかず、Ｎ型ＭＯＳトランジスタＭＮ１０６、ＭＮ１０８において、電源電圧ＶＤＤよりも高いしきい値のトランジスタがどちらであるかは外見上では区別がつかない。 Note that the layout of the two N-type MOS transistors MN105 and MN106 and the layout of the two N-type MOS transistors MN107 and MN108 have the same shape including the wirings related to them. N-type MOS transistors MN105 and MN107 have the same layout and wiring shapes, and N-type MOS transistors MN106 and MN108 have the same layout and wiring shapes. Therefore, in the N-type MOS transistors MN105 and MN107, it is not apparent from the outside whether the transistor having a threshold value higher than the power supply voltage VDD is present. It is indistinguishable in terms of which transistor has a high threshold.
　図１Ｂに示したように接続された回路では、電源電圧ＶＤＤよりも高いしきい値電圧のＮ型ＭＯＳトランジスタＭＮ１０６、ＭＮ１０７はオフ状態になり、一般的（標準的）なしきい値電圧のＮ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０８はオン状態になる。したがって、Ｎ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６の接続点の電圧（信号ＳＩＮＡ）は、電源電圧ＶＤＤよりＮ型ＭＯＳトランジスタＭＮ１０５のしきい値ＶＴＨ分低い（ＶＤＤ－ＶＴＨ）になり、Ｎ型ＭＯＳトランジスタＭＮ１０７、ＭＮ１０８の接続点の電圧（信号ＳＩＮＢ）は、ほぼ基準電圧ＧＮＤになる。 In the circuit connected as shown in FIG. 1B, the N-type MOS transistors MN106 and MN107 having a threshold voltage higher than the power supply voltage VDD are turned off, and the N-type having a general (standard) threshold voltage is applied. The MOS transistors MN105 and MN108 are turned on. Accordingly, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN105 and MN106 is lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN105 (VDD−VTH), and the N-type MOS transistors MN107, The voltage (signal SINB) at the connection point of the MN 108 is substantially the reference voltage GND.
　このとき、増幅部（レベルシフタ）１１では、Ｐ型ＭＯＳトランジスタＭＰ１１及びＮ型ＭＯＳトランジスタＭＮ１２はオフ状態になり、Ｐ型ＭＯＳトランジスタＭＰ１２及びＮ型ＭＯＳトランジスタＭＮ１１はオン状態になる。したがって、図１Ｂに示した回路は、出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号を出力する。 At this time, in the amplifying unit (level shifter) 11, the P-type MOS transistor MP11 and the N-type MOS transistor MN12 are turned off, and the P-type MOS transistor MP12 and the N-type MOS transistor MN11 are turned on. Therefore, the circuit shown in FIG. 1B outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
　以上のように、特性の異なるトランジスタを用い、レイアウト及び配線の形状は同じであるが、異なる機能を実現する２つの信号出力回路を用い、その２つの信号出力回路からの信号に応じて出力信号のレベルが決まる。これにより、レイアウトから回路図を読み取るだけでは動作を再現することができず、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。 As described above, transistors having different characteristics are used, the layout and wiring shape are the same, but two signal output circuits that realize different functions are used, and output signals are output in accordance with signals from the two signal output circuits. The level of is determined. As a result, the operation cannot be reproduced simply by reading the circuit diagram from the layout, and the reproduction of the semiconductor device by reverse engineering can be made difficult.
　また、図１Ａ及び図１Ｂに示したように、サイズは４入力ＮＡＮＤと同等の８トランジスタで実現することができ、半導体チップ上の自動配置配線エリアの中に多数個の信号出力回路を搭載することができる。本実施形態における信号出力回路を半導体チップ上に多数個搭載した場合、リバースエンジニアリングする際には、これらの信号出力回路のすべての機能（出力状態）を判明する必要があるが、ＦＩＢやプローブを用いた手法では、搭載されたすべての信号出力回路について解析するのは非常に困難であり現実的ではない。 Further, as shown in FIGS. 1A and 1B, the size can be realized by 8 transistors equivalent to a 4-input NAND, and a large number of signal output circuits are mounted in an automatic placement and wiring area on a semiconductor chip. be able to. When a large number of signal output circuits in this embodiment are mounted on a semiconductor chip, it is necessary to identify all functions (output states) of these signal output circuits when performing reverse engineering. In the method used, it is very difficult and unrealistic to analyze all the signal output circuits mounted.
　仮に、１層ずつ剥離して撮影することにより自動配置配線エリアでのトランジスタレベルでの回路図が判明したとしても各信号出力回路の出力状態が不明となる。各信号出力回路の出力状態を判明する方法として、すべての信号出力回路のそれぞれに‘０’又は‘１’の出力を割り当ててシミュレーションを実行し推定することが考えられるが、信号出力回路の数の２のべき乗通りのシミュレーションを実行する必要がある。例えば、本実施形態における信号出力回路を１００個搭載した場合には、２100＝１．２６×１０30という天文学的な数字となり、シミュレーションにより推定することは非常に困難であり、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。 Even if the circuit diagram at the transistor level in the automatic placement and routing area is found by separating and photographing one layer at a time, the output state of each signal output circuit is unknown. As a method for determining the output state of each signal output circuit, it is conceivable to assign a “0” or “1” output to each of the signal output circuits and perform a simulation to estimate the number. It is necessary to execute a simulation as a power of 2. For example, when 100 signal output circuits according to the present embodiment are mounted, an astronomical number of 2 100 = 1.26 × 10 30, which is very difficult to estimate by simulation, and is a semiconductor by reverse engineering. The reproduction of the apparatus can be made difficult.
（第２の実施形態）
　次に、本発明の第２の実施形態について説明する。第２の実施形態における半導体装置は、第１の実施形態において電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続される２つのＮ型ＭＯＳトランジスタを、２つのＰ型ＭＯＳトランジスタとしたものである。 (Second Embodiment)
Next, a second embodiment of the present invention will be described. The semiconductor device according to the second embodiment includes two N-type MOS transistors connected in series between the signal line that supplies the power supply voltage VDD and the signal line that supplies the reference voltage GND in the first embodiment. Two P-type MOS transistors are provided.
　第２の実施形態における半導体装置は、図２Ａ及び図２Ｂに示すような信号出力回路を複数有する。図２Ａ及び図２Ｂは、第２の実施形態における半導体装置が有する信号出力回路の例を示す図である。図２Ａに示す第１の信号出力回路は、Ｐ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０２、ＭＰ２０３、ＭＰ２０４、及び増幅部２１を有する。 The semiconductor device according to the second embodiment has a plurality of signal output circuits as shown in FIGS. 2A and 2B. 2A and 2B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the second embodiment. The first signal output circuit shown in FIG. 2A includes P-type MOS transistors MP201, MP202, MP203, MP204, and an amplifying unit 21.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＰ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０２が、この順で直列に接続され、２つのＰ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０２の接続点の電圧が信号ＳＩＮＡとして出力される。Ｐ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０２は、ゲートが基準電圧ＧＮＤを供給する信号線に接続され、バックゲートが電源電圧ＶＤＤを供給する信号線に接続される。 Two P-type MOS transistors MP201 and MP202 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the two P-type MOS transistors MP201 and MP202 is output as the signal SINA. In the P-type MOS transistors MP201 and MP202, the gate is connected to a signal line that supplies a reference voltage GND, and the back gate is connected to a signal line that supplies a power supply voltage VDD.
　また、電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＰ型ＭＯＳトランジスタＭＰ２０３、ＭＰ２０４が、この順で直列に接続され、２つのＰ型ＭＯＳトランジスタＭＰ２０３、ＭＰ２０４の接続点の電圧が信号ＳＩＮＢとして出力される。Ｐ型ＭＯＳトランジスタＭＰ２０３、ＭＰ２０４は、ゲートが基準電圧ＧＮＤを供給する信号線に接続され、バックゲートが電源電圧ＶＤＤを供給する信号線に接続される。 Two P-type MOS transistors MP203 and MP204 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point between the two P-type MOS transistors MP203 and MP204 is output as the signal SINB. In the P-type MOS transistors MP203 and MP204, the gate is connected to a signal line that supplies the reference voltage GND, and the back gate is connected to a signal line that supplies the power supply voltage VDD.
　増幅部２１は、入力端子ＩＮＡに信号ＳＩＮＡが入力されるとともに、入力端子ＩＮＢに信号ＳＩＮＢが入力される。増幅部２１は、入力される信号ＳＩＮＡ及び信号ＳＩＮＢの電圧に基づいて、出力端子ＯＵＴから出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号又は基準電圧ＧＮＤレベルの‘０’の信号を出力する。本実施形態では一例として、Ｐ型ＭＯＳトランジスタＭＰ２１、ＭＰ２２及びＮ型ＭＯＳトランジスタＭＮ２１、ＭＮ２２を有するレベルシフタ（レベルシフト回路）により増幅部２１の機能を実現する。 In the amplifying unit 21, the signal SINA is input to the input terminal INA, and the signal SINB is input to the input terminal INB. Based on the input signal SINA and the voltage of the signal SINB, the amplifying unit 21 outputs a signal “1” at the power supply voltage VDD level or a signal “0” at the reference voltage GND level as the output signal SOUT from the output terminal OUT. Output. In this embodiment, as an example, the function of the amplifying unit 21 is realized by a level shifter (level shift circuit) having P-type MOS transistors MP21 and MP22 and N-type MOS transistors MN21 and MN22.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ２１とＮ型ＭＯＳトランジスタＭＮ２１とが、この順で直列に接続される。また、電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ２２とＮ型ＭＯＳトランジスタＭＮ２２とが、この順で直列に接続される。 Between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND, the P-type MOS transistor MP21 and the N-type MOS transistor MN21 are connected in series in this order from the signal line supplying the power supply voltage VDD. Connected to. The P-type MOS transistor MP22 and the N-type MOS transistor MN22 are arranged in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. Connected in series.
　Ｐ型ＭＯＳトランジスタＭＰ２１のゲートには信号ＳＩＮＡが入力され、Ｐ型ＭＯＳトランジスタＭＰ２２のゲートには信号ＳＩＮＢが入力される。また、Ｎ型ＭＯＳトランジスタＭＮ２１のゲートがＰ型ＭＯＳトランジスタＭＰ２２とＮ型ＭＯＳトランジスタＭＮ２２との接続点に接続され、Ｎ型ＭＯＳトランジスタＭＮ２２のゲートがＰ型ＭＯＳトランジスタＭＰ２１とＮ型ＭＯＳトランジスタＭＮ２１との接続点に接続される。Ｐ型ＭＯＳトランジスタＭＰ２２とＮ型ＭＯＳトランジスタＭＮ２２との接続点の電圧が出力信号ＳＯＵＴとして出力される。 The signal SINA is input to the gate of the P-type MOS transistor MP21, and the signal SINB is input to the gate of the P-type MOS transistor MP22. The gate of the N-type MOS transistor MN21 is connected to the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22, and the gate of the N-type MOS transistor MN22 is connected between the P-type MOS transistor MP21 and the N-type MOS transistor MN21. Connected to the connection point. The voltage at the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22 is output as the output signal SOUT.
　ここで、Ｐ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０４のしきい値電圧は、同じ電圧とし、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低い値である。また、Ｐ型ＭＯＳトランジスタＭＰ２０２、ＭＰ２０３のしきい値電圧は、同じ電圧とし、一般的（標準的）なしきい値電圧である。トランジスタのしきい値電圧の制御は、第１の実施形態と同様に、チャネルインプラントドーピング制御、ゲート酸化膜厚制御、バックゲート電圧制御等により実現することが可能である。 Here, the threshold voltages of the P-type MOS transistors MP201 and MP204 are the same voltage, which is lower than the value of (reference voltage GND−power supply voltage VDD). Further, the threshold voltages of the P-type MOS transistors MP202 and MP203 are the same voltage, and are general (standard) threshold voltages. Control of the threshold voltage of the transistor can be realized by channel implant doping control, gate oxide film thickness control, back gate voltage control, and the like, as in the first embodiment.
　また、２つのＰ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０２のレイアウトと、２つのＰ型ＭＯＳトランジスタＭＰ２０３、ＭＰ２０４のレイアウトとは、それらに係る配線も含めて同じ形状になっている。すなわち、Ｐ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０３のレイアウト及び配線の形状が同じであり、Ｐ型ＭＯＳトランジスタＭＰ２０２、ＭＰ２０４のレイアウト及び配線の形状が同じである。例えば、Ｐ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０３のゲート長及びゲート幅は同じであり、Ｐ型ＭＯＳトランジスタＭＰ２０２、ＭＰ２０４のゲート長及びゲート幅は同じである。 Further, the layout of the two P-type MOS transistors MP201 and MP202 and the layout of the two P-type MOS transistors MP203 and MP204 have the same shape including the wirings related to them. That is, the layout and wiring shape of the P-type MOS transistors MP201 and MP203 are the same, and the layout and wiring shape of the P-type MOS transistors MP202 and MP204 are the same. For example, the P-type MOS transistors MP201 and MP203 have the same gate length and gate width, and the P-type MOS transistors MP202 and MP204 have the same gate length and gate width.
　このようにＰ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０３のレイアウト及び配線の形状を同じにしているため、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低いしきい値のトランジスタがどちらであるかは外見上では区別がつかない。同様に、Ｐ型ＭＯＳトランジスタＭＰ２０２、ＭＰ２０４のレイアウト及び配線の形状を同じにしているため、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低いしきい値のトランジスタがどちらであるかは外見上では区別がつかない。 Since the layouts and wiring shapes of the P-type MOS transistors MP201 and MP203 are made the same in this way, it is apparent which of the transistors has a threshold value lower than the value of (reference voltage GND−power supply voltage VDD). Then I can't distinguish. Similarly, since the layouts and wiring shapes of the P-type MOS transistors MP202 and MP204 are the same, it is apparent from which one of the transistors whose threshold value is lower than the value of (reference voltage GND−power supply voltage VDD). Then I can't distinguish.
　図２Ａに示したように接続された回路では、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低いしきい値電圧のＰ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０４はオフ状態になり、一般的（標準的）なしきい値電圧のＰ型ＭＯＳトランジスタＭＰ２０２、ＭＰ２０３はオン状態になる。したがって、Ｐ型ＭＯＳトランジスタＭＰ２０１、ＭＰ２０２の接続点の電圧（信号ＳＩＮＡ）は、基準電圧ＧＮＤよりＰ型ＭＯＳトランジスタＭＰ２０２のしきい値ＶＴＨの絶対値分高い（ＧＮＤ＋｜ＶＴＨ｜）となり、Ｐ型ＭＯＳトランジスタＭＰ２０３、ＭＰ２０４の接続点の電圧（信号ＳＩＮＢ）は、ほぼ電源電圧ＶＤＤになる。 In the circuit connected as shown in FIG. 2A, the P-type MOS transistors MP201 and MP204 having a threshold voltage lower than the value of (reference voltage GND−power supply voltage VDD) are turned off, and the general (standard) ) P-type MOS transistors MP202 and MP203 having a threshold voltage are turned on. Therefore, the voltage (signal SINA) at the connection point between the P-type MOS transistors MP201 and MP202 becomes (GND + | VTH |) higher than the reference voltage GND by the absolute value of the threshold value VTH of the P-type MOS transistor MP202. The voltage (signal SINB) at the connection point of the transistors MP203 and MP204 is substantially the power supply voltage VDD.
　このとき、増幅部（レベルシフタ）２１では、Ｐ型ＭＯＳトランジスタＭＰ２１及びＮ型ＭＯＳトランジスタＭＮ２２はオン状態になり、Ｐ型ＭＯＳトランジスタＭＰ２２及びＮ型ＭＯＳトランジスタＭＮ２１はオフ状態になる。したがって、図２Ａに示した回路は、出力信号ＳＯＵＴとして、基準電圧ＧＮＤレベルの‘０’の信号を出力する。 At this time, in the amplification unit (level shifter) 21, the P-type MOS transistor MP21 and the N-type MOS transistor MN22 are turned on, and the P-type MOS transistor MP22 and the N-type MOS transistor MN21 are turned off. Therefore, the circuit shown in FIG. 2A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
　次に、図２Ｂに示す第２の信号出力回路は、Ｐ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０６、ＭＰ２０７、ＭＰ２０８、及び増幅部２１を有する。なお、図２Ｂにおいて、図２Ａに示した構成要素と同一の構成要素には同一の符号を付し、重複する説明は省略する。 Next, the second signal output circuit shown in FIG. 2B includes P-type MOS transistors MP205, MP206, MP207, MP208, and an amplifying unit 21. In FIG. 2B, the same components as those shown in FIG. 2A are denoted by the same reference numerals, and redundant description is omitted.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＰ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０６が、この順で直列に接続され、２つのＰ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０６の接続点の電圧が信号ＳＩＮＡとして出力される。Ｐ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０６は、ゲートが基準電圧ＧＮＤを供給する信号線に接続され、バックゲートが電源電圧ＶＤＤを供給する信号線に接続される。 Two P-type MOS transistors MP205 and MP206 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point between the two P-type MOS transistors MP205 and MP206 is output as the signal SINA. In the P-type MOS transistors MP205 and MP206, the gates are connected to a signal line that supplies the reference voltage GND, and the back gates are connected to a signal line that supplies the power supply voltage VDD.
　また、電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側から２つのＰ型ＭＯＳトランジスタＭＰ２０７、ＭＰ２０８が、この順で直列に接続され、２つのＰ型ＭＯＳトランジスタＭＰ２０７、ＭＰ２０８の接続点の電圧が信号ＳＩＮＢとして出力される。Ｐ型ＭＯＳトランジスタＭＰ２０７、ＭＰ２０８は、ゲートが基準電圧ＧＮＤを供給する信号線に接続され、バックゲートが電源電圧ＶＤＤを供給する信号線に接続される。 Two P-type MOS transistors MP207 and MP208 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point between the two P-type MOS transistors MP207 and MP208 is output as the signal SINB. In the P-type MOS transistors MP207 and MP208, the gates are connected to a signal line that supplies the reference voltage GND, and the back gates are connected to the signal line that supplies the power supply voltage VDD.
　ここで、Ｐ型ＭＯＳトランジスタＭＰ２０６、ＭＰ２０７のしきい値電圧は、同じ電圧とし、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低い値である。また、Ｐ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０８のしきい値電圧は、同じ電圧とし、一般的（標準的）なしきい値電圧である。すなわち、信号ＳＩＮＡを出力する２つのＰ型ＭＯＳトランジスタ、及び信号ＳＩＮＢを出力する２つのＰ型ＭＯＳトランジスタのそれぞれについて、トランジスタの配置を入れ替えたものであり、信号ＳＩＮＡ、ＳＩＮＢを出力する回路構成が、図２Ａに示したものとは逆になっている。 Here, the threshold voltages of the P-type MOS transistors MP206 and MP207 are the same voltage, and are lower than the value of (reference voltage GND−power supply voltage VDD). Further, the threshold voltages of the P-type MOS transistors MP205 and MP208 are the same voltage, and are general (standard) threshold voltages. That is, for each of the two P-type MOS transistors that output the signal SINA and the two P-type MOS transistors that output the signal SINB, the arrangement of the transistors is changed, and a circuit configuration that outputs the signals SINA and SINB is obtained. This is the reverse of that shown in FIG. 2A.
　なお、２つのＰ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０６のレイアウトと、２つのＰ型ＭＯＳトランジスタＭＰ２０７、ＭＰ２０８のレイアウトとは、それらに係る配線も含めて同じ形状になっている。Ｐ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０７のレイアウト及び配線の形状が同じであり、Ｐ型ＭＯＳトランジスタＭＰ２０６、ＭＰ２０８のレイアウト及び配線の形状が同じである。したがって、Ｐ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０７において、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低いしきい値のトランジスタがどちらであるかは外見上では区別がつかず、Ｐ型ＭＯＳトランジスタＭＰ２０６、ＭＰ２０８において、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低いしきい値のトランジスタがどちらであるかは外見上では区別がつかない。 Note that the layout of the two P-type MOS transistors MP205 and MP206 and the layout of the two P-type MOS transistors MP207 and MP208 have the same shape including the wirings related to them. The layout and wiring shape of the P-type MOS transistors MP205 and MP207 are the same, and the layout and wiring shape of the P-type MOS transistors MP206 and MP208 are the same. Therefore, in the P-type MOS transistors MP205 and MP207, which transistor has a threshold value lower than the value of (reference voltage GND−power supply voltage VDD) cannot be distinguished in appearance, and the P-type MOS transistors MP206, In MP208, it is indistinguishable from the outside whether the transistor has a threshold value lower than the value of (reference voltage GND−power supply voltage VDD).
　図２Ｂに示したように接続された回路では、（基準電圧ＧＮＤ－電源電圧ＶＤＤ）の値よりも低いしきい値電圧のＰ型ＭＯＳトランジスタＭＰ２０６、ＭＰ２０７はオフ状態になり、一般的（標準的）なしきい値電圧のＰ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０８はオン状態になる。したがって、Ｐ型ＭＯＳトランジスタＭＰ２０５、ＭＰ２０６の接続点の電圧（信号ＳＩＮＡ）は、ほぼ電源電圧ＶＤＤになり、Ｐ型ＭＯＳトランジスタＭＰ２０７、ＭＰ２０８の接続点の電圧（信号ＳＩＮＢ）は、基準電圧ＧＮＤよりＰ型ＭＯＳトランジスタＭＰ２０８のしきい値ＶＴＨの絶対値分高い（ＧＮＤ＋｜ＶＴＨ｜）になる。 In the circuit connected as shown in FIG. 2B, the P-type MOS transistors MP206 and MP207 having a threshold voltage lower than the value of (reference voltage GND−power supply voltage VDD) are turned off. ) P-type MOS transistors MP205 and MP208 having a threshold voltage are turned on. Therefore, the voltage at the connection point of the P-type MOS transistors MP205 and MP206 (signal SINA) is substantially the power supply voltage VDD, and the voltage at the connection point of the P-type MOS transistors MP207 and MP208 (signal SINB) is P from the reference voltage GND. (GND + | VTH |) which is higher by the absolute value of the threshold value VTH of the MOS transistor MP208.
　このとき、増幅部（レベルシフタ）２１では、Ｐ型ＭＯＳトランジスタＭＰ２１及びＮ型ＭＯＳトランジスタＭＮ２２はオフ状態になり、Ｐ型ＭＯＳトランジスタＭＰ２２及びＮ型ＭＯＳトランジスタＭＮ２１はオン状態になる。したがって、図２Ｂに示した回路は、出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号を出力する。 At this time, in the amplification unit (level shifter) 21, the P-type MOS transistor MP21 and the N-type MOS transistor MN22 are turned off, and the P-type MOS transistor MP22 and the N-type MOS transistor MN21 are turned on. Therefore, the circuit shown in FIG. 2B outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
　以上のように、Ｎ型ＭＯＳトランジスタに替えてＰ型ＭＯＳトランジスタを用いた第２の実施形態においても、第１の実施形態と同様の効果が得られ、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。 As described above, also in the second embodiment using the P-type MOS transistor instead of the N-type MOS transistor, the same effect as the first embodiment can be obtained, and the reproduction of the semiconductor device by reverse engineering is difficult. can do.
（第３の実施形態）
　次に、本発明の第３の実施形態について説明する。第３の実施形態は、第１の実施形態において電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続される２つのＮ型ＭＯＳトランジスタを、電源電圧ＶＤＤよりも低い電圧を供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続するようにしたものである。 (Third embodiment)
Next, a third embodiment of the present invention will be described. In the third embodiment, two N-type MOS transistors connected in series between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage GND in the first embodiment are replaced with the power supply voltage VDD. The signal line supplying a lower voltage and the signal line supplying the reference voltage GND are connected in series.
　第３の実施形態における半導体装置は、図３Ａ及び図３Ｂに示すような信号出力回路を複数有する。図３Ａ及び図３Ｂは、第３の実施形態における半導体装置が有する信号出力回路の例を示す図である。図３Ａに示す第１の信号出力回路は、Ｎ型ＭＯＳトランジスタＭＮ３０１、ＭＮ３０２、ＭＮ３０３、ＭＮ３０４、ＭＮ３０５及び増幅部１１を有する。 The semiconductor device according to the third embodiment has a plurality of signal output circuits as shown in FIGS. 3A and 3B. 3A and 3B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the third embodiment. The first signal output circuit shown in FIG. 3A includes N-type MOS transistors MN301, MN302, MN303, MN304, MN305, and an amplifier unit 11.
　Ｎ型トランジスタＭＮ３０５は、一般的（標準的）なしきい値電圧を持つトランジスタであり、電源電圧ＶＤＤを供給する信号線と電源電圧ＶＤＤよりも低い電圧を供給する信号線との間に接続されるとともに、ゲートが電源電圧ＶＤＤを供給する信号線に接続される。すなわち、Ｎ型トランジスタＭＮ３０５は、電源電圧ＶＤＤを供給する信号線に対してダイオード接続されている。したがって、電源電圧ＶＤＤよりも低い電圧を供給する信号線の電圧は、電源電圧ＶＤＤよりもＮ型トランジスタＭＮ３０５のしきい値電圧ＶＴＨ分低い（ＶＤＤ－ＶＴＨ）となる。 The N-type transistor MN305 is a transistor having a general (standard) threshold voltage, and is connected between a signal line that supplies the power supply voltage VDD and a signal line that supplies a voltage lower than the power supply voltage VDD. At the same time, the gate is connected to a signal line for supplying the power supply voltage VDD. That is, the N-type transistor MN305 is diode-connected to the signal line that supplies the power supply voltage VDD. Therefore, the voltage of the signal line that supplies a voltage lower than the power supply voltage VDD is lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN305 (VDD−VTH).
　Ｎ型ＭＯＳトランジスタＭＮ３０１、ＭＮ３０２、ＭＮ３０３、ＭＮ３０４及び増幅部１１は、図１Ａに示したＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２、ＭＮ１０３、ＭＮ１０４及び増幅部１１とそれぞれ同様である。 The N-type MOS transistors MN301, MN302, MN303, MN304 and the amplification unit 11 are the same as the N-type MOS transistors MN101, MN102, MN103, MN104 and the amplification unit 11 shown in FIG. 1A, respectively.
　ただし、本実施形態では、２つのＮ型ＭＯＳトランジスタＭＮ３０１、ＭＮ３０２は、電圧（ＶＤＤ－ＶＴＨ）を供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続される。同様に、２つのＮ型ＭＯＳトランジスタＭＮ３０３、ＭＮ３０４は、電圧（ＶＤＤ－ＶＴＨ）を供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続される。また、Ｎ型ＭＯＳトランジスタＭＮ３０１、ＭＮ３０２、ＭＮ３０３、ＭＮ３０４のゲートは、電圧（ＶＤＤ－ＶＴＨ）を供給する信号線に接続される。 However, in this embodiment, the two N-type MOS transistors MN301 and MN302 are connected in series between a signal line that supplies a voltage (VDD-VTH) and a signal line that supplies a reference voltage GND. Similarly, the two N-type MOS transistors MN303 and MN304 are connected in series between a signal line that supplies a voltage (VDD−VTH) and a signal line that supplies a reference voltage GND. The gates of the N-type MOS transistors MN301, MN302, MN303, and MN304 are connected to a signal line that supplies a voltage (VDD-VTH).
　図３Ａに示したように接続された回路では、Ｎ型ＭＯＳトランジスタＭＮ３０１、ＭＮ３０４はオフ状態になり、Ｎ型ＭＯＳトランジスタＭＮ３０２、ＭＮ３０３はオン状態になる。したがって、Ｎ型ＭＯＳトランジスタＭＮ３０１、ＭＮ３０２の接続点の電圧（信号ＳＩＮＡ）は、ほぼ基準電圧ＧＮＤになり、Ｎ型ＭＯＳトランジスタＭＮ３０３、ＭＮ３０４の接続点の電圧（信号ＳＩＮＢ）は、電圧（ＶＤＤ－ＶＴＨ）よりＮ型ＭＯＳトランジスタＭＮ３０３のしきい値ＶＴＨ分低い（ＶＤＤ－２ＶＴＨ）になる。したがって、図３Ａに示した回路は、出力信号ＳＯＵＴとして、基準電圧ＧＮＤレベルの‘０’の信号を出力する。 In the circuit connected as shown in FIG. 3A, the N-type MOS transistors MN301 and MN304 are turned off, and the N-type MOS transistors MN302 and MN303 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN301 and MN302 is substantially the reference voltage GND, and the voltage (signal SINB) at the connection point of the N-type MOS transistors MN303 and MN304 is the voltage (VDD−VTH). ) Lower than the threshold voltage VTH of the N-type MOS transistor MN303 (VDD−2VTH). Therefore, the circuit shown in FIG. 3A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
　次に、図３Ｂに示す第２の信号出力回路は、Ｎ型ＭＯＳトランジスタＭＮ３０６、ＭＮ３０７、ＭＮ３０８、ＭＮ３０９、ＭＮ３１０、及び増幅部１１を有する。 Next, the second signal output circuit shown in FIG. 3B includes N-type MOS transistors MN306, MN307, MN308, MN309, MN310, and the amplifying unit 11.
　Ｎ型トランジスタＭＮ３１０は、一般的（標準的）なしきい値電圧を持つトランジスタであり、電源電圧ＶＤＤを供給する信号線と電源電圧ＶＤＤよりも低い電圧を供給する信号線との間に接続されるとともに、ゲートが電源電圧ＶＤＤを供給する信号線に接続される。すなわち、Ｎ型トランジスタＭＮ３１０は、電源電圧ＶＤＤを供給する信号線に対してダイオード接続されている。したがって、電源電圧ＶＤＤよりも低い電圧を供給する信号線の電圧は、電源電圧ＶＤＤよりもＮ型トランジスタＭＮ３１０のしきい値電圧ＶＴＨ分低い（ＶＤＤ－ＶＴＨ）となる。 The N-type transistor MN310 is a transistor having a general (standard) threshold voltage, and is connected between a signal line that supplies the power supply voltage VDD and a signal line that supplies a voltage lower than the power supply voltage VDD. At the same time, the gate is connected to a signal line for supplying the power supply voltage VDD. That is, the N-type transistor MN310 is diode-connected to the signal line that supplies the power supply voltage VDD. Accordingly, the voltage of the signal line that supplies a voltage lower than the power supply voltage VDD is lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN310 (VDD−VTH).
　Ｎ型ＭＯＳトランジスタＭＮ３０６、ＭＮ３０７、ＭＮ３０８、ＭＮ３０９及び増幅部１１は、図１Ｂに示したＮ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６、ＭＮ１０７、ＭＮ１０８及び増幅部１１とそれぞれ同様である。 The N-type MOS transistors MN306, MN307, MN308, and MN309 and the amplifying unit 11 are the same as the N-type MOS transistors MN105, MN106, MN107, MN108, and the amplifying unit 11 shown in FIG. 1B, respectively.
　ただし、本実施形態では、２つのＮ型ＭＯＳトランジスタＭＮ３０６、ＭＮ３０７は、電圧（ＶＤＤ－ＶＴＨ）を供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続される。同様に、２つのＮ型ＭＯＳトランジスタＭＮ３０８、ＭＮ３０９は、電圧（ＶＤＤ－ＶＴＨ）を供給する信号線と基準電圧ＧＮＤを供給する信号線との間に直列に接続される。また、Ｎ型ＭＯＳトランジスタＭＮ３０６、ＭＮ３０７、ＭＮ３０８、ＭＮ３０９のゲートは、電圧（ＶＤＤ－ＶＴＨ）を供給する信号線に接続される。 However, in this embodiment, the two N-type MOS transistors MN306 and MN307 are connected in series between a signal line that supplies a voltage (VDD-VTH) and a signal line that supplies a reference voltage GND. Similarly, the two N-type MOS transistors MN308 and MN309 are connected in series between a signal line that supplies a voltage (VDD−VTH) and a signal line that supplies a reference voltage GND. The gates of the N-type MOS transistors MN306, MN307, MN308, and MN309 are connected to a signal line that supplies a voltage (VDD-VTH).
　図３Ｂに示したように接続された回路では、Ｎ型ＭＯＳトランジスタＭＮ３０７、ＭＮ３０８はオフ状態になり、Ｎ型ＭＯＳトランジスタＭＮ３０６、ＭＮ３０９はオン状態になる。したがって、Ｎ型ＭＯＳトランジスタＭＮ３０６、ＭＮ３０７の接続点の電圧（信号ＳＩＮＡ）は、電圧（ＶＤＤ－ＶＴＨ）よりＮ型ＭＯＳトランジスタＭＮ３０６のしきい値ＶＴＨ分低い（ＶＤＤ－２ＶＴＨ）になり、Ｎ型ＭＯＳトランジスタＭＮ３０８、ＭＮ３０９の接続点の電圧（信号ＳＩＮＢ）は、ほぼ基準電圧ＧＮＤになる。したがって、図３Ｂに示した回路は、出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号を出力する。 In the circuit connected as shown in FIG. 3B, the N-type MOS transistors MN307 and MN308 are turned off, and the N-type MOS transistors MN306 and MN309 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN306 and MN307 is lower than the voltage (VDD−VTH) by the threshold VTH of the N-type MOS transistor MN306 (VDD−2VTH), and the N-type MOS The voltage (signal SINB) at the connection point of the transistors MN308 and MN309 is substantially the reference voltage GND. Therefore, the circuit shown in FIG. 3B outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
　以上のように、電源電圧ＶＤＤ側にダイオード接続されたＮ型ＭＯＳトランジスタを設け、このＮ型ＭＯＳトランジスタにより得られる電源電圧ＶＤＤよりも低い電圧を供給する信号線と基準電圧ＧＮＤを供給する信号線との間に２つのＮ型ＭＯＳトランジスタを直列に接続する第３の実施形態においても、第１の実施形態と同様の効果が得られ、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。また、第３の実施形態は、第１の実施形態において電源電圧を下げているのと同等であるので、消費電力を低減することができる。 As described above, a diode-connected N-type MOS transistor is provided on the power supply voltage VDD side, and a signal line for supplying a voltage lower than the power supply voltage VDD obtained by the N-type MOS transistor and a signal line for supplying the reference voltage GND are provided. In the third embodiment in which two N-type MOS transistors are connected in series with each other, the same effect as in the first embodiment can be obtained, and the reproduction of the semiconductor device by reverse engineering can be made difficult. . Moreover, since the third embodiment is equivalent to lowering the power supply voltage in the first embodiment, power consumption can be reduced.
（第４の実施形態）
　次に、本発明の第４の実施形態について説明する。
　第４の実施形態における半導体装置は、図４Ａ及び図４Ｂに示すような信号出力回路を複数有する。図４Ａ及び図４Ｂは、第４の実施形態における半導体装置が有する信号出力回路の例を示す図である。図４Ａに示す第１の信号出力回路は、Ｎ型ＭＯＳトランジスタＭＮ４０１、ＭＮ４０２、ＭＮ４０３、ＭＮ４０４及び増幅部１１を有する。Ｎ型ＭＯＳトランジスタＭＮ４０１、ＭＮ４０２、ＭＮ４０３、ＭＮ４０４及び増幅部１１は、図１Ａに示したＮ型ＭＯＳトランジスタＭＮ１０１、ＭＮ１０２、ＭＮ１０３、ＭＮ１０４及び増幅部１１とそれぞれ同様である。 (Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
The semiconductor device according to the fourth embodiment has a plurality of signal output circuits as shown in FIGS. 4A and 4B. 4A and 4B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the fourth embodiment. The first signal output circuit shown in FIG. 4A includes N-type MOS transistors MN401, MN402, MN403, and MN404, and an amplifier unit 11. The N-type MOS transistors MN401, MN402, MN403, and MN404 and the amplification unit 11 are the same as the N-type MOS transistors MN101, MN102, MN103, MN104, and the amplification unit 11 shown in FIG. 1A, respectively.
　ただし、本実施形態では、Ｎ型ＭＯＳトランジスタＭＮ４０１のゲートが電圧ＶＤＤを供給する信号線に接続され、Ｎ型ＭＯＳトランジスタＭＮ４０２のゲートが２つのＮ型ＭＯＳトランジスタＭＮ４０１、ＭＮ４０２の接続点に接続される。また、Ｎ型ＭＯＳトランジスタＭＮ４０３のゲートが電圧ＶＤＤを供給する信号線に接続され、Ｎ型ＭＯＳトランジスタＭＮ４０４のゲートが２つのＮ型ＭＯＳトランジスタＭＮ４０３、ＭＮ４０４の接続点に接続される。つまり、Ｎ型ＭＯＳトランジスタＭＮ４０１、ＭＮ４０２、ＭＮ４０３、ＭＮ４０４のそれぞれはダイオード接続されている。 However, in this embodiment, the gate of the N-type MOS transistor MN401 is connected to the signal line that supplies the voltage VDD, and the gate of the N-type MOS transistor MN402 is connected to the connection point of the two N-type MOS transistors MN401 and MN402. . The gate of the N-type MOS transistor MN403 is connected to a signal line that supplies the voltage VDD, and the gate of the N-type MOS transistor MN404 is connected to the connection point of the two N-type MOS transistors MN403 and MN404. That is, each of the N-type MOS transistors MN401, MN402, MN403, and MN404 is diode-connected.
　図４Ａに示したように接続された回路では、Ｎ型ＭＯＳトランジスタＭＮ４０１、ＭＮ４０４はオフ状態になり、Ｎ型ＭＯＳトランジスタＭＮ４０２、ＭＮ４０３はオン状態になる。したがって、Ｎ型ＭＯＳトランジスタＭＮ４０１、ＭＮ４０２の接続点の電圧（信号ＳＩＮＡ）は、基準電圧ＧＮＤよりＮ型ＭＯＳトランジスタＭＮ４０２のしきい値ＶＴＨ分高い（ＧＮＤ＋ＶＴＨ）になり、Ｎ型ＭＯＳトランジスタＭＮ４０３、ＭＮ４０４の接続点の電圧（信号ＳＩＮＢ）は、電源電圧ＶＤＤよりＮ型ＭＯＳトランジスタＭＮ４０３のしきい値ＶＴＨ分低い（ＶＤＤ－ＶＴＨ）になる。したがって、図４Ａに示した回路は、出力信号ＳＯＵＴとして、基準電圧ＧＮＤレベルの‘０’の信号を出力する。 In the circuit connected as shown in FIG. 4A, the N-type MOS transistors MN401 and MN404 are turned off, and the N-type MOS transistors MN402 and MN403 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN401 and MN402 is higher than the reference voltage GND by the threshold VTH of the N-type MOS transistor MN402 (GND + VTH), and the N-type MOS transistors MN403 and MN404 The voltage at the connection point (signal SINB) is lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN403 (VDD−VTH). Therefore, the circuit shown in FIG. 4A outputs a signal of “0” at the reference voltage GND level as the output signal SOUT.
　次に、図４Ｂに示す第２の信号出力回路は、Ｎ型ＭＯＳトランジスタＭＮ４０５、ＭＮ４０６、ＭＮ４０７、ＭＮ４０８、及び増幅部１１を有する。Ｎ型ＭＯＳトランジスタＭＮ４０５、ＭＮ４０６、ＭＮ４０７、ＭＮ４０８及び増幅部１１は、図１Ｂに示したＮ型ＭＯＳトランジスタＭＮ１０５、ＭＮ１０６、ＭＮ１０７、ＭＮ１０８及び増幅部１１とそれぞれ同様である。 Next, the second signal output circuit shown in FIG. 4B includes N-type MOS transistors MN405, MN406, MN407, MN408, and an amplifying unit 11. The N-type MOS transistors MN405, MN406, MN407, MN408 and the amplifying unit 11 are the same as the N-type MOS transistors MN105, MN106, MN107, MN108 and the amplifying unit 11 shown in FIG. 1B, respectively.
　ただし、本実施形態では、Ｎ型ＭＯＳトランジスタＭＮ４０５のゲートが電圧ＶＤＤを供給する信号線に接続され、Ｎ型ＭＯＳトランジスタＭＮ４０６のゲートが２つのＮ型ＭＯＳトランジスタＭＮ４０５、ＭＮ４０６の接続点に接続される。また、Ｎ型ＭＯＳトランジスタＭＮ４０７のゲートが電圧ＶＤＤを供給する信号線に接続され、Ｎ型ＭＯＳトランジスタＭＮ４０８のゲートが２つのＮ型ＭＯＳトランジスタＭＮ４０７、ＭＮ４０８の接続点に接続される。つまり、Ｎ型ＭＯＳトランジスタＭＮ４０５、ＭＮ４０６、ＭＮ４０７、ＭＮ４０８のそれぞれはダイオード接続されている。 However, in this embodiment, the gate of the N-type MOS transistor MN405 is connected to the signal line that supplies the voltage VDD, and the gate of the N-type MOS transistor MN406 is connected to the connection point of the two N-type MOS transistors MN405 and MN406. . The gate of the N-type MOS transistor MN407 is connected to a signal line that supplies the voltage VDD, and the gate of the N-type MOS transistor MN408 is connected to a connection point between the two N-type MOS transistors MN407 and MN408. That is, each of the N-type MOS transistors MN405, MN406, MN407, and MN408 is diode-connected.
　図４Ｂに示したように接続された回路では、Ｎ型ＭＯＳトランジスタＭＮ４０６、ＭＮ４０７はオフ状態になり、Ｎ型ＭＯＳトランジスタＭＮ４０５、ＭＮ４０８はオン状態になる。したがって、Ｎ型ＭＯＳトランジスタＭＮ４０５、ＭＮ４０６の接続点の電圧（信号ＳＩＮＡ）は、電源電圧ＶＤＤよりＮ型ＭＯＳトランジスタＭＮ４０５のしきい値ＶＴＨ分低い（ＶＤＤ－ＶＴＨ）になり、Ｎ型ＭＯＳトランジスタＭＮ４０７、ＭＮ４０８の接続点の電圧（信号ＳＩＮＢ）は、基準電圧ＧＮＤよりＮ型ＭＯＳトランジスタＭＮ４０８のしきい値ＶＴＨ分高い（ＧＮＤ＋ＶＴＨ）になる。したがって、図４Ｂに示した回路は、出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号を出力する。 In the circuit connected as shown in FIG. 4B, the N-type MOS transistors MN406 and MN407 are turned off, and the N-type MOS transistors MN405 and MN408 are turned on. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN405 and MN406 is lower than the power supply voltage VDD by the threshold value VTH of the N-type MOS transistor MN405 (VDD−VTH), and the N-type MOS transistors MN407, The voltage at the connection point of MN408 (signal SINB) is higher than the reference voltage GND by the threshold value VTH of the N-type MOS transistor MN408 (GND + VTH). Therefore, the circuit shown in FIG. 4B outputs a “1” signal at the power supply voltage VDD level as the output signal SOUT.
　以上説明した第４の実施形態によれば、第１の実施形態と同様の効果が得られ、リバースエンジニアリングによる半導体装置の再現を困難にすることができるとともに、消費電力を低減することができる。 According to the fourth embodiment described above, the same effects as those of the first embodiment can be obtained, making it difficult to reproduce the semiconductor device by reverse engineering and reducing the power consumption.
　なお、前述した第３の実施形態及び第４の実施形態では、Ｎ型ＭＯＳトランジスタを用いた例を示したが、Ｐ型ＭＯＳトランジスタを用いて実現することも可能である。この場合には、第２の実施形態に準じて接続を変更すればよく、リバースエンジニアリングによる半導体装置の再現を困難にすることができるとともに、消費電力を低減することができるという同様の効果が得られる。 In the third embodiment and the fourth embodiment described above, an example using an N-type MOS transistor has been shown, but it can also be realized using a P-type MOS transistor. In this case, it is only necessary to change the connection according to the second embodiment, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering and to reduce the power consumption. It is done.
（第５の実施形態）
　次に、本発明の第５の実施形態について説明する。
　第５の実施形態における半導体装置は、図５Ａ及び図５Ｂに示すような信号出力回路を複数有する。図５Ａ及び図５Ｂは、第５の実施形態における半導体装置が有する信号出力回路の例を示す図である。図５Ａに示す第１の信号出力回路は、デプレッション型のＮ型ＭＯＳトランジスタＭＮ５０１と、エンハンスメント型のＮ型ＭＯＳトランジスタＭＮ５０２とを有する。 (Fifth embodiment)
Next, a fifth embodiment of the present invention will be described.
The semiconductor device according to the fifth embodiment has a plurality of signal output circuits as shown in FIGS. 5A and 5B. 5A and 5B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the fifth embodiment. The first signal output circuit shown in FIG. 5A includes a depletion type N-type MOS transistor MN501 and an enhancement type N-type MOS transistor MN502.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＮ型ＭＯＳトランジスタＭＮ５０１、ＭＮ５０２が、この順で直列に接続され、Ｎ型ＭＯＳトランジスタＭＮ５０１、ＭＮ５０２の接続点の電圧が出力信号ＳＯＵＴとして出力される。Ｎ型ＭＯＳトランジスタＭＮ５０１のゲートがＮ型ＭＯＳトランジスタＭＮ５０１、ＭＮ５０２の接続点に接続され、Ｎ型ＭＯＳトランジスタＭＮ５０２のゲートが基準電圧ＧＮＤを供給する信号線に接続される。すなわち、Ｎ型ＭＯＳトランジスタＭＮ５０１、ＭＮ５０２はダイオード接続されている。また、Ｎ型ＭＯＳトランジスタＭＮ５０１、ＭＮ５０２のバックゲートが基準電圧ＧＮＤを供給する信号線に接続される。 N-type MOS transistors MN501 and MN502 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the type MOS transistors MN501 and MN502 is output as the output signal SOUT. The gate of the N-type MOS transistor MN501 is connected to the connection point of the N-type MOS transistors MN501 and MN502, and the gate of the N-type MOS transistor MN502 is connected to a signal line that supplies the reference voltage GND. That is, the N-type MOS transistors MN501 and MN502 are diode-connected. Further, the back gates of the N-type MOS transistors MN501 and MN502 are connected to a signal line for supplying the reference voltage GND.
　図５Ａに示したように接続された回路では、デプレッション型のＮ型ＭＯＳトランジスタＭＮ５０１がオン状態になり、エンハンスメント型のＮ型ＭＯＳトランジスタＭＮ５０２がオフ状態となる。したがって、図５Ａに示した回路は、出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号を出力する。 In the circuit connected as shown in FIG. 5A, the depletion type N-type MOS transistor MN501 is turned on, and the enhancement type N-type MOS transistor MN502 is turned off. Therefore, the circuit shown in FIG. 5A outputs a signal “1” at the power supply voltage VDD level as the output signal SOUT.
　次に、図５Ｂに示す第２の信号出力回路は、エンハンスメント型のＮ型ＭＯＳトランジスタＭＮ５０３と、デプレッション型のＮ型ＭＯＳトランジスタＭＮ５０４とを有する。ここで、Ｎ型ＭＯＳトランジスタＭＮ５０３は、Ｎ型ＭＯＳトランジスタＭＮ５０１とレイアウト及び配線の形状が同じであり、Ｎ型ＭＯＳトランジスタＭＮ５０４は、Ｎ型ＭＯＳトランジスタＭＮ５０２とレイアウト及び配線の形状が同じである。 Next, the second signal output circuit shown in FIG. 5B includes an enhancement type N-type MOS transistor MN503 and a depletion type N-type MOS transistor MN504. Here, the N-type MOS transistor MN503 has the same layout and wiring shape as the N-type MOS transistor MN501, and the N-type MOS transistor MN504 has the same layout and wiring shape as the N-type MOS transistor MN502.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＮ型ＭＯＳトランジスタＭＮ５０３、ＭＮ５０４が、この順で直列に接続され、Ｎ型ＭＯＳトランジスタＭＮ５０３、ＭＮ５０４の接続点の電圧が出力信号ＳＯＵＴとして出力される。Ｎ型ＭＯＳトランジスタＭＮ５０３のゲートがＮ型ＭＯＳトランジスタＭＮ５０３、ＭＮ５０４の接続点に接続され、Ｎ型ＭＯＳトランジスタＭＮ５０４のゲートが基準電圧ＧＮＤを供給する信号線に接続される。すなわち、Ｎ型ＭＯＳトランジスタＭＮ５０３、ＭＮ５０４はダイオード接続されている。また、Ｎ型ＭＯＳトランジスタＭＮ５０３、ＭＮ５０４のバックゲートが基準電圧ＧＮＤを供給する信号線に接続される。 N-type MOS transistors MN503 and MN504 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the type MOS transistors MN503 and MN504 is output as the output signal SOUT. The gate of the N-type MOS transistor MN503 is connected to the connection point of the N-type MOS transistors MN503 and MN504, and the gate of the N-type MOS transistor MN504 is connected to a signal line that supplies the reference voltage GND. That is, the N-type MOS transistors MN503 and MN504 are diode-connected. Further, the back gates of the N-type MOS transistors MN503 and MN504 are connected to a signal line that supplies the reference voltage GND.
　図５Ｂに示した回路では、デプレッション型のＮ型ＭＯＳトランジスタＭＮ５０４がオン状態になり、エンハンスメント型のＮ型ＭＯＳトランジスタＭＮ５０３がオフ状態となる。したがって、図５Ｂに示した回路は、出力信号ＳＯＵＴとして、基準電圧ＧＮＤレベルの‘０’の信号を出力する。なお、第５の実施形態における半導体装置が有する信号出力回路では、Ｎ型ＭＯＳトランジスタＭＮ５０１、ＭＮ５０２の接続点の電圧、及びＮ型ＭＯＳトランジスタＭＮ５０３、ＭＮ５０４の接続点の電圧は、電源電圧ＶＤＤレベル又は基準電圧ＧＮＤレベルになるので増幅部は不要である。 In the circuit shown in FIG. 5B, the depletion type N-type MOS transistor MN504 is turned on, and the enhancement type N-type MOS transistor MN503 is turned off. Therefore, the circuit shown in FIG. 5B outputs a signal of “0” at the reference voltage GND level as the output signal SOUT. In the signal output circuit included in the semiconductor device according to the fifth embodiment, the voltage at the connection point of the N-type MOS transistors MN501 and MN502 and the voltage at the connection point of the N-type MOS transistors MN503 and MN504 are the power supply voltage VDD level or Since it becomes the reference voltage GND level, an amplifying unit is unnecessary.
　以上のように、レイアウト及び配線の形状は同じであるが特性の異なるトランジスタを用いることで、レイアウトから回路図を読み取るだけでは動作を再現することができず、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。また、第５の実施形態における半導体装置が有する信号出力回路は、図１Ａ及び図１Ｂに示したような信号出力回路と比較して構成するトランジスタ数が少なく増幅部も不要であるので、実装に要する面積を小さくすることができ、半導体チップ上の自動配置配線エリアの中に、より多数の信号出力回路を搭載することが可能となる。したがって、リバースエンジニアリングによる半導体装置の再現をさらに困難にすることができる。また、電流もほとんど流れないので消費電力も低減することができる。 As described above, by using transistors with the same layout and wiring shape but different characteristics, the operation cannot be reproduced simply by reading the circuit diagram from the layout, and it is difficult to reproduce the semiconductor device by reverse engineering. Can be. Further, the signal output circuit included in the semiconductor device according to the fifth embodiment has fewer transistors than the signal output circuit shown in FIGS. 1A and 1B, and does not require an amplifier. The required area can be reduced, and a larger number of signal output circuits can be mounted in the automatic placement and wiring area on the semiconductor chip. Therefore, the reproduction of the semiconductor device by reverse engineering can be made more difficult. In addition, since almost no current flows, power consumption can be reduced.
（第６の実施形態）
　次に、本発明の第６の実施形態について説明する。第６の実施形態は、第５の実施形態におけるＮ型ＭＯＳトランジスタに替えてＰ型ＭＯＳトランジスタを用いるものである。 (Sixth embodiment)
Next, a sixth embodiment of the present invention will be described. In the sixth embodiment, a P-type MOS transistor is used in place of the N-type MOS transistor in the fifth embodiment.
　第６の実施形態における半導体装置は、図６Ａ及び図６Ｂに示すような信号出力回路を複数有する。図６Ａ及び図６Ｂは、第６の実施形態における半導体装置が有する信号出力回路の例を示す図である。図６Ａに示す第１の信号出力回路は、デプレッション型のＰ型ＭＯＳトランジスタＭＰ６０１と、エンハンスメント型のＰ型ＭＯＳトランジスタＭＰ６０２とを有する。 The semiconductor device according to the sixth embodiment has a plurality of signal output circuits as shown in FIGS. 6A and 6B. 6A and 6B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the sixth embodiment. The first signal output circuit shown in FIG. 6A includes a depletion type P-type MOS transistor MP601 and an enhancement type P-type MOS transistor MP602.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ６０１、ＭＰ６０２が、この順で直列に接続され、Ｐ型ＭＯＳトランジスタＭＰ６０１、ＭＰ６０２の接続点の電圧が出力信号ＳＯＵＴとして出力される。Ｐ型ＭＯＳトランジスタＭＰ６０１のゲートが電源電圧ＶＤＤを供給する信号線に接続され、Ｐ型ＭＯＳトランジスタＭＰ６０２のゲートがＰ型ＭＯＳトランジスタＭＰ６０１、ＭＰ６０２の接続点に接続される。すなわち、Ｐ型ＭＯＳトランジスタＭＰ６０１、ＭＰ６０２はダイオード接続されている。また、Ｐ型ＭＯＳトランジスタＭＰ６０１、ＭＰ６０２のバックゲートが電源電圧ＶＤＤを供給する信号線に接続される。 P-type MOS transistors MP601 and MP602 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the type MOS transistors MP601 and MP602 is output as the output signal SOUT. The gate of the P-type MOS transistor MP601 is connected to the signal line that supplies the power supply voltage VDD, and the gate of the P-type MOS transistor MP602 is connected to the connection point of the P-type MOS transistors MP601 and MP602. That is, the P-type MOS transistors MP601 and MP602 are diode-connected. The back gates of the P-type MOS transistors MP601 and MP602 are connected to a signal line that supplies the power supply voltage VDD.
　図６Ａに示したように接続された回路では、デプレッション型のＰ型ＭＯＳトランジスタＭＰ６０１がオン状態になり、エンハンスメント型のＰ型ＭＯＳトランジスタＭＰ６０２がオフ状態となる。したがって、図６Ａに示した回路は、出力信号ＳＯＵＴとして、電源電圧ＶＤＤレベルの‘１’の信号を出力する。 In the circuit connected as shown in FIG. 6A, the depletion type P-type MOS transistor MP601 is turned on, and the enhancement type P-type MOS transistor MP602 is turned off. Therefore, the circuit shown in FIG. 6A outputs a signal of “1” at the power supply voltage VDD level as the output signal SOUT.
　次に、図６Ｂに示す第２の信号出力回路は、エンハンスメント型のＰ型ＭＯＳトランジスタＭＰ６０３と、デプレッション型のＰ型ＭＯＳトランジスタＭＰ６０４とを有する。ここで、Ｐ型ＭＯＳトランジスタＭＰ６０３は、Ｐ型ＭＯＳトランジスタＭＰ６０１とレイアウト及び配線の形状が同じであり、Ｐ型ＭＯＳトランジスタＭＰ６０４は、Ｐ型ＭＯＳトランジスタＭＰ６０２とレイアウト及び配線の形状が同じである。 Next, the second signal output circuit shown in FIG. 6B includes an enhancement type P-type MOS transistor MP603 and a depletion type P-type MOS transistor MP604. Here, the P-type MOS transistor MP603 has the same layout and wiring shape as the P-type MOS transistor MP601, and the P-type MOS transistor MP604 has the same layout and wiring shape as the P-type MOS transistor MP602.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ６０３、ＭＰ６０４が、この順で直列に接続され、Ｐ型ＭＯＳトランジスタＭＰ６０３、ＭＰ６０４の接続点の電圧が出力信号ＳＯＵＴとして出力される。Ｐ型ＭＯＳトランジスタＭＰ６０３のゲートが電源電圧ＶＤＤを供給する信号線に接続され、Ｐ型ＭＯＳトランジスタＭＰ６０４のゲートがＰ型ＭＯＳトランジスタＭＰ６０３、ＭＰ６０４の接続点に接続される。すなわち、Ｐ型ＭＯＳトランジスタＭＰ６０３、ＭＰ６０４はダイオード接続されている。また、Ｐ型ＭＯＳトランジスタＭＰ６０３、ＭＰ６０４のバックゲートが電源電圧ＶＤＤを供給する信号線に接続される。 P-type MOS transistors MP603 and MP604 are connected in series in this order from the signal line supplying the power supply voltage VDD between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND. The voltage at the connection point of the type MOS transistors MP603 and MP604 is output as the output signal SOUT. The gate of the P-type MOS transistor MP603 is connected to the signal line that supplies the power supply voltage VDD, and the gate of the P-type MOS transistor MP604 is connected to the connection point of the P-type MOS transistors MP603 and MP604. That is, the P-type MOS transistors MP603 and MP604 are diode-connected. The back gates of the P-type MOS transistors MP603 and MP604 are connected to a signal line that supplies the power supply voltage VDD.
　図６Ｂに示したように接続された回路では、デプレッション型のＰ型ＭＯＳトランジスタＭＰ６０４がオン状態になり、エンハンスメント型のＰ型ＭＯＳトランジスタＭＰ６０３がオフ状態となる。したがって、図６Ｂに示した回路は、出力信号ＳＯＵＴとして、基準電圧ＧＮＤレベルの‘０’の信号を出力する。なお、第６の実施形態においても、Ｐ型ＭＯＳトランジスタＭＰ６０１、ＭＰ６０２の接続点の電圧、及びＰ型ＭＯＳトランジスタＭＰ６０３、ＭＰ６０４の接続点の電圧は、電源電圧ＶＤＤレベル又は基準電圧ＧＮＤレベルになるので増幅部は不要である。 In the circuit connected as shown in FIG. 6B, the depletion type P-type MOS transistor MP604 is turned on, and the enhancement type P-type MOS transistor MP603 is turned off. Therefore, the circuit shown in FIG. 6B outputs a signal of “0” at the reference voltage GND level as the output signal SOUT. Also in the sixth embodiment, the voltage at the connection point of the P-type MOS transistors MP601 and MP602 and the voltage at the connection point of the P-type MOS transistors MP603 and MP604 are at the power supply voltage VDD level or the reference voltage GND level. An amplifying unit is unnecessary.
　以上のように、Ｎ型ＭＯＳトランジスタに替えてＰ型ＭＯＳトランジスタを用いた第６の実施形態においても、第５の実施形態と同様の効果が得られ、リバースエンジニアリングによる半導体装置の再現を困難にすることができ、また消費電力も低減することができる。 As described above, in the sixth embodiment using a P-type MOS transistor instead of an N-type MOS transistor, the same effect as that of the fifth embodiment can be obtained, and it is difficult to reproduce a semiconductor device by reverse engineering. And power consumption can be reduced.
（第７の実施形態）
　次に、本発明の第７の実施形態について説明する。
　第７の実施形態における半導体装置は、図７Ａ及び図７Ｂに示すような信号出力回路を複数有する。図７Ａ及び図７Ｂは、第７の実施形態における半導体装置が有する信号出力回路の例を示す図である。図７Ａに示す第１の信号出力回路は、Ｐ型ＭＯＳトランジスタＭＰ７０１と、Ｎ型ＭＯＳトランジスタＭＮ７０１とを有する。ここで、Ｐ型ＭＯＳトランジスタＭＰ７０１とＮ型ＭＯＳトランジスタＭＮ７０１とは耐圧が異なっており、図７Ａに示す例ではＮ型ＭＯＳトランジスタＭＮ７０１が高耐圧のトランジスタであるとする。 (Seventh embodiment)
Next, a seventh embodiment of the present invention will be described.
The semiconductor device according to the seventh embodiment has a plurality of signal output circuits as shown in FIGS. 7A and 7B. 7A and 7B are diagrams illustrating examples of signal output circuits included in the semiconductor device according to the seventh embodiment. The first signal output circuit shown in FIG. 7A includes a P-type MOS transistor MP701 and an N-type MOS transistor MN701. Here, the P-type MOS transistor MP701 and the N-type MOS transistor MN701 have different withstand voltages, and in the example shown in FIG. 7A, the N-type MOS transistor MN701 is a high withstand voltage transistor.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ７０１とＮ型ＭＯＳトランジスタＭＮ７０１とが、この順で直列に接続され、Ｐ型ＭＯＳトランジスタＭＰ７０１とＮ型ＭＯＳトランジスタＭＮ７０１との接続点の電圧が出力信号ＳＯＵＴとして出力される。Ｐ型ＭＯＳトランジスタＭＰ７０１は、ゲートが基準電圧ＧＮＤを供給する信号線に接続され、バックゲートが電源電圧ＶＤＤを供給する信号線に接続される。また、Ｎ型ＭＯＳトランジスタＭＮ７０１は、ゲートが電源電圧ＶＤＤを供給する信号線に接続され、バックゲートが基準電圧ＧＮＤを供給する信号線に接続される。図７Ａに示した回路は、出力信号ＳＯＵＴとして電源電圧ＶＤＤに近い高い電圧ＶＨの信号を出力する。 Between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND, the P-type MOS transistor MP701 and the N-type MOS transistor MN701 are connected in series in this order from the signal line supplying the power supply voltage VDD. And a voltage at a connection point between the P-type MOS transistor MP701 and the N-type MOS transistor MN701 is output as the output signal SOUT. In the P-type MOS transistor MP701, the gate is connected to the signal line that supplies the reference voltage GND, and the back gate is connected to the signal line that supplies the power supply voltage VDD. The N-type MOS transistor MN701 has a gate connected to a signal line that supplies the power supply voltage VDD, and a back gate connected to a signal line that supplies the reference voltage GND. The circuit shown in FIG. 7A outputs a signal having a high voltage VH close to the power supply voltage VDD as the output signal SOUT.
　次に、図７Ｂに示す第２の信号出力回路は、Ｐ型ＭＯＳトランジスタＭＰ７０２と、Ｎ型ＭＯＳトランジスタＭＮ７０２とを有する。Ｐ型ＭＯＳトランジスタＭＰ７０２とＮ型ＭＯＳトランジスタＭＮ７０２とは耐圧が異なっており、図７Ａに示した例とは逆に、図７Ｂに示す例ではＰ型ＭＯＳトランジスタＭＰ７０２が高耐圧のトランジスタであるとする。ここで、Ｐ型ＭＯＳトランジスタＭＰ７０２は、Ｐ型ＭＯＳトランジスタＭＰ７０１とレイアウト及び配線の形状が同じであり、Ｎ型ＭＯＳトランジスタＭＮ７０２は、Ｎ型ＭＯＳトランジスタＭＮ７０１とレイアウト及び配線の形状が同じである。 Next, the second signal output circuit shown in FIG. 7B includes a P-type MOS transistor MP702 and an N-type MOS transistor MN702. The P-type MOS transistor MP702 and the N-type MOS transistor MN702 have different withstand voltages. In contrast to the example shown in FIG. 7A, in the example shown in FIG. 7B, the P-type MOS transistor MP702 is a high withstand voltage transistor. . Here, the P-type MOS transistor MP702 has the same layout and wiring shape as the P-type MOS transistor MP701, and the N-type MOS transistor MN702 has the same layout and wiring shape as the N-type MOS transistor MN701.
　電源電圧ＶＤＤを供給する信号線と基準電圧ＧＮＤを供給する信号線との間に、電源電圧ＶＤＤを供給する信号線側からＰ型ＭＯＳトランジスタＭＰ７０２とＮ型ＭＯＳトランジスタＭＮ７０２とが、この順で直列に接続され、Ｐ型ＭＯＳトランジスタＭＰ７０２とＮ型ＭＯＳトランジスタＭＮ７０２との接続点の電圧が出力信号ＳＯＵＴとして出力される。Ｐ型ＭＯＳトランジスタＭＰ７０２は、ゲートが基準電圧ＧＮＤを供給する信号線に接続され、バックゲートが電源電圧ＶＤＤを供給する信号線に接続される。また、Ｎ型ＭＯＳトランジスタＭＮ７０２は、ゲートが電源電圧ＶＤＤを供給する信号線に接続され、バックゲートが基準電圧ＧＮＤを供給する信号線に接続される。図７Ｂに示した回路は、出力信号ＳＯＵＴとして基準電圧ＧＮＤに近い低い電圧ＶＬの信号を出力する。 Between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND, the P-type MOS transistor MP702 and the N-type MOS transistor MN702 are connected in series in this order from the signal line side supplying the power supply voltage VDD. And a voltage at a connection point between the P-type MOS transistor MP702 and the N-type MOS transistor MN702 is output as the output signal SOUT. The P-type MOS transistor MP702 has a gate connected to a signal line that supplies the reference voltage GND, and a back gate connected to a signal line that supplies the power supply voltage VDD. The N-type MOS transistor MN702 has a gate connected to a signal line that supplies the power supply voltage VDD, and a back gate connected to a signal line that supplies the reference voltage GND. The circuit shown in FIG. 7B outputs a signal having a low voltage VL close to the reference voltage GND as the output signal SOUT.
　以上のように、レイアウト及び配線の形状は同じであるが耐圧が異なるトランジスタを用いることで、レイアウトから回路図を読み取るだけでは動作を再現することができず、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。また、第７の実施形態における信号出力回路は、構成するトランジスタ数が少なく、半導体チップ上の自動配置配線エリアの中に、より多数の信号出力回路を搭載することが可能となる。したがって、リバースエンジニアリングによる半導体装置の再現をさらに困難にすることができる。 As described above, by using transistors with the same layout and wiring shapes but different breakdown voltages, the operation cannot be reproduced simply by reading the circuit diagram from the layout, and it is difficult to reproduce the semiconductor device by reverse engineering. Can be. Further, the signal output circuit according to the seventh embodiment has a small number of transistors, and a larger number of signal output circuits can be mounted in the automatic placement and wiring area on the semiconductor chip. Therefore, the reproduction of the semiconductor device by reverse engineering can be made more difficult.
　なお、前述した第１～第７の実施形態を適宜組み合わせた実施形態も可能であり、それらの実施形態も本発明の実施形態に含まれる。 It should be noted that embodiments in which the first to seventh embodiments described above are appropriately combined are possible, and these embodiments are also included in the embodiments of the present invention.
（その他の実施形態）
　図８は、本実施形態における半導体装置の適用例を示す図である。図８において、１００は、本実施形態における半導体装置を含む半導体チップである。半導体チップ１００において、各種の論理処理を行う論理処理回路部１１０に対して、複数個の信号出力回路１２０の出力が接続される。論理処理回路部１１０は、信号出力回路１２０の出力を用いて一部又は全部の論理処理を行うことで、論理処理回路部１１０における入力と出力との関係は、信号出力回路１２０の出力状態にも依存する。前述したように、リバースエンジニアリングにより本実施形態における信号出力回路１２０の出力状態を判明することは困難であり、論理処理回路部１１０における入力と出力との関係を解析することも困難となり、半導体チップの不正コピー等を防止することが可能となる。 (Other embodiments)
FIG. 8 is a diagram illustrating an application example of the semiconductor device in the present embodiment. In FIG. 8, reference numeral 100 denotes a semiconductor chip including the semiconductor device according to the present embodiment. In the semiconductor chip 100, outputs of a plurality of signal output circuits 120 are connected to a logic processing circuit unit 110 that performs various logic processes. The logic processing circuit unit 110 performs a part or all of the logic processing using the output of the signal output circuit 120, so that the relationship between the input and output in the logic processing circuit unit 110 is the output state of the signal output circuit 120. Also depends. As described above, it is difficult to determine the output state of the signal output circuit 120 in this embodiment by reverse engineering, and it becomes difficult to analyze the relationship between the input and output in the logic processing circuit unit 110, and the semiconductor chip. It is possible to prevent unauthorized copying of the file.
　なお、前記実施形態は、何れも本発明を実施するにあたっての具体化のほんの一例を示したものに過ぎず、これらによって本発明の技術的範囲が限定的に解釈されてはならないものである。すなわち、本発明はその技術思想、又はその主要な特徴から逸脱することなく、様々な形で実施することができる。 Note that each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
　これらの半導体装置によれば、リバースエンジニアリングによる半導体装置の再現を困難にすることができる。 According to these semiconductor devices, it is difficult to reproduce the semiconductor device by reverse engineering.

Claims (8)

  1. 　第１の電圧を供給する信号線と前記第１の電圧より低い第２の電圧を供給する信号線との間に直列に接続されるとともに、それぞれのゲートに所定の電圧が供給される第１のトランジスタ及び第２のトランジスタを有し、前記第１のトランジスタと前記第２のトランジスタの接続点の電圧を出力する、複数の第１の信号出力回路と、
    　前記第１の電圧を供給する信号線と前記第２の電圧を供給する信号線との間に直列に接続されるとともに、それぞれのゲートに所定の電圧が供給される第３のトランジスタ及び第４のトランジスタを有し、前記第３のトランジスタは前記第１のトランジスタと同じレイアウトで特性が異なり、前記第４のトランジスタは前記第２のトランジスタと同じレイアウトで特性が異なり、前記第３のトランジスタと前記第４のトランジスタの接続点の電圧を出力する、複数の第２の信号出力回路とを含むことを特徴とする半導体装置。     A first line is connected in series between a signal line for supplying a first voltage and a signal line for supplying a second voltage lower than the first voltage, and a predetermined voltage is supplied to each gate. A plurality of first signal output circuits that output a voltage at a connection point between the first transistor and the second transistor;
    A third transistor and a fourth transistor are connected in series between the signal line supplying the first voltage and the signal line supplying the second voltage, and a predetermined voltage is supplied to each gate. The third transistor has the same layout and different characteristics as the first transistor, the fourth transistor has the same layout and different characteristics as the second transistor, and the third transistor differs from the third transistor in characteristics. And a plurality of second signal output circuits for outputting a voltage at a connection point of the fourth transistor.
  2. 　前記第１のトランジスタ及び前記第３のトランジスタが前記第１の電圧を供給する信号線に接続されており、前記第１のトランジスタと前記第３のトランジスタとはしきい値電圧が異なり、前記第２のトランジスタと前記第４のトランジスタとはしきい値電圧が異なることを特徴とするを請求項１記載の半導体装置。 The first transistor and the third transistor are connected to a signal line that supplies the first voltage, and the first transistor and the third transistor have different threshold voltages, and the first transistor 2. The semiconductor device according to claim 1, wherein the second transistor and the fourth transistor have different threshold voltages.
  3. 　前記第１の電圧は電源電圧であり、
    　前記第２の電圧は基準電圧であり、
    　前記第１のトランジスタのしきい値電圧が前記電源電圧より高く、前記第１のトランジスタ及び前記第２のトランジスタが、ゲートが前記第１の電圧を供給する信号線に接続されるＮ型トランジスタである前記第１の信号出力回路と、
    　前記第４のトランジスタのしきい値電圧が前記電源電圧より高く、前記第３のトランジスタ及び前記第４のトランジスタが、ゲートが前記第１の電圧を供給する信号線に接続されるＮ型トランジスタである前記第２の信号出力回路とを含むことを特徴とする請求項２記載の半導体装置。     The first voltage is a power supply voltage;
    The second voltage is a reference voltage;
    The threshold voltage of the first transistor is higher than the power supply voltage, and the first transistor and the second transistor are N-type transistors whose gates are connected to a signal line that supplies the first voltage. The first signal output circuit;
    The threshold voltage of the fourth transistor is higher than the power supply voltage, and the third transistor and the fourth transistor are N-type transistors whose gates are connected to a signal line that supplies the first voltage. The semiconductor device according to claim 2, further comprising: the second signal output circuit.
  4. 　前記第１の電圧を供給する信号線と第３の電圧を供給する信号線との間にダイオード接続されたＮ型トランジスタを有し、
    　前記第１のトランジスタ及び前記第２のトランジスタが前記第３の電圧を供給する信号線と前記第２の電圧を供給する信号線との間に直列に接続され、
    　前記第３のトランジスタ及び前記第４のトランジスタが前記第３の電圧を供給する信号線と前記第２の電圧を供給する信号線との間に直列に接続されることを特徴とする請求項２又は３記載の半導体装置。     An N-type transistor diode-connected between the signal line supplying the first voltage and the signal line supplying the third voltage;
    The first transistor and the second transistor are connected in series between a signal line supplying the third voltage and a signal line supplying the second voltage;
    3. The third transistor and the fourth transistor are connected in series between a signal line that supplies the third voltage and a signal line that supplies the second voltage. Or the semiconductor device of 3.
  5. 　前記第１の電圧は電源電圧であり、
    　前記第２の電圧は基準電圧であり、
    　前記第１のトランジスタのしきい値電圧が（前記第２の電圧－前記第１の電圧）の値より低く、前記第１のトランジスタ及び前記第２のトランジスタが、ゲートが前記第２の電圧を供給する信号線に接続されるＰ型トランジスタである前記第１の信号出力回路と、
    　前記第４のトランジスタのしきい値電圧が（前記第２の電圧－前記第１の電圧）の値より低く、前記第３のトランジスタ及び前記第４のトランジスタが、ゲートが前記第２の電圧を供給する信号線に接続されるＰ型トランジスタである前記第２の信号出力回路とを含むことを特徴とする請求項２～４の何れか１項に記載の半導体装置。     The first voltage is a power supply voltage;
    The second voltage is a reference voltage;
    The threshold voltage of the first transistor is lower than the value of (the second voltage minus the first voltage), and the gates of the first transistor and the second transistor have the second voltage. The first signal output circuit which is a P-type transistor connected to a signal line to be supplied;
    The threshold voltage of the fourth transistor is lower than the value of (the second voltage minus the first voltage), and the third transistor and the fourth transistor have their gates set to the second voltage. 5. The semiconductor device according to claim 2, further comprising: a second signal output circuit which is a P-type transistor connected to a signal line to be supplied.
  6. 　前記第１のトランジスタ及び前記第２のトランジスタのそれぞれがダイオード接続された前記第１の信号出力回路と、
    　前記第３のトランジスタ及び前記第４のトランジスタのそれぞれがダイオード接続された前記第２の信号出力回路とを含むことを特徴とする請求項２～５の何れか１項に記載の半導体装置。     The first signal output circuit in which each of the first transistor and the second transistor is diode-connected;
    6. The semiconductor device according to claim 2, further comprising: the second signal output circuit in which each of the third transistor and the fourth transistor is diode-connected.
  7. 　前記第１のトランジスタがデプレッション型であり、前記第２のトランジスタがエンハンスメント型である前記第１の信号出力回路と、
    　前記第３のトランジスタがエンハンスメント型であり、前記第４のトランジスタがデプレッション型である前記第２の信号出力回路とを含むことを特徴とする請求項２～６の何れか１項に記載の半導体装置。     The first signal output circuit, wherein the first transistor is a depletion type, and the second transistor is an enhancement type;
    7. The semiconductor according to claim 2, further comprising: the second signal output circuit, wherein the third transistor is an enhancement type and the fourth transistor is a depletion type. apparatus.
  8. 　前記第１のトランジスタが高耐圧のトランジスタであり、前記第２のトランジスタが前記第１のトランジスタより耐圧が低い低耐圧のトランジスタである前記第１の信号出力回路と、
    　前記第３のトランジスタが前記低耐圧のトランジスタであり、前記第４のトランジスタが前記高耐圧のトランジスタである前記第２の信号出力回路とを含むことを特徴とする請求項２～７の何れか１項に記載の半導体装置。     The first signal output circuit, wherein the first transistor is a high-breakdown-voltage transistor, and the second transistor is a low-breakdown-voltage transistor whose breakdown voltage is lower than that of the first transistor;
    8. The second signal output circuit, wherein the third transistor is the low breakdown voltage transistor and the fourth transistor is the high breakdown voltage transistor. 2. A semiconductor device according to item 1.
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