CN111712911A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN111712911A
CN111712911A CN201980012774.7A CN201980012774A CN111712911A CN 111712911 A CN111712911 A CN 111712911A CN 201980012774 A CN201980012774 A CN 201980012774A CN 111712911 A CN111712911 A CN 111712911A
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transistor
voltage
type mos
signal line
signal
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长友春敏
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Kitagawa Sistek Co ltd
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Kitagawa Sistek Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
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Abstract

The semiconductor device includes: a plurality of 1 st signal output circuits having 1 st transistors (MN101, MN105) and 2 nd transistors (MN102, MN106) for outputting voltages at connection points of the two transistors, the 1 st transistors and the 2 nd transistors being connected in series between a signal line for supplying a power supply voltage and a signal line for supplying a reference voltage, and respective gates being supplied with a predetermined voltage; and a plurality of 2 nd signal output circuits having 3 rd transistors (MN103, MN107) and 4 th transistors (MN104, MN108) for outputting a voltage at a connection point of the two transistors, the 3 rd and 4 th transistors being connected in series between a signal line for supplying a power supply voltage and a signal line for supplying a reference voltage, and having respective gates supplied with a predetermined voltage, the 3 rd transistor being identical in layout but different in characteristics from the 1 st transistor, and the 4 th transistor being identical in layout but different in characteristics from the 2 nd transistor.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a protection technique for protecting a semiconductor device from reverse engineering.
Background
In recent years, improper reverse engineering of semiconductor devices has increased. As a method of reverse engineering, not only optical analysis from the surface of a chip on which a semiconductor device is mounted, but also the following techniques are used: the wiring layers are peeled off layer by layer and photographed, the acquired images are superimposed, and wiring information is extracted by a software tool to reproduce a circuit diagram.
Various methods for preventing reverse engineering have been proposed (see, for example, patent documents 1 to 9). In order to prevent reverse engineering, the following methods have been proposed: for example, by devising a wiring layer or changing characteristics of a transistor or connection information using a diffusion layer or a bulk (bulk) which is lower than the wiring layer, a function cannot be reproduced only by reading the wiring layer. In addition, for example, patent document 1 proposes the following technique: a transistor is used with a gate in a floating state, and a signal is generated by using a difference in output voltage due to a characteristic variation of the transistor, so that it is difficult to reproduce a semiconductor device by reverse engineering.
However, the technique described in patent document 1 has the following problems. Since the gate is in a floating state, unnecessary consumption current flows from the power supply voltage to the ground, and if noise enters due to crosstalk or the like, voltage fluctuation occurs, and the operation and the consumption current become unstable. Further, since the output voltages generated by the plurality of transistors are not binary voltages but continuous analog values, a comparator receiving the output voltages is required to have high-precision analog characteristics, and the consumption current and the size increase. Due to such restrictions on the current consumption and size, the number of chips that can be mounted on one chip is restricted. In addition, other methods for preventing reverse engineering have the following problems: special processes are required, process development time and cost increase.
Documents of the prior art
Patent document
Patent document 1: specification of U.S. Pat. No. 9437555
Patent document 2: japanese laid-open patent publication No. 6-163539
Patent document 3: japanese laid-open patent publication No. 9-92727
Patent document 4: specification of U.S. Pat. No. 6117762
Patent document 5: specification of U.S. Pat. No. 6979606
Patent document 6: specification of U.S. Pat. No. 7128271
Patent document 7: specification of U.S. Pat. No. 9337156
Patent document 8: japanese Kokai publication Hei-2004-518273
Patent document 9: japanese patent laid-open No. 2014-135386
Disclosure of Invention
Problems to be solved by the invention
An object of the present invention is to provide a semiconductor device including: making it difficult to reproduce the semiconductor device by reverse engineering.
Means for solving the problems
A semiconductor device according to the present invention is characterized by comprising: a plurality of 1 st signal output circuits each having a 1 st transistor and a 2 nd transistor and outputting a voltage at a connection point between the 1 st transistor and the 2 nd transistor, wherein the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying a 1 st voltage and a signal line supplying a 2 nd voltage lower than the 1 st voltage, and a gate of each of the 1 st transistor and the 2 nd transistor is supplied with a predetermined voltage; and a plurality of 2 nd signal output circuits each having a 3 rd transistor and a 4 th transistor, each of the 3 rd transistor and the 4 th transistor being connected in series between a signal line for supplying the 1 st voltage and a signal line for supplying the 2 nd voltage, and each of the 3 rd transistor and the 4 th transistor having a gate to which a predetermined voltage is supplied, wherein the 3 rd transistor and the 1 st transistor have the same layout but different characteristics, and the 4 th transistor and the 2 nd transistor have the same layout but different characteristics.
Effects of the invention
According to the present invention, the following semiconductor device can be provided: making it difficult to reproduce the semiconductor device by reverse engineering.
Drawings
Fig. 1A is a diagram illustrating an example of a semiconductor device according to embodiment 1.
Fig. 1B is a diagram illustrating an example of the semiconductor device according to embodiment 1.
Fig. 2A is a diagram showing an example of the semiconductor device according to embodiment 2.
Fig. 2B is a diagram showing an example of the semiconductor device according to embodiment 2.
Fig. 3A is a diagram showing an example of the semiconductor device according to embodiment 3.
Fig. 3B is a diagram showing an example of the semiconductor device according to embodiment 3.
Fig. 4A is a diagram showing an example of the semiconductor device according to embodiment 4.
Fig. 4B is a diagram showing an example of the semiconductor device according to embodiment 4.
Fig. 5A is a diagram showing an example of the semiconductor device according to embodiment 5.
Fig. 5B is a diagram showing an example of the semiconductor device according to embodiment 5.
Fig. 6A is a diagram showing an example of the semiconductor device according to embodiment 6.
Fig. 6B is a diagram showing an example of the semiconductor device according to embodiment 6.
Fig. 7A is a diagram showing an example of the semiconductor device according to embodiment 7.
Fig. 7B is a diagram showing an example of the semiconductor device according to embodiment 7.
Fig. 8 is a diagram showing an application example of the semiconductor device of the present embodiment.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(embodiment 1)
Embodiment 1 of the present invention will be explained. The semiconductor device according to embodiment 1 includes a plurality of signal output circuits as shown in fig. 1A and 1B. Fig. 1A and 1B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 1. The 1 st signal output circuit shown in fig. 1A has N-type MOS transistors MN101, MN102, MN103, MN104, and an amplification section 11.
Between a signal line to which a power supply voltage VDD is supplied and a signal line to which a reference voltage GND is supplied, two N-type MOS transistors MN101 and MN102 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the two N-type MOS transistors MN101 and MN102 is output as a signal SINA. In the N-type MOS transistors MN101 and MN102, a gate is connected to a signal line to which the power supply voltage VDD is supplied, and a back gate is connected to a signal line to which the reference voltage GND is supplied.
Further, between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, two N-type MOS transistors MN103 and MN104 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and the voltage at the connection point of the two N-type MOS transistors MN103 and MN104 is output as a signal SINB. In the N-type MOS transistors MN103 and MN104, a gate is connected to a signal line to which the power supply voltage VDD is supplied, and a back gate is connected to a signal line to which the reference voltage GND is supplied.
The amplifying unit 11 receives a signal SINA at an input terminal INA, and receives a signal SINB at an input terminal INB. The amplification unit 11 outputs a signal of '1' at the level of the power supply voltage VDD or a signal of '0' at the level of the reference voltage GND as an output signal SOUT from an output terminal OUT in accordance with the voltages of the input signal SINA and the signal SINB. In the present embodiment, the amplifying unit 11 is realized by a level shifter (level shifter circuit) having, as an example, P-type MOS transistors MP11 and MP12 and N-type MOS transistors MN11 and MN 12. By using a level shifter (level shift circuit) as the amplifier 11, an excessive through current can be prevented from flowing, and the consumption current can be reduced.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, a P-type MOS transistor MP11 and an N-type MOS transistor MN11 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied. Further, between the signal line to which the power supply voltage VDD is supplied and the signal line to which the reference voltage GND is supplied, a P-type MOS transistor MP12 and an N-type MOS transistor MN12 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied.
A signal SINA is input to the gate of the N-type MOS transistor MN11, and a signal SINB is input to the gate of the N-type MOS transistor MN 12. The gate of the P-type MOS transistor MP11 is connected to the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12, and the gate of the P-type MOS transistor MP12 is connected to the connection point between the P-type MOS transistor MP11 and the N-type MOS transistor MN 11. The voltage at the connection point between the P-type MOS transistor MP12 and the N-type MOS transistor MN12 is output as the output signal SOUT.
Here, the threshold voltages of N-type MOS transistors MN101 and MN104 are the same voltage and have a value higher than power supply voltage VDD. The threshold voltages of N-type MOS transistors MN102 and MN103 are the same voltage, and are normal (standard) threshold voltages (for example, approximately + 0.5V). The control of the threshold voltage of the transistor can be achieved by channel implantation doping control for changing the doping amount to the channel, gate oxide film thickness control for changing the thickness of the gate oxide film, back gate voltage control for utilizing the back gate effect, or the like. In the drawings, a component denoted by (HVT) is a transistor having a high threshold voltage (the same applies to the following embodiments).
The layout of the two N-type MOS transistors MN101 and MN102 and the layout of the two N-type MOS transistors MN103 and MN104 have the same shape including the wiring related thereto. That is, the N-type MOS transistors MN101 and MN103 have the same layout and wiring shapes, and the N-type MOS transistors MN102 and MN104 have the same layout and wiring shapes. For example, the gate lengths and gate widths of the N-type MOS transistors MN101, MN103 are the same, and the gate lengths and gate widths of the N-type MOS transistors MN102, MN104 are the same.
Since the N-type MOS transistors MN101 and MN103 have the same layout and wiring shapes as described above, it is not possible to distinguish which transistor has a threshold higher than the power supply voltage VDD in appearance. Similarly, since the N-type MOS transistors MN102 and MN104 have the same layout and wiring shapes, it is not possible to visually distinguish which transistor has a threshold higher than the power supply voltage VDD.
In the circuit connected as shown in fig. 1A, N-type MOS transistors MN101 and MN104 having a threshold voltage higher than power supply voltage VDD are in an off state, and N-type MOS transistors MN102 and MN103 having a normal (standard) threshold voltage are in an on state. Therefore, the voltage (signal SINA) at the connection point between N-type MOS transistors MN101 and MN102 is substantially the reference voltage GND, and the voltage (signal SINB) at the connection point between N-type MOS transistors MN103 and MN104 is lower than the power supply voltage VDD by the threshold VTH of N-type MOS transistor MN103 (VDD-VTH).
At this time, in the amplifying section (level shifter) 11, the P-type MOS transistor MP11 and the N-type MOS transistor MN12 are in an on state, and the P-type MOS transistor MP12 and the N-type MOS transistor MN11 are in an off state. Therefore, the circuit shown in fig. 1A outputs a '0' signal of the reference voltage GND level as the output signal SOUT.
Next, the 2 nd signal output circuit shown in fig. 1B has N-type MOS transistors MN105, MN106, MN107, MN108, and an amplification section 11. In fig. 1B, the same components as those shown in fig. 1A are denoted by the same reference numerals, and redundant description thereof is omitted.
Between a signal line to which a power supply voltage VDD is supplied and a signal line to which a reference voltage GND is supplied, two N-type MOS transistors MN105 and MN106 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the two N-type MOS transistors MN105 and MN106 is output as a signal SINA. In the N-type MOS transistors MN105 and MN106, a gate is connected to a signal line to which the power supply voltage VDD is supplied, and a back gate is connected to a signal line to which the reference voltage GND is supplied.
Further, between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, two N-type MOS transistors MN107 and MN108 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and the voltage at the connection point of the two N-type MOS transistors MN107 and MN108 is output as a signal SINB. In the N-type MOS transistors MN107 and MN108, a gate is connected to a signal line to which the power supply voltage VDD is supplied, and a back gate is connected to a signal line to which the reference voltage GND is supplied.
Here, the threshold voltages of N-type MOS transistors MN106 and MN107 are the same voltage and have a value higher than power supply voltage VDD. The threshold voltages of N-type MOS transistors MN105 and MN108 are the same voltage, and are normal (standard) threshold voltages. That is, regarding the two N-type MOS transistors outputting the signal SINA and the two N-type MOS transistors outputting the signal SINB, the arrangement of the transistors is replaced with each other, and the circuit configuration of the output signals SINA, SINB is opposite to the circuit configuration shown in fig. 1A.
The layout of the two N-type MOS transistors MN105 and MN106 and the layout of the two N-type MOS transistors MN107 and MN108 have the same shape including the wiring related thereto. The N-type MOS transistors MN105 and MN107 have the same layout and wiring shapes, and the N-type MOS transistors MN106 and MN108 have the same layout and wiring shapes. Therefore, it is not possible to visually distinguish which of the N-type MOS transistors MN105 and MN107 is a transistor having a threshold value higher than the power supply voltage VDD, and it is not possible to visually distinguish which of the N-type MOS transistors MN106 and MN108 is a transistor having a threshold value higher than the power supply voltage VDD.
In the circuit connected as shown in fig. 1B, N-type MOS transistors MN106 and MN107 having a threshold voltage higher than power supply voltage VDD are in an off state, and N-type MOS transistors MN105 and MN108 having a normal (standard) threshold voltage are in an on state. Therefore, the voltage (signal SINA) at the connection point of N-type MOS transistors MN105 and MN106 is lower than power supply voltage VDD by (VDD-VTH) the threshold VTH of N-type MOS transistor MN105, and the voltage (signal SINB) at the connection point of N-type MOS transistors MN107 and MN108 is substantially equal to reference voltage GND.
At this time, in the amplifying section (level shifter) 11, the P-type MOS transistor MP11 and the N-type MOS transistor MN12 are in an off state, and the P-type MOS transistor MP12 and the N-type MOS transistor MN11 are in an on state. Accordingly, the circuit shown in fig. 1B outputs a '1' signal of the level of the power supply voltage VDD as the output signal SOUT.
As described above, transistors having different characteristics are used, two signal output circuits which realize different functions although the layout and wiring shapes are the same are used, and the level of an output signal is determined based on signals from the two signal output circuits. Thus, the operation cannot be reproduced only by reading the circuit diagram from the layout, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering.
As shown in fig. 1A and 1B, the size can be realized by 8 transistors equivalent to a four-input NAND, and a plurality of signal output circuits can be mounted in an automatically arranged wiring region on a semiconductor chip. When a plurality of signal output circuits according to the present embodiment are mounted on a semiconductor chip, it is necessary to know all functions (output states) of the signal output circuits in reverse engineering, and it is not realistic to analyze all the mounted signal output circuits in a method using FIB or a probe.
Even if the circuit diagram of the transistor stage in the automatic layout wiring area is known by peeling and imaging layer by layer, the output state of each signal output circuit is unclear. As a method of determining the output state of each signal output circuit, it is conceivable to assign outputs of '0' or '1' to all signal output circuits and perform simulation and estimation, but it is necessary to perform simulation of 2-power-of-the-number of signal output circuits. For example, when 100 signal output circuits according to the present embodiment are mounted, the number is 2100＝1.26×1030Such astronomical numbers are very difficult to infer by simulation and can be made very largeIt is difficult to reproduce a semiconductor device by reverse engineering.
(embodiment 2)
Next, embodiment 2 of the present invention will be explained. In the semiconductor device according to embodiment 2, two N-type MOS transistors connected in series between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND in embodiment 1 are replaced with two P-type MOS transistors.
The semiconductor device according to embodiment 2 includes a plurality of signal output circuits as shown in fig. 2A and 2B. Fig. 2A and 2B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 2. The 1 st signal output circuit shown in fig. 2A includes P-type MOS transistors MP201, MP202, MP203, MP204, and an amplifier 21.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, two P-type MOS transistors MP201 and MP202 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the two P-type MOS transistors MP201 and MP202 is output as a signal SINA. In the P-type MOS transistors MP201 and MP202, the gate is connected to a signal line to which the reference voltage GND is supplied, and the back gate is connected to a signal line to which the power supply voltage VDD is supplied.
Further, between the signal line to which the power supply voltage VDD is supplied and the signal line to which the reference voltage GND is supplied, two P-type MOS transistors MP203 and MP204 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and the voltage at the connection point of the two P-type MOS transistors MP203 and MP204 is output as a signal SINB. In the P-type MOS transistors MP203 and MP204, the gate is connected to a signal line to which the reference voltage GND is supplied, and the back gate is connected to a signal line to which the power supply voltage VDD is supplied.
The amplifier 21 receives a signal SINA at an input terminal INA, and receives a signal SINB at an input terminal INB. The amplifier 21 outputs a signal of '1' at the level of the power supply voltage VDD or a signal of '0' at the level of the reference voltage GND as an output signal SOUT from an output terminal OUT in accordance with the voltages of the input signal SINA and the signal SINB. In this embodiment, the function of the amplifying unit 21 is realized by a level shifter (level shifter circuit) having, for example, P-type MOS transistors MP21 and MP22 and N-type MOS transistors MN21 and MN 22.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, a P-type MOS transistor MP21 and an N-type MOS transistor MN21 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied. Further, between the signal line to which the power supply voltage VDD is supplied and the signal line to which the reference voltage GND is supplied, a P-type MOS transistor MP22 and an N-type MOS transistor MN22 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied.
The signal SINA is input to the gate of the P-type MOS transistor MP21, and the signal SINB is input to the gate of the P-type MOS transistor MP 22. The gate of the N-type MOS transistor MN21 is connected to the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22, and the gate of the N-type MOS transistor MN22 is connected to the connection point between the P-type MOS transistor MP21 and the N-type MOS transistor MN 21. The voltage at the connection point between the P-type MOS transistor MP22 and the N-type MOS transistor MN22 is output as the output signal SOUT.
Here, the threshold voltages of the P-type MOS transistors MP201 and MP204 are the same voltage and are lower than the value of (reference voltage GND — power supply voltage VDD). The threshold voltages of P-type MOS transistors MP202 and MP203 are the same voltage, and are normal (standard) threshold voltages. The control of the threshold voltage of the transistor can be achieved by channel implantation doping control, gate oxide film thickness control, back gate voltage control, and the like, as in embodiment 1.
The layout of the two P-type MOS transistors MP201 and MP202 and the layout of the two P-type MOS transistors MP203 and MP204 have the same shape including the wiring lines. That is, the layout and wiring shapes of the P-type MOS transistors MP201 and MP203 are the same, and the layout and wiring shapes of the P-type MOS transistors MP202 and MP204 are the same. For example, the gate lengths and gate widths of the P-type MOS transistors MP201 and MP203 are the same, and the gate lengths and gate widths of the P-type MOS transistors MP202 and MP204 are the same.
In this way, since the layout and wiring shapes of the P-type MOS transistors MP201 and MP203 are made the same, it is difficult to distinguish which transistor has a lower threshold value than the value (reference voltage GND — power supply voltage VDD) in terms of appearance. Similarly, since the P-type MOS transistors MP202 and MP204 have the same layout and wiring shapes, it is not possible to distinguish which transistor has a lower threshold value than the value (reference voltage GND — power supply voltage VDD) in terms of appearance.
In the circuit connected as shown in fig. 2A, P-type MOS transistors MP201 and MP204 having a lower threshold voltage than (reference voltage GND — power supply voltage VDD) are off, and P-type MOS transistors MP202 and MP203 having normal (standard) threshold voltages are on. Therefore, the voltage (signal SINA) at the connection point of P-type MOS transistors MP201 and MP202 is higher than the reference voltage GND by the absolute value of the threshold VTH of P-type MOS transistor MP202 (GND + | VTH |), and the voltage (signal SINB) at the connection point of P-type MOS transistors MP203 and MP204 is substantially the power supply voltage VDD.
At this time, in the amplifying section (level shifter) 21, the P-type MOS transistor MP21 and the N-type MOS transistor MN22 are in an on state, and the P-type MOS transistor MP22 and the N-type MOS transistor MN21 are in an off state. Therefore, the circuit shown in fig. 2A outputs a '0' signal of the reference voltage GND level as the output signal SOUT.
Next, the 2 nd signal output circuit shown in fig. 2B has P-type MOS transistors MP205, MP206, MP207, MP208 and an amplifying section 21. In fig. 2B, the same components as those shown in fig. 2A are denoted by the same reference numerals, and redundant description thereof is omitted.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, two P-type MOS transistors MP205 and MP206 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the two P-type MOS transistors MP205 and MP206 is output as a signal SINA. In the P-type MOS transistors MP205 and MP206, the gate is connected to a signal line to which the reference voltage GND is supplied, and the back gate is connected to a signal line to which the power supply voltage VDD is supplied.
Further, between the signal line to which the power supply voltage VDD is supplied and the signal line to which the reference voltage GND is supplied, two P-type MOS transistors MP207 and MP208 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and the voltage at the connection point of the two P-type MOS transistors MP207 and MP208 is output as a signal SINB. In the P-type MOS transistors MP207 and MP208, the gate is connected to a signal line to which the reference voltage GND is supplied, and the back gate is connected to a signal line to which the power supply voltage VDD is supplied.
Here, the threshold voltages of P-type MOS transistors MP206 and MP207 are the same voltage and are lower than the value of (reference voltage GND — power supply voltage VDD). The threshold voltages of P-type MOS transistors MP205 and MP208 are the same voltage, and are normal (standard) threshold voltages. That is, regarding the two P-type MOS transistors outputting the signal SINA and the two P-type MOS transistors outputting the signal SINB, the arrangement of the transistors is replaced with each other, and the circuit configuration of the output signals SINA, SINB is opposite to the circuit configuration shown in fig. 2A.
The layout of the two P-type MOS transistors MP205 and MP206 and the layout of the two P-type MOS transistors MP207 and MP208 have the same shape including the wiring lines. The P-type MOS transistors MP205 and MP207 have the same layout and wiring shapes, and the P-type MOS transistors MP206 and MP208 have the same layout and wiring shapes. Therefore, it is not possible to distinguish which transistor having a lower threshold value than the value (reference voltage GND — power supply voltage VDD) is in the appearance of the P-type MOS transistors MP205 and MP207, and which transistor having a lower threshold value than the value (reference voltage GND — power supply voltage VDD) is in the appearance of the P-type MOS transistors MP206 and MP 208.
In the circuit connected as shown in fig. 2B, P-type MOS transistors MP206 and MP207 having a lower threshold voltage than the value (reference voltage GND — power supply voltage VDD) are off, and P-type MOS transistors MP205 and MP208 having a normal (normal) threshold voltage are on. Therefore, the voltage (signal SINA) at the connection point of the P-type MOS transistors MP205 and MP206 is substantially the power supply voltage VDD, and the voltage (signal SINB) at the connection point of the P-type MOS transistors MP207 and MP208 is higher than the reference voltage GND by the absolute value of the threshold VTH of the P-type MOS transistor MP208 (GND + | VTH |).
At this time, in the amplifying section (level shifter) 21, the P-type MOS transistor MP21 and the N-type MOS transistor MN22 are in an off state, and the P-type MOS transistor MP22 and the N-type MOS transistor MN21 are in an on state. Accordingly, the circuit shown in fig. 2B outputs a '1' signal of the level of the power supply voltage VDD as the output signal SOUT.
As described above, also in embodiment 2 using a P-type MOS transistor instead of an N-type MOS transistor, the same effects as those in embodiment 1 can be obtained, and it is possible to make it difficult to reproduce a semiconductor device by reverse engineering.
(embodiment 3)
Next, embodiment 3 of the present invention will be explained. In embodiment 3, the two N-type MOS transistors connected in series between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage GND in embodiment 1 are connected in series between the signal line supplying the voltage lower than the power supply voltage VDD and the signal line supplying the reference voltage GND.
The semiconductor device according to embodiment 3 includes a plurality of signal output circuits as shown in fig. 3A and 3B. Fig. 3A and 3B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 3. The 1 st signal output circuit shown in fig. 3A has N-type MOS transistors MN301, MN302, MN303, MN304, MN305, and an amplification section 11.
The N-type transistor MN305 is a transistor having a normal (standard) threshold voltage, and is connected between a signal line supplying the power supply voltage VDD and a signal line supplying a voltage lower than the power supply voltage VDD, and the gate of the N-type transistor MN305 is connected to the signal line supplying the power supply voltage VDD. That is, the N-type transistor MN305 is diode-connected to a signal line supplying the power supply voltage VDD. Therefore, the voltage of the signal line supplying a voltage lower than the power supply voltage VDD is lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN305 (VDD-VTH).
The N-type MOS transistors MN301, MN302, MN303, MN304, and the amplifying section 11 are the same as the N-type MOS transistors MN101, MN102, MN103, MN104, and the amplifying section 11 shown in fig. 1A, respectively.
However, in this embodiment, two N-type MOS transistors MN301 and MN302 are connected in series between a signal line to which a voltage (VDD-VTH) is supplied and a signal line to which a reference voltage GND is supplied. Similarly, two N-type MOS transistors MN303, MN304 are connected in series between a signal line supplying a voltage (VDD-VTH) and a signal line supplying a reference voltage GND. In addition, the gates of the N-type MOS transistors MN301, MN302, MN303, and MN304 are connected to a signal line for supplying a voltage (VDD-VTH).
In the circuit connected as shown in fig. 3A, the N-type MOS transistors MN301 and MN304 are in an off state, and the N-type MOS transistors MN302 and MN303 are in an on state. Therefore, the voltage (signal SINA) at the connection point of the N-type MOS transistors MN301 and MN302 is substantially the reference voltage GND, and the voltage (signal SINB) at the connection point of the N-type MOS transistors MN303 and MN304 is lower than the voltage (VDD-VTH) by the threshold VTH of the N-type MOS transistor MN303 (VDD-2 VTH). Therefore, the circuit shown in fig. 3A outputs a '0' signal of the reference voltage GND level as the output signal SOUT.
Next, the 2 nd signal output circuit shown in fig. 3B has N-type MOS transistors MN306, MN307, MN308, MN309, MN310, and an amplifying section 11.
The N-type transistor MN310 is a transistor having a normal (standard) threshold voltage, and is connected between a signal line supplying the power supply voltage VDD and a signal line supplying a voltage lower than the power supply voltage VDD, and the gate of the N-type transistor MN310 is connected to the signal line supplying the power supply voltage VDD. That is, the N-type transistor MN310 is diode-connected to a signal line supplying the power supply voltage VDD. Therefore, the voltage of the signal line supplying a voltage lower than the power supply voltage VDD is lower than the power supply voltage VDD by the threshold voltage VTH of the N-type transistor MN310 (VDD-VTH).
The N-type MOS transistors MN306, MN307, MN308, MN309, and the amplification section 11 are the same as the N-type MOS transistors MN105, MN106, MN107, MN108, and the amplification section 11 shown in fig. 1B, respectively.
However, in the present embodiment, two N-type MOS transistors MN306 and MN307 are connected in series between a signal line supplying a voltage (VDD-VTH) and a signal line supplying a reference voltage GND. Similarly, two N-type MOS transistors MN308, MN309 are connected in series between a signal line supplying a voltage (VDD-VTH) and a signal line supplying a reference voltage GND. In addition, the gates of the N-type MOS transistors MN306, MN307, MN308, and MN309 are connected to a signal line supplying a voltage (VDD-VTH).
In the circuit connected as shown in fig. 3B, N-type MOS transistors MN307 and MN308 are in an off state, and N-type MOS transistors MN306 and MN309 are in an on state. Therefore, the voltage (signal SINA) at the connection point of N-type MOS transistors MN306 and MN307 is (VDD-2VTH) lower than the voltage (VDD-VTH) by the threshold VTH of N-type MOS transistor MN306, and the voltage (signal SINB) at the connection point of N-type MOS transistors MN308 and MN309 becomes substantially the reference voltage GND. Accordingly, the circuit shown in fig. 3B outputs a '1' signal of the level of the power supply voltage VDD as the output signal SOUT.
As described above, in embodiment 3, in which an N-type MOS transistor connected to the power supply voltage VDD side in a diode manner is provided and two N-type MOS transistors are connected in series between a signal line for supplying a voltage lower than the power supply voltage VDD obtained by the N-type MOS transistor and a signal line for supplying the reference voltage GND, the same effect as that of embodiment 1 can be obtained, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering. In addition, embodiment 3 is equivalent to the case where the power supply voltage is down-regulated in embodiment 1, and therefore power consumption can be reduced.
(embodiment 4)
Next, embodiment 4 of the present invention will be explained.
The semiconductor device according to embodiment 4 includes a plurality of signal output circuits as shown in fig. 4A and 4B. Fig. 4A and 4B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 4. The 1 st signal output circuit shown in fig. 4A has N-type MOS transistors MN401, MN402, MN403, MN404, and an amplifying section 11. The N-type MOS transistors MN401, MN402, MN403, MN404, and the amplifying portion 11 are the same as the N-type MOS transistors MN101, MN102, MN103, MN104, and the amplifying portion 11 shown in fig. 1A, respectively.
However, in the present embodiment, the gate of N-type MOS transistor MN401 is connected to a signal line to which voltage VDD is supplied, and the gate of N-type MOS transistor MN402 is connected to a connection point between two N-type MOS transistors MN401 and MN 402. The gate of the N-type MOS transistor MN403 is connected to a signal line for supplying the voltage VDD, and the gate of the N-type MOS transistor MN404 is connected to a connection point between the two N-type MOS transistors MN403 and MN 404. That is, N-type MOS transistors MN401, MN402, MN403, and MN404 are diode-connected.
In the circuit connected as shown in fig. 4A, N-type MOS transistors MN401 and MN404 are in an off state, and N-type MOS transistors MN402 and MN403 are in an on state. Therefore, the voltage (signal SINA) at the connection point between N-type MOS transistors MN401 and MN402 is (GND + VTH) higher than the reference voltage GND by the threshold VTH of N-type MOS transistor MN402, and the voltage (signal SINB) at the connection point between N-type MOS transistors MN403 and MN404 is (VDD-VTH) lower than the power supply voltage VDD by the threshold VTH of N-type MOS transistor MN 403. Therefore, the circuit shown in fig. 4A outputs a '0' signal of the reference voltage GND level as the output signal SOUT.
Next, the 2 nd signal output circuit shown in fig. 4B has N-type MOS transistors MN405, MN406, MN407, MN408, and an amplification section 11. The N-type MOS transistors MN405, MN406, MN407, MN408, and the amplifying section 11 are the same as the N-type MOS transistors MN105, MN106, MN107, MN108, and the amplifying section 11 shown in fig. 1B, respectively.
However, in the present embodiment, the gate of the N-type MOS transistor MN405 is connected to a signal line to which the voltage VDD is supplied, and the gate of the N-type MOS transistor MN406 is connected to a connection point between the two N-type MOS transistors MN405 and MN 406. The gate of the N-type MOS transistor MN407 is connected to a signal line for supplying the voltage VDD, and the gate of the N-type MOS transistor MN408 is connected to a connection point between the two N-type MOS transistors MN407 and MN 408. That is, the N-type MOS transistors MN405, MN406, MN407, and MN408 are diode-connected.
In the circuit connected as shown in fig. 4B, N-type MOS transistors MN406 and MN407 are off, and N-type MOS transistors MN405 and MN408 are on. Therefore, the voltage (signal SINA) at the connection point between N-type MOS transistors MN405 and MN406 is lower than power supply voltage VDD by (VDD-VTH) the threshold VTH of N-type MOS transistor MN405, and the voltage (signal SINB) at the connection point between N-type MOS transistors MN407 and MN408 is higher than reference voltage GND by (GND + VTH) the threshold VTH of N-type MOS transistor MN 408. Accordingly, the circuit shown in fig. 4B outputs a '1' signal of the level of the power supply voltage VDD as the output signal SOUT.
According to embodiment 4 described above, the same effects as those of embodiment 1 can be obtained, and it is possible to make it difficult to reproduce a semiconductor device by reverse engineering and to reduce power consumption.
In addition, although the above-described embodiments 3 and 4 have been described using N-type MOS transistors, they may be implemented using P-type MOS transistors. In this case, the connection may be changed based on embodiment 2, and the following similar effects can be obtained: it is possible to make it difficult to reproduce the semiconductor device by reverse engineering and to reduce power consumption.
(embodiment 5)
Next, embodiment 5 of the present invention will be explained.
The semiconductor device according to embodiment 5 includes a plurality of signal output circuits as shown in fig. 5A and 5B. Fig. 5A and 5B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 5. The 1 st signal output circuit shown in fig. 5A has a depletion type N-type MOS transistor MN501 and an enhancement type N-type MOS transistor MN 502.
Between a signal line to which a power supply voltage VDD is supplied and a signal line to which a reference voltage GND is supplied, N-type MOS transistors MN501 and MN502 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the N-type MOS transistors MN501 and MN502 is output as an output signal SOUT. The gate of the N-type MOS transistor MN501 is connected to a connection point of the N-type MOS transistors MN501 and MN502, and the gate of the N-type MOS transistor MN502 is connected to a signal line for supplying the reference voltage GND. That is, the N-type MOS transistors MN501 and MN502 are diode-connected. The back gates of the N-type MOS transistors MN501 and MN502 are connected to a signal line for supplying the reference voltage GND.
In the circuit connected as shown in fig. 5A, the depletion type N-type MOS transistor MN501 is in an on state, and the enhancement type N-type MOS transistor MN502 is in an off state. Accordingly, the circuit shown in fig. 5A outputs a '1' signal of the level of the power supply voltage VDD as the output signal SOUT.
Next, the 2 nd signal output circuit shown in fig. 5B has an N-type MOS transistor MN503 of an enhancement type and an N-type MOS transistor MN504 of a depletion type. Here, the layout and wiring shape of the N-type MOS transistor MN503 is the same as that of the N-type MOS transistor MN501, and the layout and wiring shape of the N-type MOS transistor MN504 is the same as that of the N-type MOS transistor MN 502.
Between a signal line to which a power supply voltage VDD is supplied and a signal line to which a reference voltage GND is supplied, N-type MOS transistors MN503 and MN504 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the N-type MOS transistors MN503 and MN504 is output as an output signal SOUT. The gate of the N-type MOS transistor MN503 is connected to a connection point of the N-type MOS transistors MN503 and MN504, and the gate of the N-type MOS transistor MN504 is connected to a signal line for supplying the reference voltage GND. That is, the N-type MOS transistors MN503 and MN504 are diode-connected. The back gates of the N-type MOS transistors MN503 and MN504 are connected to a signal line for supplying the reference voltage GND.
In the circuit shown in fig. 5B, the depletion type N-type MOS transistor MN504 is in an on state, and the enhancement type N-type MOS transistor MN503 is in an off state. Therefore, the circuit shown in fig. 5B outputs a '0' signal of the reference voltage GND level as the output signal SOUT. In the signal output circuit included in the semiconductor device according to embodiment 5, the voltage at the connection point between the N-type MOS transistors MN501 and MN502 and the voltage at the connection point between the N-type MOS transistors MN503 and MN504 are at the power supply voltage VDD level or the reference voltage GND level, and therefore, an amplifier unit is not required.
As described above, by using transistors having the same layout and wiring shapes but different characteristics, the operation cannot be reproduced only by reading the circuit diagram from the layout, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering. In addition, since the semiconductor device according to embodiment 5 has a signal output circuit having a smaller number of transistors and no amplifier unit than the signal output circuit shown in fig. 1A and 1B, the area required for mounting can be reduced, and a larger number of signal output circuits can be mounted in the self-layout wiring region on the semiconductor chip. Therefore, it can be made difficult to reproduce the semiconductor device by reverse engineering. In addition, since almost no current flows, power consumption can be reduced.
(embodiment 6)
Next, embodiment 6 of the present invention will be explained. In embodiment 6, a P-type MOS transistor is used instead of the N-type MOS transistor in embodiment 5.
The semiconductor device according to embodiment 6 includes a plurality of signal output circuits as shown in fig. 6A and 6B. Fig. 6A and 6B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 6. The 1 st signal output circuit shown in fig. 6A has a depletion type P-type MOS transistor MP601 and an enhancement type P-type MOS transistor MP 602.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, P-type MOS transistors MP601 and MP602 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the P-type MOS transistors MP601 and MP602 is output as an output signal SOUT. The gate of the P-type MOS transistor MP601 is connected to a signal line for supplying the power supply voltage VDD, and the gate of the P-type MOS transistor MP602 is connected to a connection point of the P-type MOS transistors MP601 and MP 602. That is, the P-type MOS transistors MP601 and MP602 are diode-connected. Back gates of the P-type MOS transistors MP601 and MP602 are connected to a signal line for supplying the power supply voltage VDD.
In the circuit connected as shown in fig. 6A, the depletion P-type MOS transistor MP601 is in an on state, and the enhancement P-type MOS transistor MP602 is in an off state. Accordingly, the circuit shown in fig. 6A outputs a '1' signal of the level of the power supply voltage VDD as the output signal SOUT.
Next, the 2 nd signal output circuit shown in fig. 6B has an enhancement type P-type MOS transistor MP603 and a depletion type P-type MOS transistor MP 604. Here, the layout and wiring shape of the P-type MOS transistor MP603 is the same as that of the P-type MOS transistor MP601, and the layout and wiring shape of the P-type MOS transistor MP604 is the same as that of the P-type MOS transistor MP 602.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, P-type MOS transistors MP603 and MP604 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the P-type MOS transistors MP603 and MP604 is output as an output signal SOUT. The gate of the P-type MOS transistor MP603 is connected to a signal line for supplying the power supply voltage VDD, and the gate of the P-type MOS transistor MP604 is connected to a connection point of the P-type MOS transistors MP603 and MP 604. That is, the P-type MOS transistors MP603 and MP604 are diode-connected. The back gates of P-type MOS transistors MP603 and MP604 are connected to a signal line for supplying power supply voltage VDD.
In the circuit connected as shown in fig. 6B, the depletion P-type MOS transistor MP604 is in an on state, and the enhancement P-type MOS transistor MP603 is in an off state. Therefore, the circuit shown in fig. 6B outputs a '0' signal of the reference voltage GND level as the output signal SOUT. In embodiment 6, the voltage at the connection point of the P-type MOS transistors MP601 and MP602 and the voltage at the connection point of the P-type MOS transistors MP603 and MP604 are at the power supply voltage VDD level or the reference voltage GND level, and therefore, an amplifier unit is not required.
As described above, also in embodiment 6 using a P-type MOS transistor instead of an N-type MOS transistor, the same effects as those in embodiment 5 can be obtained, and it is possible to make it difficult to reproduce a semiconductor device by reverse engineering and to reduce power consumption.
(7 th embodiment)
Next, embodiment 7 of the present invention will be explained.
The semiconductor device according to embodiment 7 includes a plurality of signal output circuits as shown in fig. 7A and 7B. Fig. 7A and 7B are diagrams illustrating an example of a signal output circuit included in the semiconductor device according to embodiment 7. The 1 st signal output circuit shown in fig. 7A has a P-type MOS transistor MP701 and an N-type MOS transistor MN 701. Here, the withstand voltage of the P-type MOS transistor MP701 is different from that of the N-type MOS transistor MN701, and in the example shown in fig. 7A, the N-type MOS transistor MN701 is a high withstand voltage transistor.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, a P-type MOS transistor MP701 and an N-type MOS transistor MN701 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point between the P-type MOS transistor MP701 and the N-type MOS transistor MN701 is output as an output signal SOUT. In the P-type MOS transistor MP701, a gate is connected to a signal line to which the reference voltage GND is supplied, and a back gate is connected to a signal line to which the power supply voltage VDD is supplied. In the N-type MOS transistor MN701, a gate is connected to a signal line to which the power supply voltage VDD is supplied, and a back gate is connected to a signal line to which the reference voltage GND is supplied. The circuit shown in fig. 7A outputs, as the output signal SOUT, a signal of a voltage VH, which is a high voltage close to the power supply voltage VDD.
Next, the 2 nd signal output circuit shown in fig. 7B has a P-type MOS transistor MP702 and an N-type MOS transistor MN 702. The withstand voltage of the P-type MOS transistor MP702 is different from that of the N-type MOS transistor MN702, and in contrast to the example shown in fig. 7A, the P-type MOS transistor MP702 is a high withstand voltage transistor in the example shown in fig. 7B. Here, the layout and wiring shape of the P-type MOS transistor MP702 is the same as that of the P-type MOS transistor MP701, and the layout and wiring shape of the N-type MOS transistor MN702 is the same as that of the N-type MOS transistor MN 701.
Between a signal line to which the power supply voltage VDD is supplied and a signal line to which the reference voltage GND is supplied, a P-type MOS transistor MP702 and an N-type MOS transistor MN702 are connected in series in this order from the signal line side to which the power supply voltage VDD is supplied, and a voltage at a connection point of the P-type MOS transistor MP702 and the N-type MOS transistor MN702 is output as an output signal SOUT. In the P-type MOS transistor MP702, a gate is connected to a signal line supplying the reference voltage GND, and a back gate is connected to a signal line supplying the power supply voltage VDD. In the N-type MOS transistor MN702, a gate is connected to a signal line to which the power supply voltage VDD is supplied, and a back gate is connected to a signal line to which the reference voltage GND is supplied. The circuit shown in fig. 7B outputs, as the output signal SOUT, a signal of a voltage VL that is a low voltage close to the reference voltage GND.
As described above, by using transistors having the same layout and wiring shapes but different breakdown voltages, the operation cannot be reproduced only by reading the circuit diagram from the layout, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering. In the signal output circuit according to embodiment 7, the number of transistors to be configured is small, and a larger number of signal output circuits can be mounted in the self-layout wiring region on the semiconductor chip. Therefore, it can be made difficult to reproduce the semiconductor device by reverse engineering.
Further, the above-described embodiments 1 to 7 may be combined as appropriate, and these embodiments are also included in the embodiments of the present invention.
(other embodiments)
Fig. 8 is a diagram showing an application example of the semiconductor device of the present embodiment. In fig. 8, 100 denotes a semiconductor chip including the semiconductor device of the present embodiment. In the semiconductor chip 100, the outputs of the plurality of signal output circuits 120 are connected to a logic processing circuit section 110 that performs various logic processes. Since the logic processing circuit section 110 performs a part or all of the logic processing using the output of the signal output circuit 120, the relationship between the input and the output in the logic processing circuit section 110 also depends on the output state of the signal output circuit 120. As described above, it is difficult to know the output state of the signal output circuit 120 according to the present embodiment by reverse engineering, and it is also difficult to analyze the relationship between the input and the output in the logic processing circuit unit 110, thereby preventing illegal copying of the semiconductor chip and the like.
The above embodiments are merely specific examples for carrying out the present invention, and the technical scope of the present invention is not to be construed in a limiting manner. That is, the present invention can be implemented in various forms without departing from the technical idea or main features thereof.
Industrial applicability
According to these semiconductor devices, it is possible to make it difficult to reproduce the semiconductor devices by reverse engineering.
The claims (modification according to treaty clause 19)
1. A semiconductor device is characterized in that a semiconductor element,
the semiconductor device includes:
a plurality of 1 st signal output circuits each having a 1 st transistor and a 2 nd transistor and outputting a voltage at a connection point between the 1 st transistor and the 2 nd transistor, wherein the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying a 1 st voltage and a signal line supplying a 2 nd voltage lower than the 1 st voltage, and a gate of each of the 1 st transistor and the 2 nd transistor is supplied with a predetermined voltage; and
and a plurality of 2 nd signal output circuits each having a 3 rd transistor and a 4 th transistor, each of the 3 rd transistor and the 4 th transistor being connected in series between a signal line for supplying the 1 st voltage and a signal line for supplying the 2 nd voltage, and each of the 3 rd transistor and the 4 th transistor having a gate to which a predetermined voltage is supplied, wherein the 3 rd transistor and the 1 st transistor have the same layout but different characteristics, and the 4 th transistor and the 2 nd transistor have the same layout but different characteristics.
2. The semiconductor device according to claim 1,
the 1 st transistor and the 3 rd transistor are connected to a signal line for supplying the 1 st voltage, a threshold voltage of the 1 st transistor is different from a threshold voltage of the 3 rd transistor, and a threshold voltage of the 2 nd transistor is different from a threshold voltage of the 4 th transistor.
3. The semiconductor device according to claim 2,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a reference voltage,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, a threshold voltage of the 1 st transistor is higher than the power supply voltage, and the 1 st transistor and the 2 nd transistor are N-type transistors having gates connected to a signal line supplying the 1 st voltage; and
in the 2 nd signal output circuit, a threshold voltage of the 4 th transistor is higher than the power supply voltage, and the 3 rd transistor and the 4 th transistor are N-type transistors having gates connected to a signal line for supplying the 1 st voltage.
4. The semiconductor device according to claim 2 or 3,
the semiconductor device has an N-type transistor diode-connected between a signal line supplying the 1 st voltage and a signal line supplying the 3 rd voltage,
the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying the 3 rd voltage and a signal line supplying the 2 nd voltage,
the 3 rd transistor and the 4 th transistor are connected in series between a signal line supplying the 3 rd voltage and a signal line supplying the 2 nd voltage.
5. The semiconductor device according to any one of claims 2 to 4,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a reference voltage,
the semiconductor device includes:
the 1 st signal output circuit in which a threshold voltage of the 1 st transistor is lower than a value (the 2 nd voltage — the 1 st voltage), and the 1 st transistor and the 2 nd transistor are P-type transistors whose gates are connected to a signal line supplying the 2 nd voltage; and
in the 2 nd signal output circuit, the threshold voltage of the 4 th transistor is lower than a value (the 2 nd voltage to the 1 st voltage), and the 3 rd transistor and the 4 th transistor are P-type transistors having gates connected to a signal line for supplying the 2 nd voltage.
6. The semiconductor device according to any one of claims 2 to 5,
the semiconductor device includes:
the 1 st signal output circuit, in which the 1 st transistor and the 2 nd transistor are respectively diode-connected; and
and a 2 nd signal output circuit, wherein the 3 rd transistor and the 4 th transistor are diode-connected to each other in the 2 nd signal output circuit.
7. The semiconductor device according to any one of claims 2 to 6,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, the 1 st transistor is a depletion type, and the 2 nd transistor is an enhancement type; and
in the 2 nd signal output circuit, the 3 rd transistor is an enhancement type, and the 4 th transistor is a depletion type in the 2 nd signal output circuit.
8. The semiconductor device according to any one of claims 2 to 7,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, the 1 st transistor is a high withstand voltage transistor, the 2 nd transistor is a low withstand voltage transistor having a withstand voltage lower than that of the 1 st transistor; and
in the 2 nd signal output circuit, the 3 rd transistor is the low withstand voltage transistor, and the 4 th transistor is the high withstand voltage transistor.
(additional) a semiconductor device, characterized in that,
the semiconductor device has:
a plurality of 1 st signal output circuits each having a 1 st transistor and a 2 nd transistor and outputting a voltage at a connection point between the 1 st transistor and the 2 nd transistor, wherein the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying a 1 st voltage and a signal line supplying a 2 nd voltage lower than the 1 st voltage, and a gate of each of the 1 st transistor and the 2 nd transistor is supplied with a predetermined voltage;
a plurality of 2 nd signal output circuits having a 3 rd transistor and a 4 th transistor, which output a voltage at a connection point of the 3 rd transistor and the 4 th transistor, the 3 rd transistor and the 4 th transistor being connected in series between a signal line supplying the 1 st voltage and a signal line supplying the 2 nd voltage, and respective gates of which are supplied with a predetermined voltage, the 3 rd transistor being identical in layout but different in characteristics from the 1 st transistor, and the 4 th transistor being identical in layout but different in characteristics from the 2 nd transistor; and
a logic processing circuit which performs a logic process,
the logic processing circuit is connected to an output of the 1 st signal output circuit and an output of the 2 nd signal output circuit, and performs a part or all of the logic processing using the outputs of the connected signal output circuits.
(additional) the semiconductor device according to claim 9,
the 1 st transistor and the 3 rd transistor are connected to a signal line for supplying the 1 st voltage, a threshold voltage of the 1 st transistor is different from a threshold voltage of the 3 rd transistor, and a threshold voltage of the 2 nd transistor is different from a threshold voltage of the 4 th transistor.
(additional) the semiconductor device according to claim 10,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a reference voltage,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, a threshold voltage of the 1 st transistor is higher than the power supply voltage, and the 1 st transistor and the 2 nd transistor are N-type transistors having gates connected to a signal line supplying the 1 st voltage; and
in the 2 nd signal output circuit, a threshold voltage of the 4 th transistor is higher than the power supply voltage, and the 3 rd transistor and the 4 th transistor are N-type transistors having gates connected to a signal line for supplying the 1 st voltage.
(additional) the semiconductor device according to claim 10 or 11,
the semiconductor device has an N-type transistor diode-connected between a signal line supplying the 1 st voltage and a signal line supplying the 3 rd voltage,
the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying the 3 rd voltage and a signal line supplying the 2 nd voltage,
the 3 rd transistor and the 4 th transistor are connected in series between a signal line supplying the 3 rd voltage and a signal line supplying the 2 nd voltage.
(additional) the semiconductor device according to any one of claims 10 to 12,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a reference voltage,
the semiconductor device includes:
the 1 st signal output circuit in which a threshold voltage of the 1 st transistor is lower than a value (the 2 nd voltage — the 1 st voltage), and the 1 st transistor and the 2 nd transistor are P-type transistors whose gates are connected to a signal line supplying the 2 nd voltage; and
in the 2 nd signal output circuit, the threshold voltage of the 4 th transistor is lower than a value (the 2 nd voltage to the 1 st voltage), and the 3 rd transistor and the 4 th transistor are P-type transistors having gates connected to a signal line for supplying the 2 nd voltage.
(additional) the semiconductor device according to any one of claims 10 to 13,
the semiconductor device includes:
the 1 st signal output circuit, in which the 1 st transistor and the 2 nd transistor are respectively diode-connected; and
and a 2 nd signal output circuit, wherein the 3 rd transistor and the 4 th transistor are diode-connected to each other in the 2 nd signal output circuit.
(additional) the semiconductor device according to any one of claims 10 to 14,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, the 1 st transistor is a depletion type, and the 2 nd transistor is an enhancement type; and
in the 2 nd signal output circuit, the 3 rd transistor is an enhancement type, and the 4 th transistor is a depletion type in the 2 nd signal output circuit.
(additional) the semiconductor device according to any of claims 10 to 15,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, the 1 st transistor is a high withstand voltage transistor, the 2 nd transistor is a low withstand voltage transistor having a withstand voltage lower than that of the 1 st transistor; and
in the 2 nd signal output circuit, the 3 rd transistor is the low withstand voltage transistor, and the 4 th transistor is the high withstand voltage transistor.

Claims (8)

1. A semiconductor device is characterized in that a semiconductor element,
the semiconductor device includes:
a plurality of 1 st signal output circuits each having a 1 st transistor and a 2 nd transistor and outputting a voltage at a connection point between the 1 st transistor and the 2 nd transistor, wherein the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying a 1 st voltage and a signal line supplying a 2 nd voltage lower than the 1 st voltage, and a gate of each of the 1 st transistor and the 2 nd transistor is supplied with a predetermined voltage; and
and a plurality of 2 nd signal output circuits each having a 3 rd transistor and a 4 th transistor, each of the 3 rd transistor and the 4 th transistor being connected in series between a signal line for supplying the 1 st voltage and a signal line for supplying the 2 nd voltage, and each of the 3 rd transistor and the 4 th transistor having a gate to which a predetermined voltage is supplied, wherein the 3 rd transistor and the 1 st transistor have the same layout but different characteristics, and the 4 th transistor and the 2 nd transistor have the same layout but different characteristics.
2. The semiconductor device according to claim 1,
the 1 st transistor and the 3 rd transistor are connected to a signal line for supplying the 1 st voltage, a threshold voltage of the 1 st transistor is different from a threshold voltage of the 3 rd transistor, and a threshold voltage of the 2 nd transistor is different from a threshold voltage of the 4 th transistor.
3. The semiconductor device according to claim 2,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a reference voltage,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, a threshold voltage of the 1 st transistor is higher than the power supply voltage, and the 1 st transistor and the 2 nd transistor are N-type transistors having gates connected to a signal line supplying the 1 st voltage; and
in the 2 nd signal output circuit, a threshold voltage of the 4 th transistor is higher than the power supply voltage, and the 3 rd transistor and the 4 th transistor are N-type transistors having gates connected to a signal line for supplying the 1 st voltage.
4. The semiconductor device according to claim 2 or 3,
the semiconductor device has an N-type transistor diode-connected between a signal line supplying the 1 st voltage and a signal line supplying the 3 rd voltage,
the 1 st transistor and the 2 nd transistor are connected in series between a signal line supplying the 3 rd voltage and a signal line supplying the 2 nd voltage,
the 3 rd transistor and the 4 th transistor are connected in series between a signal line supplying the 3 rd voltage and a signal line supplying the 2 nd voltage.
5. The semiconductor device according to any one of claims 2 to 4,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a reference voltage,
the semiconductor device includes:
the 1 st signal output circuit in which a threshold voltage of the 1 st transistor is lower than a value (the 2 nd voltage — the 1 st voltage), and the 1 st transistor and the 2 nd transistor are P-type transistors whose gates are connected to a signal line supplying the 2 nd voltage; and
in the 2 nd signal output circuit, the threshold voltage of the 4 th transistor is lower than a value (the 2 nd voltage to the 1 st voltage), and the 3 rd transistor and the 4 th transistor are P-type transistors having gates connected to a signal line for supplying the 2 nd voltage.
6. The semiconductor device according to any one of claims 2 to 5,
the semiconductor device includes:
the 1 st signal output circuit, in which the 1 st transistor and the 2 nd transistor are respectively diode-connected; and
and a 2 nd signal output circuit, wherein the 3 rd transistor and the 4 th transistor are diode-connected to each other in the 2 nd signal output circuit.
7. The semiconductor device according to any one of claims 2 to 6,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, the 1 st transistor is a depletion type, and the 2 nd transistor is an enhancement type; and
in the 2 nd signal output circuit, the 3 rd transistor is an enhancement type, and the 4 th transistor is a depletion type in the 2 nd signal output circuit.
8. The semiconductor device according to any one of claims 2 to 7,
the semiconductor device includes:
the 1 st signal output circuit, in the 1 st signal output circuit, the 1 st transistor is a high withstand voltage transistor, the 2 nd transistor is a low withstand voltage transistor having a withstand voltage lower than that of the 1 st transistor; and
in the 2 nd signal output circuit, the 3 rd transistor is the low withstand voltage transistor, and the 4 th transistor is the high withstand voltage transistor.
CN201980012774.7A 2018-02-15 2019-02-14 Semiconductor device with a plurality of semiconductor chips Pending CN111712911A (en)

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