WO2019153395A1 - 一种安全芯片 - Google Patents

一种安全芯片 Download PDF

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Publication number
WO2019153395A1
WO2019153395A1 PCT/CN2018/077996 CN2018077996W WO2019153395A1 WO 2019153395 A1 WO2019153395 A1 WO 2019153395A1 CN 2018077996 W CN2018077996 W CN 2018077996W WO 2019153395 A1 WO2019153395 A1 WO 2019153395A1
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module
internal
redefinition
security chip
circuit
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PCT/CN2018/077996
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English (en)
French (fr)
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王良清
李亚明
向柄宇
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深圳国微技术有限公司
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Publication of WO2019153395A1 publication Critical patent/WO2019153395A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation

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  • the present invention relates to the field of chips, and in particular to a security chip.
  • the microprobe technology can read the data transmitted on the line after the chip package is removed and connected to the physical metal line in the chip through a scanning electron microscope. Once the data transmitted on the internal connection of the security chip is acquired and analyzed, the attacker can use the micro-probe technology to steal important data including the key, thereby causing the security of the security chip to be lost.
  • Existing security chips usually use hardware scrambling on the internal bus of the chip to defend against micro-probe technology.
  • the security chip of the prior art performs hardware scrambling processing on the internal bus of the chip, so that the original plaintext data is no longer transmitted on the internal bus, and the data stolen by the attacker needs to be subjected to descrambling analysis to obtain useful information. Can play a certain anti-microprobe attack effect.
  • the prior art has the following problems:
  • the hardware scrambling circuit of the internal bus of the security chip of the prior art is solidified in the chip, and the attacker may guess the scrambling algorithm through large-scale data analysis, thereby making the hardware scrambling circuit lose meaning;
  • the prior art security chip simply performs a simple hardware scrambling process on the address signal or data signal of the internal bus, and the function classification of each bus signal is determined, and the attacker can easily analyze the function according to the function of the internal bus signal. Data transmitted on the bus;
  • the circuit in the prior art security chip is determined.
  • the attacker may extract the circuit in the chip through circuit layout analysis and chip reversal technology, and the chip has the risk of being copied and copied.
  • the object of the present invention is to provide a security chip with high security level and preventing multiple cracks and attacks against the defects of the prior art described above.
  • a security chip including at least a first internal circuit module and a first internal connection redefinition module adjacent to the first internal circuit module, the first internal connection
  • the line redefinition module is configured to map the original signal line of the first internal circuit module to the physical metal connection provided by the first internal connection redefinition module according to the configuration file of the first internal connection redefinition module port.
  • the first internal connection redefinition module is implemented by using an eFPGA.
  • the first internal connection redefinition module includes an original signal line port, a redefinition circuit, and a physical metal connection port, and the original signal line port is mapped to the physical metal by the redefinition circuit. Connection port.
  • the scrambling and redefinition algorithm for the internal connection of the redefinition circuit is determined by the configuration file of the eFPGA.
  • the redefinition circuit is a sequential scrambling circuit or a complex scrambling circuit.
  • the first internal connection redefinition module and the second internal connection redefinition module are connected by a physical metal connection inside the security chip.
  • the second internal connection redefinition module is implemented by using an eFPGA.
  • the security chip of the present invention integrates an internal connection redefinition module implemented by using eFPGA technology, and can realize different functions of internal rewiring of the chip and data scrambling circuit, so that the internal physical of the chip
  • the function definition and data of the connection are different, effectively preventing the theft of data on the physical connection line of the security chip; in addition, the internal connection redefinition module appears as a meaningless circuit when the chip is powered down, avoiding The risk of plagiarism and duplication of the chip circuit greatly increases the security of the chip.
  • FIG. 1 is a schematic structural diagram of a security chip according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of the first internal wiring redefinition module of FIG. 1.
  • the first internal connection redefinition module 102 is used to map the original signal line of the first internal circuit module 101 to the physical metal connection provided by the first internal connection redefinition module 102.
  • the port is configured to implement data scrambling and function redefinition of the original signal of the first internal circuit module 101 to prevent the original signal of the first internal circuit module 101 from being detected to improve the security performance of the security chip.
  • the first internal wiring redefinition module 102 includes original signal line ports 201 (P1, P2, ... PN), a redefinition circuit 202, and a physical metal connection port 203 (W1, W2, ... WN).
  • the original signal line port 201 is connected to the original signal line of the internal circuit module 101
  • the physical metal connection port 203 is connected to the physical metal connection 103 in the chip
  • the original signal line port 201 is connected.
  • the re-definition circuit 202 is mapped to the physical metal connection port 203.
  • the scrambling and redefinition algorithm for the internal connection of the redefinition circuit 202 is determined by the configuration file of the eFPGA, and the configuration file may be stored in a non-volatile memory inside the chip, or may be The external interface of the security chip is obtained from the outside.
  • the redefinition circuit 202 can be defined as a simple sequential disturbance circuit, such as P1 connected to W4, P3 connected to W1, ... or can be defined as a complex scrambling circuit, such as P2, P3, P4 through a specific algorithm circuit Map to W1, W2, WN.
  • a security chip 30 which includes a first internal circuit module 301, a second internal circuit module 302, and a first connection adjacent to the first internal circuit module 301.
  • the physical metal connection 306 inside the security chip is connected to the second internal connection redefinition module 304, and the first internal connection redefinition module 303 is configured to use the original of the first internal circuit module 301.
  • the signal line is mapped to the physical metal connection port provided by the first internal connection redefinition module 303, and the second internal connection redefinition module 304 is configured to map the original signal line of the second internal circuit module 302.
  • the physical metal connection port provided by module 304 is redefined to the second internal interconnect.
  • the security chip of the present invention integrates an internal connection redefinition module implemented by using eFPGA technology, and can realize different functions of internal rewiring of the chip and data scrambling circuit, so that the internal physical connection of the chip The function definition and data are different, effectively preventing the theft of data on the physical connection line of the security chip; in addition, the internal connection redefinition module appears as a meaningless circuit when the chip is powered down, avoiding the chip The risk of plagiarism and duplication of the circuit greatly increases the security of the chip.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本发明公开了一种安全芯片，其包括至少一第一内部电路模块和与所述第一内部电路模块相邻连接的第一内部连线重新定义模块，所述第一内部连线重新定义模块用于根据所述第一内部连线重新定义模块的配置文件将所述第一内部电路模块的原始信号线映射到所述第一内部连线重新定义模块提供的物理金属连线端口。本发明的安全芯片安全等级高，可防止多种破解和攻击。

Description

一种安全芯片 技术领域
本发明涉及芯片领域，尤其涉及一种安全芯片。
背景技术
随着芯片攻击手段的不断提高，人们对安全芯片的安全防护措施也提出了更高的要求。作为芯片侵入式攻击的一种，微探针技术在去除芯片封装之后，通过扫描电子显微镜连接到芯片内的物理金属线上，就能读取到线上传输的数据。安全芯片内部连线上传输的数据一旦被获取到，再加以分析，攻击者便可以利用微探针技术窃取到包括密钥在内的重要数据，从而导致安全芯片的安全性丧失。现有的安全芯片通常采用对芯片内部总线做硬件加扰的方式抵御微探针技术的攻击。
现有技术的安全芯片对芯片的内部总线做了硬件加扰处理，使内部总线上传输的不再是原始的明文数据，攻击者窃取到的数据需要再经过解扰分析才能得到有用的信息，能起到一定的抗微探针攻击的效果。然而，现有技术存在如下问题：
1、现有技术的安全芯片内部总线的硬件加扰电路固化在芯片之内，攻击者通过大批量的数据分析有可能猜出加扰算法，从而使硬件加扰电路失去意义；
2、现有技术的安全芯片只是对内部总线的地址信号或者数据信号做了简单的硬件加扰处理，各总线信号的功能分类是确定的，攻击者容易根据内部总线信号的功能分类分析出的总线上传输的数据；
3、现有技术的安全芯片内的电路是确定的，攻击者可能通过电路版图分析、芯片反向技术等手段提取出芯片中的电路，芯片存在被抄袭和复制的风险。
发明内容
本发明的目的是针对上述现有技术存在的缺陷，提供一种安全等级高，可防止多种破解和攻击的安全芯片。
本发明实施例中，提供了一种安全芯片，其包括至少一第一内部电路模块和与所述第一内部电路模块相邻连接的第一内部连线重新定义模块，所述第一内部连线重新定义模块用于根据所述第一内部连线重新定义模块的配置文件将所述第一内部电路模块的原始信号线映射到所述第一内部连线重新定义模块提供的物理金属连线端口。
本发明实施例中，所述第一内部连线重新定义模块采用eFPGA来实现。
本发明实施例中，所述第一内部连线重新定义模块包括原始信号线端口、重定义电路和物理金属连线端口，所述原始信号线端口被所述重定义电路映射到所述物理金属连线端口。
本发明实施例中，所述原始信号线端口与所述第一内部电路模块的原始信号线相连，所述物理金属连线端口与所述安全芯片内的物理金属连线相连。
本发明实施例中，所述重定义电路对内部连线的加扰及重定义算法由所述 eFPGA的配置文件来决定。
本发明实施例中，所述重定义电路为顺序扰乱电路或者复杂加扰电路。
本发明实施例中，所述安全芯片内部还包括非易失性存储器，所述eFPGA的配置文件存储于所述非易失性存储器中。
本发明实施例中，所述安全芯片还包括第二内部电路模块和与所述第二内部电路模块相邻连接的第二内部连线重新定义模块，所述第二内部连线重新定义模块用于将所述第二内部电路模块的原始信号线映射到所述第二内部连线重新定义模块提供的物理金属连线端口。
本发明实施例中，所述第一内部连线重新定义模块和所述第二内部连线重新定义模块通过所述安全芯片内部的物理金属连线相连接。
本发明实施例中，所述第二内部连线重新定义模块采用eFPGA来实现。
与现有技术相比较，本发明的安全芯片在内部集成了使用eFPGA技术实现的内部连线重定义模块，可以实现不同的芯片内部连线的功能重定义和数据加扰电路，使芯片内部物理连线的功能定义和数据都是不相同的，有效地防止了对安全芯片内部物理连线上数据的窃取；此外，内部连线重定义模块在芯片掉电时表现为无意义的电路，避免了芯片电路被抄袭和复制的风险，大大提高了芯片的安全性。
附图说明
图1是本发明实施例一的安全芯片的结构示意图。
图2是图1中的第一内部连线重新定义模块的结构示意图。
图3是本发明实施例二的安全芯片的结构示意图。
具体实施方式
以下结合具体实施例对本发明的实现进行详细描述。
实施例一
如图1所示，本实施例中，提供了一种安全芯片10，其包括至少一第一内部电路模块101和与所述第一内部电路模块101相邻连接的第一内部连线重新定义模块102，所述第一内部连线重新定义模块102通过所述安全芯片内部的物理金属连线103与所述安全芯片内部的其它电路104相连接，所述第一内部连线重新定义模块102用于根据所述第一内部连线重新定义模块102的配置文件将所述第一内部电路模块101的原始信号线映射到所述第一内部连线重新定义模块102提供的物理金属连线端口。
需要说明的是，在芯片内部，通常内部集成有多个不同功能的电路模块，比如MCU、DSP、缓存等，这些电路模块通过芯片内部的物理金属连线进行连接，从而实现这些模块之间信号的交换。因此，可通过这些电路之间的信号关系有可能被破解。本发明实施例中，采用所述第一内部连线重新定义模块102将所述第一内部电路模块101的原始信号线映射到所述第一内部连线重新定义模块102提供的物理金属连线端口，从而实现对第一内部电路模块101的原始信号的数据加扰和功能重定义，避免所述第一内部电路模块101的原始信号被侦测到，以提高所述安全芯片的安全性能。
本发明实施例中，所述第一内部连线重新定义模块102采用eFPGA(embedded Field Programmable Gate Array，嵌入式现场可编程门陈列)来实现。
如图2所示，所述第一内部连线重新定义模块102包括原始信号线端口201(P1，P2,…PN)、重定义电路202和物理金属连线端口203(W1，W2,…WN)， 所述原始信号线端口201与所述内部电路模块101的原始信号线相连，所述物理金属连线端口203与芯片内的物理金属连线103相连，所述原始信号线端口201被所述重定义电路202映射到所述物理金属连线端口203。
所述重定义电路202对内部连线的加扰及重定义算法由所述eFPGA的配置文件来决定，所述配置文件可以存储在所述芯片内部的非易失性存储器中，也可以通过所述安全芯片的外部接口从外部获取。所述重定义电路202可以被定义为简单的顺序扰乱电路，比如P1连接到W4，P3连接到W1……，也可以是被定义为复杂加扰电路，比如P2、P3、P4经过特定算法电路映射到W1、W2、WN上。
实施例二
如图3所示，本实施例中，提供了一种安全芯片30，其包括第一内部电路模块301、第二内部电路模块302、与所述第一内部电路模块301相邻连接的第一内部连线重新定义模块303、与所述第二内部电路模块302相邻连接的第二内部连线重新定义模块304和非易失性存储器305，所述第一内部连线重新定义模块303通过所述安全芯片内部的物理金属连线306与所述第二内部连线重新定义模块304相连接，所述第一内部连线重新定义模块303用于将所述第一内部电路模块301的原始信号线映射到所述第一内部连线重新定义模块303提供的物理金属连线端口，所述第二内部连线重新定义模块304用于将所述第二内部电路模块302的原始信号线映射到所述第二内部连线重新定义模块304提供的物理金属连线端口。
所述第一内部连线重新定义模块303和所述第二内部连线重新定义模块304都采用eFPGA来实现。所述第一内部连线重新定义模块303和所述第二内部连 线重新定义模块304对内部连线的加扰及重定义算法由所述eFPGA的配置文件来决定。所述非易失性存储器305用于存储所述第一内部连线重新定义模块303和所述第二内部连线重新定义模块304的eFPGA配置文件。
需要说明的是，实施例二与实施例一基于同一发明构思，其采用的技术手段和带来的技术效果与实施例一基本相同，此处不在赘述。
综上所述，本发明的安全芯片在内部集成了使用eFPGA技术实现的内部连线重定义模块，可以实现不同的芯片内部连线的功能重定义和数据加扰电路，使芯片内部物理连线的功能定义和数据都是不相同的，有效地防止了对安全芯片内部物理连线上数据的窃取；此外，内部连线重定义模块在芯片掉电时表现为无意义的电路，避免了芯片电路被抄袭和复制的风险，大大提高了芯片的安全性。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种安全芯片，其特征在于，包括至少一第一内部电路模块和与所述第一内部电路模块相邻连接的第一内部连线重新定义模块，所述第一内部连线重新定义模块用于根据所述第一内部连线重新定义模块的配置文件将所述第一内部电路模块的原始信号线映射到所述第一内部连线重新定义模块提供的物理金属连线端口。
  2. 如权利要求1所述的安全芯片，其特征在于，所述第一内部连线重新定义模块采用eFPGA来实现。
  3. 如权利要求2所述的安全芯片，其特征在于，所述第一内部连线重新定义模块包括原始信号线端口、重定义电路和物理金属连线端口，所述原始信号线端口被所述重定义电路映射到所述物理金属连线端口。
  4. 如权利要求3所述的安全芯片，其特征在于，所述原始信号线端口与所述第一内部电路模块的原始信号线相连，所述物理金属连线端口与所述安全芯片内的物理金属连线相连。
  5. 如权利要求3所述的安全芯片，其特征在于，所述重定义电路对内部连线的加扰及重定义算法由所述eFPGA的配置文件来决定。
  6. 如权利要求5所述的安全芯片，其特征在于，所述重定义电路为顺序扰乱电路或者复杂加扰电路。
  7. 如权利要求5所述的安全芯片，其特征在于，所述安全芯片内部还包括非易失性存储器，所述eFPGA的配置文件存储于所述非易失性存储器中。
  8. 如权利要求1所述的安全芯片，其特征在于，所述安全芯片还包括第二 内部电路模块和与所述第二内部电路模块相邻连接的第二内部连线重新定义模块，所述第二内部连线重新定义模块用于将所述第二内部电路模块的原始信号线映射到所述第二内部连线重新定义模块提供的物理金属连线端口。
  9. 如权利要求8所述的安全芯片，其特征在于，所述第一内部连线重新定义模块和所述第二内部连线重新定义模块通过所述安全芯片内部的物理金属连线相连接。
  10. 如权利要求9所述的安全芯片，其特征在于，所述第二内部连线重新定义模块采用eFPGA来实现。
PCT/CN2018/077996 2018-02-09 2018-03-05 一种安全芯片 WO2019153395A1 (zh)

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