WO2019149236A1 - 保护电路、电路保护方法 - Google Patents

保护电路、电路保护方法 Download PDF

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Publication number
WO2019149236A1
WO2019149236A1 PCT/CN2019/074063 CN2019074063W WO2019149236A1 WO 2019149236 A1 WO2019149236 A1 WO 2019149236A1 CN 2019074063 W CN2019074063 W CN 2019074063W WO 2019149236 A1 WO2019149236 A1 WO 2019149236A1
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Prior art keywords
module
circuit
output
comparison module
fpga
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PCT/CN2019/074063
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English (en)
French (fr)
Inventor
麻军
张琪
卫东
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中兴通讯股份有限公司
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Priority to EP19746715.2A priority Critical patent/EP3748845A4/en
Publication of WO2019149236A1 publication Critical patent/WO2019149236A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/462—Indexing scheme relating to amplifiers the current being sensed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/481—A resistor being used as sensor

Definitions

  • the present application relates to the field of circuit protection, for example, to a protection circuit and a circuit protection method.
  • the fifth-generation mobile communication (5th-Generation, 5G) technology is driven by the mobile Internet and the Internet of Things, and has broad application prospects.
  • Large-scale antenna technology As one of the key technologies of 5G wireless, Multiple-Input Multiple-Output (MIMO) technology has been widely used in the 4th generation of 4th-Generation (4G) systems. Faced with the performance challenges of 5G in terms of transmission rate and system capacity, further increase in the number of antennas will remain an important direction for the continued evolution of MIMO technology.
  • MIMO Multiple-Input Multiple-Output
  • the power amplifier (power amplifier) of a base station is typically designed with a multi-channel architecture, and the design of the power supply of the power amplifier usually adopts a power sharing scheme. When one of the power amplifiers is short-circuited, the power supply is biased, which affects the rest. The channel works normally.
  • the protection circuit in the related art generally performs power amplifier drain protection by blowing a fuse.
  • the fuse is blown by heat, and the time is long, and the power amplifier cannot be prevented from burning in time.
  • the embodiment of the present application provides a protection circuit and a circuit protection method.
  • a protection circuit including: a detection module, a comparison module, and a response module, wherein the detection module is configured to be connected to a drain of the power amplifier PA to detect dynamics of the PA drain And outputting the dynamic current to the comparison module; the comparison module is configured to be connected to the detection module, and outputting to the response module after the first response time in response to determining that the dynamic is greater than a sampling threshold a control signal; the response module is configured to be connected to the comparison module, and after the second response time, control the turn-off and turn-on of the PA drain voltage according to the control signal.
  • a circuit protection method including: detecting a dynamic current of a drain of a power amplifier PA; and outputting a control signal after a first response time in response to determining that the dynamic current is greater than a sampling threshold; After the second response time, the turn-off or turn-on of the PA drain voltage is controlled according to the control signal.
  • a storage medium comprising a stored program, wherein the program executes the method described above while it is running.
  • a processor configured to execute a program, wherein the program executes the method described above while it is running.
  • FIG. 1 is a structural diagram 1 of a protection circuit according to an embodiment of the present application.
  • FIG. 2 is a structural diagram 2 of a protection circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of application of a power amplifier protection circuit according to an embodiment
  • Embodiment 4 is a graph showing a protection circuit response curve when the initial power-on is not abnormally protected in Embodiment 1;
  • FIG. 5 is a graph showing a response curve of a protection circuit in an abnormal gate voltage according to Embodiment 1;
  • FIG. 6 is a diagram showing a normal peak-to-average ratio input signal of Embodiment 1;
  • FIG. 7 is a graph showing a protection circuit response curve of an input peak-to-average ratio signal according to Embodiment 1;
  • Figure 8 is a graph of an abnormal input signal of Embodiment 1;
  • FIG. 9 is a graph showing a protection circuit response curve of an input abnormal signal according to Embodiment 1;
  • FIG. 10 is a schematic diagram of an adjustable application of a protection threshold hardware according to Embodiment 2;
  • FIG. 11 is a schematic diagram of an adjustable application of a protection threshold software according to Embodiment 2;
  • FIG. 12 is a schematic diagram 1 of a response time hardware adjustable application of Embodiment 3;
  • FIG. 13 is a schematic diagram 2 of a response time hardware adjustable application of Embodiment 3;
  • FIG. 14 is a schematic diagram 3 of a response time hardware adjustable application of Embodiment 3;
  • Figure 15 is a schematic diagram 4 of the response time software tunable application of the third embodiment
  • FIG. 16 is a schematic diagram of a hardware application of a delay module of Embodiment 4.
  • FIG. 17 is a schematic diagram of an adjustable application of a delay module software according to Embodiment 4.
  • FIG. 18 is a schematic diagram of the application of the dynamically adjustable power amplifier drain protection circuit of the fifth embodiment.
  • the application scenarios of the protection circuit in the embodiment of the present application include: a protection circuit for a power amplifier of a power sharing base station, a circuit system using a field effect transistor, and the like.
  • FIG. 1 is a structural diagram 1 of a protection circuit according to an embodiment of the present application. As shown in FIG. 1, the detection module 10, the comparison module 12, and the response module 14 are included.
  • the detecting module 10 is configured to be connected to a drain of a power amplifier (PA), detect a dynamic current of the PA drain, and output the dynamic current to the comparison module.
  • PA power amplifier
  • the comparison module 12 is configured to be coupled to the detection module, responsive to determining that the dynamic current is greater than the sampling threshold, and outputting a control signal to the response module after the first response time.
  • the response module 14 is configured to be connected to the comparison module, and after the second response time, controls the turn-off and turn-on of the PA drain voltage according to the control signal.
  • the circuit further includes: an adjustable reference module configured to be coupled to the detection module to adjust a sampling threshold of the dynamic current. By increasing the adjustable reference module, the sampling threshold is adjusted to adjust the protection threshold of the protection circuit.
  • the adjustable reference module is configured to be coupled to the comparison module to adjust the first response time. In an embodiment, the adjustable reference module is configured to be coupled to the response module to adjust the second response time.
  • the response time of the protection circuit is adjustable by adding an adjustable reference module.
  • the circuit further includes: a delay module configured to be coupled to the comparison module to control the state of the enable terminal of the comparison module. By adding a delay module and controlling the power-on time of the comparison module enable signal, it is possible to prevent the system from being powered off.
  • the protection circuit has an enable function. By adding an enable function, the comparison module also has an enable function to control whether the protection is effective.
  • the implementation of the corresponding function of the adjustable reference module may be in the form of software or hardware.
  • An example of the hardware form of the adjustable reference module when adjusting the state of the sampling threshold and the enable terminal includes: an adjustable resistor connected between the ground terminal and the comparison module, and configured to adjust the reference voltage of the comparison module, wherein the reference voltage and The sampling threshold corresponds. According to Ohm's law, the voltage is adjusted. When the resistance is constant, the current is proportional to the voltage, so adjusting the reference voltage can adjust the sampling threshold.
  • Examples of software formats for adjustable reference modules include: Central Processing Unit/Processor (CPU), Field-Programmable Gate Array (FPGA), and Digital to Analog Converter (DAC) ).
  • CPU Central Processing Unit/Processor
  • FPGA Field-Programmable Gate Array
  • DAC Digital to Analog Converter
  • the input end of the FPGA is connected to the CPU, and the output end of the FPGA is connected to a digital to analog converter (DAC) and a comparison module, and is configured to control the state of the enable end by adjusting the output level, and set a reference voltage, wherein The reference voltage corresponds to the sampling threshold.
  • the input of the DAC is connected to the FPGA, and the output of the DAC is connected to the comparison module and set as the output reference voltage.
  • a hardware example of an adjustable reference module including the following form, when adjusting response time, including the first response time and the second response time:
  • the first capacitor is connected between the detection module and the comparison module and is set to adjust the time of the dynamic current output to the comparison module.
  • the adjusting unit including the first resistor and the second capacitor, is set to adjust the time of the dynamic current output to the comparison module, wherein the first resistor is connected between the ground and the comparison module, the second capacitor is connected in parallel with the first resistor, and the second The capacitor is connected between the ground and the comparison module.
  • a resistance-capacitance (RC) phase shifting circuit in parallel with the gate input of the PA, including a second resistor and a third capacitor, configured to adjust a second response time, wherein the second resistor is coupled to the gate input Between the terminal and the ground, a third capacitor is connected between the gate input and the ground.
  • RC resistance-capacitance
  • An example of the hardware form of the adjustable reference module includes: a central processing unit CPU, the input end of the CPU is configured to receive a control command, and the output of the CPU is connected to the FPGA, and is configured to control the FPGA according to the control instruction.
  • the input end of the FPGA and the FPGA is connected to the CPU, and the output end of the FPGA is connected to the first counter circuit, and is set to control the first counter circuit.
  • the first counter circuit has an input end connected to the FPGA, and an output end of the first counter circuit is connected to the comparison module and configured to control the first response time.
  • the implementation of the corresponding function of the delay module may be in the form of software or hardware.
  • the delay module when implemented by hardware, includes: a resistor-capacitor RC phase shift circuit, and the RC phase shift circuit includes a fourth capacitor and The third resistor adjusts the power-on timing of the enable end by adjusting the resistance value of the resistor and the capacitance value of the capacitor, wherein the fourth capacitor and the third resistor are connected in parallel, one end is commonly grounded, and the other end is connected to the enable end, and the adjustment is performed.
  • the resistance value of the third resistor and the capacitance value of the fourth capacitor are in a de-energized state when the power supply is overshooted, and the protection circuit does not have a protection function to avoid system mis-protection.
  • the delay module When implemented by software, the delay module includes a second counter circuit configured to adjust the power-on level of the enable terminal to control the enable state of the enable terminal.
  • FIG. 2 is a second structural diagram of a protection circuit according to an embodiment of the present application. As shown in FIG. 2 , on the basis of FIG. 1 , an adjustable reference module 20 and a delay module 22 are further included.
  • the adjustable reference module adjusts the sampling threshold according to at least one of the following: PA maximum withstand power, PA wideband signal capability, system requirements of the system to which the PA belongs, and peak-to-average ratio of dynamic current.
  • the delay module controls the comparison module enable terminal to be in an off state within a predetermined time after the drain voltage of the PA is turned on. Specifically, the opening time of the drain voltage can be detected, and a predetermined time is waited after detecting the voltage being turned on, thereby preventing the occurrence of the erroneous protection, because when the power amplifier leakage voltage is turned on, the overcurrent occurs at the drain, and the response module is controlled by the adjustment delay module. Avoid mis-protection when the system is powered on, increasing the stability of the system.
  • the PA includes one of the following: a Gallium Nitride (GaN) power amplifier, and a Laterally Diffused Metal Oxide Semiconductor (LDMOS) power amplifier.
  • GaN Gallium Nitride
  • LDMOS Laterally Diffused Metal Oxide Semiconductor
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are in any combination.
  • the forms are located in different processors.
  • a circuit protection method is also provided in this embodiment, which is used to implement the foregoing embodiments and example embodiments, and has not been described again.
  • This embodiment provides a circuit protection method for protecting the power amplifier PA using the protection circuit in Embodiment 1.
  • the protection circuit includes: a detection module configured to be connected to the drain of the power amplifier PA, detecting a dynamic current of the PA drain, and outputting the dynamic current to the comparison module; and the comparison module being configured to be connected to the detection module, in response to determining that the dynamic current is greater than
  • the sampling threshold outputs a control signal after the first response time; the response module is configured to be connected to the comparison module, and after the second response time, controls the off and on of the PA drain voltage according to the control signal.
  • the embodiment further provides a circuit protection method, corresponding to the implementation principle of the protection circuit, comprising: detecting a dynamic current of the drain of the power amplifier PA; responding to determining that the dynamic current is greater than the sampling threshold, and after the first response time, the output control Signal; after the second response time, the off or on of the PA drain voltage is controlled according to the control signal.
  • the method before detecting the dynamic current of the drain of the power amplifier PA, the method further comprises: adjusting at least one of: a sampling threshold, a first response time, and a second response time.
  • the method before outputting the control signal, the method further comprises: adjusting an enable state of the output, wherein the output is configured to output a control signal.
  • adjusting the enable state of the output comprises: adjusting an output level of the field programmable gate array FPGA, wherein the high level and the low level respectively correspond to different states of the output end, such as enabling and disabling.
  • adjusting the control parameter includes: setting a reference voltage, wherein the reference voltage corresponds to a sampling threshold; and adjusting an output time of the dynamic current, and outputting the dynamic current to the comparison module after detecting the dynamic current, comparing The module compares whether the dynamic current is greater than the sampling threshold.
  • adjusting the enable state of the output terminal comprises: controlling the enable state to be a disable state within a predetermined time after the drain voltage of the PA is turned on.
  • the protection circuit may also be an optional implementation in Embodiment 1, and will not be described again.
  • the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware.
  • the technical solution of the present application which is essential or contributes to the related art, may be embodied in the form of a software product stored in a storage medium such as a read only memory/random access memory. (Read Only Memory/Random Access Memory, ROM/RAM), including a number of instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform various implementations of the present application.
  • ROM/RAM Read Only Memory/Random Access Memory
  • the embodiment provides a design scheme related to the power supply protection circuit of the power amplifier.
  • the power amplifier tube is soldered, the large gate voltage, the large-frequency RF signal input, the broad spectrum, and the like, it is possible to successfully create a drain short circuit or The power amplifier tube burned, which led to the deviation of the power supply of the whole machine, causing all the transmitting channels to work abnormally.
  • This embodiment provides a method for limiting the drain current of the power amplifier, not only when the power is placed in some channels, but also when it is abnormally turned off, without affecting the normal operation of other channels, and because of its faster response speed. To a large extent, it can be very effective to prevent the power amplifier from being burnt due to large gate voltage, short circuit and abnormal large signal.
  • a power amplifier drain protection circuit as described in FIG. 2 includes a detection module 10, a response module 14, a comparison module 12, an adjustable reference module 20, and a delay module 22.
  • the detecting module 10 detects the real-time dynamic current of the PA drain and can be realized by using the detecting resistor.
  • the input of the detection module 10 is the PA drain voltage. After the detection resistor, the sampling current is obtained, and the sampling current is input to the comparison module 14 through the differential resistor. In addition, the PA drain voltage enters the response module 14 to supply power to the drain of the power amplifier.
  • the response module 14 controls the turn-off and turn-on of the PA drain voltage, and can be implemented by using a photocoupler and a P-type metal oxide semiconductor (PMOS) transistor.
  • PMOS P-type metal oxide semiconductor
  • the sampling current of the detection module 10 enters the comparison module 12, and the comparison module 12 controls the response module 14.
  • the photocoupler When the output of the comparison module 12 is high, the photocoupler is turned on, turns off the PMOS transistor, and turns off the PA drain voltage.
  • the adjustable reference module 20 controls the response time of the response module 14 to make the response time adjustable.
  • the adjustable reference module 20 sets the PA protection current threshold and the response time of the protection circuit. According to different systems, rated power and system response time, the adjustable current threshold can be adjusted and the protection response time can be adjusted by adjusting the adjustable reference module 20.
  • the adjustable reference module 20 controls the detection module 10, which can adjust the response time of the protection circuit.
  • the adjustable reference module 20 controls the comparison module 10 to implement a protection threshold and an adjustable response time.
  • Comparing module 12 the drain current sampled by the detecting module 10 passes through the operational amplifier D1, the output voltage U1, is compared with the reference voltage U2 through the operational amplifier D2, and outputs a high-low level control response module, and the response module 14 controls the drain voltage of the PA.
  • the adjustable reference module 20 controls the comparison module 12 to adjust the threshold of the protection circuit and to protect the response time of the circuit.
  • the delay module 22 controls the power-on time of the enable signal of the comparison module 12 to prevent the protection circuit from being erroneously protected when the power amplifier is powered on. In addition, the delay module 22 adjusts the comparison module 12 to control whether the protection circuit is in an enabled state.
  • FIG. 3 is a schematic diagram of application of a power amplifier drain protection circuit according to an embodiment.
  • the 101 module is a current detecting module
  • the 102 module is a response module
  • the 103 module is an adjustable reference module
  • the 104 module is a comparison module
  • the 105 module is a delay module.
  • the sampled drain current is input to the 104 module through the differential resistor through the sampling resistor.
  • the 104 module outputs the high or low level control 102 module through the op amps D1 and D2, thereby controlling the PA drain.
  • the voltage is turned off.
  • the 103 module, the 102 module, and the 104 module are controlled by the 103 module to realize the protection threshold and the adjustable response time. By adjusting the 104 module through the 105 module, it is possible to control the power-on time of the 104 enable signal and control whether the protection circuit is effective.
  • R1 is the sampling resistor.
  • the sampling current is input to the op amp D1 through the differential resistors R2 and R3, and the output voltage U1.
  • the CPU controls the FPGA.
  • the FPGA output high or low level controls the D2 enable terminal of the op amp. When the enable signal is high, D2 works normally. When it is low, D2 turns off.
  • the FPGA passes control.
  • the DAC module outputs a voltage value and sets the threshold voltage U2.
  • the op amp D2 outputs high or low level by comparing the voltages U1 and U2. When U1 is greater than U2, D2 outputs a high level, the photocoupler is turned on, the PMOS transistor is turned off, and the PA drain voltage is turned off. When U1 is less than U2, D2 outputs a low level, the photocoupler is turned off, the PMOS transistor is kept open, and the circuit operates normally.
  • the turn-off time of the protection circuit can be changed by adjusting the value of the capacitor C1.
  • the power-on of the enable terminal can be changed by adjusting the capacitance of the capacitor C5 and the resistance of the resistor R5. Time to avoid system protection.
  • the protection circuit shutdown response time is set to t 0 microseconds ( ⁇ s).
  • Figure 4 is the response curve of the protection circuit when the initial power-on is not abnormal protection. Adjust the delay module, the PA drain current is normal, and no mis-protection is caused.
  • Fig. 5 is a response curve of the protection circuit when the abnormal gate voltage is implemented in the first embodiment. At this time, the protection circuit is valid, the PA drain voltage is turned off, and the power amplifier tube is protected.
  • FIG. 6 is a diagram of a normal peak-to-average ratio input signal of Embodiment 1.
  • the protection circuit response curve is shown in FIG. 7.
  • FIG. 7 is a protection circuit response curve of the input-peak-to-average ratio signal of Embodiment 1. Comparing Figures 6 and 7, it can be seen that when the peak-to-average ratio signal appears, the peak-to-average ratio is greater than the protection signal turn-off response time, the PA drain current is normal, and no false protection is caused.
  • FIG. 8 is a graph of the abnormality input signal of the first embodiment.
  • the protection circuit response curve is shown in FIG. 9.
  • FIG. 9 is a protection circuit response curve of the first embodiment of the input abnormal signal. Comparing Figures 8 and 9, it can be seen that when the amplitude of the abnormal signal is greater than the protection current threshold and the duration is greater than the response time of the protection circuit, the protection circuit is activated, and the PA drain voltage is turned off.
  • the protection circuit of the embodiment has the characteristics of adjustable threshold. Because of different systems and different application scenarios, the protection threshold of the PA drain current is different.
  • the threshold current setting of the protection circuit should be set according to the maximum power and broadband signal capability that the power amplifier tube can withstand and the system requirements. If the protection gate is too low, the power amplifier channel is easily turned off by mistake. Too high, it is easy to cause the power amplifier tube to burn out.
  • the protection threshold is adjustable through the hardware circuit.
  • the specific application flow chart is shown in FIG. 10
  • FIG. 10 is a schematic diagram of the application of the protection threshold hardware in the second embodiment.
  • the set protection threshold is changed by adjusting the resistance of the resistor Rp through the voltage divider circuit.
  • the protection threshold is adjustable by software.
  • the specific application flow chart is shown in Figure 11.
  • Figure 11 is a schematic diagram of the application of the protection threshold software in the second embodiment.
  • the CPU controls the FPGA.
  • the FPGA output high and low level controls the D2 enable terminal of the op amp. When the enable signal is high, D2 works normally. When it is low, D2 turns off.
  • the FPGA controls the DAC module. Output voltage value, set the threshold voltage U2.
  • the protection circuit of the embodiment has the characteristics of time adjustment. For different peak-to-average ratio signals, the time required by the system is different, and the time-adjustable feature is very important.
  • the time adjustment can be realized by hardware circuits and software modules, as follows.
  • FIG. 12 is a schematic diagram of the response time hardware adjustable application of the third embodiment, and the detection current is adjusted by adjusting the capacitance value of the capacitor C1 connected in parallel with the detection resistor R1.
  • the time at the input of the op amp changes the response time of the protection circuitry.
  • FIG. 13 is a schematic diagram of the response time hardware adjustable application of the third embodiment, and the detection current is adjusted by adjusting the capacitance value of the capacitor C1 connected in parallel with the voltage dividing resistor R4. The time to the input of the op amp changes the response time of the protection circuitry.
  • FIG. 14 is a schematic diagram of the response time hardware adjustable application of the third embodiment.
  • the RC phase shifting circuit is connected in parallel with the gate input terminal of the PMOS transistor, and the resistor R6 is adjusted.
  • the resistance value and the capacitance of the capacitor C6 change the response time of the protection circuit system.
  • FIG. 15 is a schematic diagram of the response time software adjustable application of the third embodiment.
  • the counter circuit is added between the first stage operational amplifier D1 and the FPGA, and the first counter is passed.
  • the circuit controls the response time and the response time is software adjustable.
  • the enabling module by controlling the enabling module, it is possible to avoid erroneous protection. Because when the power amplifier leakage voltage is turned on, the drain will have an overshoot current. By adjusting the delay module to control the enable module to avoid false protection when the system is powered on, the stability of the system is increased.
  • FIG. 16 is a schematic diagram of the hardware application of the delay module of the fourth embodiment. Adjust the power-on sequence of the enable terminal through the RC network, adjust the resistance value of the resistor R6 and the capacitance value of the capacitor C6 to make it de-energized when the power supply is overshooted.
  • the protection circuit does not have a protection function to avoid system error protection.
  • FIG. 17 is a schematic diagram of the application of the delay module software in the fourth embodiment.
  • the FPGA adjusts the power-on level of the D2 enable terminal of the op amp through the second counter circuit, so that it is in the de-energized state when the power supply is over-shooted, and the protection circuit does not have a protection function to avoid system mis-protection.
  • FIG. 18 is a schematic diagram of the software dynamic adjustable power amplifier drain protection circuit of the fifth embodiment.
  • the 103_1 module (first counter circuit) adjusts the response time of the protection circuit, and the 103_2 module adjusts the protection threshold of the protection circuit; the 105 module (second counter circuit) adjusts the power-on time of the enable terminal to prevent the protection circuit from opening the drain of the power amplifier. Mis-protection occurs and the software is dynamically adjustable.
  • the drain protection circuit system is a new type of protection circuit, which not only protects the large gate voltage, but also effectively blocks the abnormal large signal output of the system and greatly reduces the probability of burning the power tube.
  • the drain can be effectively disconnected, so that the power of the whole machine is not affected, so that other channels can work normally.
  • this point is critical, shielding abnormal channels, baseband down-ranking, so as not to affect the main business, improve the utilization of the whole machine.
  • the protection circuit protection threshold of the embodiment is adjustable: by adding the adjustable reference module, the protection threshold of the protection circuit is adjustable.
  • the protection circuit response time is adjustable: the response time of the protection circuit can be adjusted by adding an adjustable reference module.
  • By adding a delay module the power-on time of the enabler signal of the comparison module is controlled to prevent mis-protection of the system power-on.
  • the protection circuit has an enable function: by adding an enable function, the comparison module also has an enable function to control whether the protection is effective.
  • the protection time is adjustable, and the peak-to-average ratio signal can be prevented from being misprotected.
  • the response time of the response circuit is controlled to avoid the power amplifier burning and increase the system reliability.
  • the enabling module by controlling the enabling module, the erroneous protection can be avoided, because when the power amplifier leakage voltage is turned on, the overcurrent occurs at the drain, and the response module is controlled by the adjustment delay module to avoid erroneous protection when the system is powered on, and the system is increased. Stability.
  • the protection circuit system has a fast response time, and the system response time can be controlled in the microsecond ( ⁇ s) level.
  • this embodiment by controlling the PA drain voltage to be turned off, it is possible to prevent the whole power supply from being turned over when a certain PA is burned.
  • the protection threshold and the response time can be adjusted, the implementation manner is simple, and the cost is low.
  • This embodiment has a wide application scenario, and can be applied to both a GaN power amplifier and an LDMOS power amplifier by turning off the PA drain.
  • the embodiment of the present application further provides a storage medium including a stored program, wherein the program runs to execute the method of any of the above embodiments.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a read-only memory (ROM), a random access memory (RAM), and a mobile hard disk.
  • ROM read-only memory
  • RAM random access memory
  • mobile hard disk A variety of media that can store program code, such as a disk or a disc.
  • An embodiment of the present application also provides a processor configured to execute a program, wherein the program, when executed, performs the method of any of the above.
  • modules or steps of the present application described above may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices. In an embodiment, they may be implemented in program code executable by a computing device such that they may be stored in a storage device for execution by the computing device and, in some cases, may be different than the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the application is not limited to any particular combination of hardware and software.

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Abstract

一种保护电路、电路保护方法，其中，保护电路包括：检测模块（10），与功率放大器PA的漏极连接，设置为检测所述PA漏极的动态电流，将所述动态电流输出至比较模块（12）；所述比较模块（12），与所述检测模块（10）连接，设置为响应于确定所述动态电流大于采样门限，在第一响应时间后向响应模块（14）输出控制信号；响应模块（14），与所述比较模块（12）连接，设置为在第二响应时间后，根据所述控制信号控制所述PA漏极电压的关断或开启。

Description

保护电路、电路保护方法
本申请要求在2018年01月31日提交中国专利局、申请号为201810094652.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路保护领域，例如涉及一种保护电路、电路保护方法。
背景技术
第五代移动通讯(5th-Generation，5G)技术受到移动互联网和物联网的驱动，拥有广阔的应用前景。大规模天线技术作为5G无线关键技术之一，多输入多输出(Multiple-Input Multiple-Out-put，MIMO)技术已经在第四代移动通讯(4th-Generation，4G)系统中得以广泛的应用。面对5G在传输速率和系统容量等方面的性能挑战，天线数目的进一步增加仍将是MIMO技术继续演进的重要方向。
如基站的功放(功率放大器)典型的设计是多通道架构，而功放供电电源的设计通常采用电源共享方案，当其中一路功放漏极短路的情况下，就会造成电源的供电拉偏，影响其余通道的正常工作。
相关技术中的保护电路一般是通过熔断保险丝进行功放漏极保护。该手段中，保险丝通过热方式熔断，时间较长，不能及时防止功放烧毁。
针对相关技术中存在的上述问题，目前尚未发现有效的解决方案。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供了一种保护电路、电路保护方法。
根据本申请的一个实施例，提供了一种保护电路，包括：检测模块、比较模块和响应模块，其中，检测模块，设置为与功率放大器PA的漏极连接，检测所述PA漏极的动态电流，将所述动态电流输出至所述比较模块；所述比较模块，设置为与所述检测模块连接，响应于确定所述动态大于采样门限，在第一响应 时间后向所述响应模块输出控制信号；响应模块，设置为与所述比较模块连接，在第二响应时间后，根据所述控制信号控制所述PA漏极电压的关断和开启。
根据本申请的又一个实施例，提供了一种电路保护方法，包括：检测功率放大器PA漏极的动态电流；响应于确定所述动态电流大于采样门限，在第一响应时间后输出控制信号；在第二响应时间后，根据所述控制信号控制所述PA漏极电压的关断或开启。
根据本申请的又一个实施例，还提供了一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述的方法。
根据本申请的又一个实施例，还提供了一种处理器，所述处理器设置为运行程序，其中，所述程序运行时执行上述的方法。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是根据本申请实施例的保护电路的结构图一；
图2是根据本申请实施例的保护电路的结构图二；
图3是实施方式一功放保护电路的应用示意图；
图4是实施方式一初始上电无异常保护时保护电路响应曲线图；
图5是实施方式一异常栅压时保护电路响应曲线图；
图6是实施方式一正常峰均比输入信号图；
图7是实施方式一输入峰均比信号的保护电路响应曲线图；
图8是实施方式一异常输入信号的曲线图；
图9是实施方式一输入异常信号的保护电路响应曲线图；
图10是实施方式二的保护门限硬件可调应用示意图；
图11是实施方式二的保护门限软件可调应用示意图；
图12是实施方式三的响应时间硬件可调应用示意图1；
图13是实施方式三的响应时间硬件可调应用示意图2；
图14是实施方式三的响应时间硬件可调应用示意图3；
图15是实施方式三的响应时间软件可调应用示意图4；
图16是实施方式四的延迟模块硬件可调应用示意图；
图17是实施方式四的延迟模块软件可调应用示意图；
图18是实施方式五的软件动态可调的功放漏极保护电路应用示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本申请。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
本申请实施例保护电路的应用场景包括：电源共享基站的功放供电电源的保护电路，使用场效应管的电路系统等。
在本实施例中提供了一种保护电路，图1是根据本申请实施例的保护电路的结构图一，如图1所示，包括检测模块10，比较模块12和响应模块14。
检测模块10，设置为与功率放大器(Power Amplifier，PA)的漏极连接，检测PA漏极的动态电流，将动态电流输出至比较模块。
比较模块12，设置为与检测模块连接，响应于确定动态电流大于采样门限，且在第一响应时间后，向响应模块输出控制信号。
响应模块14，设置为与比较模块连接，且在第二响应时间后，根据控制信号控制PA漏极电压的关断和开启。
通过上述步骤，通过限制功放漏极电流，不仅可以使得当功放在某些通道出现异常时，快速对其关断，不影响其它通道正常运行。而且由于其较快的响应速度，可以有效的防止功放因大栅压、短路及异常大信号等原因造成的烧毁，避免了相关技术中的保护电路响应时间慢、功放烧毁造成整机电源拉偏等情况。通过设置电路的采样门限和响应时间，避免了极限条件下导致功放烧毁，增加了系统可靠性、稳定性。
在一实施例中，电路还包括：可调基准模块，设置为与检测模块连接，调节动态电流的采样门限。通过增加可调基准模块，调整采样门限，使保护电路的保护门限可调。
在一实施例中，可调基准模块，设置为与比较模块连接，调节第一响应时间。在一实施例中，可调基准模块，设置为与响应模块连接，调节第二响应时间。通过增加可调基准模块，使保护电路的响应时间可调。
在一实施例中，电路还包括：延迟模块，设置为与比较模块连接，控制比较模块使能端的状态。通过增加延迟模块，控制比较模块使能端信号的上电时间，可以防止系统上电出现误保护。保护电路具有使能功能，通过增加使能功能，比较模块还具有使能功能，控制保护是否生效。
在一实施例中，上述可调基准模块相应功能的实现方式可以是软件形式或硬件形式。
在调整采样门限和使能端的状态时，可调基准模块的硬件形式示例，包括：可调电阻，连接在接地端和比较模块之间，设置为调整比较模块的参考电压，其中，参考电压与采样门限对应。根据欧姆定律，调整电压，在电阻不变的情况下，电流与电压成正比，所以调整参考电压能调整采样门限。可调基准模块的软件形式示例，包括：中央处理器(Central Processing Unit/Processor，CPU)，现场可编程门阵列(Field-Programmable Gate Array，FPGA)和数字模拟转换器(Digital to analog converter，DAC)。其中，CPU的输入端设置为接收控制指令，CPU的输出端与FPGA连接，设置为根据控制指令控制FPGA。FPGA的输入端与CPU连接，FPGA的输出端与数字模拟转换器(Digital to analog converter，DAC)和比较模块连接，设置为通过调节输出电平控制使能端的状态，以及设置参考电压，其中，参考电压与采样门限对应。DAC的输入端与FPGA连接，DAC的输出端与比较模块连接，设置为输出参考电压。
在调整响应时间(包括第一响应时间和第二响应时间)时，可调基准模块的硬件示例，包括以下形式：
第一电容，连接在检测模块和比较模块之间，设置为调整动态电流输出至比较模块的时间。
调整单元，包括第一电阻和第二电容，设置为调整动态电流输出至比较模块的时间，其中，第一电阻连接在接地端和比较模块之间，第二电容与第一电阻并联，第二电容连接在接地端和比较模块之间。
电阻-电容(Resistance-Capacitance，RC)移相电路，与PA的栅极输入端并联，包括第二电阻和第三电容，设置为调整第二响应时间，其中，第二电阻连 接在栅极输入端和接地端之间，第三电容连接在栅极输入端和接地端之间。
可调基准模块的硬件形式示例，包括：中央处理器CPU，CPU的输入端设置为接收控制指令，CPU的输出端与FPGA连接，设置为根据控制指令控制FPGA。FPGA，FPGA的输入端与CPU连接，FPGA的输出端与第一计数器电路连接，设置为控制第一计数器电路。第一计数器电路，第一计数器电路的输入端与FPGA连接，第一计数器电路的输出端与比较模块连接，设置为控制第一响应时间。
在一实施例中，延迟模块相应功能的实现方式可以是软件形式或硬件形式，具体的，在通过硬件实现时，延迟模块包括：电阻电容RC移相电路，RC移相电路包括第四电容和第三电阻，通过调整电阻的电阻值和电容的电容值调节使能端的上电时序，其中，第四电容和第三电阻并联，一端共同接地，另一端共同连接均连接至使能端，调整第三电阻的电阻值和第四电容的电容值，使其在电源过冲时处于去使能状态，保护电路不具有保护功能，避免出现系统误保护。
在通过软件实现时，延迟模块包括：第二计数器电路，设置为调节使能端的上电电平来控制使能端的使能状态。
图2是根据本申请实施例的保护电路的结构图二，如图2所示，在图1的基础上，还包括：可调基准模块20和延迟模块22。
在一实施例中，可调基准模块根据以下至少之一调节采样门限：PA最大承受功率、PA的宽带信号能力，PA所属系统的系统需求，以及动态电流的峰均比。
在一实施例中，延迟模块在PA的漏压开启后的预定时间内，控制比较模块使能端为去使能状态。具体可以是检测漏极电压的开启时间，在检测到电压开启后等待预定时间，可以避免出现误保护，因为当功放漏压开启后，漏极会出现过冲电流，通过调节延迟模块控制响应模块避免在系统上电时出现误保护，增加系统的稳定性。
在本实施例中，PA包括以下之一：氮化镓(Gallium Nitride，GaN)功率放大器，横向扩散金属氮化物半导体(Laterally Diffused Metal Oxide Semiconductor，LDMOS)功率放大器。当然，也可以是其他的应用场景。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
实施例2
在本实施例中还提供了一种电路保护方法，该用于实现上述实施例及示例实施方式，已经进行过说明的不再赘述。
本实施例提供一种电路保护方法，用于使用实施例1中的保护电路保护功率放大器PA。保护电路包括：检测模块，设置为与功率放大器PA的漏极连接，检测PA漏极的动态电流，将动态电流输出至比较模块；比较模块，设置为与检测模块连接，响应于确定动态电流大于采样门限，在第一响应时间后输出控制信号；响应模块，设置为与比较模块连接，在第二响应时间后，根据控制信号控制PA漏极电压的关断和开启。
本实施例还提供一种电路保护方法，与保护电路的实现原理对应，包括：检测功率放大器PA漏极的动态电流；响应于确定动态电流大于采样门限，且在第一响应时间后，输出控制信号；在第二响应时间后，根据控制信号控制PA漏极电压的关断或开启。
在一实施例中，在检测功率放大器PA漏极的动态电流之前，方法还包括：调节以下至少之一：采样门限，第一响应时间，以及第二响应时间。
在一实施例中，在输出控制信号之前，方法还包括：调节输出端的使能状态，其中，输出端设置为输出控制信号。
在一实施例中，调节输出端的使能状态包括：调节现场可编程门阵列FPGA的输出电平，其中，高电平和低电平分别对应输出端的不同状态，如使能和去使能。
在一实施例中，调节控制参数包括：设置参考电压，其中，参考电压与采样门限对应；以及调整动态电流的输出时间，在检测到动态电流后，将动态电流输出至比较模块的时间，比较模块比较动态电流是否大于采样门限。
在一实施例中，调节输出端的使能状态包括：在PA的漏压开启后的预定时间内，控制使能状态为去使能状态。
该保护电路也可以是实施例1中的可选实施方式，已经进行过说明的不再赘述。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，本申请的技术方案本质上或者说对相关技术做出 贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质,例如只读存储器/随机存取存储器(Read Only Memory/Random Access Memory，ROM/RAM)、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
实施例3
本实施例提供了一种涉及功放漏极供电保护电路的设计方案，当功放管焊接故障、大栅压、射频大信号输入、宽谱等异常情况下，均有可能造成功放管漏极短路或功放管烧毁，进而导致整机电源拉偏，引起所有发射通道工作异常。
本实施例提供了一种方法，通过限制功放漏极电流，不仅可以使得当功放在某些通道出现异常时，快速对其关断，不影响其它通道正常运行，而且由于其较快的响应速度，在很大程度上可以非常有效的防止功放因大栅压、短路及异常大信号等原因造成的烧毁。
本申请可以防止功放管烧毁和因功放管烧毁造成整机电源拉偏。本申请所述的一种功放漏极保护电路，如图2所示，包括检测模块10，响应模块14，比较模块12，可调基准模块20以及延迟模块22。
检测模块10，检测PA漏极实时动态电流，可利用检测电阻实现。检测模块10输入是PA漏极电压，经检测电阻后会得到采样电流，采样电流经过差分电阻输入到比较模块14。另外，PA漏极电压进入响应模块14，给功放管漏极供电。
响应模块14，控制PA漏极电压的关断与开启，可利用光电耦合器和P型金属氧化物半导体(positive channel Metal Oxide Semiconductor，PMOS)晶体管实现。
检测模块10的采样电流进入比较模块12，比较模块12控制响应模块14，当比较模块12输出为高电平时，光电耦合器导通，关断PMOS晶体管，进而关断PA漏极电压。可调基准模块20控制响应模块14的响应时间，使响应时间具有可调节性。
可调基准模块20，设置PA保护电流门限，以及保护电路的响应时间。针对不同的系统，额定功率以及系统响应时间不同，通过调整可调基准模块20实现保护电流门限可调、保护响应时间可调。
可调基准模块20控制检测模块10，响应模块14可以调节保护电路的响应时间。可调基准模块20控制比较模块10实现保护门限、响应时间可调。
比较模块12，检测模块10采样的漏极电流经过运放D1，输出电压U1，通过运放D2和基准电压U2作比较，输出高低电平控制响应模块，响应模块14控制PA漏极电压的关断。可调基准模块20控制比较模块12，调节保护电路的门限以及保护电路响应时间。
延迟模块22，控制比较模块12使能端信号的上电时间，避免保护电路在功放上电瞬间出现误保护。另外延迟模块22调节比较模块12，可以控制保护电路是否处于使能状态。
本实施例方案中的各个模块可以通过硬件、软件或者结合的形式实现，可以是多种形式的电路，下面通过具体实施方案作详细描述。
实施方式一
本实施方式保护电路具有保护门限可调、响应时间可调的特点，具体应用流程图见图3，图3是实施方式一功放漏极保护电路的应用示意图。
如图3所示，101模块是电流检测模块，102模块是响应模块，103模块是可调基准模块，104模块是比较模块，105模块是延迟模块。
PA漏级电压通过101模块后，经过取样电阻，取样的漏极电流通过差分电阻输入到104模块，104模块通过运放D1和D2输出高或低电平控制102模块，进而实现控制PA漏极电压的关断。另外，通过103模块控制101模块、102模块、104模块实现保护门限、响应时间可调的特点。通过105模块调节104模块，既可以控制104使能端信号的上电时间，又可以控制保护电路是否生效。R1是取样电阻，PA漏极电压经过R1后，取样电流经过差分电阻R2、R3输入到运放D1，输出电压U1。CPU控制FPGA，一方面，FPGA输出高或低电平控制运放D2使能端，当使能端信号为高电平时D2正常工作，为低电平时D2关断；另一方面，FPGA通过控制DAC模块输出电压值，设定门限电压U2。运放D2通过比较电压U1、U2输出高或低电平，当U1大于U2时，D2输出高电平，光电耦合器导通，PMOS管关断，PA漏极电压关断。当U1小于U2时，D2输出低电平，光电耦合器关闭，PMOS管保持打开，电路正常工作。
因为不同系统要求的响应时间不同，则可以通过调节电容C1的值来改变保护电路的关断时间。另外，当功放漏压打开时，漏极电流会存在过冲，为了防 止保护电路出现误保护，可以通过调节电容C5的容值、电阻R5的阻值来改变使能端高电平的上电时间，避免系统出现误保护。
设定保护电路关断响应时间是t 0微秒(μs)。
1)、当功放漏压开启后，漏极会出现过冲电流，此时保护电路响应曲线如图4所示，图4是实施方式一初始上电无异常保护时保护电路响应曲线图，通过调整延迟模块，PA漏极电流正常，没造成误保护。
2)、当功放栅压异常时会出现大电流，保护电路响应曲线如图5所示，图5是实施方式一异常栅压时保护电路响应曲线图。此时保护电路生效，关断PA漏极电压，保护功放管。
3)、出现峰均比信号时，峰均比信号持续的时间为
Figure PCTCN2019074063-appb-000001
且
Figure PCTCN2019074063-appb-000002
小于t 0，如图6所示，图6是实施方式一正常峰均比输入信号图。保护电路响应曲线如图7所示，图7是实施方式一输入峰均比信号的保护电路响应曲线图。对比图6、7可以看出，出现峰均比信号时，峰均比大信号持续时间小于保护电路关断响应时间时，PA漏极电流正常，没造成误保护。
4)、出现异常信号时，如图8所示，图8是实施方式一异常输入信号的曲线图。保护电路响应曲线如图9所示，图9是实施方式一输入异常信号的保护电路响应曲线图。对比图8、9可以看出，当异常信号的幅度大于保护电流门限，且持续时间大于保护电路响应时间时，保护电路生效，关断PA漏极电压。
实施方式二
本实施方式保护电路具有门限可调特点。因为不同的系统、不同的应用场景，PA漏极电流的保护门限不同。
保护电路的门限电流的设定，要根据功放管的自身可以承受的最大功率和宽带信号能力以及系统需求综合设定，若保护门限定的过低，功放通道容易被误关断，门限定的过高，容易导致功放管烧毁。
保护门限通过硬件电路实现可调，具体应用流程图如图10所示，图10是实施方式二的保护门限硬件可调应用示意图。通过分压电路调整电阻Rp的阻值，来改变设定的保护门限。
保护门限通过软件方式实现可调，具体应用流程图如图11所示，图11是实施方式二的保护门限软件可调应用示意图。CPU控制FPGA，一方面，FPGA输出高低电平控制运放D2使能端，当使能端信号为高电平时D2正常工作，为 低电平时D2关断；另一方面，FPGA通过控制DAC模块输出电压值，设定门限电压U2。
本实施方式中的具体应用流程图均是可实现的功放漏极保护电路系统。
实施方式三
本实施方式保护电路具有时间可调的特点。针对不同的峰均比信号，系统要求的时间不同，时间可调的特点就很重要。时间可调可通过硬件电路以及软件模块实现，具体方式如下。
硬件电路实现方式一，具体应用流程图如图12所示，图12是实施方式三的响应时间硬件可调应用示意图1，通过调整与检测电阻R1并联的电容C1的容值，调整检测电流到运放输入端的时间，改变保护电路系统的响应时间。
硬件电路实现方式二，具体应用流程图如图13所示，图13是实施方式三的响应时间硬件可调应用示意图2，通过调整与分压电阻R4并联的电容C1的容值，调整检测电流到运放输入端的时间，改变保护电路系统的响应时间。
硬件电路实现方式三，具体应用流程图如图14所示，图14是实施方式三的响应时间硬件可调应用示意图3，在PMOS管的栅级输入端并联RC移相电路，通过调整电阻R6的阻值和电容C6的容值，改变保护电路系统的响应时间。
通过软件模块实现，具体应用流程图如图15所示，图15是实施方式三的响应时间软件可调应用示意图4，在第一级运放D1和FPGA之间增加计数器电路，通过第一计数器电路控制响应时间，实现响应时间软件可调。
本实施方式中的具体应用流程图均是可实现的功放漏极保护电路系统。
实施方式四
本实施方式通过控制使能模块，可以避免出现误保护。因为当功放漏压开启后，漏极会出现过冲电流，通过调节延迟模块控制使能模块避免在系统上电时出现误保护，增加系统的稳定性。
延迟模块硬件实现方式，具体流程图如图16所示，图16是实施方式四的延迟模块硬件可调应用示意图。通过RC网络调节使能端的上电时序，调整电阻R6的阻值和电容C6的容值,使其在电源过冲时处于去使能状态，保护电路不具有保护功能，避免出现系统误保护。
延迟模块软件实现方式，具体流程图如图17所示，图17是实施方式四的延迟模块软件可调应用示意图。FPGA通过第二计数器电路调节运放D2使能端 的上电电平，使其在电源过冲时处于去使能状态，保护电路不具有保护功能，避免出现系统误保护。
本实施方式中的具体应用流程图均是可实现的功放漏极保护电路系统。
实施方式五
结合实施方式二、三、四，软件动态可调，功放漏极保护电路应用示意图如图18所示，图18是实施方式五的软件动态可调的功放漏极保护电路应用示意图。通过103_1模块(第一计数器电路)调节保护电路的响应时间，103_2模块调节保护电路的保护门限；105模块(第二计数器电路)调节使能端的上电时间，防止保护电路在功放漏极打开瞬间出现误保护，实现软件动态可调。
综上所述，漏极保护电路系统是一种新型的保护电路，该电路不仅可以防护大栅压，有效阻断系统输出的异常大信号并很大程度上降低功放管烧毁概率。当某个通道即使出现功放管异常后，也能有效断开漏极，从而不影响整机电源，使得其他通道能正常工作。对于多通道系统来说，该点至关重要，屏蔽异常通道，基带降秩处理，从而不影响主要业务，提高整机利用率。
相比于传统保护电路架构，本实施例的保护电路保护门限可调：通过增加可调基准模块，使保护电路的保护门限可调。保护电路响应时间可调：通过增加可调基准模块，使保护电路的响应时间可调。通过增加延迟模块，控制比较模块使能端信号的上电时间，防止系统上电出现误保护。保护电路具有使能功能：通过增加使能功能，比较模块还具有使能功能，控制保护是否生效。
本实施例保护时间可调，可以防止峰均比信号出现误保护。当出现射频大信号时、宽谱信号时，控制响应电路的响应时间，避免功放烧毁，增加系统可靠性。本实施例通过控制使能模块，可以避免出现误保护，因为当功放漏压开启后，漏极会出现过冲电流，通过调节延迟模块控制响应模块避免在系统上电时出现误保护，增加系统的稳定性。本实施例保护电路系统响应时间快，系统响应时间可控制在微秒(μs)级。本实施例通过控制PA漏极电压关断，可避免当某一路PA烧毁时将整机电源拉翻。本实施例通过增加两个模块，即可实现保护门限以及响应时间可调，实现方式简单，成本低。本实施例应用场景广泛，通过关断PA漏极的方式既可应用于GaN功放，也可应用于LDMOS功放。
实施例4
本申请的实施例还提供了一种存储介质，该存储介质包括存储的程序，其 中，上述程序运行时执行上述实施例任一项所述的方法。
在一实施例中，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本申请的实施例还提供了一种处理器，该处理器设置为运行程序，其中，该程序运行时执行上述任一项所述的方法。
在一实施例中，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
本领域的技术人员应该明白，上述的本申请的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，在一实施例中，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本申请不限制于任何特定的硬件和软件结合。

Claims (22)

  1. 一种保护电路，包括：检测模块、比较模块和响应模块，其中，所述检测模块，设置为与功率放大器PA的漏极连接，检测所述PA漏极的动态电流，将所述动态电流输出至所述比较模块；
    所述比较模块，设置为与所述检测模块连接，响应于确定所述动态电流大于采样门限，并在确定所述动态电流大于采样门限后的第一响应时间之后向所述响应模块输出控制信号；
    所述响应模块，设置为与所述比较模块连接，且在接收到所述输出控制信号后的第二响应时间之后，根据所述控制信号控制所述PA漏极电压的关断或开启。
  2. 根据权利要求1所述的电路，所述电路还包括：
    可调基准模块，设置为与所述检测模块连接，调节所述动态电流的所述采样门限。
  3. 根据权利要求2所述的电路，其中，所述可调基准模块，设置为与比较模块连接，调节所述第一响应时间。
  4. 根据权利要求2所述的电路，其中，所述可调基准模块，设置为与所述响应模块连接，调节所述第二响应时间。
  5. 根据权利要求1至4任一项所述的电路，所述电路还包括：
    延迟模块，设置为与所述比较模块连接，控制所述比较模块使能端的状态。
  6. 根据权利要求5所述的电路，其中，所述可调基准模块包括：
    可调电阻，连接在接地端和所述比较模块之间，设置为调整所述比较模块的参考电压，其中，所述参考电压与所述采样门限对应。
  7. 根据权利要求5所述的电路，其中，所述可调基准模块包括：中央处理器CPU、现场可编程门阵列FPGA和数字模拟转换器DAC，其中，
    所述CPU的输入端设置为接收控制指令，所述CPU的输出端与所述FPGA连接，设置为根据所述控制指令控制所述FPGA；
    所述FPGA的输入端与所述CPU连接，所述FPGA的输出端与数字模拟转换器DAC和所述比较模块连接，设置为通过调节输出电平控制所述使能端的状态，以及设置参考电压，其中，所述参考电压与所述采样门限对应；
    所述DAC的输入端与所述FPGA连接，所述DAC的输出端与所述比较模块连接，设置为输出所述参考电压。
  8. 根据权利要求5所述的电路，其中，所述可调基准模块包括：
    第一电容，连接在所述检测模块和所述比较模块之间，设置为调整所述动态电流输出至所述比较模块的时间。
  9. 根据权利要求5所述的电路，其中，所述可调基准模块包括：
    调整单元，包括第一电阻和第二电容，设置为调整所述动态电流输出至所述比较模块的时间，其中，所述第一电阻连接在接地端和所述比较模块之间，所述第二电容与所述第一电阻并联，连接在所述接地端和所述比较模块之间。
  10. 根据权利要求5所述的电路，其中，所述可调基准模块包括：
    电阻电容RC移相电路，与所述PA的栅极输入端并联，所述RC移相电路包括第二电阻和第三电容，设置为调整所述第二响应时间，其中，所述第二电阻连接在所述栅极输入端和接地端之间，所述第三电容连接在所述栅极输入端和接地端之间。
  11. 根据权利要求5所述的电路，其中，所述可调基准模块包括：中央处理器CPU、现场可编程门阵列FPGA和第一计数器电路，其中，
    所述CPU的输入端设置为接收控制指令，所述CPU的输出端与FPGA连接，设置为根据所述控制指令控制所述FPGA；
    所述FPGA的输入端与所述CPU连接，所述FPGA的输出端与第一计数器电路连接，设置为控制所述第一计数器电路；
    所述第一计数器电路的输入端与所述FPGA连接，所述第一计数器电路的输出端与所述比较模块连接，设置为控制所述第一响应时间。
  12. 根据权利要求5所述的电路，其中，所述延迟模块包括以下至少之一：
    电阻电容RC移相电路，所述RC移相电路包括第四电容和第三电阻，通过调整所述第三电阻的电阻值和所述第四电容的电容值调节所述使能端的上电时序；
    第二计数器电路，设置为调节所述使能端的上电电平来控制所述使能端的使能状态。
  13. 根据权利要求2至4任一项所述的电路，其中，所述可调基准模块设置为根据以下至少之一调节所述采样门限：PA最大承受功率，PA的宽带信号能力，PA所属系统的系统需求，以及动态电流的峰均比。
  14. 根据权利要求5所述的电路，其中，所述延迟模块在所述PA的漏压开 启后的预定时间内，控制所述比较模块使能端为去使能状态。
  15. 一种电路保护方法，包括：
    检测功率放大器PA漏极的动态电流；
    响应于确定所述动态电流大于采样门限，在第一响应时间后输出控制信号；
    在第二响应时间后，根据所述控制信号控制所述PA漏极电压的关断或开启。
  16. 根据权利要求15所述的方法，在检测功率放大器PA漏极的动态电流之前，所述方法还包括：
    调节以下控制参数至少之一：所述采样门限，所述第一响应时间，所述第二响应时间。
  17. 根据权利要求15所述的方法，在输出控制信号之前，所述方法还包括：
    调节输出端的使能状态，其中，所述输出端设置为输出所述控制信号。
  18. 根据权利要求17所述的方法，其中，调节输出端的使能状态包括：
    调节现场可编程门阵列FPGA的输出电平，其中，高电平和低电平分别对应所述调节输出端的不同状态。
  19. 根据权利要求16所述的方法，其中，调节控制参数包括：
    设置参考电压，其中，所述参考电压与所述采样门限对应；以及调整所述动态电流的输出时间。
  20. 根据权利要求17所述的方法，其中，调节输出端的使能状态包括：
    在所述PA的漏压开启后的预定时间内，控制所述使能状态为去使能状态。
  21. 一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求15至20任一项中所述的方法。
  22. 一种处理器，所述处理器被设置为运行计算机程序以执行所述权利要求15至20任一项中所述的方法。
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