WO2019148327A1

WO2019148327A1 - Thin-film transistor and manufacturing method therefor, gate drive circuit and flat panel display

Info

Publication number: WO2019148327A1
Application number: PCT/CN2018/074589
Authority: WO
Inventors: 陈丹; 金志河; 黄斌
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2018-01-30
Filing date: 2018-01-30
Publication date: 2019-08-08
Also published as: CN111742413A

Abstract

A thin-film transistor and a manufacturing method therefor, a gate drive circuit and a flat panel display. The thin-film transistor comprises: a substrate (11); one of a source layer (12) and a drain layer (14), which is provided on the substrate (11); an insulating separation layer (13) provided on one of the source layer (12) and the drain layer (14); the other of the source layer (12) and the drain layer (14), which is provided on the insulating separation layer (13); an active layer (15), which covers one of the source layer (12) and the drain layer (14), the insulating separation layer (13) and the other of the source layer (12) and the drain layer (14), and conductively connects one of the source layer (12) and the drain layer (14) to the other of the source layer (12) and the drain layer (14); a gate insulating layer (16) provided on the active layer (15); and a gate layer (17) provided on the gate insulating layer (16). The beneficial effect is that a source layer and a drain layer are vertically arranged, so that a channel length can be effectively reduced, thereby reducing the size of a thin-film transistor.

Description

Thin film transistor and manufacturing method thereof, gate driving circuit, flat panel display

Technical field

The present invention relates to a display, and more particularly to a thin film transistor, a method of fabricating the same, a gate drive circuit, and a flat panel display.

Background technique

FIG. 11 is a schematic structural diagram of a thin film transistor 40 in the related art. As shown, the thin film transistor 40 can be used in a gate driver circuit (GOA) of a liquid crystal display, which includes a substrate 41 and a setting. a gate layer 42 on the substrate 41, a gate insulating layer 43 disposed on the gate layer 42, an active layer 44 disposed on the gate insulating layer 43, and an interlayer insulating layer disposed on the active layer 44 45 and a source 46 and a drain 47 which are disposed on the interlayer insulating layer 45, and the source 46 and the drain 47 are respectively connected to the active layer 44.

Fig. 12 is a circuit diagram showing a gate driving circuit using the thin film transistor, which is composed of four thin film transistors M1 to M4 and a capacitor. In some cases, the number of thin film transistors needs to be increased for the lifetime of the gate driving circuit, and the number of thin film transistors is increased, which increases the width of the gate driving circuit and, correspondingly, increases the edge size of the display.

technical problem

The technical problem to be solved by the present invention is to provide an improved thin film transistor, a method of fabricating the same, a gate driving circuit, and a flat panel display.

Technical solution

The technical solution adopted by the present invention to solve one of the technical problems is to provide a thin film transistor including:

Substrate

One of a source layer and a drain layer, disposed on the substrate;

An insulating spacer layer disposed on one of the source layer and the drain layer;

Another one of the source layer and the drain layer is disposed on the insulating spacer layer;

An active layer covering one of the source layer and the drain layer, the insulating spacer layer, and the other of the source layer and the drain layer, and the source layer and the drain layer are One of the two is electrically connected to the other of the source layer and the drain layer;

a gate insulating layer disposed on the active layer;

A gate layer is disposed on the gate insulating layer.

In some embodiments, the thin film transistor further includes a dividing groove extending from the outer surface of the gate layer toward the substrate to the other of the source layer and the drain layer, forming two common sources and Thin film transistor unit of the drain.

In some embodiments, the thin film transistor further includes a thin trench transistor unit extending from the outer surface of the gate layer toward the substrate to the insulating spacer layer to form two common source or drain.

In some embodiments, the thin film transistor further includes a dividing groove extending from the outer surface of the gate layer toward the substrate toward the substrate to form two independent thin film transistor units.

In some embodiments, the insulating spacer layer has a thickness of 1 to 1.5 μm.

A gate driving circuit including the thin film transistor of any of the above is provided.

In some embodiments, the gate drive circuit is a secondary gate drive circuit.

A flat panel display is provided, including the gate drive circuit described above.

In some embodiments, the flat panel display is a flexible display.

A method of fabricating a thin film transistor is provided, comprising the steps of:

Providing a substrate;

Forming one of a source layer and a drain layer on the substrate;

Forming an insulating spacer layer on one of the source layer and the drain layer;

Forming another one of the source layer and the drain layer on the insulating spacer layer;

Covering the active layer on one of the source layer and the drain layer, the insulating spacer layer, and the other of the source layer and the drain layer, the active layer is a source layer and a drain layer Another electrically conductive connection between the source layer and the drain layer;

Forming a gate insulating layer on the active layer;

A gate layer is formed on the gate insulating layer.

In some embodiments, the method further includes the step of forming a dividing groove extending from the outer surface of the gate layer toward the substrate to the other of the source layer and the drain layer.

In some embodiments, the method further includes the step of forming a dividing groove extending from the outer surface of the gate layer toward the substrate to the insulating spacer layer.

In some embodiments, the method further includes the step of forming a dividing groove extending from the outer surface of the gate layer toward the substrate toward the substrate.

Beneficial effect

The invention has the beneficial effects that the source layer and the drain layer are arranged vertically, which can effectively reduce the channel length, thereby reducing the size of the thin film transistor.

In addition, by the arrangement of the dividing grooves, two thin film transistor units can be formed in one conventional size range, which can further reduce the width of the gate driving circuit using the thin film transistor, thereby significantly reducing the flat panel display using the gate driving circuit. Edge size.

DRAWINGS

The present invention will be further described below in conjunction with the accompanying drawings and embodiments, in which:

1 is a schematic longitudinal sectional view showing a thin film transistor in a first embodiment of the present invention;

2 is a schematic longitudinal sectional view showing a thin film transistor in a second embodiment of the present invention;

3 is a schematic longitudinal sectional structural view of a thin film transistor in a third embodiment of the present invention;

Figure 4 is a circuit diagram of the thin film transistor shown in Figure 3;

Figure 5 is a schematic longitudinal sectional view showing the thin film transistor shown in Figure 3 when bent;

6 is a schematic longitudinal sectional view showing a thin film transistor in a fourth embodiment of the present invention;

Figure 7 is a circuit diagram of the thin film transistor shown in Figure 6;

Figure 8 is a schematic longitudinal sectional view showing a thin film transistor in a fifth embodiment of the present invention;

Figure 9 is a circuit diagram of the thin film transistor shown in Figure 8;

Figure 10 is a circuit diagram of a gate driving circuit with the thin film transistor shown in Figure 8;

11 is a schematic longitudinal sectional view of a thin film transistor in the related art;

Figure 12 is a circuit diagram of a related art gate driving circuit with the thin film transistor shown in Figure 11.

BEST MODE FOR CARRYING OUT THE INVENTION

For a better understanding of the technical features, objects and effects of the present invention, the embodiments of the present invention are described in detail with reference to the accompanying drawings.

The embodiments of the present invention will now be described in detail with reference to the accompanying drawings In order to explain aspects of the invention, embodiments are described below with reference to the drawings. The described exemplary embodiments may be modified in various different ways without departing from the spirit or scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not limiting. In addition, when an element is referred to as "above" another element, it can be directly over the other element, or one or more intervening elements can be inserted into the element. Similarly, when an element is referred to as "connected to another element," it can be directly connected to the element, or one or more intervening elements can be inserted and indirectly connected to the element.

1 shows a thin film transistor 10 in a first embodiment of the present invention, which can meet the size miniaturization requirement, and can include a substrate 11, a source layer 12 disposed on the substrate 11, and a source layer. An insulating spacer layer 13 on the 12, a drain layer 14 disposed on the insulating spacer layer 13, covering the source layer 12, the insulating spacer layer 13 and the drain layer 14, and electrically conducting the source layer 12 and the drain layer 14 The active layer 15 is connected, the gate insulating layer 16 is disposed on the active layer 15, and the gate layer 17 is disposed on the gate insulating layer 16. In some embodiments, the active layer 15 may be made of a channel layer material such as indium gallium zinc oxide (IGZO). In some embodiments, the active layer 15 covers the entire source layer 12, the insulating spacer layer 13, and the drain layer 14, and a portion of the region also covers the surface of the substrate 11, and the active layer 15 and the source layer 12 are respectively The sides of the drain layer 14 are electrically connected.

In the first embodiment, since the source layer 12 and the drain layer 14 are vertically arranged, the channel length L of the thin film transistor 10 depends on the thickness of the insulating spacer layer 13, and the thickness of the insulating spacer layer is generally 1 ~1.5μm, even smaller. Therefore, compared with the case where the channel length L of the general thin film transistor is about 7 μm in the background art, the channel length L of the thin film transistor can be remarkably reduced, so that the size of the thin film transistor 10 can be significantly larger than that of a general thin film transistor. The reduction, and thus the width of the gate drive circuit fabricated using the thin film transistor 10, can also be significantly reduced.

The manufacturing method of the thin film transistor 10 can take the following steps:

Forming a source layer 12 on the substrate 11;

Forming an insulating spacer layer 13 on the source layer 12;

Forming a drain layer 14 on the insulating spacer layer 13;

An active layer 15 is formed on the source layer 12, the insulating spacer layer 13 and the drain layer 14, and the active layer 15 electrically connects the source layer 12 and the drain layer 14;

Forming a gate insulating layer 16 on the active layer 15;

A gate layer 17 is formed on the gate insulating layer 16.

2 shows a thin film transistor 20 in a second embodiment of the present invention, which may include a substrate 21, a drain layer 22 disposed on the substrate 21, and an insulating spacer layer 23 disposed on the drain layer 22, disposed in the insulating layer. The source layer 24 on the spacer layer 23, the active layer 25 overlying the drain layer 22, the insulating spacer layer 23 and the source layer 24 and electrically connecting the drain layer 22 and the source layer 24 are disposed on the active layer A gate insulating layer 26 on the layer 25, and a gate layer 27 disposed on the gate insulating layer 26. The thin film transistor 20 is similar to the thin film transistor 10 of the first embodiment in that the upper and lower positions of the source layer and the drain layer are exchanged.

The manufacturing method of the thin film transistor 20 can take the following steps:

Forming a drain layer 22 on the substrate 21;

Forming an insulating spacer layer 23 on the drain layer 22;

Forming a source layer 24 on the insulating spacer layer 23;

An active layer 25 is formed on the drain layer 22, the insulating spacer layer 23, and the source layer 24, and the active layer 25 electrically connects the drain layer 22 and the source layer 24;

Forming a gate insulating layer 26 on the active layer 25;

A gate layer 27 is formed on the gate insulating layer 26.

3 shows a thin film transistor 30 in a third embodiment of the present invention. The thin film transistor 10 may include a substrate 31, a source layer 32 disposed on the substrate 31, and an insulating spacer layer 33 disposed on the source layer 32. a drain layer 34 disposed on the insulating spacer layer 33, an active layer 35 overlying the source layer 32, the insulating spacer layer 33 and the drain layer 34 and electrically connecting the source layer 32 and the drain layer 34, A gate insulating layer 36 on the active layer 35, and a gate layer 37 disposed on the gate insulating layer 36. In some embodiments, the active layer 35 may be made of a channel layer material such as indium gallium zinc oxide (IGZO).

The middle portion of the thin film transistor 30 further includes a dividing groove S1 extending from the outer surface of the gate layer 37 toward the substrate 31 to the drain layer 34, and the dividing groove S1 divides the active layer 35 into the first active layer 35a and the second layer. The active layer 35b divides the gate insulating layer 36 into a first gate insulating layer 36a and a second gate insulating layer 36b, and divides the gate layer 37 into a first gate layer 37a and a second gate layer 37b; The first active layer 35a and the second active layer 35b electrically connect the source layer 32 and the drain layer 34, respectively. Thus, two thin film transistor units sharing the source and drain are formed, and the circuit diagram thereof is as shown in FIG. That is to say, in the size of a conventional single thin film transistor, two thin film transistor units are provided, and the size of the gate driving circuit using the thin film transistor 30 can be further reduced. Therefore, the use of the secondary gate drive circuit of the thin film transistor 30 significantly reduces the space occupied by the conventional secondary gate drive circuit.

In addition, as can be seen from Fig. 5, the mechanical deformation performance is better in the flexible and stretchable display regions due to the presence of the dividing groove S1 on the thin film transistor 30. Particularly suitable for flexible displays.

The manufacturing method of the thin film transistor 30 can take the following steps:

Forming a source layer 32 on the substrate 31;

Forming an insulating spacer layer 33 on the source layer 32;

Forming a drain layer 34 on the insulating spacer layer 33;

An active layer 35 is formed on the source layer 32, the insulating spacer layer 33, and the drain layer 34, and the active layer 35 electrically connects the source layer 32 and the drain layer 34;

Forming a gate insulating layer 36 on the active layer 35;

Forming a gate layer 37 on the gate insulating layer 36;

Forming a dividing groove S1 extending from the outer surface of the gate layer 37 toward the substrate 31 to the drain layer 34, the dividing groove S1 dividing the active layer 35 into the first active layer 35a and the second active layer 35b, The pole insulating layer 36 is divided into a first gate insulating layer 36a and a second gate insulating layer 36b, and the gate layer 37 is divided into a first gate layer 37a and a second gate layer 37b; the first active layer 35a and The second active layer 35b electrically connects the source layer 32 and the drain layer 34, respectively.

6 shows a thin film transistor 40 in a fourth embodiment of the present invention. The thin film transistor 40 may include a substrate 41, a source layer 42 disposed on the substrate 41, and an insulating spacer layer 43 disposed on the source layer 42. a drain layer 44 disposed on the insulating spacer layer 43 and an active layer 45 covering the source layer 42, the insulating spacer layer 43 and the drain layer 44 and electrically connecting the source layer 42 and the drain layer 44 A gate insulating layer 46 on the active layer 45, and a gate layer 47 disposed on the gate insulating layer 46. In some embodiments, the active layer 45 may be made of a channel layer material such as indium gallium zinc oxide (IGZO).

The middle portion of the thin film transistor 40 further includes a dividing groove S2 extending from the outer surface of the gate layer 47 toward the substrate 41 to the insulating spacer layer 43. The dividing groove S2 divides the drain layer 44 into the first drain layer 44a and the second layer. The drain layer 44b divides the active layer 45 into the first active layer 45a and the second active layer 45b, and divides the gate insulating layer 46 into the first gate insulating layer 46a and the second gate insulating layer 46b, The gate layer 47 is divided into a first gate layer 47a and a second gate layer 47b; the first active layer 45a and the second active layer 45b respectively connect the source layer 42 with the first drain layer 44a and the second The drain layer 44b is electrically connected. Thus, two thin film transistor units of a common source are formed, and the circuit diagram thereof is as shown in FIG. Also, with the secondary gate drive circuit of the thin film transistor 40, the space occupied by the conventional secondary gate drive circuit is significantly reduced.

The manufacturing method of the thin film transistor 40 can take the following steps:

Forming a source layer 42 on the substrate 41;

Forming an insulating spacer layer 43 on the source layer 42;

Forming a drain layer 44 on the insulating spacer layer 43;

An active layer 45 is formed on the source layer 42, the insulating spacer layer 43, and the drain layer 44, and the active layer 45 electrically connects the source layer 42 and the drain layer 44;

Forming a gate insulating layer 46 on the active layer 45;

Forming a gate layer 47 on the gate insulating layer 46;

Forming a dividing groove S2 extending from the outer surface of the gate layer 47 toward the substrate 41 to the insulating spacer layer 43, the dividing groove S2 dividing the drain layer 44 into the first drain layer 44a and the second drain layer 44b, which will have The source layer 45 is divided into a first active layer 45a and a second active layer 45b, and the gate insulating layer 46 is divided into a first gate insulating layer 46a and a second gate insulating layer 46b, and the gate layer 47 is divided into The first gate layer 47a and the second gate layer 47b; the first active layer 45a and the second active layer 45b electrically connect the source layer 42 to the first drain layer 44a and the second drain layer 44b, respectively.

8 shows a thin film transistor 50 in a fifth embodiment of the present invention. The thin film transistor 50 may include a substrate 51, a source layer 52 disposed on the substrate 51, and an insulating spacer layer 53 disposed on the source layer 52. a drain layer 54 disposed on the insulating spacer layer 53, an active layer 55 overlying the source layer 52, the insulating spacer layer 53 and the drain layer 54 and electrically connecting the source layer 52 and the drain layer 54 A gate insulating layer 56 on the active layer 55, and a gate layer 57 disposed on the gate insulating layer 56. In some embodiments, the active layer 55 may be made of a channel layer material such as indium gallium zinc oxide (IGZO).

The middle portion of the thin film transistor 50 further includes a dividing groove S3 extending from the outer surface of the gate layer 57 toward the substrate 51 to the substrate 51. The dividing groove S3 divides the source layer 52 into the first source layer 52a and the second source. The layer 52b divides the insulating spacer layer 53 into a first insulating spacer layer 53a and a second insulating spacer layer 53b, and divides the drain layer 54 into a first drain layer 54a and a second drain layer 54b, and the active layer 55 Dividing into a first active layer 55a and a second active layer 55b, dividing the gate insulating layer 56 into a first gate insulating layer 56a and a second gate insulating layer 56b, and dividing the gate layer 57 into a first gate a second layer 57a and a second gate layer 57b; the first active layer 55a and the second active layer 55b respectively have the first source layer 52a and the second source layer 52b and the first drain layer 44a and the second drain The pole layer 44b is electrically connected. Thus, two independent thin film transistor units are formed, the circuit diagram of which is shown in FIG.

The manufacturing method of the thin film transistor 50 can take the following steps:

Forming a source layer 52 on the substrate 51;

Forming an insulating spacer layer 53 on the source layer 52;

Forming a drain layer 54 on the insulating spacer layer 53;

An active layer 55 is formed on the source layer 52, the insulating spacer layer 53, and the drain layer 54, and the active layer 55 electrically connects the source layer 52 and the drain layer 54;

Forming a gate insulating layer 56 on the active layer 55;

Forming a gate layer 57 on the gate insulating layer 56;

A dividing groove S3 extending from the outer surface of the gate layer 57 toward the substrate 51 to the substrate 51 is formed, the dividing groove S3 dividing the source layer 52 into the first source layer 52a and the second source layer 52b, separating the insulation The layer 53 is divided into a first insulating spacer layer 53a and a second insulating spacer layer 53b, and the drain layer 54 is divided into a first drain layer 54a and a second drain layer 54b, and the active layer 55 is divided into first active layers. The layer 55a and the second active layer 55b divide the gate insulating layer 56 into the first gate insulating layer 56a and the second gate insulating layer 56b, and divide the gate layer 57 into the first gate layer 57a and the second The gate layer 57b; the first active layer 55a and the second active layer 55b electrically connect the first source layer 52a and the second source layer 52b with the first drain layer 44a and the second drain layer 44b, respectively.

FIG. 10 shows a circuit diagram of a gate driving circuit with the thin film transistor 50. As can be seen from the figure, the gate drive circuit is a two-stage gate drive circuit. Since the second gate driving circuit uses the thin film transistor 50, it occupies only the space of the conventional primary gate driving circuit, and the space occupied by the conventional secondary gate driving circuit is significantly reduced.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation of the present invention and the contents of the drawings may be directly or indirectly applied to other related technologies. The fields are all included in the scope of patent protection of the present invention.

Claims

A thin film transistor characterized by comprising:

Substrate

One of a source layer and a drain layer, disposed on the substrate;

An insulating spacer layer disposed on one of the source layer and the drain layer;

Another one of the source layer and the drain layer is disposed on the insulating spacer layer;

An active layer covering one of the source layer and the drain layer, the insulating spacer layer, and the other of the source layer and the drain layer, and the source layer and the drain layer are One of the two is electrically connected to the other of the source layer and the drain layer;

a gate insulating layer disposed on the active layer;

A gate layer is disposed on the gate insulating layer.
The thin film transistor according to claim 1, wherein the thin film transistor further comprises a dividing groove extending from an outer surface of the gate layer toward a base direction to another of the source layer and the drain layer Forming two thin film transistor units sharing a source and a drain.
The thin film transistor according to claim 1, further comprising a dividing groove extending from the outer surface of the gate layer toward the substrate to the insulating spacer layer to form two common sources or drains A very thin film transistor unit.
The thin film transistor according to claim 1, wherein the thin film transistor further comprises a dividing groove extending from the outer surface of the gate layer toward the substrate toward the substrate to form two independent thin film transistor units.
The thin film transistor according to any one of claims 1 to 4, wherein the insulating spacer layer has a thickness of 1 to 1.5 μm.
A gate driving circuit comprising the thin film transistor according to any one of claims 1 to 5.
The gate driving circuit according to claim 6, wherein the gate driving circuit is a two-stage gate driving circuit.
A flat panel display comprising the gate drive circuit of claim 6 or 7.
The flat panel display of claim 8 wherein the flat panel display is a flexible display.
A method of manufacturing a thin film transistor, comprising the steps of:

Providing a substrate;

Forming one of a source layer and a drain layer on the substrate;

Forming an insulating spacer layer on one of the source layer and the drain layer;

Forming another one of the source layer and the drain layer on the insulating spacer layer;

Covering the active layer on one of the source layer and the drain layer, the insulating spacer layer, and the other of the source layer and the drain layer, the active layer is a source layer and a drain layer Another electrically conductive connection between the source layer and the drain layer;

Forming a gate insulating layer on the active layer;

A gate layer is formed on the gate insulating layer.
The method of manufacturing a thin film transistor according to claim 10, further comprising the step of forming another one of the source layer and the drain layer extending from the outer surface of the gate layer toward the substrate direction Split the slot.
The method of manufacturing a thin film transistor according to claim 10, further comprising the step of forming a dividing groove extending from the outer surface of the gate layer toward the base direction to the insulating spacer layer.
The method of manufacturing a thin film transistor according to claim 10, further comprising the step of forming a dividing groove extending from the outer surface of the gate layer toward the substrate toward the substrate.