JP2009070862A - Display device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device having a thin-film transistor for increasing source/drain currents without forming any amorphous semiconductor layer thinly. <P>SOLUTION: In a thin-film transistor TFT1 formed on the substrate of the display device, a thin-film transistor comprises a gate electrode GT formed on the substrate, a gate insulation film GI formed while covering the gate electrode, a pair of first-conductivity-type pseudo single crystal layers or polycrystalline layers placed side by side on the gate insulation film while being disconnected at least at the center of the gate electrode in a direction crossing the gate electrode, a second-conductivity-type pseudo single crystal layer or polycrystalline layer formed continuously on the pair of first-conductivity-type pseudo single crystal layers or polycrystalline layers and on the gate insulation film, an i-type amorphous semiconductor layer formed on it, and drain and source electrodes that are positioned on a lower layer and extended onto the gate insulation film for formation via a contact layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device and a manufacturing method thereof, and more particularly to a display device in which a thin film transistor is formed on a substrate and a manufacturing method thereof.

  A drive circuit having a plurality of pixels arranged in a matrix in a display area on a substrate as an active matrix type display device, and driving each pixel independently on the substrate around the display area A device in which (a scanning signal driving circuit, a video signal driving circuit) is formed is known.

  The display device having such a configuration sequentially selects each pixel arranged in each row direction, for example, in the column direction by a scanning signal from the scanning signal driving circuit via a gate signal line provided in common to the pixels. In accordance with the selection timing, a video signal is supplied from the video signal driving circuit to the selected pixels via drain signal lines provided in common to the pixels arranged in the column direction.

  For this reason, each of the pixels is provided with a thin film transistor that is turned on by the supply of the scanning signal and takes in the video signal to the pixel when the pixel is turned on. The structure is provided with a thin film transistor.

  In this case, a thin film transistor made of amorphous silicon is used for each pixel, and a thin film transistor made of polycrystalline silicon (Low Temperature Poly Si) obtained by crystallizing amorphous silicon is used for the drive circuit.

  This is because the driving circuit requires a thin film transistor with improved field effect mobility, and the thin film transistor made of polycrystalline silicon sufficiently satisfies this requirement.

An example of such a thin film transistor is disclosed in Patent Document 1 below.
JP-A-5-63196

  However, in the thin film transistor described in Patent Document 1, the pseudo single crystal layer disposed under the non-doped amorphous silicon layer functions as a substantial channel layer.

  Therefore, the so-called amorphous silicon layer is interposed between each of the drain electrode and the source electrode formed on the upper surface of the amorphous silicon layer via a contact layer and the pseudo single crystal layer, The resistance of the amorphous silicon layer has an effect as a series resistance.

  That is, when the voltage applied between the source electrode and the drain electrode is small, there is a disadvantage that the current flowing between the source electrode and the drain electrode is reduced by the resistance.

  In this case, it can be considered that the amorphous silicon layer is formed to have a small thickness to avoid the above-described disadvantages.

  However, a contact layer formed between each of the drain electrode and the source electrode formed on the upper surface of the amorphous silicon layer and the amorphous silicon layer is formed over the entire surface of the amorphous silicon layer, and the drain At the stage of forming the electrode and the source electrode, a manufacturing process for etching the contact layer exposed using the drain electrode and the source electrode as a mask is required.

  In this case, in order to electrically and completely separate the contact layer under the drain electrode and the contact layer under the source electrode, the contact layer is etched until the underlying amorphous silicon layer is sufficiently exposed.

  For this reason, there is a limit to reducing the thickness of the amorphous silicon layer, and the configuration for reducing the thickness of the amorphous silicon layer is not appropriate.

  An object of the present invention is to provide a display device including a thin film transistor in which a source / drain current is increased without forming an amorphous semiconductor layer thin.

  The objective of this invention is providing the manufacturing method of the display apparatus which can manufacture the said display apparatus, without causing the increase in a manufacturing man-hour.

   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

(1) The display device according to the present invention is, for example, a thin film transistor formed on a substrate of the display device, and the thin film transistor includes:
A gate electrode formed on the substrate;
A gate insulating film formed on the substrate also covering the gate electrode;
A pair of quasi-single crystal layers or polycrystalline layers of the first conductivity type arranged in parallel and intermittently at least at the central portion of the gate electrode in a direction intersecting the gate electrode on the gate insulating film;
The first conductive type quasi-single crystal layer or polycrystalline layer of the first conductivity type and the gate insulating film formed on the gate insulating film at the intermittent portion of the pair of first conductivity type quasi-single crystal layer or polycrystalline layer are continuously formed. A two-conductivity type pseudo single crystal layer or a polycrystalline layer;
An i-type amorphous semiconductor layer formed on the second conductivity type quasi-single crystal layer or polycrystalline layer;
The contact layer is positioned as a lower layer, and at least one of the first conductivity type pseudo single crystal layer or polycrystalline layer of the pair of first conductivity type pseudo single crystal layers or polycrystalline layers from the upper surface of the amorphous semiconductor layer. A drain electrode formed in contact with the side wall surface and extending on the gate insulating film;
Positioning the contact layer as a lower layer, the other first conductivity type pseudo single crystal layer or polycrystalline layer of the pair of first conductivity type pseudo single crystal layers or polycrystalline layers from the upper surface of the amorphous silicon layer A source electrode formed in contact with the wall surface and extending to the gate insulating film;
It is characterized by including the thing of the structure which consists of.

(2) The display device according to the present invention has, for example, a thin film transistor incorporated in a pixel and a thin film transistor incorporated in a drive circuit on a substrate of the display device,
The thin film transistor incorporated in the drive circuit is a thin film transistor having the configuration described in (1) above.

(3) The display device according to the present invention is based on, for example, the configuration of (2), and the thin film transistor incorporated in the pixel includes a gate electrode formed on the substrate,
A gate insulating film formed on the substrate also covering the gate electrode;
An i-type amorphous semiconductor layer formed on the upper surface of the gate insulating film;
A drain electrode and a source electrode formed on the upper surface of the amorphous semiconductor layer through a contact layer are provided.

(4) A display device according to the present invention is, for example, a display device including a switching element that performs video signal supply to each pixel in charge of red (R), green (G), and blue (B) by time-division driving. ,
The switch element is constituted by the thin film transistor described in (1).

(5) A method for manufacturing a display device according to the present invention is, for example, a thin film transistor formed on a substrate of a display device, and the thin film transistor includes:
Forming a gate electrode on the substrate;
Forming a gate insulating film overlying the gate electrode on the substrate;
Forming an amorphous semiconductor layer on the upper surface of the gate insulating film and making the amorphous semiconductor layer a pseudo single crystal layer or a polycrystalline layer;
Melting the pseudo single crystal layer or the polycrystalline layer and eliminating a step due to the gate electrode on the surface thereof;
The quasi-single crystal layer or the polycrystalline layer has a portion having a thickness larger than the surface of the gate insulating film formed on the gate electrode from the surface as a boundary surface, and the quasi-single crystal on the substrate side from the boundary surface A layer or a polycrystalline layer having a first conductivity type, and a pseudo single crystal layer or a polycrystalline layer on the surface side from the boundary surface being a second conductivity type;
Forming an i-type amorphous semiconductor layer on the upper surface of the pseudo single crystal layer or the polycrystalline layer;
A stack of the quasi-single crystal layer or polycrystalline layer and the i-type amorphous semiconductor layer is formed in an island shape, and the second conductivity type quasi formed by being intermittently formed on both sides of the gate electrode on the side wall surface thereof. A step of exposing each of the single crystal layer or the polycrystalline layer;
The quasi-single crystal layer or polycrystal layer and the i-type amorphous semiconductor layer formed in an island shape are electrically connected to at least each of the quasi-single crystal layer or polycrystal layer of the second conductivity type. And a device manufactured by a step of forming a drain electrode and a source electrode.

(6) A method for manufacturing a display device according to the present invention is based on the configuration of (5), for example, and a first conductivity type portion and a second conductivity type portion are formed in the pseudo single crystal layer or the polycrystalline layer. When
Doping the pseudo-single crystal layer or the polycrystalline layer with the first conductivity type impurity by matching the implantation peak from the surface to the thickest portion of the layer thickness,
The method is characterized in that the second conductive type impurity is doped by matching the implantation peak to the thickness portion from the surface to the surface of the gate insulating film formed on the gate electrode.

  In addition, this invention is not limited to the above structure, A various change is possible in the range which does not deviate from the technical idea of this invention.

  The display device configured as described above can form a thin film transistor in which the source / drain current is increased without forming a thin amorphous semiconductor layer.

  Further, it is possible to obtain a display device manufacturing method that can manufacture the display device without increasing the number of manufacturing steps.

  Embodiments of a display device according to the present invention will be described below with reference to the drawings.

<Schematic configuration of display device>
FIG. 8 is a schematic plan view showing a display device according to the present invention by taking a liquid crystal display device as an example.

  In FIG. 8, the liquid crystal display device uses, as an envelope, substrates SUB1 and SUB2 made of glass, for example, which are arranged to face each other with a liquid crystal layer interposed therebetween, and the liquid crystal layer is interposed between the substrates SUB1 and SUB2 by a sealing material (not shown). Is sealed.

  For example, on the liquid crystal side surface of the substrate SUB1, gate signal lines GL extending in the x direction in the drawing and arranged in parallel in the y direction, and drain signal lines extending in the y direction in the drawing and arranged in parallel in the x direction. DL is formed.

  A region surrounded by a pair of adjacent gate signal lines GL and a pair of adjacent drain signal lines DL is defined as a pixel region, and a liquid crystal display region AR is configured by an aggregate arranged in a matrix of these pixel regions. It is like that.

  The gate signal line GL is connected to the scanning signal drive circuit V at the left end in the figure, for example. For example, the scanning signal from the scanning signal driving circuit V is supplied to the gate signal line GL in the order of returning from the upper stage to the lower stage in the drawing.

  The drain signal line DL is connected to the video drive circuit He at the lower end in the figure, for example. The video signal from the video drive circuit He is supplied to the drain signal line DL in synchronization with the supply timing of the scanning signal.

  The scanning signal driving circuit V and the video signal driving circuit He are each composed of a shift register, and includes a plurality of thin film transistors THT1.

  Further, in the pixel region, as shown in FIG. A which is an enlarged view of the solid line frame α in the figure, the thin film transistor TFT2 which is turned on by the supply of the scanning signal from the gate signal line GL, and the turned on thin film transistor The pixel electrode PX to which the video signal from the drain signal line DL is supplied via the TFT 2, and the gate signal line GL adjacent to the pixel electrode PX and the pixel electrode PX, not the gate signal line for driving the thin film transistor TFT2. The capacitor element Cadd is connected to the other gate signal line GL.

  For example, the pixel electrode PX generates an electric field between a counter electrode (not shown) formed in common in each pixel region on the liquid crystal side surface of the substrate SUB2.

  In the liquid crystal display device configured as described above, in manufacturing the configuration on the substrate SUB1, the scanning signal driving circuit V and the video signal driving circuit He are usually formed in parallel with the configuration in the pixel region. As a result, the thin film transistor TFT1 and the thin film transistor TFT2 are also formed in parallel.

  Here, in this embodiment, the thin film transistor THT1 formed in the scanning signal drive circuit V and the video signal drive circuit He and the thin film transistor TFT2 formed in the pixel region are made of materials and structures in their gate insulating film and semiconductor layer. For this reason, the former thin film transistor is denoted by the reference numeral TFT1, and the latter thin film transistor is denoted by the numeral TFT2 for distinction.

<Configuration of Thin Film Transistor TFT1>
FIG. 1 is a cross-sectional view showing an embodiment of a thin film transistor TFT1 formed by being incorporated in the scanning signal driving circuit or the video signal driving circuit.

  In FIG. 1, there is a substrate SUB1, and a gate electrode GT is formed on the surface of the substrate SUB1. Although not shown, the gate electrode GT is formed integrally with a wiring connected to the gate electrode GT.

An insulating film GI made of, for example, SiO ₂ is formed on the surface of the substrate SUB1 so as to cover the gate electrode GT and the like. This insulating film GI functions as a gate insulating film.

  On the surface of the insulating film GI, the semiconductor layer SC is formed in an island shape so as to intersect the gate electrode, that is, in such a manner that the gate electrode GT is disposed across the center.

  The semiconductor layer SC has a configuration in which an n-type pseudo single crystal layer SC1, a p-type pseudo single crystal layer SC2, and an i type amorphous semiconductor layer SC3 are sequentially stacked from the insulating film GI side.

  Here, the n − type quasi-single crystal layer SC1 is formed without reaching the surface of the convex portion covered with the gate electrode GT of the insulating film, and is thus interrupted by the convex portion on both sides of the convex portion. Each is formed in a state. In other words, the n − type pseudo single crystal layer SC1 is separated in parallel at least at the central portion of the gate electrode GT in a direction intersecting with the gate electrode GT, and a pair of n type pseudo single crystal layers SC1 ( (Indicated by SC1a and SC1b in the figure).

  The p − type pseudo single crystal layer SC2 is also formed so as to cover the surfaces of the n − type pseudo single crystal layers SC1a and SC1b and the protrusions of the insulating film GI. In other words, the p-type pseudo single crystal layer SC2 is formed on the insulating film GI at the intermittent portion of the pair of p-type pseudo single crystal layers SC1a and SC1b and the pair of p-type pseudo single crystal layers SC1a and SC1b. Are formed continuously.

  Further, the i-type amorphous semiconductor layer SC3 is formed so as to cover the entire area of the p-type pseudo single crystal layer SC2.

  As described above, a part of the surface of the semiconductor layer SC composed of the sequential stacked body of the n-type pseudo single crystal layer SC1, the p-type pseudo single crystal layer SC2, and the i type amorphous semiconductor layer SC3, and the semiconductor layer SC side. An n + single crystal layer is formed on a part of the wall surface and the surface of the insulating film GI. The n + single crystal layer functions as a contact layer CNa formed at the interface between a drain electrode DT and the semiconductor layer SC, which will be described later, and a contact layer CNb formed at the interface between the source electrode ST and the semiconductor layer SC. It has become.

  That is, on the surface of the semiconductor layer SC, the drain electrode DT and the source electrode ST, which are arranged to face each other with the gate electrode GT interposed therebetween, respectively locate the contact layers CNa and CNb in the lower layer, respectively. The SC is formed to extend to the upper surface of the insulating film GI across the side wall surface of the SC.

  That is, the drain electrode DT is formed from the surface on one end side of the semiconductor layer SC to the side wall surface intersecting with the surface and the surface of the insulating film GI intersecting with the side wall surface, and the contact layer CNa includes the semiconductor layer It is formed between the surface of the SC and the drain electrode DT, between the sidewall surface of the semiconductor layer SC and the drain electrode DT, and between the surface of the insulating film GI and the drain electrode DT.

  Similarly, the source electrode ST is formed from the surface on the other end side of the semiconductor layer SC to the side wall surface intersecting with this surface and the surface of the insulating film GI intersecting with the side wall surface, and the contact layer CNb includes It is formed between the surface of the semiconductor layer SC and the source electrode ST, between the sidewall surface of the semiconductor layer SC and the source electrode ST, and between the surface of the insulating film GI and the source electrode ST.

  A recess DNT having a slight depth is formed on the surface of the i-type amorphous semiconductor layer exposed from the drain electrode DT and the source electrode ST, and etching is performed using the drain electrode DT and the source electrode ST as a mask. The contact layer is removed from the surface of the i-type amorphous semiconductor layer SC3 other than the region where the drain electrode DT and the source electrode ST are formed.

  The thin film transistor TFT formed in this way is formed by being covered with a protective film PAS.

  In such a thin film transistor TFT1, the n − type pseudo single crystal layers SC1a and SC1b are respectively connected to the p − type pseudo single crystal layer SC2 functioning as a channel layer, and the contact layer CNa and source of the drain electrode DT The electrode ST is configured to be connected to the contact layer CNb.

  Therefore, no large resistance is interposed between the drain electrode DT and the p − type pseudo single crystal layer SC2 and between the source electrode ST and the p − type pseudo single crystal layer SC2. Therefore, there is an effect that the source / drain current can be increased.

  Incidentally, FIG. 6 is a diagram showing an example of the configuration of a conventional thin film transistor, and the same reference numerals are given to portions having the same functions as those of the thin film transistor TFT1 of the present embodiment. The thin film transistor shown in FIG. 6 includes a drain electrode DT having a contact layer CNa interposed between a pseudo single crystal layer SC2 functioning as a channel layer and a source electrode ST having a contact layer CNb interposed between the pseudo single crystal layer SC2. An amorphous semiconductor layer SC2 is interposed therebetween, and this amorphous semiconductor layer SC2 becomes a resistance R, so that a large source / drain current cannot be obtained.

<Method for Manufacturing Thin Film Transistor TFT1>
2 and 3 are process diagrams showing an embodiment of a method of manufacturing the thin film transistor. Hereinafter, it demonstrates in order of a process.

Step 1. (Fig. 2 (a))
A substrate SUB1 made of glass is prepared, and a gate electrode GT and wiring (not shown) connected to the gate electrode GT are formed on the surface of the substrate SUB1.

  That is, for example, MoW is formed to a thickness of 50 nm to 100 nm by sputtering over the entire surface of the substrate SUB1, and the gate electrode GT and the like are formed by selective etching using a photolithography technique.

  Then, an insulating film GI made of SiO2 is formed to a thickness of 100 to 200 nm by CVD, covering the upper surface of the substrate SUB1 with the gate electrode GT and the like.

  Further, a semiconductor layer SC ′ made of amorphous Si (a-Si) is formed to 50 nm to 150 nm on the upper surface of the insulating film GI.

Step 2. (Fig. 2 (b))
The semiconductor layer SC ′ is subjected to, for example, laser annealing by a pseudo single crystal forming method to form a so-called pseudo single crystal layer. The laser annealing may be performed only on the region where the thin film transistor TFT is formed in the semiconductor layer SC ′ formed on the substrate SUB1.

  By this laser annealing, the semiconductor layer SC 'is melted, and the surface where the step is formed by the gate electrode GT is smoothed. As a result, the upper surface of the pseudo single crystal layer SC 'is formed in a substantially flat cross-sectional shape.

Step 3. (Fig. 2 (c))
An n-type impurity made of, for example, phosphorus is implanted into the pseudo single crystal layer SC ′. In this case, in the quasi-single crystal layer SC ′, the position where the film thickness is the largest from the surface (the part which is almost positioned on each end in the width direction of the gate electrode GT in the figure is, for example, t2). The n-type impurity is ion-implanted with an acceleration energy at which an implantation peak is obtained.

  Next, a p-type impurity made of boron, for example, is implanted into the pseudo single crystal layer SC '. In this case, in the pseudo single crystal layer SC ′, the acceleration energy at which the injection peak comes at a position corresponding to the bottom surface of the portion positioned on the gate electrode GT (the film thickness is, for example, t1 (<t2)). The p-type impurity is ion-implanted.

  As a result, in the quasi-single crystal layer SC ′, p is at a low concentration from the surface to a depth of about t1 (in fact, a portion slightly deeper than t1 as can be seen in the description of FIG. 4 later). A quasi-single crystal layer SC2 made of a type is formed, and a portion deeper than that is a quasi-single crystal layer SC1 made of a low concentration n-type (indicated by reference numerals SC1a and SC1b in the figure).

  That is, the low concentration n-type pseudo single crystal layer SC1 is formed on both sides in the width direction of the gate electrode GT, and the low concentration p type pseudo single crystal layer SC2 is the pseudo single crystal layers SC1a and SC1b. And is formed on the upper surface of the insulating film GI exposed between the pseudo single crystal layers SC1a and SC1b.

  FIG. 4 shows an example of the concentration distribution of each of the n-type impurity and the p-type impurity in the pseudo single crystal layer SC ′ when the n-type impurity and the p-type impurity are implanted into the pseudo single crystal layer SC ′. It is the shown graph.

  In the graph, the horizontal axis represents the depth (DP) from the surface of the pseudo single crystal layer SC ', and the vertical axis represents the impurity dose (DQ).

  In the implantation of the n-type impurity, the distribution of the n-type impurity at the time of implantation is a distribution shown by a curve a. The peak coincides with the position of the depth t2 from the surface of the pseudo single crystal layer SC '. Further, in the implantation of the p-type impurity, the distribution of the p-type impurity at the time of the implantation is a distribution shown by a curve b. Peaks coincide with each other at a depth t1 from the surface of the pseudo single crystal layer SC '.

  Then, after the implantation of the n-type impurity and the p-type impurity into the pseudo single crystal layer SC ′, the distribution of the n-type impurity concentration shown in the curve a ′ and the distribution of the n-type impurity and the p-type impurity are as follows: The distribution of the p-type impurity concentration shown by the curve b ′ is generated.

  As a result, a layer (pseudo single crystal layer SC2) showing a p-type region is formed from the surface of the pseudo single crystal layer SC ′ to a portion slightly deeper than t1, and the n type extends from that portion to the depth of t2. Layers indicating the regions (the pseudo single crystal layers SC1a and SC1b) are formed.

  The pseudo single crystal layers SC1a and SC1b thus formed can be formed in a self-aligned manner with respect to the gate electrode GT without using, for example, a photoresist film. For this reason, the number of manufacturing steps can be reduced, and inconvenience due to mask displacement can be eliminated.

Step 4. (Fig. 2 (d))
An amorphous semiconductor layer SC3 made of amorphous Si (a-Si) is formed on the upper surface of the substrate SUB1 so as to cover the semiconductor layer SC ′ by a CVD method, for example, to a thickness of about 150 nm.

  The amorphous semiconductor layer SC3, the low-concentration p-type quasi-single crystal layer SC2, and the low-concentration n-type quasi-single-crystal layers SC1a and SC1b are each etched in the same pattern by selective etching using a photolithography technique.

  Thereby, on the gate electrode GT, the sequential stacked body of the low concentration n-type pseudo single crystal layers SC1a and SC1b, the low concentration p type pseudo single crystal layer SC2 and the amorphous semiconductor layer SC3 is formed in an island shape. Form.

  In this case, at least each of the low-concentration n-type pseudo single crystal layers SC1a and SC1b is sufficiently exposed on the side wall surface of the stacked body.

Step 5. (Fig. 3 (a))
The upper surface of the substrate SUB1 is covered with a low-concentration n-type quasi-single crystal layer SC1a, SC1b, a low-concentration p-type quasi-single-crystal layer SC2, and an amorphous semiconductor layer SC3, and a high-concentration stack. The n-type semiconductor layer SC ″ is formed with a film thickness of 20 nm to 50 nm by using the CVD method. This high-concentration n-type semiconductor layer SC ″ is also formed on the side wall surface of the stacked body, and will be described later. And it functions as a contact layer formed at the interface with the source electrode ST.

Step 6. (Fig. 3 (b)))
A metal layer MT is formed on the upper surface of the high-concentration n-type semiconductor layer SC ″ by, for example, a sputtering method.

  The metal layer MT is formed as the drain electrode DT or the source electrode ST. For example, it is preferable to use a layer in which a barrier film made of Mo-based or Ti-based metal is used as a main component.

Step 7. (Fig. 3 (c))
Using a selective etching method by a photolithography technique, the metal layer MT is connected to the drain electrode DT, the wiring connected to the drain electrode DT (not shown), the source electrode ST, and the wiring connected to the source electrode ST (FIG. (Not shown).

   Thereafter, using the drain electrode DT and the source electrode ST as a mask, the high-concentration n-type semiconductor layer SC ″ formed exposed from the drain electrode DT and the source electrode ST is removed by etching.

  In this case, the amorphous semiconductor layer SC3 is over-etched so that the high-concentration n-type semiconductor layer SC ″ does not remain on the amorphous semiconductor layer SC3 between the drain electrode DT and the source electrode ST.

Step 8. (Fig. 3 (d))
A protective film PAS made of, for example, SiN is formed over the entire area of the substrate SUB1.

<Thin film transistor TFT2>
FIG. 5 is a cross-sectional view showing the thin film transistor TFT2 formed in the pixel region in comparison with the above-described thin film transistor TFT1.

  The right side of the figure shows the thin film transistor TFT2, and the left side of the figure shows the thin film transistor TFT1.

  In the thin film transistor TFT2, first, a gate electrode GT1 is formed on the surface of a substrate SUB1 made of glass, for example, and an insulating film GI made of a silicon nitride film is formed so as to cover the gate electrode GT1.

  On the upper surface of the insulating film GI, the amorphous silicon layer SC3 is formed in an island shape so as to straddle the gate electrode GT1.

  On the top surface of the amorphous silicon layer SC3, when viewed in a plan view, the drain electrode DT1 and the source electrode ST1 that overlap with the gate electrode GT1 and are spaced apart from each other at the tip end portion are connected to the drain electrode DT1 and the drain electrode DT1. A contact layer CNa1 made of a high-concentration n-type amorphous silicon layer is interposed at the interface of the amorphous silicon layer SC3, and a contact layer CNb1 made of a high-concentration n-type amorphous silicon layer is interposed at the interface between the source electrode ST1 and the amorphous silicon layer SC3. Is formed.

  The upper surface of the thin film transistor TFT2 thus formed is covered with a protective film PAS made of a silicon nitride film.

  The manufacture of the thin film transistor TFT2 differs from the manufacture of the thin film transistor TFT1 in that the formation of the pseudo single crystal layer SC '(see FIGS. 2A and 2B) is excluded.

  That is, the pseudo single crystal SC 'is selectively formed and processed in the formation region of the thin film transistor TFT1. Other than that, the corresponding members are formed and processed in parallel in the respective formation regions of the thin film transistors TFT1 and TFT2.

<Other Examples>
In the embodiment described above, the thin film transistor TFT1 having a semiconductor layer obtained by quasi-single-crystallizing an amorphous silicon layer is configured to be incorporated in a peripheral circuit for driving a pixel.

  However, when video signals are supplied to the pixels in charge of red (R), green (G), and blue (B) via the drain signal line DL, they are used for time division for supplying the video signals in a time division manner. In a display device incorporating switches SW (R), SW (G), and SW (B), the thin film transistor TFT1 is applied to the time-division switches SW (R), SW (G), and SW (B). You may make it make it.

  FIG. 7 is a plan view showing an outline of a display device in which the division switches SW (R), SW (G), and SW (B) are arranged, for example, on the lower side of the display area AR.

  In each pixel in the display area AR, for example, each pixel arranged in parallel in the y direction in the figure is responsible for a common color, and red (R), green (G), and blue (B) are assigned from the left side to the right side in the figure. Suppose you are in charge and repeat this step by step.

  In the figure, a video signal is supplied from the drain signal line DLc to the drain signal line DL (indicated by DL (R) in the figure) common to the pixels responsible for red (R) through the time division switch SW (R). It is like that. In addition, a video signal is supplied from the drain signal line DLc to the drain signal line DL (indicated by DL (G) in the figure) common to the pixels in charge of green (G) in the figure via the time division switch SW (G). It has come to be. Further, a video signal is supplied from the drain signal line DLc to the common drain signal line DL (indicated by DL (B) in the figure) via the time-division switch SW (B) to the pixel responsible for blue (B) in the figure. It has come to be.

  The time-division switches SW (R), SW (G), and SW (B) are turned on in order, for example, by supplying signals to their gate electrodes. In accordance with the timing, the video signal is supplied to the corresponding drain signal line DL through the drain signal line DLc.

  The display device configured as described above can be configured to be able to supply a video signal to each of the three drain signal lines DL through one drain signal line DLc from the video signal driving circuit (see FIG. 2). become.

  The thin film transistor TFT1 shown in the above-described embodiment is formed by forming a pseudo single crystal layer from an amorphous semiconductor layer as a part of the semiconductor layer, but is not limited to the pseudo single crystal layer and is a polycrystalline layer. Of course, you may.

  Although the thin film transistor TFT1 shown in the above-described embodiment has been described as an n-channel thin film transistor, it is needless to say that the present invention is not limited to this and may be a p-channel thin film transistor.

  In this case, the n− type pseudo single crystal layers SC1a and SC1b are p− type pseudo single crystal layers, the p− type pseudo single crystal layer SC2 is an n− type pseudo single crystal layer, and the contact layer is an n + single crystal layer. By using CNa and CNb as p + single crystal layers, a p-channel thin film transistor can be formed.

  Each of the embodiments described above may be used alone or in combination. This is because the effects of the respective embodiments can be achieved independently or synergistically.

It is sectional drawing which shows one Example of the thin-film transistor formed in the display apparatus by this invention. FIG. 4 is a process diagram illustrating an embodiment of a method of manufacturing a thin film transistor formed in a display device according to the present invention, and is a diagram illustrating the entire process together with FIG. 3. FIG. 3 is a process diagram showing an embodiment of a method of manufacturing a thin film transistor formed in a display device according to the present invention, and is a diagram showing all processes together with FIG. 2. It is the graph which showed the distribution at the time of doping an impurity in the process of the manufacturing method of the thin-film transistor shown in FIG. It is sectional drawing which showed the thin-film transistor formed in the display apparatus by this invention with another kind of thin-film transistor. It is sectional drawing which showed an example of the conventional thin-film transistor. It is explanatory drawing which showed the other Example of the display apparatus by this invention. It is the top view which showed the outline of the display apparatus by this invention.

Explanation of symbols

  SUB1, SUB2 ... Substrate, DL ... Drain signal line, GL ... Gate signal line, AR ... Display area, V ... Scanning signal drive circuit, He ... Video signal drive circuit, TFT1, TFT2 ... Thin film transistor, PX ... Pixel electrode, Cadd ... Capacitance element, GT ... Gate electrode, GI, GI1 ... Gate insulating film, SC1a, SC1b ... n-type pseudo single crystal layer, SC2 ... p-type pseudo single crystal layer , SC3... I-type amorphous silicon, CNa, CNb, CNa1, CNb1... Contact layer, DT, DT1... Drain electrode, ST, ST1... Source electrode, PAS .. protective film, SW (R), SW ( G), SW (B)... Time-division switching element.

Claims (6)

A thin film transistor formed on a substrate of a display device, wherein the thin film transistor is
A gate electrode formed on the substrate;
A gate insulating film formed on the substrate also covering the gate electrode;
A pair of quasi-single crystal layers or polycrystalline layers of the first conductivity type arranged in parallel and intermittently at least at the central portion of the gate electrode in a direction intersecting the gate electrode on the gate insulating film;
The first conductive type quasi-single crystal layer or polycrystalline layer of the first conductivity type and the gate insulating film formed on the gate insulating film at the intermittent portion of the pair of first conductivity type quasi-single crystal layer or polycrystalline layer are continuously formed. A two-conductivity type pseudo single crystal layer or a polycrystalline layer;
An i-type amorphous semiconductor layer formed on the second conductivity type quasi-single crystal layer or polycrystalline layer;
The contact layer is positioned as a lower layer, and at least one of the first conductivity type pseudo single crystal layer or polycrystalline layer of the pair of first conductivity type pseudo single crystal layers or polycrystalline layers from the upper surface of the amorphous semiconductor layer. A drain electrode formed in contact with the side wall surface and extending on the gate insulating film;
Positioning the contact layer as a lower layer, the other first conductivity type pseudo single crystal layer or polycrystalline layer of the pair of first conductivity type pseudo single crystal layers or polycrystalline layers from the upper surface of the amorphous silicon layer A source electrode formed in contact with the wall surface and extending to the gate insulating film;
A display device characterized by comprising a component comprising: A substrate of a display device has a thin film transistor incorporated in a pixel and a thin film transistor incorporated in a driver circuit,
2. A display device, wherein the thin film transistor incorporated in the drive circuit is a thin film transistor having the configuration according to claim 1. A thin film transistor incorporated in a pixel includes a gate electrode formed on the substrate,
A gate insulating film formed on the substrate also covering the gate electrode;
An i-type amorphous semiconductor layer formed on the upper surface of the gate insulating film;
The display device according to claim 2, further comprising a drain electrode and a source electrode formed on a top surface of the amorphous semiconductor layer via a contact layer. In a display device including a switching element that performs video signal supply to each pixel in charge of red (R), green (G), and blue (B) by time-division driving
The display device according to claim 1, wherein the switch element includes the thin film transistor according to claim 1. A thin film transistor formed on a substrate of a display device, wherein the thin film transistor is
Forming a gate electrode on the substrate;
Forming a gate insulating film overlying the gate electrode on the substrate;
Forming an amorphous semiconductor layer on the upper surface of the gate insulating film and making the amorphous semiconductor layer a pseudo single crystal layer or a polycrystalline layer;
Melting the pseudo single crystal layer or the polycrystalline layer and eliminating a step due to the gate electrode on the surface thereof;
The quasi-single crystal layer or the polycrystalline layer has a portion having a thickness larger than the surface of the gate insulating film formed on the gate electrode from the surface as a boundary surface, and the quasi-single crystal on the substrate side from the boundary surface A layer or a polycrystalline layer having a first conductivity type, and a pseudo single crystal layer or a polycrystalline layer on the surface side from the boundary surface being a second conductivity type;
Forming an i-type amorphous semiconductor layer on the upper surface of the pseudo single crystal layer or the polycrystalline layer;
A stack of the quasi-single crystal layer or polycrystalline layer and the i-type amorphous semiconductor layer is formed in an island shape, and the second conductivity type quasi formed by being intermittently formed on both sides of the gate electrode on the side wall surface thereof. A step of exposing each of the single crystal layer or the polycrystalline layer;
The quasi-single crystal layer or polycrystal layer and the i-type amorphous semiconductor layer formed in an island shape are electrically connected to at least each of the quasi-single crystal layer or polycrystal layer of the second conductivity type. What is manufactured by the process of forming the drain electrode and source electrode which are performed is shown, The manufacturing method of the display apparatus characterized by the above-mentioned. When forming the first conductivity type portion and the second conductivity type portion in the pseudo single crystal layer or the polycrystalline layer,
Doping the pseudo-single crystal layer or the polycrystalline layer with the first conductivity type impurity by matching the implantation peak from the surface to the thickest portion of the layer thickness,
6. The etching is performed by doping an impurity of the second conductivity type with an injection peak matched to a portion of the thickness from the surface to the surface of the gate insulating film formed on the gate electrode. The manufacturing method of the display apparatus as described in any one of.

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