WO2019144403A1 - 芯片的访问方法、安全控制模块、芯片和调试设备 - Google Patents

芯片的访问方法、安全控制模块、芯片和调试设备 Download PDF

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Publication number
WO2019144403A1
WO2019144403A1 PCT/CN2018/074451 CN2018074451W WO2019144403A1 WO 2019144403 A1 WO2019144403 A1 WO 2019144403A1 CN 2018074451 W CN2018074451 W CN 2018074451W WO 2019144403 A1 WO2019144403 A1 WO 2019144403A1
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WIPO (PCT)
Prior art keywords
chip
debugging device
authentication information
debugging
authentication
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PCT/CN2018/074451
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English (en)
French (fr)
Inventor
陈道宇
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深圳市汇顶科技股份有限公司
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Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201880000241.2A priority Critical patent/CN110337652B/zh
Priority to EP18875000.4A priority patent/EP3543881B1/en
Priority to PCT/CN2018/074451 priority patent/WO2019144403A1/zh
Priority to US16/416,125 priority patent/US11093600B2/en
Publication of WO2019144403A1 publication Critical patent/WO2019144403A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/44—Program or device authentication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/554—Detecting local intrusion or implementing counter-measures involving event detection and direct action
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/03—Indexing scheme relating to G06F21/50, monitoring users, programs or devices to maintain the integrity of platforms
    • G06F2221/034—Test or assess a computer or a system

Definitions

  • the present application relates to the field of electronic chip testing, and in particular, to a chip access method, a security control module, a chip, and a debugging device.
  • a chip is an integrated circuit that combines various electronic components on a silicon board to achieve a specific function. It is the most important part of an electronic device and functions as a computing and storage device. In recent years, integrated circuits have continued to evolve toward smaller form factors, allowing each chip to package more circuits, and the application of integrated circuits covers almost all electronic devices used in military and civilian applications. As the application of the chip becomes more and more extensive, debugging of the chip is also particularly important. However, there are some security risks when debugging, and some sensitive information in the chip is not expected to be accessed by the outside world. In the prior art, in order to eliminate these security risks, there are generally three methods: (1) Using jumper protection, the debug device can access the chip only after the correct jumper is shorted.
  • the chip is protected by a hardware irreversible circuit, and the non-reversible circuit is programmed at the factory to control whether the debug interface of the chip is turned on.
  • the debug device can debug the chip only if the open code written when the debug device is debugging the chip is correct.
  • the inventor has found that at least the following problems exist in the prior art: for the above method (1), the method of jumper protection is adopted, and the jumper connection mode is easily leaked. Once the jumper connection method is leaked, the debug device can be used to access sensitive information in the chip. , the security is weak.
  • the above method (2) the hardware irreversible circuit design is adopted. Once the non-reversible circuit is programmed and the debug interface is sealed, it cannot be opened any more, and the debugging of the chip can no longer be performed by the debugging device, which is not flexible enough.
  • For the above method (3) to write an open code in a specific register, manual operation is required, which is very cumbersome and inconvenient, and the open code must tell the user that the user cannot be compromised.
  • the security measures adopted by the debugging device to access the chip still lack certain security, convenience and flexibility.
  • the purpose of some embodiments of the present application is to provide a chip access method, a security control module, a chip, and a debugging device, which are beneficial to improving the security, convenience, and flexibility of the debugging device when accessing the chip.
  • An embodiment of the present application provides a method for accessing a chip, which is applied to a chip, including: after detecting a debugging device, triggering a security authentication on the debugging device, and a security card is inserted in the debugging device, and the first private card is pre-stored in the security card.
  • the first authentication information is obtained from the debugging device.
  • the first authentication information is the first authentication information generated by the debugging device based on the first private key.
  • the first authentication information is used to determine whether the debugging device passes the authentication. Turning on the debug interface allows the debug device to access the chip through the debug interface.
  • the embodiment of the present application further provides a method for accessing a chip, which is applied to a debugging device, including: a security card is inserted in the debugging device, and the method for accessing the chip includes: after detecting the chip, obtaining a first private pre-stored in the security card The first authentication information is generated based on the first private key; the first authentication information is sent to the chip, so that the chip determines whether the debugging device passes the authentication according to the first authentication information; and after the debugging device passes the authentication, the debugging is started by the chip.
  • the interface accesses the chip, wherein the debug interface is opened after the chip determines that the debug device passes the authentication.
  • the embodiment of the present application further provides a security control module, which is disposed in the chip, and includes: a detecting unit, an acquiring unit, a determining unit, and a control unit; and the detecting unit is configured to trigger a security authentication of the debugging device after detecting the debugging device.
  • a security card is inserted in the debugging device, and the first private key is stored in the security card;
  • the acquiring unit is configured to obtain the first authentication information from the debugging device, where the first authentication information is generated by the debugging device based on at least the first private key.
  • the first authentication information is used to determine whether the debugging device passes the authentication according to the first authentication information.
  • the control unit is configured to open the debugging interface when the debugging device passes the authentication, and allow the debugging device to access the chip through the debugging interface.
  • the embodiment of the present application further provides a chip, including the foregoing security control module.
  • the embodiment of the present application further provides a debugging device, including: a debugging interface, a security card slot, a processor, and a memory.
  • the processor is connected to the security card slot and the debug interface; the debug interface is also used to connect to the chip to be debugged.
  • the memory stores instructions executable by the processor, the instructions being executed by the at least one processor, and when the security card slot is inserted into the security card pre-stored with the first private key, the instructions are executed by the processor to enable the processor to execute The access method of the chip applied to the debug device.
  • the security authentication of the debugging device is triggered after the debugging device is detected, the security card is inserted into the debugging device, and the first private key is pre-stored in the security card; An authentication information, where the first authentication information is first authentication information generated by the debugging device based on the first private key; determining whether the debugging device passes the authentication according to the first authentication information; and if the debugging device passes the authentication, opening the debugging interface, allowing debugging The device accesses the chip through the debug interface. Since the chip can detect whether the debug device attempts to access the internal data of the chip through the debug interface, the chip triggers the secure authentication of the debug device after detecting the debug device.
  • the chip can determine whether the debugging device passes the authentication according to the first authentication information obtained from the debugging device. Since the first authentication information is generated by the debugging device based on at least the first private key, the confidentiality of the first private key is strong, and therefore, according to the first authentication.
  • the information determines whether the debugging device is authenticated, so that the security of the data in the chip is higher.
  • the debugging interface of the chip can be opened multiple times. Even if the debugging interface is closed after the last debugging, the debugging data can be accessed by the debugging device in the next debugging, and there is no debugging interface in the prior art. Close, you can't open it anymore. Therefore, compared with the prior art access method of the chip in the embodiment of the present application, the convenience and security are improved, and the flexibility is also improved.
  • determining whether the debugging device passes the authentication according to the first authentication information includes: generating second authentication information based on at least a second private key pre-stored in the chip; comparing the first authentication information with the second authentication information, and obtaining a ratio For the result; judge whether the debugging device passes the authentication according to the comparison result. Comparing the first authentication information generated based on the first private key pre-existing in the debugging device with the second authentication information generated based on the second private key stored in the chip, thereby determining whether the debugging device is authenticated according to the result of the comparison . Since the confidentiality of the first private key and the second private key are both strong, it is determined that the authentication is more secure according to the comparison result between the first authentication information and the second authentication information, thereby further improving the security of accessing the data in the chip.
  • the method further includes: generating a random number and sending the random number to the debugging device; wherein the first authentication information is specifically the first authentication generated by the debugging device based on the first private key and the random number And generating the second authentication information based on the second private key pre-stored in the chip, specifically: generating the second authentication information based on the second private key and the random number.
  • the first authentication information generated by the debugging device and the second authentication information generated by the chip are combined with the random number factor, and further, according to the ratio of the first authentication information to the second authentication information It is safer to judge whether the result is authenticated, and the security of accessing the data in the chip is further improved.
  • the method further includes: maintaining communication with the debugging device by using a heartbeat mechanism, and when detecting that the heartbeat packet is abnormal, the debugging interface is closed, and the debugging device is prohibited from accessing the chip through the debugging interface.
  • the heartbeat mechanism is used to maintain communication with the debugging device to ensure an effective connection between the debugging device and the chip.
  • the debugging interface is closed; that is, only the debugging interface is normally opened and the chip and the debugging device are always in an active connection state.
  • the debugging interface is kept open, the data in the chip can be prevented from being maliciously stolen after the debugging interface is normally opened, and the security of the data in the chip is ensured.
  • FIG. 1 is a schematic flow chart of a method for accessing a chip according to a first embodiment of the present application
  • FIG. 2 is a schematic flow chart of a method for accessing a chip according to a second embodiment of the present application
  • FIG. 3 is a schematic flowchart of a method for accessing a chip according to a third embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for accessing a chip according to a fourth embodiment of the present application.
  • FIG. 5 is a schematic flowchart diagram of a method for accessing a chip according to a fifth embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a method for accessing a chip according to a sixth embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a security control module according to a seventh embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a chip according to an eighth embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a debugging apparatus according to a ninth embodiment of the present application.
  • the access method of the chip in the first embodiment of the present application is applied to the chip; that is, the chip access method in this embodiment is a processing method performed by the chip when the debugging device accesses the chip.
  • the chip can be installed on the embedded development board, and the embedded development board includes a debugging interface connected to the chip; the debugging device also includes another debugging interface, and the debugging device and the chip are connected through two debugging interfaces.
  • the chip can be a system-on-chip ("SOC"), and the debugging device can be a JTAG (Joint Test Action Group, "JTAG”) device.
  • the debug interface is a JTAG interface.
  • a preset security card is inserted into the debugging device.
  • a card slot can be set on the debugging device, and the security card can be inserted into the debugging device through the card slot; the first private key is stored in the security card, preferably, The first private key can be generated by an encryption server of the chip manufacturer.
  • Step 101 After detecting the debugging device, triggering the security authentication of the debugging device.
  • the chip triggers the security authentication of the debugging device.
  • the debugging device sends an authentication trigger signal to the chip through the debugging interface when detecting that the security card is inserted and detecting the connection with the chip.
  • the chip in this embodiment includes multiple preset modes: a debug interface open mode, a security card authentication mode, and a debug interface shutdown mode. That is, the chip includes a non-reversible circuit (similar to the prior art, except that a switching mode is added) and a new security control module, and the non-reversible circuit can be switched to one of the above three modes (through different programming) The method is to program the irreversible circuit to achieve mode switching).
  • the debug device When the irreversible circuit is switched to the debug interface open mode, the debug device is allowed to access the internal data of the chip (similar to the prior art); when the irreversible circuit is switched to the secure card authentication mode, the security control module is activated to execute the present The chip access method of the embodiment; when switching to the debug interface shutdown mode, the debug device is prohibited from accessing the internal data of the chip (similar to the prior art). Three modes are available for the tester to select the appropriate mode as needed.
  • the switching order of the debug interface open mode, the security card authentication mode, and the debug interface closed mode is irreversible, that is, when in the debug interface open mode, the switch to the secure card authentication mode or the debug interface closed mode may be continued;
  • the security card authentication mode can be switched to the debug interface shutdown mode as needed; however, it is no longer possible to switch to the debug interface open mode; when switching to the debug interface shutdown mode, It is no longer possible to switch to debug interface open mode and security card authentication mode.
  • the chip described in this embodiment may also only include the security card authentication mode.
  • Step 102 Acquire first authentication information from the debugging device.
  • the first authentication information is the first authentication information that is generated by the debugging device based on the first private key, and the chip obtains the first authentication information from the debugging device.
  • the debugging device may send the first authentication information to the chip. For chip acquisition.
  • Step 103 Determine whether the debugging device passes the authentication according to the first authentication information, and if yes, execute step 104, otherwise the process ends.
  • the debugging device sends the first authentication information generated based on the first private key to the chip, and the chip determines, according to the first authentication information, whether the debugging device passes the authentication.
  • the chip can determine whether the debugging device passes the authentication according to whether the first authentication information is the same as the pre-stored information in the chip.
  • the first authentication information may be determined according to whether the first authentication information carries the correct model of the chip, and whether the debugging device passes the authentication.
  • the chip can also determine whether the first authentication information determines whether the debugging device passes the authentication according to whether the first authentication information is a certain type of information, for example, the type can be text, numbers, letters, symbols, or any combination thereof. .
  • Step 104 Open the debug interface, allowing the debug device to access the chip through the debug interface.
  • the chip can allow the debug device to access the chip with the preset authority through the debug interface.
  • the security card further stores preset permissions, and the preset permissions may be privileged permissions, system permissions, and user rights.
  • the privilege authority means that the debugging device can access all resources in the chip; the system authority refers to the debugging device can access the system resource except that the sensitive data cannot be accessed; the user authority refers to the debugging device can only access the user resource.
  • the chip is provided to developers, in order to facilitate research and development, the developer needs to access all the resources inside the chip, and the chip can be accessed through privilege.
  • the chip is only available to ordinary users, in order to ensure the security of sensitive data within the chip, the user is only allowed to access the chip through user rights. By setting different permissions, while ensuring security, it can also meet the different needs of different people, which greatly increases flexibility and practicability.
  • the chip since the chip can detect whether the debugging device attempts to access the internal data of the chip through the debugging interface, the chip triggers the security authentication of the debugging device after detecting the debugging device. In the entire authentication process of the debugging device, it is automatically completed after being triggered, without the intervention of the debugging personnel, which makes it more convenient to access the chip through the debugging device.
  • the prerequisite for the debugging device to pass the authentication is that the security card is inserted into the debugging device, and since the first private key is pre-stored in the security card, it will not be stolen by others, which makes the confidentiality stronger.
  • the chip can determine whether the debugging device passes the authentication according to the first authentication information obtained from the debugging device. Since the first authentication information is generated by the debugging device based on at least the first private key, the confidentiality of the first private key is strong, and therefore, according to the first authentication. The information determines whether the debugging device is more secure by the authentication chip.
  • the debugging interface of the chip can be opened multiple times. Even if the debugging interface is closed after the last debugging, the debugging data can be accessed by the debugging device in the next debugging, and there is no debugging interface in the prior art. Close, you can't open it anymore. Therefore, the access method of the chip relative to the prior art embodiment of the present application is advantageous for improving the security, convenience, and flexibility of the debug device accessing the chip.
  • the access method of the chip of the second embodiment of the present application is applied to a chip.
  • the second embodiment is a further improvement of the first embodiment, and the main improvement is that the second authentication information is generated based on at least the second private key pre-stored in the chip; the first authentication information is compared with the second authentication information, and The comparison result is obtained; whether the debugging device passes the authentication is judged according to the comparison result.
  • the specific flow of the method for accessing the chip in this embodiment is as shown in FIG. 2.
  • Step 201 After detecting the debugging device, triggering security authentication on the debugging device.
  • Step 202 Acquire first authentication information from the debugging device.
  • Step 203 Generate second authentication information based on at least a second private key pre-stored in the chip.
  • the second private key may be generated by an encryption server of the chip manufacturer and programmed in the chip, and the chip may generate the second authentication information based on at least the second private key.
  • the chip may perform operations such as adding, subtracting, multiplying, multiplying, and dividing the second private key in a preset manner to generate second authentication information.
  • the manner in which the debugging device generates the first authentication information and the manner in which the chip generates the second authentication information are maintained. Consistent.
  • the second private key is the same as the first private key.
  • the debugging device internally and the chip are pre-set with the same encryption algorithm, and the debugging device uses the encryption algorithm to perform encryption operation on the first private key to obtain the first authentication information; the chip uses the encryption algorithm to the second private key. Encryption operations are performed to generate second authentication information, thereby further enhancing the security and confidentiality effect.
  • step 202 there is no obvious relationship between the step 202 and the step 203.
  • This embodiment only provides an example, and is not limited thereto in practical applications.
  • Step 204 Compare the first authentication information with the second authentication information, and obtain a comparison result.
  • the chip may compare the first authentication information with the second authentication information.
  • the first private key and the second private key may be generated by an encryption server of the chip manufacturer, and the first private key and the first The second private key is the same.
  • the chip is simpler and faster in comparing the first authentication information with the second authentication information. Based on the above situation, the chip compares the first authentication information with the second authentication information, and obtains a comparison result, where the comparison result may be the same or different from the first authentication information and the second authentication information.
  • the first private key and the second private key may be set to be different, but the first authentication information generated based on the first private key and the second authentication information generated based on the second private key need to be determined in advance. Correspondence relationship, and the corresponding correspondence is stored in advance in the chip. Based on the above situation, the chip compares the first authentication information with the second authentication information, and the obtained comparison result may be a correspondence between the first authentication information and the second authentication information.
  • the first private key and the second private key are pre-encrypted and pre-stored in the security card and the chip in the form of a private key ciphertext, thereby further enhancing confidentiality.
  • Step 205 Determine, according to the comparison result, whether the debugging device passes the authentication, and if yes, execute step 206, otherwise the process ends.
  • the debugging device passes the authentication, and proceeds to step 206; otherwise, the debugging device does not After the certification, the chip cannot be accessed, and the process ends.
  • the debugging device passes the authentication, and proceeds to step 206; otherwise, the debugging device fails to pass the authentication. The chip cannot be accessed and the process ends.
  • Step 206 Open the debug interface, and allow the debug device to access the chip through the debug interface.
  • the embodiment of the present application compares the first authentication information generated based on the first private key pre-existing in the debugging device with the second authentication information generated based on the second private key stored in the chip. Therefore, according to the result of the comparison, it is judged whether the debugging device passes the authentication. Since the confidentiality of the first private key and the second private key are both strong, it is determined that the authentication is more secure according to the comparison result between the first authentication information and the second authentication information, thereby further improving the security of accessing the data in the chip.
  • the access method of the chip of the third embodiment of the present application is applied to a chip.
  • the third embodiment is a further improvement of the second embodiment, and the main improvement is that the factors of the random number are also combined when generating the first authentication information and the second authentication information.
  • Step 301 After detecting the debugging device, triggering security authentication on the debugging device.
  • Step 302 Generate a random number and send the random number to the debugging device.
  • the chip can generate a random number
  • the random number can be two types of random numbers of a character type and a numeric type
  • the character type can randomly generate a string of any length
  • the digital type generates a certain range of numbers
  • Step 303 Acquire first authentication information from the debugging device.
  • the first authentication information acquired by the chip from the debugging device is the first authentication information generated based on the first private key and the random number.
  • Step 304 Generate second authentication information based on the second private key and the random number.
  • the chip may generate the second authentication information based on the second private key and the random number pre-stored in the chip.
  • the second private key and the random number may be integrated in a preset manner (eg, the second private key is in front and the random number is in the back); wherein the debugging device generates the first authentication information and the chip generates the second The way to authenticate information is consistent.
  • the same encryption algorithm is pre-configured inside the debugging device and the chip, and the debugging device uses the encryption algorithm to perform encryption operation on the first private key and the random number to obtain the first authentication information; the chip uses the encryption algorithm to The second private key and the random number perform an encryption operation to generate second authentication information, thereby further enhancing the security and confidentiality effect.
  • step 303 there is no obvious relationship between the step 303 and the step 304.
  • This embodiment only provides an example, and is not limited thereto in practical applications.
  • Steps 305 to 307 are substantially the same as steps 204 to 206 in the second embodiment. To avoid repetition, details are not described herein again.
  • the embodiment of the present application by sending the random number generated by the chip to the debugging device, the first authentication information generated by the debugging device and the second authentication information generated by the chip are combined with the random number factor. Since random numbers are always generated randomly, it is possible to prevent others from easily guessing the authentication information according to a certain assumption, resulting in loss. In this embodiment, it is determined whether the authentication result is more secure according to the comparison result of the first authentication information and the second authentication information, and the security of accessing data in the chip is further improved.
  • the access method of the chip of the fourth embodiment of the present application is applied to a chip.
  • the fourth embodiment is a further improvement of the third embodiment.
  • the main improvement is that the communication device maintains communication with the debugging device through the heartbeat mechanism, and when the abnormality of the heartbeat packet is detected, the debugging interface is closed, and the debugging device is prohibited from being debugged through the debugging interface.
  • the chip is accessed.
  • FIG. 4 A specific process of the method for accessing the chip of the fourth embodiment of the present application is shown in FIG. 4 .
  • the step 401 of the step 401 is substantially the same as the step 301 to the step 307 in the embodiment. To avoid repetition, details are not described herein again.
  • Step 408 Maintain communication with the debugging device by using a heartbeat mechanism, and turn off the debugging interface when an abnormality of the heartbeat packet is detected.
  • the heartbeat mechanism is a mechanism for periodically transmitting a custom heartbeat packet to ensure the validity of the connection between the two parties. Therefore, the debugging device and the chip can communicate with the debugging device through the heartbeat mechanism.
  • the debugging device can send a heartbeat packet to the chip every preset time. If the chip receives the normal heartbeat packet, the debugging interface continues to be opened. If an abnormality is detected in the heartbeat packet, for example, the heartbeat packet is not received within the preset time, the debugging device is abnormal, or the debugging device is disconnected from the chip. At this time, the debugging interface is closed, and the debugging device is prohibited from passing. The debug interface accesses the chip.
  • the fourth embodiment of the present application uses a heartbeat mechanism to maintain communication with the debugging device to ensure an effective connection between the debugging device and the chip, and when the abnormality of the heartbeat packet is detected, the debugging interface is closed. Only when the debug interface is normally opened and the chip and the debug device are always in an active connection state, the debug interface will remain open, thereby preventing the data in the chip from being maliciously stolen after the debug interface is normally opened, and ensuring the data in the chip. safety.
  • the access method of the chip in the fifth embodiment of the present application is applied to the debugging device; that is, the chip access method in this embodiment is a processing method performed by the debugging device when the debugging device accesses the chip.
  • FIG. 5 A specific process of the method for accessing the chip of the fifth embodiment of the present application is shown in FIG. 5.
  • Step 501 After detecting the chip, obtain the first private key pre-stored in the security card.
  • the debug device detects the chip, it can be understood that the debug device is inserted into the embedded development board where the chip is located.
  • a security card is inserted in the debugging device, and the first private key is stored in the security card.
  • the first private key may be generated by an encryption server of the chip manufacturer, and the first private key is used to encrypt and decrypt the data.
  • the debugging device detects the chip, the first private key pre-stored in the security card can be obtained.
  • Step 502 Generate first authentication information based on at least the first private key.
  • the debugging device can generate the first authentication information based on at least the first private key only after the security card is inserted into the debugging device. That is to say, only if there is a security card and the security card is inserted on the debugging device, the debugging device may generate the first authentication information based on at least the first private key. If the security card is not available, the first private key cannot be obtained, and the debugging device cannot obtain the first authentication information based on the first private key.
  • Step 503 Send the first authentication information to the chip, so that the chip determines, according to the first authentication information, whether the debugging device passes the authentication.
  • the debugging device sends the first authentication information to the chip, and the chip determines whether the debugging device passes the authentication according to the first authentication information, and the chip determines whether the debugging device passes the authentication method on the chip.
  • the method embodiments for performing the main body are described in detail. To avoid repetition, details are not described herein again.
  • Step 504 After the debugging device passes the authentication, the chip is accessed through the debug interface opened by the chip.
  • the debug interface can be opened after the chip determines that the debug device is authenticated, so that the debug device can access the chip through the debug interface opened by the chip.
  • the access method of the chip in this embodiment is applied to the debugging device.
  • the access method of the chip in the first and second embodiments is applied to the chip.
  • This embodiment can be implemented in cooperation with the first and second embodiments.
  • the related technical details mentioned in the first and second embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related technical details mentioned in this embodiment can also be applied to the first and second embodiments.
  • the premise that the debugging device passes the authentication in the embodiment of the present application is that the security card is inserted into the debugging device, and the first private key is pre-stored in the security card, and the other party has no knowledge, so the confidentiality is improved.
  • the debugging device sends the first authentication information to the chip, and the chip determines whether the debugging device passes the authentication. Because the first authentication information is generated by the debugging device based on at least the first private key, the confidentiality of the first private key is strong, and therefore, according to the first authentication information. It is judged whether the debugging device is authenticated or not, so that the data in the chip is more secure.
  • the debugging interface of the chip can be opened multiple times.
  • the access method of the chip of the embodiment is advantageous for improving the security, convenience and flexibility of the debugging device to access the chip.
  • the method for accessing the chip of the sixth embodiment of the present application is applied to the debugging device.
  • the sixth embodiment is a further improvement of the fifth embodiment.
  • the main improvement is that the debugging device receives the random number sent by the chip, and is based on the random number and The first private key generates first authentication information.
  • FIG. 6 A specific process of the method for accessing the chip of the sixth embodiment of the present application is shown in FIG. 6.
  • Step 601 After detecting the chip, obtain the first private key pre-stored in the security card.
  • Step 602 Receive a random number sent by the chip.
  • the random number received by the debugging device is a random number generated by the chip in step 302 in the third embodiment, and the related description is detailed in step 302.
  • Step 603 Generate first authentication information based on the random number and the first private key.
  • the first authentication information may be generated based on the first private key and the random number.
  • the first private key and the random number may be integrated in a preset manner (eg, the first private key is in front and the random number is in the back); wherein the debugging device generates the first authentication information and the chip generates the second The way to authenticate information is consistent.
  • the same encryption algorithm is pre-configured inside the debugging device and the chip, and the debugging device uses the encryption algorithm to perform encryption operation on the first private key and the random number to obtain the first authentication information; the chip uses the encryption algorithm to The second private key and the random number perform an encryption operation to generate second authentication information, thereby further enhancing the security and confidentiality effect.
  • Step 604 Send the first authentication information to the chip, so that the chip determines, according to the first authentication information, whether the debugging device passes the authentication.
  • Step 605 After the debugging device passes the authentication, the chip is accessed through the debug interface opened by the chip.
  • the debug device and the chip can communicate with the debug device through a heartbeat mechanism.
  • the debugging device can send a heartbeat packet to the chip every preset time. If the chip receives the normal heartbeat packet, the debugging interface continues to be opened. If an abnormality is detected in the heartbeat packet, for example, the heartbeat packet is not received within the preset time, the debugging device is abnormal, or the debugging device is disconnected from the chip. At this time, the debugging interface is closed, and the debugging device is prohibited from passing. The debug interface accesses the chip. Therefore, it is possible to prevent the data in the chip from being maliciously stolen after the debug interface is normally opened, thereby ensuring the security of the data in the chip.
  • the access method of the chip in this embodiment is applied to the debugging device, and the access method of the chip in the third and fourth embodiments is applied to the chip.
  • This embodiment can be implemented in cooperation with the second to fourth embodiments. .
  • the related technical details mentioned in the third and fourth embodiments are still effective in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in this embodiment can also be applied to the third and fourth embodiments.
  • the seventh embodiment of the present invention relates to a security control module, which is disposed in a chip.
  • the detection unit 701 includes an detecting unit 701, an obtaining unit 702, a determining unit 703, and a control unit 704.
  • the detecting unit 701 is configured to trigger the security authentication of the debugging device after detecting the debugging device, and the security device is inserted into the debugging device, and the preset first private key is stored in the security card.
  • the obtaining unit 702 is configured to obtain first authentication information from the debugging device, where the first authentication information is first authentication information generated by the debugging device based on at least the first private key.
  • the determining unit 703 is configured to determine, according to the first authentication information, whether the debugging device passes the authentication.
  • the control unit 704 is configured to open the debug interface when the debug device passes the authentication, and allows the debug device to access the chip through the debug interface.
  • the security control module includes a switch for controlling the opening of the debugging interface; when the debugging device passes the authentication, the control unit 704 controls the switch to close to turn on the access path, that is, the debugging interface is opened, and the debugging device is allowed to pass.
  • the debug interface accesses the chip.
  • this embodiment is an apparatus embodiment corresponding to the first embodiment, and this embodiment can be implemented in cooperation with the first embodiment.
  • the related technical details mentioned in the first embodiment are still effective in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in the embodiment can also be applied to the first embodiment.
  • each unit involved in this embodiment is a logical unit.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical entities.
  • a combination of units is implemented.
  • the present embodiment does not introduce a unit that is not closely related to solving the technical problem proposed by the present application, but this does not indicate that there are no other units in this embodiment.
  • the eighth embodiment of the present application relates to a chip, as shown in FIG. 8, including the security control module in the seventh embodiment.
  • the chip 801 includes a security control module 802.
  • the chip 801 may further include: a non-reversible circuit 803, a random number module 804; the non-reversible circuit 803 and the random number module 804 are both connected to the security control module 802.
  • the non-reversible circuit 803 includes three programming modes: a debug interface open mode, a security card authentication mode, and a debug interface shutdown mode; when the irreversible circuit 803 is programmed into the secure card authentication mode, the security control module 801 is activated, and is controlled by the control unit. 704 controls the opening or closing of the switch according to the judgment result of the judgment unit 703.
  • the random number module 804 is configured to generate a random number and is obtained by the security control module 802.
  • the debug interface 805 is connected to the chip 801.
  • the debug interface 805 is a debug interface connected to the chip on the embedded development board, and is used for connecting the debug device to the chip to be debugged.
  • the irreversible circuit 803 when programmed to be the debug interface open mode, the non-reversible circuit 803 directly controls the switch to be in a closed state to turn on the access path; when the irreversible circuit 803 is programmed to be the debug interface off mode, the irreversible circuit 803 directly The control switch is on to disconnect the access path.
  • the chip provided by the embodiment of the present application makes other debugging devices more secure, convenient, and flexible when debugging the chip.
  • the ninth embodiment of the present application relates to a debugging device.
  • the debugging device 901 includes a debug interface 901, a security card slot 902, a processor 903, and a memory 904.
  • the processor 903 is connected to the security card slot 902 and the debug interface 901; the debug interface 901 is also used to connect to the chip to be debugged.
  • the memory 904 stores instructions executable by the processor 903, and the instructions are executed by the at least one processor 903. When the security card slot 902 is inserted into the security card pre-stored with the first private key, the instructions are executed by the processor 903 to The processor 903 is enabled to execute an access method applied to the chip of the debug device.
  • the security card slot is set on the debugging device provided by the embodiment of the present application, and after inserting the security card pre-stored with the first private key, the processor may perform the access method of the chip applied to the debugging device.
  • the first authentication information is generated based on the first private key, and the chip determines, according to the first authentication information, whether the debugging device can access data inside the chip.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

Abstract

本申请部分实施例提供了一种芯片的访问方法、安全控制模块、芯片和调试设备。芯片的访问方法，应用于芯片，包括：在检测到调试设备后，触发对调试设备的安全认证，调试设备上插有安全卡，安全卡内预存有第一私钥；从调试设备获取第一认证信息，第一认证信息为调试设备至少基于第一私钥生成的第一认证信息；根据第一认证信息判断调试设备是否通过认证；如果调试设备通过认证，则将调试接口打开，允许调试设备通过调试接口对芯片进行访问。采用本申请的实施例，有利于提高调试设备访问芯片时的安全性、方便性和灵活性。

Description

芯片的访问方法、安全控制模块、芯片和调试设备 技术领域
本申请涉及电子芯片测试领域，特别涉及一种芯片的访问方法、安全控制模块、芯片和调试设备。
背景技术
芯片是指在硅板上集合多种电子元器件实现某种特定功能的集成电路，它是电子设备中最重要的部分，承担着运算和存储的功能。近年来，集成电路持续向更小的外型尺寸发展，使得每个芯片可以封装更多的电路，而集成电路的应用范围覆盖了军工、民用中使用的几乎所有的电子设备。随着芯片的应用越来越广泛，对于芯片的调试也显得尤为重要。但在调试的同时会存在一些安全隐患，对于芯片中的一些敏感的信息是不希望被外界访问到的。而现有技术中为了消除这些安全隐患通常采用的方法有三种：(1)采用跳线保护，只有正确的跳线短接后，调试设备才能访问芯片。(2)芯片中采用硬件不可逆电路进行保护，在出厂时通过烧写不可逆电路，来控制芯片的调试接口是否打开。(3)通过在芯片中的特定寄存器中写一段打开码，只有在调试设备对芯片进行调试时写入的打开码是正确的情况下，调试设备才能对芯片进行调试。
发明人发现现有技术至少存在以下问题：对于上述方法(1)采用跳线保护的方法，很容易泄露跳线连接方式，一旦跳线连接方式泄露，就可以用调试设备访问芯片中的敏感信息，安全性较弱。对于上述方法(2)采用硬件不可逆 电路设计，一旦烧写不可逆电路，把调试接口封死，就不能再打开，不能再通过调试设备进行对芯片进行调试，不够灵活。对于上述方法(3)在特定寄存器中写一段打开码，需要手动操作，非常繁琐不够方便，而且打开码必须告诉使用者，无法保证使用者不泄密。总之，现有技术中，调试设备访问芯片采用的安全措施，依然缺乏一定的安全性、方便性和灵活性。
发明内容
本申请部分实施例的目的在于提供一种芯片的访问方法、安全控制模块、芯片和调试设备，有利于提高调试设备访问芯片时的安全性、方便性和灵活性。
本申请实施例提供了一种芯片的访问方法，应用于芯片，包括：在检测到调试设备后，触发对调试设备的安全认证，调试设备上插有安全卡，安全卡内预存有第一私钥；从调试设备获取第一认证信息，第一认证信息为调试设备至少基于第一私钥生成的第一认证信息；根据第一认证信息判断调试设备是否通过认证；如果调试设备通过认证，则将调试接口打开，允许调试设备通过调试接口对芯片进行访问。
本申请实施例还提供了一种芯片的访问方法，应用于调试设备，包括：调试设备上插有安全卡，芯片的访问方法包括：在检测到芯片后，获取安全卡内预存的第一私钥；至少基于第一私钥生成第一认证信息；将第一认证信息发送至芯片，以供芯片根据第一认证信息判断调试设备是否通过认证；在调试设备通过认证后，通过芯片打开的调试接口对芯片进行访问，其中，调试接口在芯片判断出调试设备通过认证后被打开。
本申请实施例还提供了一种安全控制模块，设置于芯片内，包括：检测 单元、获取单元、判断单元、控制单元；检测单元用于在检测到调试设备后，触发对调试设备的安全认证，调试设备上插有安全卡，安全卡内存储有预设的第一私钥；获取单元用于从调试设备获取第一认证信息，第一认证信息为调试设备至少基于第一私钥生成的第一认证信息；判断单元用于根据第一认证信息判断调试设备是否通过认证；控制单元用于在调试设备通过认证时将调试接口打开，允许调试设备通过调试接口对芯片进行访问。
本申请实施例还提供了一种芯片，包括上述的安全控制模块。
本申请实施例还提供了一种调试设备，包括：调试接口、安全卡插槽、处理器以及存储器。处理器连接于安全卡插槽和调试接口；调试接口还用于连接至待调试的芯片。存储器中储存有可被处理器执行的指令，指令被至少一个处理器执行，当安全卡插槽内插入预存有第一私钥的安全卡时，指令被处理器执行，以使处理器能够执行应用于调试设备的芯片的访问方法。
本申请实施例现对于现有技术而言，在检测到调试设备后，触发对调试设备的安全认证，调试设备上插有安全卡，安全卡内预存有第一私钥；从调试设备获取第一认证信息，第一认证信息为调试设备至少基于第一私钥生成的第一认证信息；根据第一认证信息判断调试设备是否通过认证；如果调试设备通过认证，则将调试接口打开，允许调试设备通过调试接口对芯片进行访问。由于芯片可以检测到是否有调试设备试图通过调试接口访问芯片内部数据，因此芯片在检测到调试设备后，会触发对调试设备的安全认证。在对调试设备的整个认证过程中，都是被触发后自动完成，无需调试人员介入，使得在通过调试设备对芯片进行访问时更加方便。要使调试设备通过认证的前提是，调试设备上插入安全卡，而且由于安全卡中预存有第一私钥，因此他人无从得知，保密 性得到提高。芯片可以根据从调试设备获取的第一认证信息判断调试设备是否通过认证，由于第一认证信息为调试设备至少基于第一私钥生成，第一私钥的保密性很强，因此根据第一认证信息判断调试设备是否通过认证，使得芯片内数据的安全性更高。芯片的调试接口可以被多次打开，即使上次调试结束关闭了调试接口，下次调试时只要调试设备通过认证，就可以访问到芯片内部的数据，并不存在现有技术中只要把调试接口关闭，就不能再打开的情况。因此，相对与现有技术本申请实施例中的芯片的访问方法，在提高了方便性、安全性的同时，还提高了灵活性。
另外，根据第一认证信息判断调试设备是否通过认证，具体包括：至少基于芯片内预存的第二私钥生成第二认证信息；将第一认证信息与第二认证信息进行比对，并得到比对结果；根据比对结果判断调试设备是否通过认证。通过将基于预存在调试设备的第一私钥生成的第一认证信息与基于芯片内存储的第二私钥生成的第二认证信息进行比对，从而根据比对的结果判断调试设备是否通过认证。由于第一私钥与第二私钥的保密性都较强，因此根据第一认证信息与第二认证信息的比对结果判断是否通过认证更加安全，进一步提高了访问芯片内数据的安全性。
另外，在触发对调试设备的安全认证之后，还包括：生成随机数并将随机数发送至调试设备；其中，第一认证信息具体为调试设备基于第一私钥和随机数生成的第一认证信息；至少基于芯片内预存的第二私钥生成第二认证信息，具体为：至少基于第二私钥和随机数生成第二认证信息。将芯片生成的随机数发送给调试设备，调试设备生成的第一认证信息与芯片生成的第二认证信息中均结合了随机数的因素，进一步使得根据第一认证信息与第二认证信息的比对 结果判断是否通过认证更加安全，更进一步提高了访问芯片内数据的安全性。
另外，在将调试接口打开之后，还包括：通过心跳机制与调试设备保持通信，并在检测到心跳包出现异常时，将调试接口关闭，禁止调试设备通过调试接口对芯片进行访问。采用心跳机制与调试设备保持通信以确保调试设备与芯片的有效连接，在检测到心跳包出现异常时，将调试接口关闭；即，只有调试接口被正常打开且芯片与调试设备始终处于有效连接状态时，调试接口才会保持在打开状态，从而能够避免调试接口在正常打开后芯片内的数据被恶意窃取，保证了芯片内数据的安全性。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例的芯片的访问方法的流程示意图；
图2是根据本申请第二实施例的芯片的访问方法的流程示意图；
图3是根据本申请第三实施例的芯片的访问方法的流程示意图；
图4是根据本申请第四实施例的芯片的访问方法的流程示意图；
图5是根据本申请第五实施例的芯片的访问方法的流程示意图；
图6是根据本申请第六实施例的芯片的访问方法的流程示意图；
图7是根据本申请第七实施例的安全控制模块的结构示意图；
图8是根据本申请第八实施例的芯片的结构示意图；
图9是根据本申请第九实施例的调试设备的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例的芯片的访问方法，应用于芯片；即，本实施例的芯片访问方法，为调试设备对芯片进行访问时，芯片所做的处理方法。其中，芯片可以安装在嵌入式开发板上，且嵌入式开发板上包括与芯片连接的一个调试接口；调试设备也包括另一个调试接口，且调试设备与芯片通过两个调试接口连接。芯片可以为系统级芯片(System on Chip，简称“SOC”)，调试设备可以为JTAG(Joint Test Action Group，国际标准测试协议，简称“JTAG”)设备，此时，调试接口为JTAG接口。本实施例中，调试设备上插入预设的安全卡，如调试设备上可以设置卡槽，安全卡可以通过卡槽插在调试设备中；安全卡内存储有第一私钥，较佳的，第一私钥可以由芯片出厂商的加密服务器产生。
本实施例的芯片的访问方法的具体流程如图1所示。
步骤101：在检测到调试设备后，触发对调试设备的安全认证。
具体地说，芯片检测到调试设备发送的认证触发信号后，触发对调试设备的安全认证。其中，调试设备在检测到插入安全卡且检测到与芯片连接时，会通过调试接口发送认证触发信号至芯片。
较佳的，本实施例中的芯片包括多种预设模式：调试接口打开模式、安全卡认证模式、调试接口关闭模式。即，芯片中包括不可逆电路(与现有技术相似，只是增加了一种切换模式)以及新增的安全控制模块，不可逆电路可以 被切换至上述三种模式中的一种(通过不同的烧写方式对不可逆电路进行烧写来实现模式切换)。当不可逆电路被切换至调试接口打开模式时，允许调试设备对芯片内部数据的访问(与现有技术类似)；当不可逆电路被切换至安全卡认证模式时，启动安全控制模块，以可以执行本实施例的芯片访问方法；当切换至调试接口关闭模式时，禁止调试设备对芯片内部数据的访问(与现有技术类似)。提供三种模式可选，可以供测试人员根据需要选择相应的模式。
需要说明的时，调试接口打开模式、安全卡认证模式、调试接口关闭模式的切换顺序具有不可逆性，即，当处于调试接口打开模式时，可以继续切换至安全卡认证模式或调试接口关闭模式；当由调试接口打开模式切换至安全卡认证模式后，还可以根据需要，由安全卡认证模式切换至调试接口关闭模式；但是无法再切换至调试接口打开模式；当切换至调试接口关闭模式后，无法再切换至调试接口打开模式和安全卡认证模式。
然不限于此，本实施例所述的芯片也可以仅包含安全卡认证模式。
步骤102：从调试设备获取第一认证信息。
具体地说，第一认证信息为调试设备至少基于第一私钥生成的第一认证信息，芯片从调试设备获取该第一认证信息；或者，调试设备生成第一认证信息后可以主动发送至芯片，以供芯片获取。
步骤103：根据第一认证信息判断调试设备是否通过认证，如果是，则执行步骤104，否则该流程结束。
具体地说，调试设备将至少基于第一私钥生成的第一认证信息发送给芯片，芯片根据第一认证信息判断调试设备是否通过认证。比如说，芯片可以根据第一认证信息是否和芯片中预存的信息相同，来判断第一认证信息判断调试 设备是否通过认证。再比如说，可以根据第一认证信息是否携带所述芯片的正确型号，来判断第一认证信息判断调试设备是否通过认证。再比如说，芯片还可以根据第一认证信息是否为某种预设类型的信息来判断第一认证信息判断调试设备是否通过认证，比如说类型可以为文字、数字、字母、符号或其任意组合。
步骤104：将调试接口打开，允许调试设备通过调试接口对芯片进行访问。
具体地说，调试接口打开后，芯片可以允许调试设备通过调试接口以预设权限对芯片进行访问。优选的，安全卡内还存储有预设权限，预设权限可以为特权权限、系统权限、用户权限。其中，特权权限是指调试设备可以访问芯片内一切资源；系统权限指的是调试设备除敏感数据不能访问外，可访问系统资源；用户权限指的是调试设备只能访问用户资源。比如说，如果芯片是提供给研发人员使用的，为了便于研发，研发人员需要访问芯片内部的一切资源，就可以通过特权权限对芯片进行访问。如果芯片只是提供给普通用户使用，为了保证芯片内敏感数据的安全性，只允许用户通过用户权限对芯片进行访问。通过设置不同的权限，在保证安全性的同时，还能满足不同人员的不同需求，使得灵活性和实用性也大大提高。
相对于现有技术而言，本申请实施例由于芯片可以检测到是否有调试设备试图通过调试接口访问芯片内部数据，因此芯片在检测到调试设备后，会触发对调试设备的安全认证。在对调试设备整个的认证过程中，都是被触发后自动完成，无需调试人员介入，使得在通过调试设备对芯片进行访问时更加方便。要使调试设备通过认证的前提是，调试设备上插入安全卡，而且由于安全卡中 预存有第一私钥，不会被他人窃取，使得保密性更强。而且私钥加密速度较快(与公钥算法相比)，特别适用于对较大的数据流执行加密操作。芯片可以根据从调试设备获取的第一认证信息判断调试设备是否通过认证，由于第一认证信息为调试设备至少基于第一私钥生成，第一私钥的保密性很强，因此根据第一认证信息判断调试设备是否通过认证芯片安全性更高。芯片的调试接口可以被多次打开，即使上次调试结束关闭了调试接口，下次调试时只要调试设备通过认证，就可以访问到芯片内部的数据，并不存在现有技术中只要把调试接口关闭，就不能再打开的情况。因此，相对与现有技术本申请实施例的芯片的访问方法有利于提高调试设备访问芯片的安全性、方便性和灵活性。
本申请第二实施例的芯片的访问方法，应用于芯片。第二实施例是第一实施例的进一步改进，主要改进之处在于：至少基于芯片内预存的第二私钥生成第二认证信息；将第一认证信息与第二认证信息进行比对，并得到比对结果；根据比对结果判断调试设备是否通过认证。本实施例中的芯片的访问方法的具体流程如图2所示。
步骤201：在检测到调试设备后，触发对调试设备的安全认证。
步骤202：从调试设备获取第一认证信息。
步骤203：至少基于芯片内预存的第二私钥生成第二认证信息。
其中，第二私钥可以由芯片出厂商的加密服务器产生，并烧写在芯片中，芯片可以至少基于第二私钥生成第二认证信息。比如说，芯片可以对第二私钥以预设的方式进行加减乘除等运算，以生成第二认证信息；其中，调试设备生成第一认证信息的方式与芯片生成第二认证信息的方式保持一致。较佳的，本实施例中，第二私钥与第一私钥相同。
较佳的，调试设备内部和芯片内部还预设有相同的加密算法，调试设备利用加密算法，对第一私钥进行加密运算，以得到第一认证信息；芯片利用加密算法对第二私钥进行加密运算，以生成第二认证信息，从而进一步增强安全保密效果。
需要说明的是步骤202与步骤203并无明显的先后关系，本实施例只是提供一个例子，在实际应用中并不以此为限。
步骤204：将第一认证信息与第二认证信息进行比对，并得到比对结果。
具体地说，芯片可以将第一认证信息与第二认证信息进行比对，优选的，第一私钥和第二私钥都可以为芯片出厂商的加密服务器产生，而且第一私钥和第二私钥相同。第一私钥和第二私钥相同也使得芯片在将第一认证信息与第二认证信息进行比对时，运算较简单且速度较快。基于上述情况，芯片将第一认证信息与第二认证信息进行比对，并得到比对结果，比对结果可以为第一认证信息与第二认证信息相同或不同。
需要说明的是，也可以将第一私钥和第二私钥设定为不相同，但需要提前确定基于第一私钥生成的第一认证信息与基于第二私钥生成的第二认证信息的对应关系，并将该对应预先存储至芯片中。基于上述情况，芯片将第一认证信息与第二认证信息进行比对，得到的比对结果可以为第一认证信息与第二认证信息的对应关系。
较佳的，第一私钥和第二私钥都可以进行预先加密，以私钥密文的形式分别预存在安全卡和芯片中，从而进一步增强保密性。
步骤205：根据比对结果判断调试设备是否通过认证，如果是则执行步骤206，否则该流程结束。
具体地说，如果第一私钥和第二私钥相同，在比对结果中若第一认证信息与第二认证信息相同，则判定调试设备通过认证，进入步骤206，否则，该调试设备未通过认证，不能访问芯片，该流程结束。
如果第一私钥和第二私钥不相同，在比对结果中若对应关系与上述提前确定的对应关系相同，则判定调试设备通过认证，进入步骤206，否则，该调试设备未通过认证，不能访问芯片，该流程结束。
步骤206：将调试接口打开，允许调试设备通过调试接口对芯片进行访问。
相对于现有技术而言，本申请实施例，通过将基于预存在调试设备的第一私钥生成的第一认证信息与基于芯片内存储的第二私钥生成的第二认证信息进行比对，从而根据比对的结果判断调试设备是否通过认证。由于第一私钥与第二私钥的保密性都较强，因此根据第一认证信息与第二认证信息的比对结果判断是否通过认证更加安全，进一步提高了访问芯片内数据的安全性。
本申请第三实施例的芯片的访问方法，应用于芯片。第三实施例是第二实施例的进一步改进，主要改进之处在于：在生成第一认证信息和第二认证信息时还结合了随机数的因素。
本实施例中的芯片的访问方法的具体流程如图3所示。
步骤301：在检测到调试设备后，触发对调试设备的安全认证。
步骤302：生成随机数并将随机数发送至调试设备。
具体地说，芯片可以生成随机数，随机数可以为字符类型和数字类型两种类型的随机数，字符类型可随机生成任意长度的字符串，而数字类型则是生成一定范围内的数字，在生成随机数时，还可以选择允许重复或不允许重复。 芯片在生成随机数后，将生成的随机数发送给调试设备，调试设备接收到随机数后，基于随机数和第一私钥生成第一认证信息。
步骤303：从调试设备获取第一认证信息。
具体地说，由于芯片将生成的随机数发送给调试设备，芯片从调试设备获取的第一认证信息为基于第一私钥和随机数生成的第一认证信息。
步骤304：基于第二私钥和随机数生成第二认证信息。
具体的说，芯片在生成随机数后，可以基于芯片内预存的第二私钥和随机数生成第二认证信息。比如说，可以将第二私钥和随机数按照预设的方式整合起来(如第二私钥在前，随机数在后)；其中，调试设备生成第一认证信息的方式与芯片生成第二认证信息的方式保持一致。
较佳的，调试设备内部和芯片内部还预设有相同的加密算法，调试设备利用加密算法，对第一私钥和随机数进行加密运算，以得到第一认证信息；芯片利用加密算法对第二私钥和随机数进行加密运算，以生成第二认证信息，从而进一步增强安全保密效果。
需要说明的是步骤303与步骤304并无明显的先后关系，本实施例只是提供一个例子，在实际应用中并不以此为限。
步骤305至步骤307与第二实施例中步骤204至步骤206大致相同，为避免重复，在此不再赘述。
相对于现有技术而言，本申请实施例，通过将芯片生成的随机数发送给调试设备，调试设备生成的第一认证信息与芯片生成的第二认证信息中均结合了随机数的因素，由于随机数总是随机产生，因此可防止他人按照一定设想的规律猜测性的对认证信息轻易破解，造成损失。本实施例使得根据第一认证信 息与第二认证信息的比对结果判断是否通过认证更加安全，进一步提高了对访问芯片内数据的安全性。
本申请的第四实施例的芯片的访问方法，应用于芯片。第四实施例是第三实施例的进一步改进，主要改进之处在于：通过心跳机制与调试设备保持通信，并在检测到心跳包出现异常时，将调试接口关闭，禁止调试设备通过调试接口对芯片进行访问。
本申请第四实施例的芯片的访问方法的具体流程如图4所示。
本实施例中步骤401值步骤407分别与步骤301至步骤307大致相同，为避免重复，在此不再赘述。
步骤408：通过心跳机制与调试设备保持通信，并在检测到心跳包出现异常时，将调试接口关闭。
具体地说，心跳机制是定时发送一个自定义的心跳包，以确保连接双方连接的有效性的机制，因此，调试设备与芯片可以通过心跳机制与调试设备保持通信。本实施例中，调试设备可以每隔预设时间向芯片发送一个心跳包，如果芯片接收到正常的心跳包，则继续打开调试接口。如果检测到心跳包出现异常，比如说在预设时间内未接收到心跳包，则说明调试设备出现异常，或是调试设备已经和芯片断开连接，此时将调试接口关闭，禁止调试设备通过调试接口对芯片进行访问。
相对于现有技术而言，本申请第四实施例，采用心跳机制与调试设备保持通信以确保调试设备与芯片的有效连接，在检测到心跳包出现异常时，将调试接口关闭。只有调试接口被正常打开且芯片与调试设备始终处于有效连接状态时，调试接口才会保持在打开状态，从而能够避免调试接口在正常打开后芯 片内的数据被恶意窃取，保证了芯片内数据的安全性。
本申请第五实施例的芯片的访问方法，应用于调试设备；即，本实施例的芯片访问方法，为调试设备对芯片进行访问时，调试设备所做的处理方法。
本申请第五实施例的芯片的访问方法的具体流程如图5所示。
步骤501：在检测到芯片后，获取安全卡内预存的第一私钥。
具体地说，调试设备在检测到芯片后，可以理解为，调试设备插入芯片所在的嵌入式开发板上。调试设备上插有安全卡，安全卡内存储有第一私钥，优选的，第一私钥可以由芯片出厂商的加密服务器产生，使用第一私钥来加密和解密数据。当调试设备检测到芯片后，可以获取安全卡内预存的第一私钥。
步骤502：至少基于第一私钥生成第一认证信息。
具体地说，由于第一私钥是预存在安全卡中的，因此只有安全卡插入调试设备后，调试设备才能至少基于第一私钥生成第一认证信息。也就是说，只有具有安全卡，并把安全卡插在调试设备上，调试设备才可能至少基于第一私钥生成第一认证信息。而如果没有安全卡，就无法获取第一私钥，调试设备就无法基于第一私钥获取第一认证信息。
步骤503：将第一认证信息发送至芯片，以供芯片根据第一认证信息判断调试设备是否通过认证。
具体地说，调试设备在生成第一认证信息后，将第一认证信息发送至芯片，芯片会根据第一认证信息判断调试设备是否通过认证，关于芯片判断调试设备是否通过认证的方法在上述芯片为执行主体的方法实施例中均有详细描述，为避免重复，在此不再赘述。
步骤504：在调试设备通过认证后，通过芯片打开的调试接口对芯片进 行访问。
具体地说，调试接口可以在芯片判断出调试设备通过认证后被打开，使得调试设备可以通过芯片打开的调试接口对芯片进行访问。
不难发现，本实施例中的芯片的访问方法应用于调试设备，第一、二实施例中的芯片的访问方法应用于芯片，本实施例可以与第一、二实施例互相配合实施。第一、二实施例中提到的相关技术细节在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一、二实施例中。
相对于现有技术而言，本申请实施例中调试设备通过认证的前提是，调试设备上插入安全卡，而且安全卡中预存有第一私钥，他人无从得知，因此保密性得到提高。调试设备向芯片发送第一认证信息，芯片判断调试设备是否通过认证，由于第一认证信息为调试设备至少基于第一私钥生成，第一私钥的保密性很强，因此根据第一认证信息判断调试设备是否通过认证使得芯片内数据的安全性更高。芯片的调试接口可以被多次打开，即使上次调试结束关闭了调试接口，下次调试时只要调试设备通过认证，依然可以访问到芯片内部的数据，并不存在现有技术中只要把调试接口关闭，就不能再打开的情况。因此，本实施例的芯片的访问方法有利于提高调试设备访问芯片的安全性、方便性和灵活性。
本申请第六实施例的芯片的访问方法，应用于调试设备，第六实施例是第五实施例的进一步改进，主要改进之处在于：调试设备接收芯片发送的随机数，并基于随机数和第一私钥生成第一认证信息。
本申请第六实施例的芯片的访问方法的具体流程如图6所示。
步骤601：在检测到芯片后，获取安全卡内预存的第一私钥。
步骤602：接收芯片发送的随机数。
具体地说，调试设备接收的随机数为第三实施例中步骤302中芯片生成的随机数，相关说明在步骤302中均有详细记载，为避免重复此处不再赘述。
步骤603：基于随机数和第一私钥生成第一认证信息。
具体地说，在接收到随机数后，可以基于第一私钥和随机数生成第一认证信息。比如说，可以将第一私钥和随机数按照预设的方式整合起来(如第一私钥在前，随机数在后)；其中，调试设备生成第一认证信息的方式与芯片生成第二认证信息的方式保持一致。
较佳的，调试设备内部和芯片内部还预设有相同的加密算法，调试设备利用加密算法，对第一私钥和随机数进行加密运算，以得到第一认证信息；芯片利用加密算法对第二私钥和随机数进行加密运算，以生成第二认证信息，从而进一步增强安全保密效果。
步骤604：将第一认证信息发送至芯片，以供芯片根据第一认证信息判断调试设备是否通过认证。
步骤605：在调试设备通过认证后，通过芯片打开的调试接口对芯片进行访问。
较佳的，在调试接口打开后，调试设备与芯片可以通过心跳机制与调试设备保持通信。本实施例中，调试设备可以每隔预设时间向芯片发送一个心跳包，如果芯片接收到正常的心跳包，则继续打开调试接口。如果检测到心跳包出现异常，比如说在预设时间内未接收到心跳包，则说明调试设备出现异常，或是调试设备已经和芯片断开连接，此时将调试接口关闭，禁止调试设备通过 调试接口对芯片进行访问。从而能够避免调试接口在正常打开后芯片内的数据被恶意窃取，保证了芯片内数据的安全性。
需要说明的是，本实施例中的芯片的访问方法应用于调试设备，第三、四实施例中的芯片的访问方法应用于芯片，本实施例可以与第二至第四实施例互相配合实施。第三、四实施例中提到的相关技术细节在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第三、四实施例中。
上面各种方法的步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对算法中或者流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其算法和流程的核心设计都在该专利的保护范围内。
本申请第七实施例涉及一种安全控制模块，设置于芯片内，如图7所示，包括：检测单元701、获取单元702、判断单元703、控制单元704。
检测单元701用于在检测到调试设备后，触发对调试设备的安全认证，调试设备上插有安全卡，安全卡内存储有预设的第一私钥。
获取单元702用于从调试设备获取第一认证信息，第一认证信息为调试设备至少基于第一私钥生成的第一认证信息。
判断单元703用于根据第一认证信息判断调试设备是否通过认证。
控制单元704用于在调试设备通过认证时将调试接口打开，允许调试设备通过调试接口对芯片进行访问。
本实施例中，安全控制模块中包括用于控制调试接口打开的开关；当调试设备通过认证时，控制单元704控制该开关闭合以导通访问路径，即，将调 试接口打开，允许调试设备通过调试接口对芯片进行访问。
不难发现，本实施例为与第一实施例相对应的装置实施例，本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
值得一提的是，本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本申请第八实施例涉及一种芯片，如图8所示，包括第七实施例中的安全控制模块。
具体地说，芯片801中包括：安全控制模块802。芯片801还可以包括：不可逆电路803、随机数模块804；不可逆电路803和随机数模块804均连接于安全控制模块802。不可逆电路803包括三种烧写方式：调试接口打开模式、安全卡认证模式、调试接口关闭模式；当不可逆电路803被烧写为安全卡认证模式时，安全控制模块801被启动，并由控制单元704根据判断单元703的判断结果控制开关的打开或关闭。随机数模块804用于生成随机数，并供安全控制模块802获取。调试接口805与芯片801相连，调试接口805为嵌入式开发板上与芯片连接的一个调试接口，用于将调试设备与待调试的芯片连接。其中，当不可逆电路803被烧写为调试接口打开模式时，不可逆电路803直接控制开关处于关闭状态，以导通访问路径；当不可逆电路803被烧写为调试接口关闭 模式时，不可逆电路803直接控制开关处于打开状态，以断开访问路径。
与现有技术相比，本申请实施例提供的芯片，使得其他调试设备在对芯片进行调试时更加安全、方便和灵活。
本申请第九实施例涉及一种调试设备，如图9所示，包括：调试接口901、安全卡插槽902、处理器903以及存储器904。
处理器903连接于安全卡插槽902和调试接口901；调试接口901还用于连接至待调试的芯片。存储器904中储存有可被处理器903执行的指令，指令被至少一个处理器903执行，当安全卡插槽902内插入预存有第一私钥的安全卡时，指令被处理器903执行，以使处理器能903够执行应用于调试设备的芯片的访问方法。
与现有技术相比，本申请实施例提供的调试设备上设置了安全卡插槽，插入预存第一私钥的安全卡后，使得处理器在执行应用于调试设备的芯片的访问方法时可以基于第一私钥生成第一认证信息，芯片根据第一认证信息判断该调试设备是否能够访问芯片内部的数据。使用本实施例提供的调试设备，提高了在对芯片进行调试时的安全性、方便性和灵活性。
即，本领域技术人员可以理解，实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (14)

  1. 一种芯片的访问方法，其特征在于，应用于芯片，包括：
    在检测到调试设备后，触发对所述调试设备的安全认证，所述调试设备上插有安全卡，所述安全卡内预存有第一私钥；
    从所述调试设备获取第一认证信息，所述第一认证信息为所述调试设备至少基于所述第一私钥生成的第一认证信息；
    根据所述第一认证信息判断所述调试设备是否通过认证；
    如果所述调试设备通过认证，则将调试接口打开，允许所述调试设备通过所述调试接口对所述芯片进行访问。
  2. 根据权利要求1所述的芯片的访问方法，其特征在于，所述根据所述第一认证信息判断所述调试设备是否通过认证，具体包括：
    至少基于所述芯片内预存的第二私钥生成第二认证信息；
    将所述第一认证信息与所述第二认证信息进行比对，并得到比对结果；
    根据所述比对结果判断所述调试设备是否通过认证。
  3. 根据权利要求2所述的芯片的访问方法，其特征在于，在所述触发对所述调试设备的安全认证之后，还包括：
    生成随机数并将所述随机数发送至所述调试设备；其中，所述第一认证信息具体为所述调试设备基于所述第一私钥和所述随机数生成的第一认证信息；
    所述至少基于所述芯片内预存的第二私钥生成第二认证信息，具体为：基于所述第二私钥和所述随机数生成所述第二认证信息。
  4. 根据权利要求2所述的芯片的访问方法，其特征在于，所述第一私钥与所述第二私钥相同。
  5. 根据权利要求1所述的芯片的访问方法，其特征在于，在所述将调试接口打开之后，还包括：
    通过心跳机制与所述调试设备保持通信，并在检测到心跳包出现异常时，将所述调试接口关闭，禁止所述调试设备通过所述调试接口对所述芯片进行访问。
  6. 根据权利要求1所述的芯片的访问方法，其特征在于，所述允许所述调试设备通过所述调试接口对所述芯片进行访问具体为：允许所述调试设备通过所述调试接口以预设权限对所述芯片进行访问，所述预设权限存储在所述安全卡内。
  7. 根据权利要求1所述的芯片的访问方法，其特征在于，所述芯片处于预设模式中的安全卡认证模式；
    所述预设模式包括：调试接口打开模式、安全卡认证模式、调试接口关闭模式。
  8. 根据权利要求1所述芯片的访问方法，其特征在于，所述调试设备具体为JTAG设备。
  9. 一种芯片的访问方法，其特征在于，应用于调试设备，所述调试设备上插有安全卡，所述芯片的访问方法包括：
    在检测到所述芯片后，获取所述安全卡内预存的第一私钥；
    至少基于所述第一私钥生成第一认证信息；
    将所述第一认证信息发送至所述芯片，以供所述芯片根据所述第一认证信息判断所述调试设备是否通过认证；
    在所述调试设备通过认证后，通过所述芯片打开的调试接口对所述芯片进 行访问，其中，所述调试接口在所述芯片判断出所述调试设备通过认证后被打开。
  10. 根据权利要求9所述的芯片的访问方法，其特征在于，在所述至少基于所述第一私钥生成第一认证信息之前，还包括：
    接收所述芯片发送的随机数；
    所述至少基于所述第一私钥生成第一认证信息，具体为：基于所述第一私钥和所述随机数生成第一认证信息。
  11. 一种安全控制模块，其特征在于，设置于芯片内，包括：检测单元、获取单元、判断单元、控制单元；
    所述检测单元用于在检测到调试设备后，触发对所述调试设备的安全认证，所述调试设备上插有安全卡，所述安全卡内存储有预设的第一私钥；
    所述获取单元用于从所述调试设备获取第一认证信息，所述第一认证信息为所述调试设备至少基于所述第一私钥生成的第一认证信息；
    所述判断单元用于根据所述第一认证信息判断所述调试设备是否通过认证；
    所述控制单元用于在所述调试设备通过认证时将调试接口打开，允许所述调试设备通过所述调试接口对所述芯片进行访问。
  12. 一种芯片，其特征在于，包括如权利要求11所述的安全控制模块。
  13. 根据权利要求12所述的芯片，其特征在于，所述芯片还包括不可逆电路，且所述不可逆电路连接于所述安全控制模块；
    所述不可逆电路可以被烧写成以下三种模式中的一种：调试接口打开模式、安全卡认证模式、调试接口关闭模式；当所述不可逆电路被烧写为安全卡认证模式时，所述安全控制模块被启动。
  14. 一种调试设备，其特征在于，包括：调试接口、安全卡插槽、处理器以及存储器；
    所述处理器连接于所述安全卡插槽和所述调试接口；所述调试接口还用于连接至待调试的芯片；
    所述存储器中储存有可被所述处理器执行的指令，所述指令被所述至少一个处理器执行，
    当所述安全卡插槽内插入预存有第一私钥的安全卡时，所述指令被所述处理器执行，以使所述处理器能够执行如权利要求9或10所述的芯片的访问方法。
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CN110337652A (zh) 2019-10-15
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