WO2019142496A1

WO2019142496A1 - Nitride semiconductor epitaxial substrate

Info

Publication number: WO2019142496A1
Application number: PCT/JP2018/043406
Authority: WO
Inventors: 好伸成田
Original assignee: 株式会社サイオクス; 住友化学株式会社
Priority date: 2018-01-18
Filing date: 2018-11-26
Publication date: 2019-07-25
Also published as: JP2019125737A

Abstract

A nitride semiconductor epitaxial substrate which comprises a substrate, a buffer layer that is formed on the substrate, and a nitride semiconductor layer that is formed on the buffer layer, and which is configured such that the buffer layer comprises a nucleation layer that has a recessed and projected surface that faces the nitride semiconductor layer, and a uniform heating layer that is composed of a continuous film and is arranged on the substrate side.

Description

Nitride semiconductor epitaxial substrate

The present invention relates to a nitride semiconductor epitaxial substrate.

For example, as a nitride semiconductor epitaxial substrate used for a high electron mobility transistor (HEMT: High Electron Mobility Transistor), gallium nitride (GaN) on a silicon carbide (SiC) substrate via an aluminum nitride (AlN) buffer layer And the like are known to be formed by epitaxial growth of nitride semiconductor layers such as, for example, see Patent Documents 1 and 2.

JP, 2008-251966, A JP, 2013-4924, A

However, in the conventional nitride semiconductor epitaxial substrate, the heat dissipation may be a problem. Specifically, although the AlN buffer layer has an uneven surface serving as a nucleus when epitaxially growing the nitride semiconductor layer, the heat on the side of the nitride semiconductor layer is less likely to be transmitted to the side of the SiC substrate due to the unevenness It is possible.

An object of the present invention is to provide a nitride semiconductor epitaxial substrate capable of improving the heat radiation effect to the side of the substrate.

According to one aspect of the invention:
A substrate,
A buffer layer formed on the substrate;
And a nitride semiconductor layer formed on the buffer layer.
The buffer layer is
A nucleation layer having an irregular surface facing the nitride semiconductor layer;
A heat equalizing layer comprising a continuous film disposed on the side of the substrate;
A nitride semiconductor epitaxial substrate is provided.

According to the present invention, the heat radiation effect to the side of the substrate can be made favorable.

It is explanatory drawing which shows typically the schematic structural example of the nitride semiconductor epitaxial substrate which concerns on one Embodiment of this invention. It is explanatory drawing which shows one specific example of the relationship between surface temperature of the nitride semiconductor layer in the nitride semiconductor epitaxial substrate which concerns on one Embodiment of this invention, and surface roughness Rz of the uneven surface of a nucleation layer. It is explanatory drawing which shows one specific example of the relationship between the surface temperature of the nitride semiconductor layer in the nitride semiconductor epitaxial substrate which concerns on one Embodiment of this invention, and the film thickness of a soaking layer.

<One embodiment of the present invention>
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(1) Basic Configuration of Nitride Semiconductor Epitaxial Substrate First, a basic configuration example of the nitride semiconductor epitaxial substrate according to the present embodiment will be described.
The nitride semiconductor epitaxial substrate is a substrate-like structure used as a base when manufacturing a semiconductor device such as HEMT described later. Hereinafter, the nitride semiconductor epitaxial substrate may be referred to as "intermediate" or "intermediate precursor" because it is used as a substrate of a semiconductor device.

As shown in FIG. 1, the intermediate 10 according to this embodiment includes at least a substrate 11, a buffer layer 12 formed on the substrate 11, and a first nitride semiconductor layer formed on the buffer layer 12. (Hereinafter referred to as “first nitride semiconductor layer” or “first layer”) 13 and a second nitride semiconductor layer formed on first nitride semiconductor layer 13 (hereinafter referred to as “second nitride” A semiconductor layer "or" second layer "14).

(substrate)
The substrate 11 is configured as a base substrate on which the buffer layer 12, the first nitride semiconductor layer 13 and the like are grown, and is configured using, for example, a SiC substrate. Specifically, for example, a semi-insulating SiC substrate of polytype 4H or polytype 6H is used as the substrate 11. The numbers 4H and 6H indicate the repetition cycle in the c-axis direction, and H indicates a hexagonal crystal. In addition, “semi-insulating” as referred to herein means, for example, a state in which the specific resistance is 10 ⁵ Ω · cm or more. If the substrate 11 has a semi-insulating property, the diffusion of free electrons from the side of the first nitride semiconductor layer 13 to the substrate 11 is suppressed when configuring the semiconductor device 20 described later, and the leakage current is It can be suppressed. The substrate 11 is preferably a semi-insulating SiC substrate, but may be a conductive SiC substrate, a sapphire substrate, a silicon substrate, a GaN substrate or the like.

(Buffer layer)
The buffer layer 12 is formed mainly of, for example, AlN, which is a group III nitride semiconductor. The buffer layer 12 mainly functions as a buffer layer (buffer layer) that buffers the lattice constant difference between the substrate 11 and the first nitride semiconductor layer 13. The buffer layer 12 also functions as a nucleation layer in which the first nitride semiconductor layer 13 side forms a nucleus for crystal growth of the first nitride semiconductor layer 13 as described later. There is. Hereinafter, the buffer layer 12 may be referred to as an “AlN layer” or an “AlN buffer layer”.

(First nitride semiconductor layer)
The first nitride semiconductor layer 13 is formed mainly of GaN, which is, for example, a group III nitride semiconductor. The first nitride semiconductor layer 13 is a buffer layer in which a partial region (for example, a region located on the side of the AlN buffer layer 12) mainly buffers the lattice constant difference between the AlN buffer layer 12 and the first nitride semiconductor layer 13. While functioning as a (buffer layer), other regions (for example, a region located on the side of the second nitride semiconductor layer 14) function as an electron transit layer (channel layer) for mainly causing electrons to travel. ing. In the region functioning as the electron transit layer, the piezoelectric effect (the crystal is distorted in the second nitride semiconductor layer 14 due to the lattice constant difference between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 Two dimensional electron gas (2DEG: Two Dimensional Electron Gas) induced by the effect of the electric field is present. Further, the surface of the region functioning as the electron transit layer (upper surface of the first nitride semiconductor layer 13) is a group III atom polar surface (+ c surface). Hereinafter, the first nitride semiconductor layer 13 may be referred to as a “GaN layer” or a “GaN channel / buffer layer”.

(Second nitride semiconductor layer)
The second nitride semiconductor layer 14 has a wider band gap than the group III nitride semiconductor constituting the GaN channel / buffer layer 13 and is smaller than the lattice constant of the group III nitride semiconductor constituting the GaN channel / buffer layer 13 It consists of a group III nitride semiconductor having a lattice constant, and is composed mainly of, for example, Al _x Ga ₁ -xN (where 0 <x <1). The second nitride semiconductor layer 14 functions as an electron supply layer that supplies electrons to the electron transit layer of the GaN channel / buffer layer 13 and also functions as a barrier layer (barrier layer) that spatially confines the 2DEG. ing. The surface (upper surface) of the second nitride semiconductor layer 14 is a group III atom polar surface (+ c surface). With such a configuration, spontaneous polarization and piezoelectric polarization occur in the second nitride semiconductor layer 14. The polarization action induces a high concentration of 2DEG near the heterojunction interface in the GaN channel / buffer layer 13. Hereinafter, the second nitride semiconductor layer 14 may be referred to as an "AlGaN layer" or an "AlGaN barrier layer".

(2) Basic Configuration of Semiconductor Device Subsequently, a basic configuration example of the semiconductor device 20 configured using the intermediate body 10 having the above-described configuration will be described. Here, as the semiconductor device 20, a HEMT, which is one of field effect transistors (FETs), is taken as an example.

As shown in FIG. 1, the HEMT 20 according to this embodiment includes the intermediate 10 having the above-described configuration, a third nitride semiconductor layer 21 formed on the AlGaN barrier layer 14 in the intermediate 10, and a third nitride. A gate electrode 22, a source electrode 23 and a drain electrode 24 formed on the semiconductor layer 21 are provided.

(Third nitride semiconductor layer)
The third nitride semiconductor layer 21 is formed mainly of GaN, which is, for example, a group III nitride semiconductor. The third nitride semiconductor layer 21 is interposed between the AlGaN barrier layer 14 and the gate electrode 22 in order to improve, for example, the device characteristics (controllability of the threshold voltage, etc.) when the HEMT 20 is configured. The HEMT 20 is not necessarily an essential component and may be omitted. Hereinafter, the third nitride semiconductor layer 21 may be referred to as a "GaN cap layer".

(electrode)
The gate electrode 22 has, for example, a multilayer structure (Ni / Au) of nickel (Ni) and gold (Au). In addition, when it describes as the multilayer structure of X / Y in this specification, it shall show that it laminated | stacked in order of X and Y. FIG.
The source electrode 23 is disposed at a predetermined distance from the gate electrode 22 and has, for example, a multilayer structure (Ti / Al) of titanium (Ti) and aluminum (Al).
The drain electrode 24 is disposed opposite to the source electrode 23 with the gate electrode 22 on the opposite side of the gate electrode 22 and at a predetermined distance from the gate electrode 22, similarly to the source electrode 23, for example, a multilayer structure of Ti and Al (Ti / Al. It consists of Al).
The source electrode 23 and the drain electrode 24 may have a multilayer structure of Ni / Au stacked on a multilayer structure of Ti / Al.

(3) Findings Obtained by the Inventor It is desirable that the HEMT 20 having the above-described configuration has good heat dissipation. For example, in the HEMT 20, the heat generated in the vicinity of the gate electrode 22 is dissipated at once if it reaches the substrate 11. Therefore, in order to obtain good heat dissipation, the resistance component of heat transfer to reach the substrate 11 is very important.

Therefore, when the inventors of the present application examined the resistive component of heat transfer in the HEMT 20, in particular, the resistive component of heat transfer in the intermediate body 10 constituting the HEMT 20, it is presumed that the surface shape of the AlN buffer layer 12 is related. It became clear. Specifically, although the AlN buffer layer 12 has an uneven surface on the side of the first nitride semiconductor layer 13 to function as a nucleation layer, the uneven surface affects the resistance component of heat transfer. I understood it. More specifically, it has been found that the magnitude of the heat transfer resistive component may change due to the uneven surface, for example, the heat transfer resistive component tends to be smaller when the uneven surface is closer to being flat.

On the other hand, it is known that the uneven surface of the AlN buffer layer 12 affects the crystal quality of the first nitride semiconductor layer 13 formed thereon. Specifically, the crystal quality of the first nitride semiconductor layer 13 formed thereon tends to deteriorate as the size of the unevenness on the uneven surface decreases. As to the crystal quality of the first nitride semiconductor layer 13, if the film thickness of the first nitride semiconductor layer 13 is increased, the deterioration of the crystal quality is suppressed, but for that purpose, the growth time of crystal growth is prolonged As a result, the productivity of the intermediate 10 and the like is impaired. Therefore, the film thickness of the first nitride semiconductor layer 13 is preferably suppressed to a certain extent.

That is, since the resistive component of heat transfer and the crystal quality of the first nitride semiconductor layer 13 are in a trade-off relationship, in order to reduce the resistive component of heat transfer and improve the heat dissipation, the AlN buffer is simply used. It is not always appropriate to configure the uneven surface of the layer 12 to be flatter.

As a result of repeated studies on this point, the inventor of the present application found that when the AlN buffer layer 12 is divided in the in-plane direction by the uneven surface of the AlN buffer layer 12, the heat transfer resistance component becomes large. It came to gain the knowledge that there is a risk of In other words, even if the size of the asperities on the asperity surface is such that good crystal quality can be obtained, heat transfer is not performed unless the AlN buffer layer 12 is divided in the in-plane direction by the asperity surface. The idea is that it becomes feasible to obtain good heat dissipation by reducing the resistance component.

The present invention is based on the above-mentioned findings newly found by the present inventor.

(4) Characteristic Configuration of the Embodiment Next, the characteristic configuration of the intermediate body 10 constituting the HEMT 20 will be specifically described. The intermediate 10 according to the present embodiment is characterized in that the AlN buffer layer 12 is a major feature.

(Buffer layer)
The AlN buffer layer 12 includes a nucleation layer 12 b having an uneven surface 12 a facing the first nitride semiconductor layer 13 and a heat equalizing layer 12 c formed of a continuous film disposed on the side of the substrate 11. There is. The nucleation layer 12 b and the heat equalizing layer 12 c are each formed of, for example, AlN as a main component.

(Nucleation layer)
The nucleation layer 12 b is for forming a nucleus when crystal growth of the first nitride semiconductor layer 13 is performed, and has a concavo-convex surface 12 a facing the first nitride semiconductor layer 13. The shape of the convex part or recessed part which comprises the uneven surface 12a will not be specifically limited if it can form a nucleus.

The uneven surface 12a of the nucleation layer 12b has a surface roughness Rz of the uneven surface 12a (that is, the sum of the maximum value of the peak height of the protrusions and the maximum value of the valley depth of the recesses) is, for example, 7 nm or more Is formed.

If the size of the unevenness on the uneven surface 12a is too small, the crystal quality of the first nitride semiconductor layer 13 formed thereon may be adversely affected, but if the value of the surface roughness Rz is 7 nm or more, An adverse effect on the crystal quality of the mono-nitride semiconductor layer 13 can be suppressed. Therefore, if crystal growth is performed on the uneven surface 12a, the first nitride semiconductor layer 13 of good crystal quality can be obtained, for example, as the defect density is low, as described in detail later. Become.

In addition, when the size of the unevenness on the uneven surface 12 a is too small, the residual impurity concentration in the first nitride semiconductor layer 13 tends to increase. When the residual impurity concentration is increased, the crystal at the interface between the nucleation layer 12 b and the first nitride semiconductor layer 13 has a low resistance, which makes it easy for the current to leak when the HEMT 20 is formed. However, if the value of the surface roughness Rz is 7 nm or more, the increase of the residual impurity concentration can be suppressed, and the leak current when configuring the HEMT 20 can be suppressed low.

The uneven surface 12a of the nucleation layer 12b has a surface roughness Rz of, for example, less than 20 nm.
If the size of the unevenness on the uneven surface 12a of the nucleation layer 12b is small so that the value of the surface roughness Rz is less than 20 nm, compared to the case where the unevenness is large, from the side of the first nitride semiconductor layer 13 Heat is easily transmitted to the AlN buffer layer 12. This is considered to be because energy transfer is more likely to occur between the crystal lattices because the smaller the unevenness, the more the crystal lattices are aligned. That is, by reducing the unevenness on the uneven surface 12a, it is possible to transfer the heat transmitted from the side of the first nitride semiconductor layer 13 to the side of the substrate 11 favorably, and the side of the substrate 11 via the AlN buffer layer 12 It is very effective in improving the heat radiation effect to the substrate.

Specifically, when the heat on the side of the first nitride semiconductor layer 13 is considered by, for example, the surface temperature of the second nitride semiconductor layer 14 in the intermediate 10, the surface temperature and the uneven surface of the nucleation layer 12b The surface roughness Rz of 12a has a relationship as shown in FIG.
For example, when the surface roughness Rz of the uneven surface 12a is 30 nm or more, the surface temperature of the second nitride semiconductor layer 14 is a high temperature of about 120 ° C. when the size of the unevenness on the uneven surface 12a is large. However, as the value of the surface roughness Rz decreases, the surface temperature also decreases. That is, when the value of the surface roughness Rz of the uneven surface 12a is large, heat is hardly transmitted to the side of the substrate 11. However, as the value of the surface roughness Rz becomes smaller, the substrate 11 is closer to the first nitride semiconductor layer 13 side. Heat is easily transmitted to the side.
Then, when the size of the unevenness on the uneven surface 12a decreases to such an extent that the value of the surface roughness Rz is less than 20 nm, the drop of the surface temperature of the second nitride semiconductor layer 14 tends to saturate, and the surface temperature Is a low temperature of about 60 to 70.degree. That is, when the value of the surface roughness Rz is less than 20 nm, the heat on the side of the first nitride semiconductor layer 13 can be favorably conducted to the side of the substrate 11.

(Uniform heat layer)
The heat equalizing layer 12 c is a layer that constitutes the AlN buffer layer 12 together with the nucleation layer 12 b, and is formed of a continuous film disposed on the side of the substrate 11. Here, a continuous film refers to a film in which a film is continuously formed in a plane and there is no part divided in the in-plane direction.

By having such a heat equalizing layer 12 c, the AlN buffer layer 12 includes not only the nucleation layer 12 b but also the heat equalizing layer 12 c which is a continuous film. Therefore, even if the nucleation layer 12b has the uneven surface 12a, since the heat equalizing layer 12c which is a continuous film is present, the AlN buffer layer 12 is divided in the in-plane direction by the uneven surface 12a. The heat transferred from the side of the first nitride semiconductor layer 13 is diffused in the in-plane direction by the heat equalizing layer 12c which is a continuous film, and the heat is efficiently transmitted to the substrate 11 side. It will be possible to communicate. That is, since the AlN buffer layer 12 is not divided in the in-plane direction by having the heat equalizing layer 12 c, it is possible to reduce the resistance component of heat transfer and obtain good heat dissipation. .

The heat equalizing layer 12 c is formed to have a film thickness of 3 nm or more. If the film thickness is 3 nm or more, the heat equalizing layer 12c can be reliably made a continuous film. Further, if the heat spreader 12c has a thickness of 3 nm or more, for example, even if the nucleation layer 12b is a discontinuous film, the thinnest portion of the AlN buffer layer 12 has a thickness of 3 nm or more. This is very effective in improving the heat radiation effect to the side of the substrate 11.

Specifically, when the heat on the side of the first nitride semiconductor layer 13 is considered by, for example, the surface temperature of the second nitride semiconductor layer 14 in the intermediate 10, the surface temperature and the film thickness of the heat equalizing layer 12c And have a relationship as shown in FIG.
For example, when the film thickness of the heat equalizing layer 12c is very thin such as 1 nm or less, the surface temperature of the second nitride semiconductor layer 14 is in a high temperature state of about 120 ° C. As the film thickness of the thermal layer 12c increases, the surface temperature also decreases. That is, when the film thickness of the heat equalizing layer 12c is small, heat is not easily transmitted to the side of the substrate 11, but as the film thickness of the heat equalized layer 12c increases, from the side of the first nitride semiconductor layer 13 to the side of the substrate 11 The heat is easily transmitted.
Then, when the film thickness of the heat equalizing layer 12c becomes 3 nm or more (that is, the thickness that ensures a continuous film), the drop of the surface temperature of the second nitride semiconductor layer 14 tends to be saturated, and the surface temperature is It becomes a low temperature state of about 60 to 70 ° C. That is, when the film thickness of the heat equalizing layer 12 c is 3 nm or more, it is possible to transfer the heat on the side of the first nitride semiconductor layer 13 to the side of the substrate 11 favorably.

If the film thickness of the heat equalizing layer 12c is 3 nm or more, the value (upper limit value, etc.) is not particularly limited, and the AlN buffer layer 12 having the nucleation layer 12b and the heat equalizing layer 12c is not particularly limited. It is sufficient if the thickness can buffer the difference in lattice constant between the substrate 11 and the first nitride semiconductor layer 13 as a whole.

(First nitride semiconductor layer)
It is preferable that the first nitride semiconductor layer 13 formed on the uneven surface 12 a of the nucleation layer 12 b of the AlN buffer layer 12 as described above is formed to have a thickness of 0.4 μm to 2.0 μm. .

As for the first nitride semiconductor layer 13, as the film thickness increases, the adverse effect on the crystal quality due to the size of the unevenness of the uneven surface 12 a can be alleviated, while the growth time is extended (that is, the productivity is increased). Worse). If the film thickness of the first nitride semiconductor layer 13 is set to 0.4 μm or more and 2.0 μm or less, it is possible to achieve both the suppression of deterioration of crystal quality and the suppression of deterioration of productivity in a well-balanced manner. That is, while making it possible to reliably reduce the adverse effect on the crystal quality by setting the film thickness to 0.4 μm or more, suppressing the deterioration of productivity as much as possible by setting the film thickness to 2.0 μm or less it can. In addition, it is assumed that the crystal quality referred to here includes both of those relating to crystallinity (defect density and the like) and those relating to residual impurity concentration (purity).

As a parameter | index about the crystallinity of the 1st nitride semiconductor layer 13, the half value width of a X-ray rocking curve is mentioned, for example. The full width at half maximum of the X-ray rocking curve indicates the uniformity of the plane orientation of the crystal of a specific plane orientation within the area of the spot size (usually about 1 mm in diameter) of the X-ray beam at the measurement point. Therefore, the half value width of the X-ray rocking curve of the growth surface of the crystal to be epitaxially grown is an indicator of the uniformity of the surface orientation of the growth surface. For example, the half value width of the X-ray rocking curve of the (002) plane of the nitride semiconductor crystal is a spot of the growth direction of a large number of micro crystal columns constituting the nitride semiconductor layer grown in the [002] direction It is an index showing how the regions of the size are aligned, and the larger the half-width is, the more irregular the growth direction of the crystal column is.

Also, for example, when an n-type conductive layer is formed in a nitride semiconductor layer, silicon (Si (Si) is grown while epitaxial growth of the nitride semiconductor crystal forming the nitride semiconductor layer is performed by metal organic vapor phase epitaxy (MOVPE) or the like). Introduce n-type impurities such as oxygen and oxygen (O). At this time, in particular, O which behaves as an n-type impurity is difficult to be taken in when the growth surface of the nitride semiconductor crystal is the (002) plane, and is easily taken in when it is the other surface. Therefore, as the uniformity of the growth direction of the micro crystal columns constituting the nitride semiconductor crystal grown with the (002) plane as the growth surface is lower, O is more easily taken into the nitride semiconductor crystal, and as a result thereof The concentration of n-type impurities is increased. Therefore, the half value width of the X-ray rocking curve of the nitride semiconductor layer which is a nitride semiconductor crystal grown with the (002) plane as the growth plane and whose top surface has the (002) plane orientation is the n-type at the measurement point It also serves as an indicator of the n-type impurity concentration in the conductive layer.

The surface roughness Rz of the uneven surface 12a of the nucleation layer 12b of the AlN buffer layer 12 is 7 nm or more, and the film thickness of the first nitride semiconductor layer 13 formed thereon is 0.4 μm or more If so, for the first nitride semiconductor layer 13, the full width at half maximum of the X-ray rocking curve in the (002) plane can be made 300 seconds or less in the whole area in the plane. If the half width of the X-ray rocking curve is 300 seconds or less, it can be said that the plane orientation of the crystals constituting the first nitride semiconductor layer 13 is uniform, and it is clear that good crystal quality is obtained. .

(5) Method of Manufacturing Nitride Semiconductor Epitaxial Substrate and Semiconductor Device Next, a method of manufacturing the intermediate having the above-described configuration (that is, nitride semiconductor epitaxial substrate) 10 and a method of manufacturing HEMT (that is, semiconductor device) 20 will be described. Do.

(Method of manufacturing nitride semiconductor epitaxial substrate)
First, a case of manufacturing an intermediate 10 which is an example of a nitride semiconductor epitaxial substrate will be described.

In the present embodiment, for example, an intermediate 10 is manufactured by the following procedure using a metal organic vapor phase epitaxy (MOVPE) apparatus.

(S110: Substrate preparation process)
In the production of the intermediate 10, first, for example, a semi-insulating SiC substrate of polytype 4H is prepared as the substrate 11.

(S120: AlN layer formation process)
After preparing the substrate 11, the prepared substrate 11 is carried into the processing chamber of the MOVPE apparatus. Then, hydrogen (H ₂ ) gas (or a mixed gas of H ₂ gas and nitrogen (N ₂ ) gas) is supplied as a carrier gas (dilution gas) into the processing chamber, and the temperature of the substrate 11 is set to a predetermined growth temperature (for example, The temperature is raised to 1100 ° C. or more and 1300 ° C. or less. When the temperature of the substrate 11 reaches a predetermined growth temperature, for example, trimethylaluminum (TMA) gas as a group III source gas and ammonia (NH ₃ ) gas as a group V source gas are supplied to the substrate 11, respectively. . Thus, the AlN layer 12 made of AlN is grown on the substrate 11.

At this time, the epitaxial growth of the AlN layer 12 is first performed on the soaking layer 12 c and then on the nucleation layer 12 b.

The epitaxial growth of the heat equalizing layer 12c is performed under growth conditions that can form a continuous film. Specifically, the temperature of the substrate 11 is adjusted to a growth temperature (for example, 1200 ° C. or more and 1300 ° C. or less) suitable for the growth of the continuous film. That is, the growth temperature is adjusted to a temperature higher than that in the film formation of the nucleation layer 12 b described later. Thereby, the heat equalizing layer 12c can be formed as a continuous film.

Then, crystal growth is performed for a predetermined time to grow the heat equalizing layer 12c to a film thickness of 3 nm or more, and then the growth conditions are changed, and the nucleation layer 12b is epitaxially grown under the growth conditions after the change. . The epitaxial growth of the nucleation layer 12b is performed under growth conditions that can form the uneven surface 12a. Specifically, the temperature of the substrate 11 is adjusted to a growth temperature (for example, 1100 ° C. or more and 1200 ° C. or less) suitable for the formation of the uneven surface 12 a. That is, the growth temperature is adjusted to a temperature lower than at the time of forming the heat equalizing layer 12c described above. Thereby, it is possible to form the nucleation layer 12 b having the uneven surface 12 a whose surface roughness Rz is 7 nm or more and less than 20 nm.

Here, although the growth temperature has been exemplified as the growth condition to be changed, the growth temperature is not limited thereto, and it is possible to form each of the heat equalizing layer 12 c and the nucleation layer 12 b as follows: Other growth conditions (eg, V / III ratio, growth rate, etc.) may be used. Specifically, for example, while the V / III ratio is lowered so as to form a continuous film for the heat equalizing layer 12c, the V / III ratio so as to form the irregular surface 12a for the nucleation layer 12b. Can be considered as high. Also, for example, while the growth rate is decreased so as to form a continuous film for the heat equalizing layer 12c, the growth rate is increased so as to form the uneven surface 12a for the nucleation layer 12b. Conceivable. Furthermore, the growth conditions such as the growth temperature, the V / III ratio, and the growth rate may be appropriately combined and adjusted.

With such a change in growth conditions, the surface roughness Rz of the uneven surface 12a of the AlN layer 12 is 7 nm or more on the soaking layer 12c which is a continuous film having a thickness of 3 nm or more. The nucleation layer 12b which is present and less than 20 nm is formed. Then, when the growth of the AlN layer 12 having a predetermined thickness is completed, the supply of TMA gas is stopped. At this time, the supply of NH ₃ gas is continued.

(S130: GaN layer formation process)
Next, the temperature of the substrate 11 is adjusted to a predetermined growth temperature of the GaN layer 13 (for example, 1000 ° C. or more and 1100 ° C. or less). Then, when the temperature of the substrate 11 reaches a predetermined growth temperature, for example, trimethylgallium (TMG) gas is supplied as a group III source gas while the supply of the NH ₃ gas is continued. Thereby, the GaN layer 13 made of single crystal GaN is epitaxially grown on the AlN layer 12.

Then, when the growth of the GaN layer 13 of 0.4 μm or more and 2.0 μm or less is completed, the supply of TMG gas is stopped. At this time, the supply of NH ₃ gas is continued.

(S140: AlGaN layer formation process)
Next, for example, while the temperature of the substrate 11 is maintained, the supply of the NH ₃ gas is continued, for example, the TMG gas and the TMA gas are supplied as the group III source gas. Thereby, the AlGaN layer 14 made of single crystal AlGaN is epitaxially grown on the electron transit layer 140.

Then, when the growth of the AlGaN layer 14 having a predetermined thickness is completed, the supply of TMG gas and TMA gas is stopped, and the temperature of the substrate 11 is lowered from the growth temperature of the AlGaN layer 14. At this time, normally, the carrier gas is stopped, the N ₂ gas is supplied as the purge gas, and the supply of the NH ₃ gas is continued. Then, when the temperature of the nitride semiconductor epitaxial substrate 11 becomes 500 ° C. or less, the supply of NH ₃ gas is stopped, the atmosphere in the processing chamber of the MOVPE apparatus is replaced with only N ₂ gas, and the pressure is restored to atmospheric pressure.

Thereafter, when the temperature of the intermediate 10 including the GaN layer 13 and the AlGaN layer 14 decreases to a temperature at which the intermediate 10 can be unloaded, the intermediate 10 is unloaded from the processing chamber.
Thus, the intermediate 10 (that is, an example of the nitride semiconductor epitaxial substrate) shown in FIG. 1 is manufactured.

(Method of manufacturing semiconductor device)
Subsequently, a case of manufacturing the HEMT 20 which is an example of the semiconductor device using the intermediate body 10 will be described.

(S150: GaN layer formation process)
In manufacturing the HEMT 20, first, the intermediate 10 is prepared, and the intermediate 10 is carried into the processing chamber of the MOVPE apparatus. Then, the same process as in the case of the GaN layer forming step (S130) described above is performed to epitaxially grow the GaN cap layer 21 made of single crystal GaN on the AlGaN layer 14 in the intermediate 10. Thereafter, when the growth of the GaN cap layer 21 having a predetermined thickness is completed, the intermediate 10 on which the GaN cap layer 21 is formed is unloaded from the processing chamber. Note that the growth of the GaN cap layer 21 may be carried out continuously in the high temperature state after the above-described AlGaN layer forming step (S140).

(S160: electrode formation process)
Next, a resist film is formed on the GaN cap layer 21, and the resist film is patterned so that the region where the source electrode 23 and the drain electrode 24 are to be formed in plan view becomes an opening. Then, for example, a Ti / Al multilayer structure (or a Ti / Al / Ni / Au multilayer structure) is formed by electron beam evaporation so as to cover the GaN cap layer 21 and the resist film. Thereafter, the resist film is removed by liftoff using a predetermined solvent to form the source electrode 23 and the drain electrode 24 in the predetermined region, and the whole is annealed at a predetermined temperature in an N ₂ atmosphere for a predetermined time. (Eg, 650 ° C. for 3 minutes). Thereby, each of the source electrode 23 and the drain electrode 24 can be in ohmic contact with the GaN cap layer 21.

Next, a resist film is formed to cover the GaN cap layer 21, the source electrode 23, and the drain electrode 24, and the resist film is patterned so that the region where the gate electrode 22 is to be formed in plan view becomes an opening. . Then, a Ni / Au multilayer structure is formed to cover the GaN cap layer 21 and the resist film, for example, by electron beam evaporation. Thereafter, the resist film is removed by liftoff using a predetermined solvent to form the gate electrode 22 in the predetermined region, and the whole is annealed at a predetermined temperature in an N ₂ atmosphere for a predetermined time (for example, 450 ° C 10 minutes).

Thus, the HEMT 20 (that is, an example of the semiconductor device) shown in FIG. 1 is manufactured.

(6) Effects Obtained by the Present Embodiment According to the present embodiment, one or more effects described below can be obtained.

(A) In the present embodiment, the AlN buffer layer 12 is formed of a nucleation layer 12 b having an uneven surface 12 a facing the first nitride semiconductor layer 13 and a continuous film disposed on the side of the substrate 11. And a thermal layer 12c. That is, the AlN buffer layer 12 includes not only the nucleation layer 12 b but also the heat equalizing layer 12 c which is a continuous film. Therefore, even if the nucleation layer 12b has the uneven surface 12a, since the heat equalizing layer 12c which is a continuous film is present, the AlN buffer layer 12 is divided in the in-plane direction by the uneven surface 12a. The heat transferred from the side of the first nitride semiconductor layer 13 is diffused in the in-plane direction by the heat equalizing layer 12c which is a continuous film, and the heat is efficiently transmitted to the substrate 11 side. It will be possible to communicate. As described above, according to the present embodiment, since the AlN buffer layer 12 is not divided in the in-plane direction by having the heat equalizing layer 12 c, the heat transfer resistance component is reduced to achieve good heat dissipation. As a result, it is possible to obtain the property, and as a result, the heat radiation effect to the side of the substrate 11 through the AlN buffer layer 12 can be made favorable.

(B) In particular, as described in the present embodiment, if the heat equalizing layer 12c has a thickness of 3 nm or more, the heat equalizing layer 12c can be reliably made a continuous film. Further, if the heat spreader 12c has a thickness of 3 nm or more, for example, even if the nucleation layer 12b is a discontinuous film, the thinnest portion of the AlN buffer layer 12 has a thickness of 3 nm or more. This is very effective in improving the heat radiation effect to the side of the substrate 11.

(C) Further, according to the present embodiment, since the size of the concavities and convexities in the concavo-convex surface 12 a is small to such an extent that the surface roughness Rz of the concavo-convex surface 12 a in the nucleation layer 12 b is less than 20 nm The heat from the side of the first nitride semiconductor layer 13 is more easily transmitted to the AlN buffer layer 12 compared to the case where. This is considered to be because energy transfer is more likely to occur between the crystal lattices because the smaller the unevenness, the more the crystal lattices are aligned. That is, by reducing the unevenness on the uneven surface 12a, it is possible to transfer the heat transmitted from the side of the first nitride semiconductor layer 13 to the side of the substrate 11 favorably, and the side of the substrate 11 via the AlN buffer layer 12 It is very effective in improving the heat radiation effect to the substrate.

(D) Further, according to the present embodiment, since the value of the surface roughness Rz of the concavo-convex surface 12 a in the nucleation layer 12 b is 7 nm or more, a good crystal is obtained for the first nitride semiconductor layer 13 formed thereon Quality will be obtained. That is, if the size of the unevenness on the uneven surface 12a is too small, the crystal quality of the first nitride semiconductor layer 13 formed thereon may be adversely affected, but if the value of the surface roughness Rz is 7 nm or more The adverse effect on the crystal quality of the first nitride semiconductor layer 13 can be suppressed. Therefore, for example, it is possible to obtain the first nitride semiconductor layer 13 of good crystal quality in which the defect density is low and the residual impurity concentration is suppressed.

(E) Further, in the present embodiment, the first nitride semiconductor layer 13 formed on the concavo-convex surface 12 a of the nucleation layer 12 b of the AlN buffer layer 12 is formed with a thickness of 0.4 μm to 2.0 μm. It is done. The first nitride semiconductor layer (GaN layer) 13 epitaxially grown on the concavo-convex surface 12 a of the nucleation layer 12 b can alleviate the adverse effect on the crystal quality caused by the size of the concavities and convexities of the concavo-convex surface 12 a, This leads to an increase in growth time (that is, deterioration in productivity). According to the present embodiment, since the film thickness of the first nitride semiconductor layer 13 is set to 0.4 μm or more and 2.0 μm or less, both the deterioration suppression of the crystal quality and the deterioration suppression of the productivity are satisfied in a balanced manner. Is possible. That is, while making it possible to reliably reduce the adverse effect on the crystal quality by setting the film thickness to 0.4 μm or more, suppressing the deterioration of productivity as much as possible by setting the film thickness to 2.0 μm or less it can.

Other Embodiments
The embodiments of the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

In the above-described embodiment, mainly, the heat equalizing layer 12c has a thickness of 3 nm or more, and the surface roughness Rz of the concavo-convex surface 12a of the nucleation layer 12b is 7 nm or more and is less than 20 nm. However, the present invention is not limited thereto.
For example, depending on the film thickness of the heat equalizing layer 12c, the relationship between the surface temperature of the second nitride semiconductor layer 14 and the surface roughness Rz of the uneven surface 12a of the nucleation layer 12b exhibits different behavior from that of FIG. Even if the value of the roughness Rz is out of the range shown in the present embodiment, good heat dissipation may be obtained. Similarly, for example, depending on the value of the surface roughness Rz of the uneven surface 12a of the nucleation layer 12b, the relationship between the surface temperature of the second nitride semiconductor layer 14 and the film thickness of the heat equalizing layer 12c is as shown in FIG. Shows a different behavior, and good heat dissipation may be obtained even if the film thickness of the heat equalizing layer 12c is out of the range shown in this embodiment. That is, the film thickness of the heat equalizing layer 12c and the value of the surface roughness Rz of the uneven surface 12a of the nucleation layer 12b mutually affect each other in terms of heat dissipation. Therefore, with regard to the heat dissipation, depending on the combination of the film thickness of the heat equalizing layer 12c and the value of the surface roughness Rz of the uneven surface 12a, the heat dissipation may occur even if these numerical values are out of the range shown in this embodiment. It may be possible to make the sex a good thing.
The same can be said for the crystal quality of the first nitride semiconductor layer 13 as well as the heat dissipation. That is, if the value of the surface roughness Rz of the uneven surface 12a is appropriately set, a good crystal is obtained regardless of the combination of the value of the surface roughness Rz and the film thickness of the heat equalizing layer 12c. Quality and heat dissipation may be obtained.
Based on the above, even if any numerical value is out of the range shown in the present embodiment, the AlN buffer layer 12 is added to the nucleation layer 12 b and the heat spreader layer 12 c is a continuous film. As long as it is included, it becomes feasible to obtain good heat dissipation while maintaining good crystal quality.

In the embodiment described above, the intermediate (nitride semiconductor epitaxial substrate) 10 is the substrate 11, the AlN layer (AlN buffer layer) 12, the GaN layer (first nitride semiconductor layer) 13, and the AlGaN layer (second nitride) Although the case where the semiconductor layer 14 is stacked is taken as an example, the present invention is not limited to this. In the nitride semiconductor epitaxial substrate according to the present invention, the nitride semiconductor layer may be a single layer, as long as the nitride semiconductor layer is formed at least on the substrate via the buffer layer. It may have other layers not described in the above embodiment.

In the above-described embodiment, the first nitride semiconductor layer is the GaN layer 13 and the second nitride semiconductor layer is the AlGaN layer 14 by way of example, but the present invention is limited thereto is not. That is, the nitride semiconductor layer is not limited to the GaN crystal or the AlGaN crystal as long as it is made of a single crystal of a group III nitride semiconductor, and for example, aluminum nitride (AlN), indium nitride (InN), indium gallium nitride A nitride crystal such as InGaN) or aluminum indium nitride nitride (AlInGaN), that is, a nitride crystal represented by a composition formula of Al _x In _y Ga _{1 -x-} N (0 ≦ x + y ≦ 1) It may be.

In the above-described embodiment, the HEMT 20 which is one of the FETs is taken as an example of a semiconductor device manufactured using the intermediate (nitride semiconductor epitaxial substrate) 10, but the present invention is limited thereto The same applies to other semiconductor devices.

<Preferred embodiment of the present invention>
Hereinafter, preferred embodiments of the present invention will be additionally stated.

[Supplementary Note 1]
According to one aspect of the invention:
A substrate,
A buffer layer formed on the substrate;
And a nitride semiconductor layer formed on the buffer layer.
The buffer layer is
A nucleation layer having an irregular surface facing the nitride semiconductor layer;
A heat equalizing layer comprising a continuous film disposed on the side of the substrate;
A nitride semiconductor epitaxial substrate is provided.

[Supplementary Note 2]
In the nitride semiconductor epitaxial substrate described in Appendix 1, preferably
The heat equalizing layer is formed to have a film thickness of 3 nm or more.

[Supplementary Note 3]
Preferably, in the nitride semiconductor epitaxial substrate described in the supplementary note 1 or 2,
The nucleation layer is formed to have a surface roughness Rz of less than 20 nm.

[Supplementary Note 4]
In the nitride semiconductor epitaxial substrate described in Appendix 3, preferably,
The nucleation layer is formed to have a surface roughness Rz of 7 nm or more.

[Supplementary Note 5]
Preferably, in the nitride semiconductor epitaxial substrate as set forth in Appendix 3 or 4,
The nitride semiconductor layer has a first layer formed on the uneven surface of the nucleation layer,
The first layer is formed to have a thickness of 0.4 μm to 2.0 μm.

DESCRIPTION OF SYMBOLS 10 Nitride semiconductor epitaxial substrate (intermediate) 11 11 substrate 12 buffer layer (AlN buffer layer) 12a uneven surface

12b nucleation layer

12c soaking layer 13 first nitride semiconductor Layer (GaN layer, GaN channel / buffer layer), 14 ... second nitride semiconductor layer (AlGaN layer, AlGaN barrier layer), 15 ... two-dimensional electron gas (2DEG), 17 ... near interface region, 20 ... semiconductor device ( HEMT), 21: third nitride semiconductor layer (GaN layer, GaN cap layer), 22: gate electrode, 23: source electrode, 24: drain electrode

Claims

A substrate,
A buffer layer formed on the substrate;
And a nitride semiconductor layer formed on the buffer layer.
The buffer layer is
A nucleation layer having an irregular surface facing the nitride semiconductor layer;
A heat equalizing layer comprising a continuous film disposed on the side of the substrate;
A nitride semiconductor epitaxial substrate including:
The nitride semiconductor epitaxial substrate according to claim 1, wherein the heat equalizing layer is formed to have a film thickness of 3 nm or more.
The nitride semiconductor epitaxial substrate according to claim 1, wherein the nucleation layer is formed such that the value of the surface roughness Rz of the uneven surface is less than 20 nm.
The nitride semiconductor epitaxial substrate according to claim 3, wherein the nucleation layer is formed such that the value of the surface roughness Rz of the uneven surface is 7 nm or more.
The nitride semiconductor layer has a first layer formed on the uneven surface of the nucleation layer,
The nitride semiconductor epitaxial substrate according to claim 3, wherein the first layer is formed to have a thickness of 0.4 μm or more and 2.0 μm or less.