WO2019130337A1 - Method for the fabrication of ultralow voltage operated, reduced bias stress, multi-layer dielectric system comprising n-type organic field effect transistors - Google Patents

Method for the fabrication of ultralow voltage operated, reduced bias stress, multi-layer dielectric system comprising n-type organic field effect transistors Download PDF

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Publication number
WO2019130337A1
WO2019130337A1 PCT/IN2018/050853 IN2018050853W WO2019130337A1 WO 2019130337 A1 WO2019130337 A1 WO 2019130337A1 IN 2018050853 W IN2018050853 W IN 2018050853W WO 2019130337 A1 WO2019130337 A1 WO 2019130337A1
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dielectric layer
dielectric
layer
type organic
ofet device
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PCT/IN2018/050853
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French (fr)
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Parameswar Krishnan Iyer
Anamika DEY
Ashish Singh
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Indian Institute Of Technology, Guwahati
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
    • H10K10/476—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure comprising at least one organic layer and at least one inorganic layer

Definitions

  • the present invention relates to transistor device. More specifically, the present invention is directed to develop an ultra-low voltage operated, highly stable, n-type Organic Field Effect Transistor (OFET) device and a method for fabricating such OFET devices.
  • the OFET devices of the present invention can be used as a flexible, cheap and disposable optoelectronics sensor for stable, low-powered electronic component for the next generation of electronics appliances.
  • OFETs Organic Field Effect Transistors
  • Si0 2 Highly doped Silicon dioxide
  • Si0 2 is traditionally used as dielectric material for OFET fabrication because of its stable dielectric strength. But due to the low k-value, the operating voltage of Si0 2 based OFETs are observed to be higher which further increases the consumption of power. Additionally with this, the device having Si0 2 as gate insulating layer, show poor stability under continuous electrical operation [Ref: Bobbert, P. A.; Sharma, A.; Mathijssen, S. G.; Kemerink, M.; de Leeuw, D. M. Operational Stability of Organic Field- Effect Transistors. Adv. Mater. 2012, 24, 1146-1158; Ng, T. N.; Daniel, J.
  • the basic object of the present invention is to develop an ultra-low voltage operated organic thin film transistor.
  • Another object of the present invention is to develop an ultra-low voltage operated organic thin film transistor which would be operable below 2V and exhibit high electron mobility.
  • Another object of the present invention is to develop an ultra-low voltage operated n-type organic semiconductor based transistor which be operable below 2V and exhibit high electron mobility.
  • Yet another object of the present invention is to develop an ultra-low voltage operated n-type organic semiconductor based transistor which be adapted to operate as a flexible, cheap and disposable sensor for stable, low-powered electronic component.
  • a still further object of the present invention is to develop a simple, low cost method for fabricating the ultra-low voltage operated n-type organic semiconductor based transistor.
  • an ultra-low voltage operated Organic Field Effect Transistor (OFET) device comprising a base substrate; a gate electrode deposited on said base substrate; layered hybrid dielectrics deposited on said gate electrode having top and bottom dielectric layer of low dielectric constant (k) based dielectric materials and intermediate dielectric layer of high dielectric constant (k) based dielectric material; n-type organic semiconducting layer based active channel deposited on top of said layered hybrid dielectrics; a source electrode and a drain electrode deposited on the top side of said n- type organic semiconducting layer.
  • OFET Organic Field Effect Transistor
  • the layered hybrid dielectrics comprises said bottom dielectric layer of low-k dielectric material on the gate electrode constituting a thin barrier layer in between the intermediate dielectric layer and the gate electrode to prevent gate leakage current and isolate the intermediate dielectric layer from said gate electrode; said intermediate dielectric layer of metal oxide nano-particle based high-k dielectric material on said bottom dielectric layer to reduce operating voltage and threshold voltage of the OFET device by accumulating charge carriers in semiconducting layer-dielectric interface and filling trap energy level; and said top dielectric layer of low-k dielectric material on said intermediate dielectric layer acting as buffer layer in between the metal oxide NPs dielectric based intermediate layer and the active n-type organic semiconducting layer to prevent modification of the NPs dielectric surface of the intermediate layer and prevents the degradation of the n-type organic semiconductor of the active n-type organic semiconducting layer by protecting direct contact of it's with oxygen molecule of the intermediate dielectric layer.
  • the low-k dielectric material for the bottom dielectric layer having k value preferably within 10-12, the low-k dielectric material for the top dielectric layer having k value preferably within 3-9 and high-k dielectric material for the intermediate dielectric layer having k value preferably within 20-30 are selected to enable the intermediate dielectric layer dominant dielectric layer in the layered hybrid dielectrics.
  • the gate electrode comprises thermally deposited metal film preferably having thickness more than 200 nm with gate contact for application of gate voltage to the OFET device.
  • the bottom dielectric layer comprises a portion of the metal film oxidized through anodic oxidation preferably having thickness of with k-value ⁇ 10-12 to prevent the gate leakage up to 5 mA, whereby rest of the thick metal film operates as the gate electrode.
  • the intermediate dielectric layer comprises solution processable spin coated metal oxide NPs based high-k dielectric material deposition on the bottom dielectric layer having thickness of ⁇ 100-110 nm.
  • the top dielectric layer comprises spin coated dielectric material deposition on the intermediate dielectric layer having thickness of 80 ⁇ 200 nm and k value 3-9.
  • the n-type organic semiconducting layer based active channel includes thermal deposition of n- type monomer thin film having thickness of 60-100 nm.
  • the source electrode and the drain electrode includes thermally deposited metallic source-drain contact deposited on the top side of said n-type organic semiconducting layer to provide n-type organic semiconducting layer based active channel having channel length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
  • n-type organic semiconducting layer based active channel on top of said layered hybrid dielectric structure; depositing the source electrode and the drain electrode deposited on the top side of said n-type organic semiconducting layer.
  • the base substrate preferably includes glass substrate cleaned by acidic piranha solution (3: 1 ratio of H 2 S0 4 : H 2 0 2 ) or PET substrate cleaned by detergent.
  • the deposition of the gate electrode includes thermally depositing metal through a shadow mask on the base substrate forming the metal film preferably having thickness more than 200 nm with gate contact.
  • the fabrication of the layered hybrid dielectric structure comprises
  • sol-gel solution of the metal-oxide NPs based dielectric material having k-value ⁇ 20-30 by involving its isopropoxide solution, alcohol, acetic acid and water and spin coating the sol-gel solution on the bottom dielectric layer to grow the intermediate dielectric layer of thickness ⁇ 100-110 nm and k-value ⁇ 20-30;
  • the fabrication of the n-type organic semiconducting layer based active channel comprises
  • n-type monomer preparing n-type monomer; applying a thin film of the n-type monomer on the layered hybrid dielectrics having thickness of 60-100 nm by involving thermal deposition technique in organic thermal deposition chamber, wherein the monomer is sublimed during deposition to ensure the substrate temperature can be kept constant, ranging from room temperature to 150°C under 10 7 mbar pressure.
  • the deposition of the source electrode and the drain electrode includes thermally depositing metallic source-drain contact of thickness 80-130 on the n-type organic semiconducting layer through a shadow mask to define the active channel on the n-type organic semiconducting layer having length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
  • FIG. 1 shows schematic illustration of a preferred embodiment of the present n type Organic Field Effect Transistor (OFET) device.
  • OFET Organic Field Effect Transistor
  • Figure 2 shows Drain Characteristics of PDI-C8 based OFET device with respect to different Ti0 2 deposition speed (r.p.m) (a) 2000 r.p.m. (b) 3000 r.p.m. (c) 4000 r.p.m. and (d) 5000 r.p.m. respectively in accordance with an embodiment of the present invention.
  • Figure 3 shows Transfer Characteristics of PDI-C8 based OFET device with respect to different Ti0 2 deposition speed (r.p.m) (a) 2000 r.p.m. (b) 3000 r.p.m. (c) 4000 r.p.m. and (d) 5000 r.p. m. respectively in accordance with an embodiment of the present invention.
  • the present invention discloses an ultra-low voltage operated, highly stable, n-type Organic Field Effect Transistor (OFET) device which can be used as a flexible, cheap and disposable optoelectronics sensor for stable, low-powered electronic component.
  • the OFET device of the present invention advantageously includes a hybrid multilayered dielectric structure which significantly lower the operating voltage of the OFET device and prevent the gate leakage current.
  • This invention also explains a very simple, highly stable, cost effective and compatible over flexible substrate, layered hybrid dielectric structure for ultra-low voltage operated n-channel organic field effect transistor.
  • the present OFET device (1) basically comprises a base substrate (2), a gate electrode (3), hybrid multilayered dielectrics (4-5-6), a organic semiconducting layer (7), a source electrode (8) and a drain electrode (9).
  • the base substrate (2) constitutes the lowest level of the OFET device (1).
  • the base substrate (2) is preferably made of glass or PET and provides structural stability to the entire OFET device (1).
  • the gate electrode (3) which is basically a metal film with gate contact is thermally deposited on the base substrate (2).
  • the hybrid layered dielectrics (4-5-6) of the OFET device (1) is fabricated on the gate electrode (3).
  • the hybrid multilayered dielectric structure preferably includes three types of dielectric layers of dielectric materials with different dielectric constant (k) viz. top dielectric layer (4), bottom dielectric layer (6) and intermediate dielectric layer (5). Each of the dielectric layers has very important role in lowering operating voltage of the OFET device.
  • the bottom dielectric layer (6) comprises dielectric material with low dielectric constant (k) (preferably k-value ⁇ 10-12) and it is deposited on the gate electrode (3) by using low-cost anodic oxidation method to constitute a thin barrier layer in between the intermediate dielectric layer (5) and the gate electrode (3).
  • the intermediate dielectric layer (5) preferably comprises metal oxide nano- particle (NPs) based dielectric material (having k-value ⁇ 20-30) and deposited over the bottom low-k dielectric layer (6).
  • NPs metal oxide nano- particle
  • the intermediate dielectric layer (5) accumulates charge carriers in semiconducting layer- dielectric interface so that it can fill the trap energy level and reduce the threshold voltage and operating voltage of the OFET device.
  • the top dielectric layer (4) of dielectric material with low k value (having k- value ⁇ 3-9) is deposited over the intermediate dielectric layer (5).
  • the top dielectric layer (4) acts as a buffer layer in between the metal oxide NPs dielectric based intermediate layer (5) and the active semiconducting layer (7) deposited over the layered hybrid dielectrics.
  • the top dielectric layer (4) modify the NPs dielectric surface of the intermediate layer (5) and prevents the degradation of the semiconductor by protecting direct contact of it's with oxygen molecule of the intermediate dielectric layer (5).
  • the organic semiconducting layer (7) which is deposited over the hybrid layered dielectrics comprise n-type organic semiconductor and constitutes active channel of the present OFET device.
  • the OFET device (1) also includes a source electrode (8) and a drain electrode (9) which are deposited on the top side of the n-type organic semiconducting layer (7).
  • the bottom low-k dielectric layer (6) is provided to prevent gate current leakage and avoid any direct contact between the intermediate dielectric layer (5) and the gate electrode (3).
  • the bottom dielectric layer (6) is constituted by oxidizing upper surface portion of the metallic film of the gate electrode (3) through anodic oxidation.
  • the intermediate high-k NPs dielectric layer (5) is fabricated by spin coating sol-gel solution of the high-k NPs dielectric material onto the bottom dielectric layer (6).
  • the synthesized sol-gel solution of the NPs dielectric material of the dielectric layer (5) is systematically examined by various characterization techniques like, UV-Vis spectroscopy, X-ray diffraction spectroscopy (XRD), Field-emission scanning electron microscopy (FESEM) and Transmission electron microscopy (TEM) to control its average particle size and polycrystalline in nature.
  • this multi-dielectric layer based OFET device showing similar suitable gate dielectric property in case of flexible and transparent substrate with same ultra-low operational voltage.
  • This high performance OFET device having operating voltage ⁇ 2V, with optimum high-k metal oxide NPs dielectric contained hybrid multi-layer dielectric system is expected to have diverse applications in next generation of portable electronics. The results are shown in the accompanying figure 2 and the figure 3.
  • the present invention also relates to a novel fabrication method of the present ultra-low voltage operated OFET device comprising of three specific layers of dielectric system which are compatible with any desired substrate viz. on simple glass slide or plastic substrate and can be used for the application of optoelectronic applications with n-type organic semiconductor as the active layer under room temperature.
  • Step 1 Substrate cleaning method :
  • the substrate is initially cut into (1 cm x 2.5 cm) square substrate.
  • the substrate is dried separately by N 2 air flash under room temperature.
  • Step 2 Gate electrode and bottom low-k dielectric layer deposition by anodic oxidation method :
  • a metal thin film having thickness more than 200 nm is thermally deposited through a shadow mask in such a way that 13-60 nm of the upper surface of the metal can be oxidized by anodic oxidation method to grow the bottom dielectric layer having k-value ⁇ 10-12.
  • the rest portion of the metal film is used for the gate contact. This function of this dielectric layer is to prevent the gate leakage up to 5 mA and prevent the direct contact of the bottom dielectric layer with the gate electrode.
  • the metal oxide NPs based dielectric material is first prepared by sol-gel method with the help of its isopropoxide solution, alcohol, acetic acid and water.
  • the possible metal-oxide NPs based dielectric material can be synthesized by above mentioned components and can be used for low voltage operations and are listed below in Table 1.
  • the sol-gel solution of this high-k metal oxide NPs based dielectric material is then spin coated on the bottom dielectric layer in such a way that the thickness of the layer is ⁇ 100-110 nm. Note that the synthesized metal oxide NPs dielectric must have k-value ranges from 20-30.
  • Step 4 Deposition of top low-k dielectric layer:
  • the top dielectric layer (having k-value ⁇ 3-9) is spin coated on it to reduce the micro cracks of the surface of the intermediate dielectric layer in such a way that it can be used as a buffer layer in between metal oxide NPs dielectric layer and the n-type active semiconducting layer. It is also used to prevent the degradation of n-type semiconductor by protecting direct contact of it's with the oxygen molecule of the intermediate dielectric layer.
  • the possible top dielectric layer materials which can be used for the purpose are listed below in Table 2.
  • Step 5 Deposition of n-type active organic semiconducting layer and source- drain electrodes:
  • a n-type semiconducting thin film of monomer is deposited on the layered hybrid dielectrics by thermal deposition technique in an organic thermal deposition chamber to constitute the n-type active organic semiconducting layer.
  • the monomer is sublimed in such a way that during deposition, the substrate temperature can be kept constant, ranging from room temperature to 150°C under 10 7 mbar pressure.
  • the thickness of the film is varied between 60-100 nm.
  • 80-130 nm thick metallic source-drain contact is thermally deposited on the top side of the n-type active organic semiconducting layer through a shadow mask to constitute the active channel of length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
  • the present invention provides a method for characterization of device comprising the following steps:
  • the gate voltage and drain voltage applied may be between about 0 V and 2 V.
  • This ultra-low operating voltage n-type OFET device with multi-layer dielectric system is thus can have diverse applications in future for portable organic electronics application.

Abstract

The present invention reports an ultra-low voltage operated, highly stable, n-type Organic Field Effect Transistor (OFET) device and a method for fabricating such OFET device. The OFET device of the present invention includes a base substrate (1); a gate electrode (3) deposited on said base substrate; layered hybrid dielectrics (4-5-6) deposited on said gate electrode having top and bottom dielectric layer of low dielectric constant based dielectric materials and intermediate dielectric layer of high dielectric constant based dielectric material; n-type organic semiconducting layer (7) based active channel deposited on top of said layered hybrid dielectrics and a source electrode and a drain electrode (8, 9) deposited on the top side of said n-type organic semiconducting layer.

Description

Title: METHOD FOR THE FABRICATION OF ULTRALOW VOLTAGE OPERATED, REDUCED BIAS STRESS, MULTI-LAYER DIELECTRIC SYSTEM COMPRISING N-TYPE ORGANIC FIELD EFFECT TRANSISTORS FIELD OF THE INVENTION:
The present invention relates to transistor device. More specifically, the present invention is directed to develop an ultra-low voltage operated, highly stable, n-type Organic Field Effect Transistor (OFET) device and a method for fabricating such OFET devices. The OFET devices of the present invention can be used as a flexible, cheap and disposable optoelectronics sensor for stable, low-powered electronic component for the next generation of electronics appliances.
BACKGROUND OF THE INVENTION:
Organic Field Effect Transistors (OFETs) is one of the most attractive electronic components which are expected to be one of the best alternatives of amorphous Si -transistors in near future due to its superior qualities like easy fabrication technique, low-cost, mechanical flexibility and biocompatibility under low operating voltage range. [Ref: Chua, L.-L.; Zaumseil, J.; Chang, J.-F.; Ou, E. C.-W.; Ho, P. K.-H.; Sirringhaus, Friend, H.; R. H. General Observation of n-Type Field-Effect behaviour in Organic Semiconductors. Nature 2005, 434, 194-198; Hardigree, J. F. M.; Howard E. K. Through Thick and Thin: Tuning the Threshold Voltage in Organic Field- Effect Transistors. Acc. Chem. Res. 2014, 47, 1369-1377; Hlaing, H.; Kim C.-H.; Carta F.; Nam, C.-Y.; Barton R.A.; Petrone, N.; Hone, J.; Kymissis, I. Low-Voltage Organic Electronics based on a Gate-Tunable Injection Barrier in Vertical Graphene-Organic Semiconductor Heterostructures. Nano Lett. 2015, 15, 69-74; Dey, A .} Singh, A.; Das, D.; Iyer, P. K. High-Performance ZnPc Thin Film-based Photosensitive Organic Field-Effect Transistors: Influence of Multilayer Dielectric Systems and Thin Film Growth Structure. ACS Omega 2017, 2, 1241 -1248]. However, to achieve these targets, urgent efforts have to be diverted in reducing the operating voltage of the device and on its l electrical stability so that it can be efficiently used as a stable, low-powered electronic component for the next generation of electronics market.
Generally, most of the reported OFETs are found to be operating under large operating voltage range due to the high band gap of the organic semiconductors and low k-value of gate dielectric, which restricted their use towards low cost portable electronic applications. [Ref: Dey, A.; Kalita, A.; Iyer, P. K. High-Performance n -Channel Organic Thin-Film Transistor based on Naphthalene Diimide. ACS Appl. Mater. Interfaces 2014, 6, 12295-12301; Shukla, D.; Nelson, S. F.; Freeman, D. C.; Rajeswaran, M.; Ahearn, W. G.; Meyer, D. M.; Carey, J. T. Thin-Film Morphology Control in Naphthalene- Diimide-based Semiconductors: High Mobility n-Type Semiconductor for
Figure imgf000004_0001
Transport in Solution-Processed n-Channel Organic Thin-Film Transistors. Adv. Mater. 2016, 28, 5276-5283.]
Highly doped Silicon dioxide (Si02) is traditionally used as dielectric material for OFET fabrication because of its stable dielectric strength. But due to the low k-value, the operating voltage of Si02 based OFETs are observed to be higher which further increases the consumption of power. Additionally with this, the device having Si02 as gate insulating layer, show poor stability under continuous electrical operation [Ref: Bobbert, P. A.; Sharma, A.; Mathijssen, S. G.; Kemerink, M.; de Leeuw, D. M. Operational Stability of Organic Field- Effect Transistors. Adv. Mater. 2012, 24, 1146-1158; Ng, T. N.; Daniel, J. H.; Sambandan, S.; Arias, A.-C.; Chabinyc, M. L.; Street, R. A. Gate Bias Stress Effects due to Polymer Gate Dielectrics in Organic Thin-Film Transistors. J. Appl. Phys. 2008, 103, 044506(1 -5)]. Similarly, there are several other high-k organic, inorganic and hybrid gate insulating materials that have been mentioned in literature to achieve efficient OFET performance [Ref: Kumar, S.; Dhar A. Low Operating Voltage n-Channel Organic Field Effect Transistors using Lithium Fluoride/PMMA Bilayer Gate Dielectric. Mater. Res. Bull. 2015, 70, 590-594; Ye, X.; Lin, H.; Yu, X.; Han, S.; Shang, M.; Zhang, L.; Jiang, Q.; Zhong, J. High Performance Low-Voltage Organic Field-Effect Transistors Enabled by Solution Processed Alumina and Polymer Bilayer Dielectrics. Synth. Met. 2015, 209, 337-342; Ortiz, R. P.; Facchetti, A.; Marks, T. J. High-k Organic, Inorganic, and Hybrid Dielectrics for Low-Voltage Organic Field-Effect Transistors. Chem. Rev. 2010, 110, 205-239].
Though these materials have very good capacitance value and film forming probability, these are not high enough to accumulate large number of charge carriers at the semiconductor-dielectric interface and therefore does not able to reduce the operating voltage below 2 V. Furthermore, if the operating voltage is not reduced to 2V, it limited OFETs application especially in case of biosensor, display, smart card, etc.
Thus there has been a need for developing new ultra-low operating voltage organic thin film transistors which will be operable below 3V and adapted to be used as a flexible, cheap and disposable sensor for stable, low-powered electronic component for the next generation of electronics market are demonstrated.
OBJECT OF THE INVENTION:
It is thus the basic object of the present invention is to develop an ultra-low voltage operated organic thin film transistor.
Another object of the present invention is to develop an ultra-low voltage operated organic thin film transistor which would be operable below 2V and exhibit high electron mobility.
Another object of the present invention is to develop an ultra-low voltage operated n-type organic semiconductor based transistor which be operable below 2V and exhibit high electron mobility.
Yet another object of the present invention is to develop an ultra-low voltage operated n-type organic semiconductor based transistor which be adapted to operate as a flexible, cheap and disposable sensor for stable, low-powered electronic component. A still further object of the present invention is to develop a simple, low cost method for fabricating the ultra-low voltage operated n-type organic semiconductor based transistor.
SUMMARY OF THE INVENTION:
Thus according to the basic aspect of the present invention there is provided an ultra-low voltage operated Organic Field Effect Transistor (OFET) device comprising a base substrate; a gate electrode deposited on said base substrate; layered hybrid dielectrics deposited on said gate electrode having top and bottom dielectric layer of low dielectric constant (k) based dielectric materials and intermediate dielectric layer of high dielectric constant (k) based dielectric material; n-type organic semiconducting layer based active channel deposited on top of said layered hybrid dielectrics; a source electrode and a drain electrode deposited on the top side of said n- type organic semiconducting layer.
According to another aspect in the present OFET device, the layered hybrid dielectrics comprises said bottom dielectric layer of low-k dielectric material on the gate electrode constituting a thin barrier layer in between the intermediate dielectric layer and the gate electrode to prevent gate leakage current and isolate the intermediate dielectric layer from said gate electrode; said intermediate dielectric layer of metal oxide nano-particle based high-k dielectric material on said bottom dielectric layer to reduce operating voltage and threshold voltage of the OFET device by accumulating charge carriers in semiconducting layer-dielectric interface and filling trap energy level; and said top dielectric layer of low-k dielectric material on said intermediate dielectric layer acting as buffer layer in between the metal oxide NPs dielectric based intermediate layer and the active n-type organic semiconducting layer to prevent modification of the NPs dielectric surface of the intermediate layer and prevents the degradation of the n-type organic semiconductor of the active n-type organic semiconducting layer by protecting direct contact of it's with oxygen molecule of the intermediate dielectric layer.
According to yet another aspect in the present OFET device, the low-k dielectric material for the bottom dielectric layer having k value preferably within 10-12, the low-k dielectric material for the top dielectric layer having k value preferably within 3-9 and high-k dielectric material for the intermediate dielectric layer having k value preferably within 20-30 are selected to enable the intermediate dielectric layer dominant dielectric layer in the layered hybrid dielectrics.
According to a further aspect in the present OFET device, the gate electrode comprises thermally deposited metal film preferably having thickness more than 200 nm with gate contact for application of gate voltage to the OFET device.
According to a further aspect in the present OFET device, the bottom dielectric layer comprises a portion of the metal film oxidized through anodic oxidation preferably having thickness of with k-value ~10-12 to prevent the gate leakage up to 5 mA, whereby rest of the thick metal film operates as the gate electrode. According to yet another aspect in the present OFET device, the intermediate dielectric layer comprises solution processable spin coated metal oxide NPs based high-k dielectric material deposition on the bottom dielectric layer having thickness of ~100-110 nm.
According to another aspect in the present OFET device, the top dielectric layer comprises spin coated dielectric material deposition on the intermediate dielectric layer having thickness of 80 ~ 200 nm and k value 3-9.
According to another aspect in the present OFET device, the n-type organic semiconducting layer based active channel includes thermal deposition of n- type monomer thin film having thickness of 60-100 nm.
According to another aspect in the present OFET device, the source electrode and the drain electrode includes thermally deposited metallic source-drain contact deposited on the top side of said n-type organic semiconducting layer to provide n-type organic semiconducting layer based active channel having channel length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
According to another aspect in the present invention there is provided a method for fabricating the OFET device comprising the steps of involving the base substrate;
depositing the gate electrode on said base substrate;
fabricating layered hybrid dielectric structure on said gate electrode by involving low-k dielectric materials in top and bottom dielectric layers and high-k dielectric material in intermediate dielectric layer;
fabricating n-type organic semiconducting layer based active channel on top of said layered hybrid dielectric structure; depositing the source electrode and the drain electrode deposited on the top side of said n-type organic semiconducting layer.
According to another aspect in the present method for fabricating the OFET, the base substrate preferably includes glass substrate cleaned by acidic piranha solution (3: 1 ratio of H2S04: H202) or PET substrate cleaned by detergent.
According to another aspect in the present method for fabricating the OFET, the deposition of the gate electrode includes thermally depositing metal through a shadow mask on the base substrate forming the metal film preferably having thickness more than 200 nm with gate contact.
According to another aspect in the present method for fabricating the OFET, the fabrication of the layered hybrid dielectric structure comprises
oxidizing upper surface of the metal film by anodic oxidation to grow the bottom dielectric layer with k-value ~10-12 and thickness 13-60 nm;
preparing sol-gel solution of the metal-oxide NPs based dielectric material having k-value ~20-30 by involving its isopropoxide solution, alcohol, acetic acid and water and spin coating the sol-gel solution on the bottom dielectric layer to grow the intermediate dielectric layer of thickness ~100-110 nm and k-value ~20-30;
preparing solution of dialectic material having k-value 3-9 and spin coating the dielectric solution on the intermediate dielectric layer to grow the top dielectric layer of thickness ~80 - 200 nm and k-value ~3-9.
According to another aspect in the present method for fabricating the OFET, the fabrication of the n-type organic semiconducting layer based active channel comprises
preparing n-type monomer; applying a thin film of the n-type monomer on the layered hybrid dielectrics having thickness of 60-100 nm by involving thermal deposition technique in organic thermal deposition chamber, wherein the monomer is sublimed during deposition to ensure the substrate temperature can be kept constant, ranging from room temperature to 150°C under 10 7 mbar pressure.
According to another aspect in the present method for fabricating the OFET, the deposition of the source electrode and the drain electrode includes thermally depositing metallic source-drain contact of thickness 80-130 on the n-type organic semiconducting layer through a shadow mask to define the active channel on the n-type organic semiconducting layer having length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
According to another aspect in the present invention there is provided a method for operating the OFET device including
involving OFET device;
applying a gate voltage at the gate electrode and a drain voltage at the drain electrode of said OFET device between about 0 V and 2 V enabling the n-type organic semiconducting layer exhibiting electron mobility as high as 0.3 cm2/Vs under vacuum with threshold voltage of 0.2 V and current on/off ratio ~104 under the operating voltage of 2V;
measuring drain current and gate current of the OFET device under application of the gate voltage and the drain voltage.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS:
Figure 1 shows schematic illustration of a preferred embodiment of the present n type Organic Field Effect Transistor (OFET) device.
Figure 2 shows Drain Characteristics of PDI-C8 based OFET device with respect to different Ti02 deposition speed (r.p.m) (a) 2000 r.p.m. (b) 3000 r.p.m. (c) 4000 r.p.m. and (d) 5000 r.p.m. respectively in accordance with an embodiment of the present invention. Figure 3 shows Transfer Characteristics of PDI-C8 based OFET device with respect to different Ti02 deposition speed (r.p.m) (a) 2000 r.p.m. (b) 3000 r.p.m. (c) 4000 r.p.m. and (d) 5000 r.p. m. respectively in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING DRAWINGS:
The present invention discloses an ultra-low voltage operated, highly stable, n-type Organic Field Effect Transistor (OFET) device which can be used as a flexible, cheap and disposable optoelectronics sensor for stable, low-powered electronic component. The OFET device of the present invention advantageously includes a hybrid multilayered dielectric structure which significantly lower the operating voltage of the OFET device and prevent the gate leakage current. This invention also explains a very simple, highly stable, cost effective and compatible over flexible substrate, layered hybrid dielectric structure for ultra-low voltage operated n-channel organic field effect transistor.
Reference is first invited from the accompanying figure 1 which shows a schematic illustration of a preferred embodiment of the present OFET device. As shown in the referred figure 1, the present OFET device (1) basically comprises a base substrate (2), a gate electrode (3), hybrid multilayered dielectrics (4-5-6), a organic semiconducting layer (7), a source electrode (8) and a drain electrode (9).
As shown in the referred figure 1, the base substrate (2) constitutes the lowest level of the OFET device (1). The base substrate (2) is preferably made of glass or PET and provides structural stability to the entire OFET device (1). The gate electrode (3) which is basically a metal film with gate contact is thermally deposited on the base substrate (2).
The hybrid layered dielectrics (4-5-6) of the OFET device (1) is fabricated on the gate electrode (3). The hybrid multilayered dielectric structure preferably includes three types of dielectric layers of dielectric materials with different dielectric constant (k) viz. top dielectric layer (4), bottom dielectric layer (6) and intermediate dielectric layer (5). Each of the dielectric layers has very important role in lowering operating voltage of the OFET device. The bottom dielectric layer (6) comprises dielectric material with low dielectric constant (k) (preferably k-value~10-12) and it is deposited on the gate electrode (3) by using low-cost anodic oxidation method to constitute a thin barrier layer in between the intermediate dielectric layer (5) and the gate electrode (3).
The intermediate dielectric layer (5) preferably comprises metal oxide nano- particle (NPs) based dielectric material (having k-value ~20-30) and deposited over the bottom low-k dielectric layer (6). The intermediate dielectric layer (5) accumulates charge carriers in semiconducting layer- dielectric interface so that it can fill the trap energy level and reduce the threshold voltage and operating voltage of the OFET device.
The top dielectric layer (4) of dielectric material with low k value (having k- value ~3-9) is deposited over the intermediate dielectric layer (5). The top dielectric layer (4) acts as a buffer layer in between the metal oxide NPs dielectric based intermediate layer (5) and the active semiconducting layer (7) deposited over the layered hybrid dielectrics. The top dielectric layer (4) modify the NPs dielectric surface of the intermediate layer (5) and prevents the degradation of the semiconductor by protecting direct contact of it's with oxygen molecule of the intermediate dielectric layer (5).
The organic semiconducting layer (7) which is deposited over the hybrid layered dielectrics comprise n-type organic semiconductor and constitutes active channel of the present OFET device. The OFET device (1) also includes a source electrode (8) and a drain electrode (9) which are deposited on the top side of the n-type organic semiconducting layer (7).
In the present OFET device (1), the bottom low-k dielectric layer (6) is provided to prevent gate current leakage and avoid any direct contact between the intermediate dielectric layer (5) and the gate electrode (3). In a preferred embodiment, the bottom dielectric layer (6) is constituted by oxidizing upper surface portion of the metallic film of the gate electrode (3) through anodic oxidation.
The intermediate high-k NPs dielectric layer (5) is fabricated by spin coating sol-gel solution of the high-k NPs dielectric material onto the bottom dielectric layer (6). Before the device fabrication, the synthesized sol-gel solution of the NPs dielectric material of the dielectric layer (5) is systematically examined by various characterization techniques like, UV-Vis spectroscopy, X-ray diffraction spectroscopy (XRD), Field-emission scanning electron microscopy (FESEM) and Transmission electron microscopy (TEM) to control its average particle size and polycrystalline in nature. To check the effect of this ordered, high-k dielectric material on the performance of n-channel organic filed effect transistor, four different types of OFETs with different device architecture is designed where the thickness of the bottom and the top dielectric layers are kept constant for all the devices and only the thickness of the intermediate dielectric layer is modulated very carefully in nanoscale range by varying the spin coating r.p.m. value viz., 2000, 3000, 4000 and 5000 respectively. It is observed that at 4000 r.p.m. (-100+10 nm) the devices with top contact bottom gate configuration exhibit excellent and highest n-channel behavior with highest electron mobility with ultra-low operating voltage of 2V. The electrical stability of the devices is also analyzed by bias stress instability study during long term operation under vacuum condition. Moreover, it is also observed that this multi-dielectric layer based OFET device showing similar suitable gate dielectric property in case of flexible and transparent substrate with same ultra-low operational voltage. This high performance OFET device having operating voltage ~2V, with optimum high-k metal oxide NPs dielectric contained hybrid multi-layer dielectric system is expected to have diverse applications in next generation of portable electronics. The results are shown in the accompanying figure 2 and the figure 3.
The present invention also relates to a novel fabrication method of the present ultra-low voltage operated OFET device comprising of three specific layers of dielectric system which are compatible with any desired substrate viz. on simple glass slide or plastic substrate and can be used for the application of optoelectronic applications with n-type organic semiconductor as the active layer under room temperature.
The detail of the device fabrication method for solution process, ultra-low operating voltage, stable organic field effect transistor with a top contact bottom-gate configuration are summarized in below-
Step 1 : Substrate cleaning method :
Two different types of substrates can be used as the base substrate according to their compatibility with the dielectric layers, namely, (a) Microscope glass slides and (b) plastic sheet. The substrate is initially cut into (1 cm x 2.5 cm) square substrate.
(a) The glass substrate is cleaned by dipping the substrate in acidic piranha solution (3: 1 ratio of h^SC^ I-^C^) for 1 hour. After that it is vigorously washed by de-ionized water for 8-10 times to remove the acidic layer on the substrate surface and then dried at 100°C on hot plate.
(b) The sliced plastic substrate is first cleaned with detergent 2-3 times and then vigorously washed by de-ionized water for 8-10 times.
After completing the washing operation, the substrate is dried separately by N2 air flash under room temperature.
Step 2: Gate electrode and bottom low-k dielectric layer deposition by anodic oxidation method :
After cleaning the base substrate, a metal thin film having thickness more than 200 nm is thermally deposited through a shadow mask in such a way that 13-60 nm of the upper surface of the metal can be oxidized by anodic oxidation method to grow the bottom dielectric layer having k-value ~10-12. The rest portion of the metal film is used for the gate contact. This function of this dielectric layer is to prevent the gate leakage up to 5 mA and prevent the direct contact of the bottom dielectric layer with the gate electrode. Step 3: Synthetic and deposition of metal oxide NPs based intermediate high- k dielectric layer:
The metal oxide NPs based dielectric material is first prepared by sol-gel method with the help of its isopropoxide solution, alcohol, acetic acid and water. The possible metal-oxide NPs based dielectric material can be synthesized by above mentioned components and can be used for low voltage operations and are listed below in Table 1. The sol-gel solution of this high-k metal oxide NPs based dielectric material is then spin coated on the bottom dielectric layer in such a way that the thickness of the layer is ~100-110 nm. Note that the synthesized metal oxide NPs dielectric must have k-value ranges from 20-30.
Table 1
Figure imgf000015_0001
Step 4: Deposition of top low-k dielectric layer:
Over the metal oxide NPs dielectric layer, the top dielectric layer (having k-value ~3-9) is spin coated on it to reduce the micro cracks of the surface of the intermediate dielectric layer in such a way that it can be used as a buffer layer in between metal oxide NPs dielectric layer and the n-type active semiconducting layer. It is also used to prevent the degradation of n-type semiconductor by protecting direct contact of it's with the oxygen molecule of the intermediate dielectric layer. The possible top dielectric layer materials which can be used for the purpose are listed below in Table 2.
Table 2
Figure imgf000015_0002
Figure imgf000016_0001
Step 5: Deposition of n-type active organic semiconducting layer and source- drain electrodes:
A n-type semiconducting thin film of monomer is deposited on the layered hybrid dielectrics by thermal deposition technique in an organic thermal deposition chamber to constitute the n-type active organic semiconducting layer. The monomer is sublimed in such a way that during deposition, the substrate temperature can be kept constant, ranging from room temperature to 150°C under 10 7 mbar pressure. The thickness of the film is varied between 60-100 nm. After that 80-130 nm thick metallic source-drain contact is thermally deposited on the top side of the n-type active organic semiconducting layer through a shadow mask to constitute the active channel of length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
In a further aspect, the present invention provides a method for characterization of device comprising the following steps:
(a) providing a device of the first aspect;
(b) applying a gate voltage and a drain voltage to the device
(c) measuring drain current; and gate current.
(d) The gate voltage and drain voltage applied may be between about 0 V and 2 V.
The present n-type OFET device can exhibit electron mobility as high as pe= 0.3 cm2/Vs, threshold voltages VTh= 0.2 V and current on/off ratio ~104 with an operating voltage of only 2V. This ultra-low operating voltage n-type OFET device with multi-layer dielectric system is thus can have diverse applications in future for portable organic electronics application.

Claims

WE CLAIM:
1. An ultra-low voltage operated Organic Field Effect Transistor (OFET) device comprising a base substrate; a gate electrode deposited on said base substrate; layered hybrid dielectrics deposited on said gate electrode having top and bottom dielectric layer of low dielectric constant (k) based dielectric materials and intermediate dielectric layer of high dielectric constant (k) based dielectric material; n-type organic semiconducting layer based active channel deposited on top of said layered hybrid dielectrics; a source electrode and a drain electrode deposited on the top side of said n- type organic semiconducting layer.
2. An OFET device as claimed in claim 1, wherein the layered hybrid dielectrics comprises said bottom dielectric layer of low-k dielectric material on the gate electrode constituting a thin barrier layer in between the intermediate dielectric layer and the gate electrode to prevent gate leakage current and isolate the intermediate dielectric layer from said gate electrode; said intermediate dielectric layer of metal oxide nano-particle based high-k dielectric material on said bottom dielectric layer to reduce operating voltage and threshold voltage of the OFET device by accumulating charge carriers in semiconducting layer-dielectric interface and filling trap energy level; and said top dielectric layer of low-k dielectric material on said intermediate dielectric layer acting as buffer layer in between the metal oxide NPs dielectric based intermediate layer and the active n-type organic semiconducting layer to prevent modification of the NPs dielectric surface of the intermediate layer and prevents the degradation of the n-type organic semiconductor of the active n-type organic semiconducting layer by protecting direct contact of it's with oxygen molecule of the intermediate dielectric layer.
3. An OFET device as claimed in claim 1 or 2, wherein the low-k dielectric material for the bottom dielectric layer having k value preferably within 10- 12, the low-k dielectric material for the top dielectric layer having k value preferably within 3-9 and high-k dielectric material for the intermediate dielectric layer having k value preferably within 20-30 are selected to enable the intermediate dielectric layer dominant dielectric layer in the layered hybrid dielectrics.
4. An OFET device as claimed in anyone of claims 1 to 3, wherein the gate electrode comprises thermally deposited metal film preferably having thickness more than 200 nm with gate contact for application of gate voltage to the OFET device.
5. An OFET device as claimed in anyone of claims 1 to 4, wherein the bottom dielectric layer comprises a portion of the metal film oxidized through anodic oxidation preferably having thickness of with k-value ~10-12 to prevent the gate leakage up to 5 mA, whereby rest of the thick metal film operates as the gate electrode.
6. An OFET device as claimed in anyone of claims 1 to 5, wherein the intermediate dielectric layer comprises solution processable spin coated metal oxide NPs based high-k dielectric material deposition on the bottom dielectric layer having thickness of ~100-110 nm.
7. An OFET device as claimed in anyone of claims 1 to 6, wherein the top dielectric layer comprises spin coated dielectric material deposition on the intermediate dielectric layer having thickness of 80 ~ 200 nm and k value 3-
9.
8. An OFET device as claimed in anyone of claims 1 to 7, wherein the n-type organic semiconducting layer based active channel includes thermal deposition of n-type monomer thin film having thickness of 60-100 nm.
9. An OFET device as claimed in anyone of claims 1 to 8, wherein the source electrode and the drain electrode includes thermally deposited metallic source-drain contact deposited on the top side of said n-type organic semiconducting layer to provide n-type organic semiconducting layer based active channel having channel length (L) and width (W) of 10-80 pm and 500- 1000 pm respectively.
10. A method for fabricating the OFET device as claimed in anyone of claims 1 to 9, comprising involving the base substrate; depositing the gate electrode on said base substrate; fabricating layered hybrid dielectric structure on said gate electrode by involving low-k dielectric materials in top and bottom dielectric layers and high-k dielectric material in intermediate dielectric layer;
fabricating n-type organic semiconducting layer based active channel on top of said layered hybrid dielectric structure; depositing the source electrode and the drain electrode deposited on the top side of said n-type organic semiconducting layer.
11. A method for fabricating the OFET device as claimed in claim 10, wherein the base substrate preferably includes glass substrate cleaned by acidic piranha solution (3: 1 ratio of H2S04: H202) or PET substrate cleaned by detergent.
12. A method for fabricating the OFET device as claimed in claim 10 or 11, wherein the deposition of the gate electrode includes thermally depositing metal through a shadow mask on the base substrate forming the metal film preferably having thickness more than 200 nm with gate contact.
13. A method for fabricating the OFET device as claimed in claim 10 or 11, wherein the fabrication of the layered hybrid dielectric structure comprises oxidizing upper surface of the metal film by anodic oxidation to grow the bottom dielectric layer with k-value ~10-12 and thickness 13-60 nm; preparing sol-gel solution of the metal-oxide NPs based dielectric material having k-value ~20-30 by involving its isopropoxide solution, alcohol, acetic acid and water and spin coating the sol-gel solution on the bottom dielectric layer to grow the intermediate dielectric layer of thickness ~100-110 nm and k-value ~20-30; preparing solution of dialectic material having k-value 3-9 and spin coating the dielectric solution on the intermediate dielectric layer to grow the top dielectric layer of thickness ~80 - 200 nm and k-value ~3-9.
14. A method for fabricating the OFET device as claimed in anyone of claim 10 to 13, wherein fabrication of the n-type organic semiconducting layer based active channel comprises preparing n-type monomer; applying a thin film of the n-type monomer on the layered hybrid dielectrics having thickness of 60-100 nm by involving thermal deposition technique in organic thermal deposition chamber, wherein the monomer is sublimed during deposition to ensure the substrate temperature can be kept constant, ranging from room temperature to 150°C under 10 7 mbar pressure.
15. A method for fabricating the OFET device as claimed in anyone of claim 10 to 14, wherein deposition of the source electrode and the drain electrode includes thermally depositing metallic source-drain contact of thickness 80- 130 on the n-type organic semiconducting layer through a shadow mask to define the active channel on the n-type organic semiconducting layer having length (L) and width (W) of 10-80 pm and 500-1000 pm respectively.
16. A method for operating the OFET device as claimed in anyone of claims 1 to 9, includes involving OFET device; applying a gate voltage at the gate electrode and a drain voltage at the drain electrode of said OFET device between about 0V and 2V enabling the n-type organic semiconducting layer exhibiting electron mobility as high as 0.3 cm2/Vs under vacuum with threshold voltage of 0.2 V and current on/off ratio ~104 under the operating voltage of 2V; measuring drain current and gate current of the OFET device under application of the gate voltage and the drain voltage.
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