WO2019129279A1 - 原边反馈反激电源ccm模式下的死区时间自动优化系统、原边反馈反激电源ccm模式下的控制系统及方法 - Google Patents

原边反馈反激电源ccm模式下的死区时间自动优化系统、原边反馈反激电源ccm模式下的控制系统及方法 Download PDF

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WO2019129279A1
WO2019129279A1 PCT/CN2018/125640 CN2018125640W WO2019129279A1 WO 2019129279 A1 WO2019129279 A1 WO 2019129279A1 CN 2018125640 W CN2018125640 W CN 2018125640W WO 2019129279 A1 WO2019129279 A1 WO 2019129279A1
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current
primary
voltage
output
peak
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PCT/CN2018/125640
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English (en)
French (fr)
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徐申
陈明刚
王浩
肖金玉
苏巍
孙伟锋
时龙兴
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无锡华润上华科技有限公司
东南大学
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Priority to US16/959,015 priority Critical patent/US11557959B2/en
Publication of WO2019129279A1 publication Critical patent/WO2019129279A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a flyback switching power supply using synchronous rectification primary side feedback, in particular to a dead time automatic optimization system for a synchronous rectification primary side feedback flyback power supply CCM mode, which belongs to the technical field of isolated switching power supply converters. It also relates to a control system and method in the CCM mode of the primary feedback flyback power supply.
  • Switching power supply also known as switching converter, is a kind of power source that uses modern power electronics technology to make the output voltage constant by adjusting the conduction ratio of the switching device.
  • the flyback converter Since the flyback converter has the dual functions of transformer and inductor, the flyback converter does not need to output the filter inductor, which is especially important for reducing the volume and reducing the cost. Therefore, the flyback converter topology is widely used.
  • Synchronous rectification is a new technology that replaces rectifier diodes with very low on-resistance MOSFETs. It is mainly used in low voltage and high current applications. In order to improve efficiency and reduce losses, the use of synchronous rectification technology has become a necessary means.
  • the synchronous rectifier has low on-resistance and small forward voltage drop, so the rectification loss is low, which meets the current design requirements.
  • the synchronous rectification structure is shown in Figure 2.
  • the gates of the primary side switching tube SW and the secondary side rectifier tube SR are driven by two voltages of opposite timings, that is, when the switching tube SW is turned on, the rectifier tube SR is turned off, and when the switching tube SW is turned off, the rectifier tube SR is turned on.
  • the input voltage V in causes the current on the inductor L to rise linearly, and the inductor stores energy.
  • the rectifier SR is turned on and the switch SW is turned off, the energy stored in the primary inductor is coupled to the secondary side through the transformer to supply power to the load and the output capacitor.
  • the secondary side switch tube can be opened; after the secondary side switch tube is turned off, the primary side switch can be opened.
  • the operating state of the flyback converter can be divided into continuous mode (CCM) and discontinuous mode (DCM).
  • CCM continuous mode
  • DCM discontinuous mode
  • the conduction loss of the parasitic diode is present in both the CCM mode and the DCM mode before the primary switching transistor is turned off and the secondary rectifier is turned on.
  • the CCM mode Before the secondary rectifier is closed and the primary switching transistor is turned on, the CCM mode has a large loss due to the reverse recovery of the parasitic diode and the diode.
  • the DCM mode the secondary current I s has dropped to zero before the secondary rectifier is turned off, so there is no parasitic diode loss and diode reverse recovery loss at this time. Therefore, under the same conditions, the CCM mode is less efficient than the DCM mode.
  • the DCM mode peak current is 2-3 times that of the CCM mode.
  • the DCM mode will generate large output voltage spikes at the moment the output synchronous rectifier is turned off, requiring a larger LC filter, and this can cause serious RFI problems.
  • the DCM enters the CCM mode there is a possibility of oscillation, which makes the circuit unstable. Therefore, in certain situations (such as smaller peak currents), the CCM mode works better.
  • the main problem of the synchronous rectified flyback switching power supply operating in CCM mode is that there is a serious parasitic diode conduction loss and diode reverse recovery loss in the dead time when the secondary rectifier is closed and the primary switching transistor is turned on.
  • the present application gives a corresponding optimization scheme.
  • a dead time automatic optimization system in a primary side feedback flyback power supply CCM mode is provided.
  • a dead time automatic optimization system for the primary side feedback flyback power supply CCM mode comprising a single output DAC midpoint sampling module, a digital control module, a current detecting module, a dead time calculation module and a PWM driving module control system and
  • the controlled synchronous rectification primary feedback flyback converter main topology forms a closed loop;
  • the single output DAC midpoint sampling module samples the voltage on the auxiliary winding at the midpoint of the secondary current reset time T r , ie, T r /2
  • the signal V sense (t mid ) is output to the digital control module, and the digital control module calculates the error e(n) of the voltage signal V sense (t mid ) from the system preset fixed value V REF and calculates the PWM drive module by using the proportional and integral
  • the input voltage control amount V c (n) is output to the PWM driving module, and at the same time, the digital control module gives the digital value V peak_d of the peak voltage on the primary current sampling resistor R cs according to the
  • the application also provides a control system and method in the CCM mode of the primary feedback flyback power supply.
  • a primary side feedback flyback power supply control system in a CCM mode includes a primary side of the transformer, a secondary side of the transformer, and an auxiliary winding, the primary side comprising a primary winding and a primary side switch And a primary current sampling resistor connected in series with the primary switching tube, the secondary side comprising a secondary winding and a secondary rectifier, the system comprising: a single output DAC midpoint sampling module, the secondary current reset the middle time period of T r T r voltage V sense signals on / 2 samples of the auxiliary winding (t mid); error digital control module, calculates a voltage signal V sense (t mid) with a preset fixed value of V REF e(n), calculating an input voltage control amount V c (n) of the PWM driving module by using the ratio and the integral according to the error e(n), and obtaining the primary current sampling resistor according to the error e(n) a digital value of the peak voltage V peak_d ; a current detecting module
  • a primary side feedback flyback power supply CCM mode control method the primary side feedback flyback power supply includes a transformer primary side, a transformer secondary side, and an auxiliary winding, and the primary side includes a primary winding and a primary side switch a tube and a primary current sampling resistor connected in series with the primary switching tube, the secondary side comprising a secondary winding and a secondary rectifier, the method comprising: at a midpoint T of the secondary current reset time T r r /2 samples the voltage signal V sense (t mid ) on the auxiliary winding; calculates an error e(n) of the voltage signal V sense (t mid ) from a predetermined fixed value V REF , according to the error e(n Calculating the input voltage control amount V c (n) of the PWM driving module by using the ratio and the integral, and obtaining the digital value V peak_d of the peak voltage on the primary current sampling resistor according to the error e(n); The digital value V peak_d and the voltage V cs across the primary side current sampling resist
  • FIG. 1 is a circuit diagram of a conventional primary feedback flyback switching converter using a diode rectification method
  • FIG. 2 is a circuit diagram of a primary feedback flyback switching converter using a low on-resistance MOSFET switching transistor rectification method
  • Figure 3 shows the main signal waveform of the synchronous rectification primary feedback flyback converter in CCM mode
  • Figure 4 is a plot of current versus time for a parasitic diode reverse recovery process
  • FIG. 5 is a circuit diagram of the shutdown delay phase
  • Figure 6 is a working circuit diagram of the Miller effect phase
  • Figure 7 shows the main signal waveforms during the turn-off of the secondary rectifier
  • FIG. 8 is a circuit diagram of an overall implementation of an automatic optimization system for dead time in a CCM mode of a primary feedback flyback switching converter using a synchronous rectification method
  • FIG. 9 is an internal structural diagram of the current detecting module of FIG. 8;
  • Figure 10 is an internal structural diagram of the dead time calculation module of Figure 8.
  • FIG 11 is a block diagram of the internal structure of the PWM driving module of Figure 8.
  • FIG. 12 is an internal structural diagram of a single-output DAC midpoint sampling module of FIG. 8;
  • Figure 13 is a diagram showing the internal structure of the digital control module of Figure 8.
  • FIG. 1 is a circuit diagram of a conventional primary-side feedback flyback converter using diode rectification.
  • diode rectification is adopted, as shown in FIG.
  • the loss of rectifier diodes has become a bottleneck for improving system efficiency. For this reason, a more efficient synchronous rectification structure has been proposed.
  • Synchronous rectification is a new technology that replaces rectifier diodes with very low on-resistance MOSFETs. It is mainly used in low voltage and high current applications. In order to improve efficiency and reduce losses, the use of synchronous rectification technology has become a necessary means.
  • the synchronous rectifier has low on-resistance and small forward voltage drop, so the rectification loss is low, which meets the current design requirements.
  • FIG. 2 is a circuit diagram of a primary feedback flyback switching converter using a low on-resistance MOSFET switching transistor rectification method.
  • the gates of the primary side switching tube SW and the secondary side rectifier tube SR are driven by two voltages of opposite timings, that is, when the switching tube SW is turned on, the rectifier tube SR is turned off, and when the switching tube SW is turned off, the rectifier tube SR is turned on.
  • the switch SW is turned on and the rectifier SR is turned off, the input voltage V in causes the current on the inductor L to rise linearly, and the inductor stores energy.
  • the rectifier SR is turned on and the switch SW is turned off, the energy stored in the primary inductor is coupled to the secondary side through the transformer to supply power to the load and the output capacitor.
  • the secondary side switch tube can be opened; after the secondary side switch tube is turned off, the primary side switch can be opened.
  • Figure 3 is the main signal waveform of the synchronous rectification primary feedback flyback converter in CCM mode.
  • Figure 3 shows the main signal waveform of the synchronous rectification flyback converter in CCM mode.
  • the following is divided into several different stages.
  • the primary side switch SW is opened, the primary current I p flows through the primary inductance L m and the primary switching transistor SW, and the primary current I p increases linearly.
  • the primary switching transistor SW Conduction voltage at both ends Zero.
  • the secondary side switching transistor SR has not been turned on.
  • the primary side current I p drops to zero, and the primary side energy is transmitted to the secondary side through the transformer.
  • the secondary side switching tube SR is still in the off state.
  • the parasitic diode D R is turned on, and the secondary current I S is rapidly increased. Since the on-resistance of the parasitic diode D R is much larger than the MOSFET on-resistance of the secondary side switch SR, the secondary current I S flowing through the parasitic diode D R causes a large diode conduction loss, resulting in flyback converter efficiency. Reduced, so the time of the dead zone t 1 -t 3 should be as small as possible.
  • the secondary side switching transistor SR is turned on, the secondary side current I S flows through the MOSFET, instead of flowing through the parasitic diode D R , and the MOSFET on-resistance of the secondary side switching transistor SR is extremely low, so The through loss is greatly reduced.
  • the secondary side switching transistor SR is turned off, and during t 4 -t 5 , the MOSFET of the secondary side switching transistor SR is not turned on, current flows from the parasitic diode D R of the MOSFET, and the primary side switching transistor SW is turned on at time t 5
  • the time of the dead zone t 4 -t 5 should also be as small as possible.
  • Figure 4 is a plot of current versus time for a parasitic diode reverse recovery process.
  • the current flowing through the parasitic diode D R is I F
  • the current flowing through the parasitic diode D R is I F
  • the current is I F becomes positive reverse I R
  • t s remains unchanged at the time of storage
  • the transit time t t was gradually decreased to the 0.1I R, at this time the size of the reverse current is negligible, That is, after the storage time t s and the transit time t t , the parasitic diode D R enters the reverse cut-off state.
  • FIG. 5 shows the working circuit diagram of the shutdown delay phase. The part inside the dotted line frame is not considered at this stage.
  • the gate square wave drive signal of the secondary side switch SR is lowered from the high level to 0, the SR tube begins to enter the shutdown process, the gate current i g is discharged to C gs , C dg is charged, and U gs begins. decline.
  • I s is divided into i ch flowing through the channel and flowing through C ds in the SR tube.
  • i ds and i dg are much smaller than I s at this stage, so i ch ⁇ I s , U ds ⁇ I s R ds , where R ds is the drain-source on-resistance of the SR tube.
  • U gs I s R ds +U T , where U T is the threshold voltage of the MOSFET, the SR tube will be transferred from the unsaturated region (linear resistance region) into the saturation region, and the Miller effect occurs, and the process ends. .
  • This phase is the turn-off delay phase during MOSFET turn-off.
  • FIG. 6 shows the working circuit diagram of the Miller effect stage.
  • the part inside the dotted line frame is not considered at this stage.
  • the U gs is basically unchanged from the original trajectory in this stage, and its value is called the Miller platform voltage and is represented by U P , which is known from the previous stage analysis U P ⁇ I s R Ds + U T .
  • C gs no longer discharges, i g flows through C dg and U dg rises.
  • U ds U P +U dg
  • U X is an important parameter for analyzing the MOSFET switching process. Although most MOSFET manuals fail to give U X , they can be measured by simple test experiments. This phase is the Miller effect phase of the MOSFET turn-off process, and the sum of its duration and the duration of the turn-off delay phase is the turn-off time of the MOSFET.
  • Figure 7 shows the main signal waveforms during the turn-off of the secondary rectifier.
  • the secondary side of the switching gate electrode tube SR square wave drive signal to decrease from the high level 0, SR tube entered shutdown process, the gate current i g to discharge the gate-source capacitance C GS, the gate-drain capacitance C
  • U gs begins to drop.
  • the SR tube remains conductive at this time.
  • I s is divided into i ch flowing through the channel and flowing through C ds in the SR tube.
  • i ds and i dg are much smaller than I s at this stage, so i ch ⁇ I s , U ds ⁇ I s R ds , where R ds is the drain-source on-resistance of the SR tube.
  • U gs I s R ds +U T , where U T is the threshold voltage of the MOSFET, the SR tube will be transferred from the unsaturated region (linear resistance region) into the saturation region, and the Miller effect occurs, and the process ends. .
  • This phase is the turn-off delay phase during MOSFET turn-off.
  • the module can obtain a reasonable dead time t d , and finally control the PWM driving module through the primary feedback loop and the obtained dead time t d to generate the primary switching transistor driving signal duty and the secondary rectifier driving signal duty_SR. This makes it possible to rationally optimize the dead time between the secondary side rectifier closing and the primary switching tube opening in the CCM mode.
  • FIG. 8 is a block diagram of an automatic optimization scheme for dead time in a CCM mode of a primary feedback flyback switching converter using a synchronous rectification method.
  • the present application is based on a main topology of a flyback converter adopting a synchronous rectification method, which includes a primary side switching tube, a secondary side rectifier tube and a transformer, and the CCM mode dead time optimization system includes Current detection module, dead time calculation module, PWM drive module, single output DAC midpoint sampling module and digital control module.
  • the present application provides an all-digital control method for automatically optimizing the dead time according to different working conditions.
  • the single-output DAC midpoint sampling module of the control system compares the magnitude relationship of ⁇ t r_half and T r /2 according to each switching cycle through the internal feedback amount calculation module.
  • the digital value of the single-slope digital wave starting voltage V initial is accurately and carefully generated for the triangular wave generator to generate a digital single-slope wave, and then superimposed with the analog reference voltage generated by the DAC to form a single-slope digital wave V ref_slope .
  • the comparator compares the sampled ramp voltage with the Vsens voltage obtained by the auxiliary winding to accurately sample the voltage signal V sense on the auxiliary winding.
  • the feedback amount calculation module accurately adjusts the digital value of the single-ramp digital wave starting voltage V initial to ensure the single-ramp digital wave voltage signal V ref_slope
  • V initial the voltage signal V sense on the auxiliary winding
  • V sense the sampled midpoint sampling voltage signal V sense (t mid )
  • the average current I s (t mid ) is input to the output secondary secondary current I s (t mid ) to the dead time calculation module, and the current reasonable dead time t d is obtained by the operation of the dead time calculation module.
  • the digital control module calculates the control amount V c (n) by using the proportional and integral based on the error e(n) of the midpoint voltage signal V sense (t mid ) sampled by the single output DAC and the system preset value V REF .
  • the feedback adjustment eliminates the steady-state error and stabilizes the output voltage V o .
  • the operation of the PWM drive module is adjusted by the dead time t d and the digital control module output control amount V c (n).
  • the PWM driver module can be the same as the PWM driver module used in the prior art, and internally includes an RS flip-flop, a comparator, a digital-to-analog converter DAC, and a driver circuit.
  • this application uses the output t d of the dead time calculation module to control the secondary side synchronous rectifier duty cycle control signal duty_SR generated by the PWM drive module, so that it is at the falling edge, low level
  • the width follows the change in dead time t d .
  • the PWM drive module controls the switching of the primary side switch and the secondary side synchronous rectifier tube through the duty signal and the duty_SR signal to realize the conversion from the digital signal to the time signal, thereby forming a closed loop system of the digitally controlled switching power supply.
  • This application uses the DAC sampling mechanism to sample the primary current to calculate the secondary average current, and obtain the primary average current I mid_p and the secondary average current I s (t mid ) in the CCM case, and then the secondary When the side current is input to the dead time calculation module, a reasonable dead time t d can be obtained.
  • the PWM drive module is controlled by the primary feedback loop and the obtained dead time t d to generate the primary switch drive signal duty and The secondary side rectifier drive signal duty_SR enables a reasonable optimization of the dead time between the secondary rectifier turn-off and the primary switch open in CCM mode.
  • Figure 9 is the internal structure diagram of the current detection module.
  • the DAC sampling mechanism is used to sample the primary current to calculate the secondary average current, and the CCM is obtained.
  • the primary average current I mid_p and the secondary average current I s (t mid ), and the secondary average current I s (t mid ) is input as an output signal to the dead time calculation module to calculate a reasonable dead time t d .
  • the current detection module includes a single-input dual-output DAC and two comparators CMP3 and CMP4, and a primary current time counting module and a secondary current average current calculation module.
  • the DAC input is the output signal of the peak current by the primary control module corresponds to the voltage on the primary digital current sampling resistor V peak_d given value, output a corresponding analog value V peak_d V peak and V peak_half, wherein the value V peak_half Is k ⁇ I peak_p (0 ⁇ k ⁇ 1).
  • the module; the primary current time counting module is composed of two counters, and the input signals are the output signals V cmp3 and V cmp4 of the two comparators respectively, and the primary side of the CCM case is obtained according to the change of the high and low levels of V cmp3 and V cmp4 .
  • the current is linearly increased from zero amperes or initial current to the peak current, thereby calculating the required times t a and t b , respectively, and inputting them as output signals to the secondary average current calculation module.
  • FIG 10 is an internal structure diagram of the dead time calculation module. It can be seen from the above analysis that the dead time is composed of the turn-off delay phase and the Miller effect phase of the MOSFET. To calculate the dead time, it is necessary to derive the turn-off delay. The relationship between the time phase and the Miller effect phase should be respectively deduced below.
  • C rss (t) and U dg (t) are conventional parameters in the MOSFET manual, and U dg (t) is typically taken as 25V.
  • the optimum dead time t d between the secondary rectifier tube SR being turned off and the primary switching transistor SW being turned on is:
  • the dead time t d is realized by the adders A 2 , A 3 .
  • FIG 11 is a PWM drive module. It contains a traditional PWM driver module.
  • This PWM driver module can be used in the same way as the PWM driver unit used in the prior art. It includes an RS flip-flop, a comparator, a digital-to-analog converter DAC and a driver circuit.
  • the PWM driving module generates a primary side switching tube duty ratio control signal duty and a secondary side synchronous rectifier duty ratio control signal duty_SR, resets the RS trigger, generates a PWM waveform with a different duty ratio, and controls the primary side switching tube and the secondary side
  • the switch of the synchronous rectifier realizes the conversion from the digital signal to the time signal, thereby forming a closed loop system of the digitally controlled switching power supply.
  • the primary side switching tube control signal duty generated by the internal traditional PWM driving unit will directly control the primary side switching tube as an output signal, and the generated secondary side rectifier control signal duty_SR1 needs to go through a simple logic circuit to optimize the dead. District time.
  • the output t d of the dead time calculation module is passed through a zero-crossing comparator to generate a forward pulse, and the forward pulse is passed through an inverter to obtain a negative pulse.
  • the D flip-flop is on the falling edge of the signal duty_SR. Under the trigger, the negative pulse and the duty_SR are logically operated, so that the dead time at this time follows the width change of the negative pulse, thereby realizing the optimization of the dead time.
  • FIG 12 is an internal block diagram of a single output DAC midpoint sampling module.
  • Single-output module comprises a digital to analog converter DAC DAC sampling midpoint, a triangular wave generator, a comparator CMP1, the CMP2 comparator, a counter, and the feedback amount calculation module; function which is the midpoint of the secondary current reset time t mid, auxiliary sampled
  • the voltage signal V sense (t mid ) on the winding The signal flow direction is: the voltage signal V sense on the auxiliary winding flows as an input signal, is input to the positive ends of the two comparators, and is respectively compared with the voltage signal V ref_slope and the zero voltage of the single-ramp digital wave, and respectively obtains a feedback comparison signal.
  • V ref_comp and zero comparison signal V zvs_comp The counter counts the magnitudes of ⁇ t r_half and Tr according to the high-low level change of the feedback comparison signal V ref — comp and the zero-cross comparison signal V zvs — comp , and ⁇ t r — half is a single-ramp digital wave V ref — slope rising from the initial voltage V initial position to the auxiliary
  • T r is the reset time required for the secondary current to decrease from the peak to the lowest point.
  • the feedback amount calculation module Depending on the size relationship between ⁇ t r_half and T r, the next adjustment period of a single wave digital ramp digital value V initial starting voltage when the voltage signal V sense single digital ramp wave on the auxiliary winding
  • the value of the voltage signal V ref_slope of the single-slope digital wave is assigned to the midpoint voltage signal V sense (t mid ) as the output signal of the single-output DAC midpoint sampling module in the current switching cycle.
  • the midpoint voltage signal V sense (t mid ) is output every cycle, although the output signal of the single sampling DAC midpoint sampling module is dynamic when the load changes and the voltage signal V sense on the auxiliary winding changes.
  • midpoint voltage signal V sense (t mid) is not the voltage signal V sense (t mid) in the auxiliary winding in the strict sense T r / 2 time, only the approximate amount of a gradually approaching, but constant through each cycle Comparing the magnitude relationship between ⁇ t r_half and T r /2, with the gradual approximation, the midpoint voltage signal V sense (t mid ) output from the single-output DAC midpoint sampling module is numerically strict after multiple switching cycles. Equal to the exact amount of voltage signal V sense (t mid ) on the auxiliary winding at time T r /2).
  • the single-output DAC midpoint sampling module adjusts at a fast rate, the dynamic adjustment period is very small compared to the steady-state period, so each switching cycle, the voltage signal V sense on the auxiliary winding and the single-ramp digital wave When the voltage signals V ref_slope are equal, the assigned single output DAC midpoint sampling module output signal is referred to as the midpoint voltage signal V sense (t mid ).
  • FIG. 13 is a diagram showing the internal structure of a digital control module.
  • the digital control module can be the same as the prior art digital control module, in one embodiment a digital PI control module, the core of which is PI control, ie proportional integral control.
  • the digital control module includes an adder, a subtractor, a multiplier, a register, an operational amplifier K p and K i , and a mode judging module, and the specific connection relationship is: a midpoint sampling voltage signal V sense (t mid ) of the DAC and a system preset
  • the fixed value V REF is subtracted by the subtractor to obtain the error e(n), which on the one hand inputs the register and on the other hand controls the mode determination module.
  • the mode judging module outputs two signals Vpeak_d and a state state.
  • the state signal state is divided into two through the operational amplifier and then summed by the adder.
  • the output e(n-1) of the register is multiplied by a signal of the state state and the result is given to the subsequent subtractor.
  • the summed state signal is multiplied by the error e(n), and then passed through the subtractor and the adder, and finally the control signal V c (n) is obtained, where the control signal V c (n) is fed back to the previous stage through the register. Adder.
  • the midpoint sampling voltage signal V sense (t mid ) whose input signal is a single output DAC is the digital value V peak — d of the peak voltage on the primary current sampling resistor R cs , and the control signal V c (n).
  • the output of the proportional control is proportional to the input error signal
  • the output of the integral control is proportional to the integral of the input error signal.
  • V c (n) V c (n-1)+K p ⁇ (e(n)-e(n-1))+K i ⁇ e(n) (11)
  • V c (n) represents the current period control amount
  • V c (n-1) represents the previous period control amount
  • e(n) represents the current period error
  • e(n-1) represents the previous period error
  • K p and K i is the integral parameter and the differential parameter respectively. It is not unique within the full load range. It is necessary to set different values according to different modes.
  • the application also provides a control system in the CCM mode of the primary feedback flyback power supply.
  • the primary side feedback flyback power source includes a primary side of the transformer, a secondary side of the transformer, and an auxiliary winding, and the primary side includes a primary winding, a primary switching transistor, and a primary current sampling in series with the primary switching transistor a resistor, the secondary side comprising a secondary winding and a secondary rectifier, the system comprising: a single output DAC midpoint sampling module, sampling the secondary at a midpoint time T r /2 of the secondary current reset time T r a voltage signal V sense (t mid ) on the winding; a digital control module that calculates an error e(n) of the voltage signal V sense (T mid ) from a predetermined fixed value V REF , using a ratio according to the error e(n) And integrating the input voltage control amount V c (n) of the PWM driving module, and obtaining the digital value V peak_d of the peak voltage on the primary current sampling
  • the single output DAC midpoint sampling module comprises a digital to analog converter, a triangular wave generator, a comparator CMP1, a comparator CMP2, a counter and a feedback amount calculation module; a voltage signal V on the auxiliary winding Sense is input as an input signal to the positive terminal of the comparator CMP1 and the positive terminal of the CMP2, respectively, and the digital single ramp wave outputted by the triangular wave generator is superimposed with the analog reference voltage output by the digital-to-analog converter to obtain a single-slope digital
  • the voltage signal V ref_slope of the wave is input to the negative terminal of the comparator CMP1, the negative terminal of the comparator CMP2 is connected to the zero voltage, the comparator CMP1 outputs the feedback comparison signal V ref — comp , and the comparator CMP2 outputs the zero crossing.
  • V ref_initial outputs a feedback signal to the triangular wave generator input
  • the input terminal of the terminal and the digital-to-analog converter adjusts the digital value of the initial voltage V initial of the next cycle.
  • the current detecting module comprises a single input dual output digital to analog converter, a comparator CMP3, a comparator CMP4, a primary current time counting module, a secondary side average current calculating module, and the single input dual output.
  • the digital-to-analog converter and the secondary-side average current calculation module receive the digital value V peak_d output by the digital control module, and the positive terminal of the comparator CMP3 and the positive terminal of the comparator CMP4 receive the voltage V cs , the single input primary peak current of the first output terminal of the dual output voltage corresponding to the digital-analog value V peak on the primary current sampling resistor, and the output to the negative terminal of the comparator CMP3, said single input
  • the comparator CMP4 outputs a comparison signal V cmp4 to the primary current time count of the second counter module, the primary module in accordance with the current time count V cmp3 comparison signal and the comparison signal V cmp4 high and low levels change, derived from zero ampere primary current increases linearly or initial current peak current required where the DCM at time t a, CCM case of the primary current from zero ampere or The initial current linearly increases to the peak current time t b and is output to the secondary side average current calculation module, the secondary average current calculation module dividing the digital value V peak — d by the resistance of the primary current sampling resistor, Obtain the digital quantity I peak_p corresponding to the peak current of the primary winding inductance and substitute the times t a and t b into the expression of I s (t mid ):
  • N p and N s are the turns of the primary and secondary windings of the transformer, respectively, and the secondary average current I s (t mid ) in the case of CCM is obtained and output.
  • the dead time calculation module calculates the dead time t d according to the following formulas:
  • n R ds ;
  • U P is the Miller plateau voltage
  • U g is the gate voltage of the secondary rectifier
  • R g is the gate resistance of the secondary rectifier
  • Q g is the gate of the secondary rectifier during shutdown.
  • the total dissipated charge, Q gd is the amount of gate dissipated charge in the Miller effect phase during the turn-off of the secondary rectifier
  • Q gs is the secondary shunt during the turn-off process.
  • U GS is lowered by the Miller platform voltage U P
  • the gate to 0 phase dissipates the amount of charge
  • I L is the load current
  • C rss is the inverting transfer capacitance of the secondary rectifier
  • I S is the secondary current
  • U X is Experimental measurement
  • U T is the threshold voltage of the secondary rectifier
  • R ds is the source-drain resistance of the secondary rectifier.
  • the PWM driving module includes a comparator, an inverter, a D flip-flop, an OR gate, and a PWM driving unit, and a positive input terminal of the comparator inputs the dead time t d ,
  • the negative input of the comparator is connected to zero voltage
  • the output of the comparator is connected to the input of the inverter
  • the output of the inverter is connected to the D input of the D flip-flop
  • the input signal of the unit is the input voltage control amount V c (b)
  • the first output end of the PWM driving unit outputs a primary side duty ratio control signal duty and a second output end output signal duty_SR1 to the D flip-flop a clock control end
  • the Q output of the D flip-flop is connected to one input of the OR gate
  • the signal duty_SR1 is input to the other input end of the OR gate
  • the output end of the OR gate outputs the secondary side The air ratio control signal duty_SR.
  • the secondary side rectifier is a MOS tube.
  • the primary side switching transistor is a MOS transistor
  • the primary side current sampling resistor is connected in series between the source of the primary side switching transistor and the ground.
  • the present application further provides a control method in a primary side feedback flyback power supply CCM mode, wherein the primary side feedback flyback power supply includes a primary side of the transformer, a secondary side of the transformer, and an auxiliary winding, and the primary side includes a primary winding a primary side switching tube and a primary current sampling resistor connected in series with the primary side switching tube, the secondary side comprising a secondary winding and a secondary rectifier, the method comprising: resetting the time T r at the secondary current The midpoint time T r /2 samples the voltage signal V sense (t mid ) on the auxiliary winding; calculates an error e(n) of the voltage signal V sense (t mid ) from a preset fixed value V REF , according to The error e(n) calculates the input voltage control amount V c (n) of the PWM driving module by using the proportional and integral, and obtains the digital value V of the peak voltage on the primary current sampling resistor according to the error e(n) Peak_d ; according to
  • the step of sampling the voltage signal V sense (T mid ) on the auxiliary winding at the midpoint time T r /2 of the secondary current reset time T r includes:
  • the positive terminal of the comparator CMP1 is input to the voltage signal V sense on the auxiliary winding, and the digital single ramp output from the triangular wave generator is superimposed with the analog reference voltage outputted by the digital-to-analog converter to obtain a voltage signal V ref_slope of the single-ramp digital wave and input.
  • the comparator CMP1 outputs a feedback comparison signal V ref_comp at the negative end of the comparator CMP1;
  • the positive terminal of the comparator CMP1 inputs the voltage signal V sense on the auxiliary winding, the negative terminal inputs the zero voltage, and the comparator CMP2 outputs the zero-cross comparison signal V zvs_comp ;
  • V ref_initial outputs a feedback signal to the input terminal of the input terminal and a digital triangle wave generator, the start of the next cycle adjustment voltage V initial digital Value;
  • the indirect sampling is performed by digital-to-analog conversion according to the digital value Vpeak_d and the voltage V cs across the primary-side current sampling resistor, and the primary average current I mid_p and the pair in the case of CCM are obtained.
  • the steps of the average current I s (t mid ) include:
  • the positive terminal of the comparator CMP3 and the positive terminal of the comparator CMP4 receive the voltage V cs ;
  • the primary current is zero or the initial current in the case of DCM.
  • the time required peak current increases linearly t a, where the CCM primary current increases from zero amperes peak current or initial linear current time t b;
  • V peak_d the digital value divided by the primary current sampling resistor resistance, to give the primary winding peak current in the inductor digital I peak_p;
  • N p and N s are the turns of the primary and secondary windings of the transformer, respectively, and the secondary average current I s (t mid ) in the case of CCM is obtained.
  • the step of calculating the dead time t d between the turn-off of the secondary rectifier and the opening of the primary switch according to the secondary average current I s (t mid ) is based on The dead time t d is calculated by the following formulas:
  • n R ds ;
  • U P is the Miller plateau voltage
  • U g is the gate voltage of the secondary rectifier
  • R g is the gate resistance of the secondary rectifier
  • Q g is the gate of the secondary rectifier during shutdown.
  • the total dissipated charge, Q gd is the amount of gate dissipated charge in the Miller effect phase during the turn-off of the secondary rectifier
  • Q gs is the secondary shunt during the turn-off process.
  • U GS is lowered by the Miller platform voltage U P
  • the gate to 0 phase dissipates the charge
  • I L is the load current
  • C rss is the inverting transfer capacitance of the secondary rectifier
  • I s is the secondary current
  • U X is Experimental measurement
  • U T is the threshold voltage of the secondary rectifier
  • R ds is the source-drain resistance of the secondary rectifier.

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Abstract

一种原边反馈反激电源CCM模式下的死区时间自动优化系统，包括单输出DAC中点采样模块、数字控制模块、电流检测模块、死区时间计算模块和PWM驱动模块构成的控制系统与受控的同步整流原边反馈反激式变换器形成闭环，通过DAC采样机制，采样原边电流推算副边平均电流，得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)，将副边电流输入到死区时间计算模块，得到合理的死区时间t d，最后通过原边反馈回路和得到的死区时间t d共同控制PWM驱动模块，产生原边开关管驱动信号duty以及副边整流管驱动信号duty_SR，使得在CCM模式下副边整流管关闭与原边开关管开启之间的死区时间能够的合理的优化。

Description

原边反馈反激电源CCM模式下的死区时间自动优化系统、原边反馈反激电源CCM模式下的控制系统及方法 技术领域
本申请涉及采用同步整流原边反馈的反激式开关电源，特别涉及一种同步整流原边反馈反激式电源CCM模式下的死区时间自动优化系统，属于隔离式开关电源变换器技术领域，还涉及一种原边反馈反激电源CCM模式下的控制系统及方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
电源是各个电子设备不可或缺的组成部分，其性能的优劣直接关系到电子设备的技术指标以及其能否安全可靠的工作，而目前主流应用是开关电源(Switch Mode Power Supply)。开关电源又称之为开关变换器，是利用现代电力电子技术，通过调整开关器件的导通比来使输出电压恒定的一种电源。
由于反激变换器有着变压器和电感的双重功能，因此反激变换器不需要输出滤波电感，这对减小体积和降低成本尤为重要，因此反激变换器拓扑得到广泛应用。
在传统的反激式开关变换器中，采用二极管整流方式，如图1所示。对于大功率的电源系统应用上，整流二极管的损耗己成为提高系统效率的瓶颈，为此提出了效率更高的同步整流结构。
同步整流是用通态电阻极低的MOSFET来取代整流二极管的一项新技术，主要应用在低压、大电流的场合。为了提高效率和降低损耗的需要，采用同步整流技术已经成为了一种必要的手段。同步整流管导通电阻低、正向压降小，因而整流损耗低，符合目前的设计需求。
同步整流结构如图2。原边开关管SW和副边整流管SR的栅极由两个时序相反的电压驱动，即当开关管SW开启时，整流管SR关闭，当开关管SW关闭时，整流管SR开启。当开关管SW开启，整流管SR关闭时，输入电压V in使电感L上的电流线性上升，电感储存能量。当整流管SR开启，开关管SW关闭时，原边电感储存的能量通过变压器耦合到副边，给负载和输出电容供电。
为了避免反激变换器原副边开关切换过程中出现原边开关管与副边开关管同时导通造成的击穿现象，必须保证原副边管才开关管之间存在死区时间，即原边开关管关断后，副边开关管才能打开；副边开关管关断后，原边开关才能打开。
根据在下一次原边开关管开启时，副边电流I s是否下降到0，可以将反激变换器的工作状态分为连续模式(CCM)和断续模式(DCM)。在原边开关管关闭，副边整流管开启之前，CCM模式和DCM模式均存在寄生二极管的导通损耗。在副边整流管关闭，原边开关管开启之前，CCM模式由于寄生二极管和二极管的反向恢复，使得此时的损耗较大。DCM模式下，副边整流管关闭之前，副边电流I s已经下降到0，所以此时就不存在寄生二极管损耗和二极管反向恢复损耗。因此，在相同的条件下，CCM模式比DCM模式的效率更低。
在同等功率等级的情况下，DCM模式峰值电流是CCM模式的2-3倍。而且，DCM模式将在输出同步整流管关断的瞬间产生较大的输出电压尖峰，从而需要较大的LC滤波器，并且这可能造成严重的RFI问题。此外，当DCM进入CCM模式下的时候有可能会出现震荡，从而使电路不稳定。因此，在某些特定场合下(如较小的峰值电流)，CCM模式能够更好地工作。
目前同步整流反激开关电源工作在CCM模式下的主要问题在于：在副边整流管关闭与原边开关管开启的死区时间内，存在严重的寄生二极管导通损耗和二极管反向恢复损耗。针对此问题，本申请给出了相应的优化方案。
发明内容
根据本申请的各种实施例，提供一种原边反馈反激电源CCM模式下的死区时间自动优化系统。
一种原边反馈反激电源CCM模式下的死区时间自动优化系统，包括单输出DAC中点采样模块、数字控制模块、电流检测模块、死区时间计算模块和PWM驱动模块构成的控制系统与受控的同步整流原边反馈反激式变换器主拓扑形成闭环；单输出DAC中点采样模块在副边电流复位时间T r的中点时刻，即T r/2时刻采样辅助绕组上的电压信号V sense(t mid)输出给数字控制模块，数字控制模块计算电压信号V sense(t mid)与系统预设的固定值V REF的误差e(n)并利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)输出给PWM驱动模块，同时，数字控制模块根据误差e(n)大小给出原边电流采样电阻R cs上的峰值电压的数字值V peak_d，该数字值V peak_d与原边电流采样电阻R cs两端的电压V cs一起输出给电流检测模块，电流检测模块使用纯数字的方式，通过DAC间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)并将副边平均电流I s(t mid)作为输出信号输出给死区时间计算模块计算出副边整流管SR关断到原边开关管SW开启之间合理的死区时间t d，PWM驱动模块在死区时间计算模块输出的死区时间t d和数字控制模块输出的控制量V c(n)的共同控制下，产生占空比控制信号duty和duty_SR，分别控制原边开关管SW和副边同步整流管SR的开关，实现对同步整流原边反馈反激式电源CCM模式下死区时间的自动优化。
本申请还提供一种原边反馈反激电源CCM模式下的控制系统及方法。
一种原边反馈反激电源CCM模式下的控制系统，所述原边反馈反激电源包括变压器原边侧、变压器副边侧及辅助绕组，所述原边侧包括原边绕组、原边开关管及与所述原边开关管串联的原边电流采样电阻，所述副边侧包括副边绕组和副边整流管，所述系统包括：单输出DAC中点采样模块，在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)；数字控制模块，计算电压信号V sense(t mid)与预设的固定值V REF的误差e(n)，根据所述误差e(n)利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)， 并根据所述误差e(n)得到所述原边电流采样电阻上的峰值电压的数字值V peak_d；电流检测模块，根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)；死区时间计算模块，根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d；及PWM驱动模块，根据所述死区时间t d和所述输入电压控制量V c(n)，产生原边占空比控制信号duty和副边占空比控制信号duty_SR；并根据所述原边占空比控制信号duty控制原边开关管的开关，根据所述副边占空比控制信号duty_SR控制副边整流管的开关。
一种原边反馈反激电源CCM模式下的控制方法，所述原边反馈反激电源包括变压器原边侧、变压器副边侧及辅助绕组，所述原边侧包括原边绕组、原边开关管及与所述原边开关管串联的原边电流采样电阻，所述副边侧包括副边绕组和副边整流管，所述方法包括：在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)；计算电压信号V sense(t mid)与预设的固定值V REF的误差e(n)，根据所述误差e(n)利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)，并根据所述误差e(n)得到所述原边电流采样电阻上的峰值电压的数字值V peak_d；根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)；根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d；PWM驱动模块根据所述死区时间t d和所述输入电压控制量，V c(n)产生原边占空比控制信号duty和副边占空比控制信号duty_SR；及根据所述原边占空比控制信号duty控制原边开关管的开关，根据所述副边占空比控制信号duty_SR控制副边整流管的开关。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为传统的采用二极管整流方式的原边反馈反激式开关变换器电路图；
图2为采用低导通电阻的MOSFET开关管整流方式的原边反馈反激式开关变换器电路图；
图3同步整流原边反馈反激变换器在CCM模式下的主要信号波形；
图4为寄生二极管反向恢复过程电流随时间变化曲线；
图5为关断延时阶段工作电路图；
图6为密勒效应阶段工作电路图；
图7副边整流管关断期间主要信号波形图；
图8为本申请采用同步整流方式的原边反馈反激式开关变换器CCM模式下死区时间自动优化系统整体实现电路图；
图9为图8中电流检测模块的内部结构图；
图10为图8中死区时间计算模块内部结构图；
图11是图8中PWM驱动模块内部结构图；
图12是图8中的单输出DAC中点采样模块内部结构图；
图13为图8中数字控制模块的内部结构图。
具体实施方式
为了更清楚地说明本申请，下面将结合附图及实施例，对本申请的技术方案进行清楚、完整的描述。
图1为传统的采用二极管整流方式的原边反馈反激式开关变换器电路图。在传统的反激式开关变换器中，采用二极管整流方式，如图1所示。对于大功率的电源系统应用上，整流二极管的损耗己成为提高系统效率的瓶颈，为此提出了效率更高的同步整流结构。
同步整流是用通态电阻极低的MOSFET来取代整流二极管的一项新技术，主要应用在低压、大电流的场合。为了提高效率和降低损耗的需要，采用同步整流技术已经成为了一种必要的手段。同步整流管导通电阻低、正向压降小，因而整流损耗低，符合目前的设计需求。
图2是采用低导通电阻的MOSFET开关管整流方式的原边反馈反激式开关变换器电路图。原边开关管SW和副边整流管SR的栅极由两个时序相反的电压驱动，即当开关管SW开启时，整流管SR关闭，当开关管SW关闭时，整流管SR开启。当开关管SW开启，整流管SR关闭时，输入电压V in使电感L上的电流线性上升，电感储存能量。当整流管SR开启，开关管SW关闭时，原边电感储存的能量通过变压器耦合到副边，给负载和输出电容供电。
为了避免反激变换器原副边开关切换过程中出现原边开关管与副边开关管同时导通造成的击穿现象，必须保证原副边管才开关管之间存在死区时间，即原边开关管关断后，副边开关管才能打开；副边开关管关断后，原边开关才能打开。
图3是同步整流原边反馈反激变换器在CCM模式下的主要信号波形。图3给出了同步整流反激变换器在CCM模式下的主要信号波形，为了便于分析，下面将一个工作周期划分为若干个不同的阶段。
t 0时刻，原边开关管SW打开，原边电流I p流过原边电感L m和原边开关管SW，原边电流I p线性增加，t 0-t 1期间，原边开关管SW导通，两端的电压
Figure PCTCN2018125640-appb-000001
为零。
t 1时刻，原边开关管SW关闭，开关管两端的等效寄生电容C eqp被励磁电流I p充电，直到t 2时刻原边开关管SW两端的电压
Figure PCTCN2018125640-appb-000002
大小达到V in+NV o。
t 1-t 3期间，副边开关管SR尚未开启，t 2时刻，原边电流I p下降到零，原边能量通过变 压器传递到副边，此时副边开关管SR依然处于关断状态，寄生二极管D R导通，副边电流I S迅速增大。由于寄生二极管D R的导通电阻远大于副边开关管SR的MOSFET导通电阻，流过寄生二极管D R的副边电流I S会造成较大的二极管导通损耗，导致反激变换器效率降低，因此死区t 1-t 3的时间应当尽可能小。
t 3-t 4期间，副边开关管SR导通，副边电流I S从MOSFET流过，而不是从寄生二极管D R流过，副边开关管SR的MOSFET导通电阻极低，因此导通损耗大大降低。
t 4时刻，副边开关管SR关断，t 4-t 5期间，副边开关管SR的MOSFET不导通，电流从MOSFET的寄生二极管D R流过，当t 5时刻原边开关管SW开启时，寄生二极管D R两端压降由正向突然变为反向，在这个过程中会产生反向恢复电流，引起寄生二极管D R的反向恢复损耗。因此，为了减小CCM模式下寄生二极管D R的反向恢复损耗，死区t 4-t 5的时间也应当尽可能小。
图4为寄生二极管反向恢复过程电流随时间变化曲线。如图4所示，当正向导通t f期间，流过寄生二极管D R的电流大小为I F，当寄生二极管D R两端压降由正向V F变为反向V R，电流由正向的I F变为反向的I R，在存储时间t s内保持不变，然后在渡越时间t t内才逐渐下降至0.1I R，此时反向电流的大小可以忽略不计，即经过存储时间t s和渡越时间t t后，寄生二极管D R才会进入反向截止状态。这是由于寄生二极管D R的PN结的电荷存储效应引起的：正向导通期间，寄生二极管D R的PN结内积累了一定数量的非平衡少子，当两端压降由正向变为反向时，存储的非平衡少数载流子不会立刻消失，而是形成反向漂移电流以及和多数载流子复合逐渐消耗掉，这个时间就是寄生二极管D R的反向恢复时间，在这个过程中会产生反向恢复电流，引起寄生二极管D R的反向恢复损耗。
图5为关断延时阶段工作电路图，虚线框内的部分在本阶段不考虑。在t 4时刻，副边开关管SR的门极方波驱动信号由高电平降低至0，SR管开始进入关断过程，栅极电流i g给C gs放电、C dg充电，U gs开始下降。此期间内，U gs的衰减时间常数τ＝R g(C dg+C gs)，SR 管此时保持导通，I s在SR管内分为流过沟道的i ch、流过C ds的i ds和流过C dg的i dg。i ds、i dg在本阶段远小于I s，故可认为i ch≈I s、U ds≈I sR ds，其中R ds为SR管的漏源导通电阻。在t 5时刻，U gs＝I sR ds+U T，其中U T为MOSFET的阈值电压，SR管将由非饱和区(线性电阻区)转入饱和区工作，密勒效应出现，此过程结束。本阶段是MOSFET关断过程中的关断延时阶段。
图6为密勒效应阶段工作电路图，虚线框内的部分在本阶段不考虑。鉴于密勒效应的存在，在本阶段内U gs脱离原有的轨迹而基本不变，其值称作密勒平台电压并由U P表示，由前一阶段分析易知U P≈I sR ds+U T。此外，C gs不再放电，i g全部流过C dg并使U dg上升。鉴于i g较小且U ds＝U P+U dg，U ds缓慢上升并在t 6时刻升至U X，此时SR管的N -外延层由耗尽转变为累积，沟道关断且i ch＝0，故I s仅流过C ds、C dg。U X是分析MOSFET开关过程的重要参数，虽然大部分MOSFET手册未能给出U X，但其可经简单的测试实验测取。本阶段是MOSFET关断过程中的密勒效应阶段，且其持续时间与关断延时阶段持续时间的和值即为MOSFET的关断时间。
图7副边整流管关断期间主要信号波形图。在t 4时刻，副边开关管SR的门极方波驱动信号由高电平降低至0，SR管开始进入关断过程，栅极电流i g给栅源电容C gs放电、栅漏电容C dg充电，U gs开始下降。此期间内，U gs的衰减时间常数τ＝R g(C dg+C gs)，SR管此时保持导通，I s在SR管内分为流过沟道的i ch、流过C ds的i ds和流过C dg的i dg。i ds、i dg在本阶段远小于I s，故可认为i ch≈I s、U ds≈I sR ds，其中R ds为SR管的漏源导通电阻。在t 5时刻，U gs＝I sR ds+U T，其中U T为MOSFET的阈值电压，SR管将由非饱和区(线性电阻区)转入饱和区工作，密勒效应出现，此过程结束。本阶段是MOSFET关断过程中的关断延时阶段。
针对现有的同步整流原边反馈反激变换器在CCM模式下存在寄生二极管正向导通损耗以及反相恢复损耗，本申请提出了CCM模式下死区时间自动优化系统，能够合理优化死区时间，从而尽量减小寄生二极管正向导通损耗和反向恢复损耗。本申请通过DAC采样机制，采样原边电流推算副边平均电流，得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)，然后将副边电流输入到死区时间计算模块，即可得合理的死区时间t d，最后通过原边反馈回路和得到的死区时间t d共同控制PWM驱动模块，产生原边开关管驱动信号duty以及副边整流管驱动信号duty_SR，使得在CCM模式下副边整流管关闭与原边开关管 开启之间的死区时间能够的合理的优化。
图8是本申请采用同步整流方式的原边反馈反激式开关变换器CCM模式下死区时间自动优化方案框图。与传统二极管整流方式相比，本申请基于采用同步整流方式的反激式变换器主拓扑结构，该拓扑结构包括原边开关管、副边整流管和变压器，CCM模式下死区时间优化系统包括电流检测模块、死区时间计算模块、PWM驱动模块、单输出DAC中点采样模块和数字控制模块。本申请提供了一种全数字控制方式、根据不同的工作条件下自动优化死区时间的方案。如图所示，在原边反馈主拓扑结构下，本控制系统的单输出DAC中点采样模块通过内部的反馈量计算模块，根据每个开关周期不断的比较Δt r_half和T r/2的大小关系，精确周密地产生单斜坡数字波起始电压V initial的数字值，用于三角波发生器产生数字单斜波，再和DAC产生的模拟参考电压相叠加，形成用于单斜坡数字波V ref_slope。最后利用比较器将采样的斜坡电压与辅助绕组采得的V sense电压进行比较，可以准确在辅助绕组上采样电压信号V sense。通过每个开关周期不断的比较Δt r_half和T r/2的大小关系，反馈量计算模块精确周密地调整单斜坡数字波起始电压V initial的数字值，可以保证单斜坡数字波电压信号V ref_slope的起始位置，在不同负载条件下，始终能够跟随辅助绕组上的电压信号V sense的变化而变化，准确输出采样得到的中点采样电压信号V sense(t mid)，从而在稳态和动态条件下获得较好的中点跟随效果。此外，通过电流检测模块，在不采用传统大面积的模数转换器情况下，完全使用纯数字的方式，通过DAC采样机制，间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)的大小，将输出的副边平均电流I s(t mid)输入到死区时间计算模块，通过死区时间计算模块的运算得到当前的合理死区时间t d。数字控制模块根据单输出DAC采样得到的中点电压信号V sense(t mid)与系统预设值V REF的误差e(n)，利用比例和积分计算出控制量V c(n)，经过负反馈调节消除稳态误差，使输出电压V o趋于稳定。通过死区时间t d和数字控制模块输出控制量V c(n)来调整PWM驱动模块的工作。PWM驱动模块可以与现有技术所采用的PWM驱动模块相同，内部包括RS触发器，比较器，数模转换器DAC和驱动电路。此处略有不同的是：本申请利用死区时间计算模块的输出t d来控制PWM驱动模块产生的副边同步整流管占空比控制信号duty_SR，使其在下降沿的时候，低电平的宽度跟随死区时间t d的变化。在整体上，PWM驱动模块通过duty信号和duty_SR信号控制原边开关管和副边同步整流管的开关，实现从数字信号到时间信号的转换，从而形成了数字控制开关电源的闭环系统。
本申请的优点及显著效果：本申请通过DAC采样机制，采样原边电流推算副边平均电流，得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)，然后将副边电流输入到 死区时间计算模块，即可得合理的死区时间t d，最后通过原边反馈回路和得到的死区时间t d共同控制PWM驱动模块，产生原边开关管驱动信号duty以及副边整流管驱动信号duty_SR，使得在CCM模式下副边整流管关闭与原边开关管开启之间的死区时间能够的合理的优化。
图9是电流检测模块内部结构图，在不采用传统大面积的模数转换器情况下，完全使用纯数字的方式，通过DAC采样机制，采样原边电流推算副边平均电流，得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)，并将副边平均电流I s(t mid)作为输出信号输入到死区时间计算模块，计算合理的死区时间t d。电流检测模块包括一个单输入双输出的DAC和两个比较器CMP3和CMP4以及原边电流时间计数模块和副边平均电流计算模块。DAC的输入是由控制模块的输出信号原边峰值电流对应于原边电流采样电阻上的电压数字值V peak_d给出，输出为V peak_d对应的模拟值V peak和V peak_half，其中V peak_half取值为k·I peak_p(0<k<1)。比较器CMP3的正端接原边电流采样电阻R cs两端的电压V cs，负端接原边峰值电流对应于原边电流采样电阻上的电压模拟值V peak，输出信号V cmp3作为输入信号输入至原边电流时间计数模块，比较器CMP4的正端接原边电流采样电阻R cs两端的电压V cs，负端接原边峰值电流的k倍(0<k<1)对应于原边电流采样电阻上的电压模拟值V peak_half，为便于计算，此处k取值为0.5，则V peak_half＝k·V peak＝0.5·V peak，输出信号V cmp4作为输入信号输入至原边电流时间计数模块；原边电流时间计数模块由两个计数器构成，输入信号分别为两个比较器的输出信号V cmp3与V cmp4，根据V cmp3和V cmp4高低电平的变化，得出CCM情况下原边电流从零安培或初始电流线性增加到峰值电流的时间，从而分别计算出所需要的时间t a和t b，并作为输出信号输入到副边平均电流计算模块。副边平均电流计算模块的输入信号为t a和t b，以及原边峰值电流对应于原边电流采样电阻上的电压数字值V peak_d，利用V peak_d除以原边电流采样电阻R cs的阻值，可以推出原边绕组电感峰值电流I peak_p对应的数字量，并代入I s(t mid)的表达式即可得CCM情况下的副边平均电流I s(t mid)，从而得到合理的死区时间t d,实现下一工作周期死区时间的合理优化。
图10是死区时间计算模块的内部结构图，由上述的分析可知死区时间由MOSFET的关断延时阶段和密勒效应阶段组成，要计算死区时间的大小，需要推导上述关断延时阶段和 密勒效应阶段的时间分别应满足的关系式，下面分别进行推导。
关断延时阶段：本阶段的电路如图5所示。由前面的分析表明，此阶段内I s主要经SR管沟道流通，故有U ds≈I sR ds，U dg≈I sR ds-U gs；同时C gs、C dg经电阻R g放电，U gs由U g降至U P。由此分析SR管的门极可得：
Figure PCTCN2018125640-appb-000003
将C iss＝C gs+C dg代入上式，可解得关断延时阶段的持续时间ΔT 1如下：
Figure PCTCN2018125640-appb-000004
因U gs≥U P，故
Figure PCTCN2018125640-appb-000005
所以上式可以写成：
Figure PCTCN2018125640-appb-000006
密勒效应阶段：本阶段的电路如图6所示。由前面的分析可知，此时U gs、i g基本不变，U gs(t)≈U P，
Figure PCTCN2018125640-appb-000007
且i g仅流过C dg并使U dg由I sR ds-U P上升至U X-U P。此过程SR管栅极耗散的电荷Q P可计算如下：
Figure PCTCN2018125640-appb-000008
由前述分析知U P≈I sR ds+U T且C dg＝C rss1，则上式可化为：
Figure PCTCN2018125640-appb-000009
考虑到
Figure PCTCN2018125640-appb-000010
所以Q P1＝Q gd。
根据MOSFET的数据手册可知
Figure PCTCN2018125640-appb-000011
其中，C rss(t)为U dg＝U dg(t)时C rss的实测数据。C rss(t)和U dg(t)是MOSFET手册中的常规参数，且U dg(t)通常取25V。
将Q P1＝Q gd及式(6)带入式(5)
可推得：
Figure PCTCN2018125640-appb-000012
由式(7)以及
Figure PCTCN2018125640-appb-000013
则本阶段即密勒效应阶段的持续时间ΔT 2可计算如下：
Figure PCTCN2018125640-appb-000014
综上所述，在副边整流管SR关断到原边开关管SW开启之间最优的死区时间t d为：
Figure PCTCN2018125640-appb-000015
由以上分析可知，对于一个给定的电路，在上式中除了I s，其余均为常量，故可设以下常量：
Figure PCTCN2018125640-appb-000016
Figure PCTCN2018125640-appb-000017
Figure PCTCN2018125640-appb-000018
对于式(9)中的第四项，此处采用泰勒级数展开并忽略高次项：
Figure PCTCN2018125640-appb-000019
其中
Figure PCTCN2018125640-appb-000020
n＝R ds。所以死区时间t d可以表示为：
t d＝K 1+K 2+K 3+f(I s)       (10)
对于图10死区时间计算模块的内部框图，由分析可知，除了副边电流I s是变量，其余均为常量。对于死区时间的四个组成部分，K 1、K 2、K 3为常量，最后一项f(I s)为副边电流I s的幂函数。所以，将输入常量K 1、K 2、K 3输入加法器A 1，用除法器D 1、乘法器M 1实现I s的系数，用除法器D 2、乘法器M 2、M 3、M 4实现I s 2的系数最后通过加法器A 2、A 3实现死区时间t d。
图11是PWM驱动模块。其内部包含一个传统的PWM驱动模块，这个PWM驱动模块可以与现有技术所采用的PWM驱动单元相同，内部包括RS触发器，比较器，数模转换器DAC 和驱动电路。PWM驱动模块产生原边开关管占空比控制信号duty和副边同步整流管占空比控制信号duty_SR，复位RS触发器，去产生占空比不同的PWM波形，控制原边开关管和副边同步整流管的开关，实现从数字信号到时间信号的转换，从而形成了数字控制开关电源的闭环系统。其中内部传统的PWM驱动单元产生的原边开关管控制信号duty将作为输出信号直接控制原边开关管，而产生的副边整流管控制信号duty_SR1需要经过一个简单的逻辑电路，才能用于优化死区时间。此处将死区时间计算模块的输出t d经过一个过零比较器，产生一个正向脉冲，才将正向脉冲通过一个反相器得到一个负向脉冲，D触发器在信号duty_SR下降沿的触发下，使负向脉冲与duty_SR进行与逻辑运算，使此时的死区时间跟随负向脉冲的宽度变化，从而实现了死区时间的优化。
图12是单输出DAC中点采样模块的内部结构图。单输出DAC中点采样模块包括数模转换器DAC、三角波发生器、比较器CMP1、比较器CMP2、计数器和反馈量计算模块；其功能是在副边电流复位时间中点t mid，采样得到辅助绕组上的电压信号V sense(t mid)。信号流向为：辅助绕组上的电压信号V sense作为输入信号流入，输入到两个比较器的正端，分别与单斜坡数字波的电压信号V ref_slope和零电压进行比较，并分别得到反馈比较信号V ref_comp和零比较信号V zvs_comp。计数器根据反馈比较信号V ref_comp和过零比较信号V zvs_comp的高低电平变化，计数得到Δt r_half与T r的大小，Δt r_half为单斜坡数字波V ref_slope从起始电压V initial位置上升到与辅助绕组上电压信号V sense相交所需要的总时间，T r为副边电流从峰值降低到最低点所需要的复位时间。最后反馈量计算模块根据Δt r_half与T r之间大小关系的不同，调整下一周期的单斜坡数字波起始电压V initial的数字值，当辅助绕组上的电压信号V sense与单斜坡数字波的电压信号V ref_slope相等时，将此刻单斜坡数字波的电压信号V ref_slope的值赋值给中点电压信号V sense(t mid)，作为本次开关周期内单输出DAC中点采样模块的输出信号输出。需要说明的是，每一周期都会输出中点电压信号V sense(t mid)，虽然当负载变化、辅助绕组上的电压信号V sense发生变化的动态阶段，单输出DAC中点采样模块的输出信号中点电压信号V sense(t mid)并不是严格意义上的T r/2时刻的辅助绕组上的电压信号V sense(t mid)，只是一个逐渐逼近的近似量，但是通过每个周期不断的比较Δt r_half和T r/2的大小关系，随着逐渐逼近，在多个开关周期后，单输出DAC中点采样模块输出的中点电压信号V sense(t mid)，就会是数值上严格等于T r/2时刻辅助绕组上电压信号V sense(t mid)的精确量)。因为单输出DAC中点采样模块调整的速率很快，动态调整的周期 跟稳态周期相比所占比例非常小，所以每个开关周期，辅助绕组上的电压信号V sense与单斜坡数字波的电压信号V ref_slope相等时，被赋值的单输出DAC中点采样模块输出信号都被称为中点电压信号V sense(t mid)。
图13是数字控制模块的内部结构图。数字控制模块与可以与现有技术的数字控制模块相同，在一个实施例中为数字PI控制模块，其核心是PI控制，即比例积分控制。数字控制模块包括加法器，减法器，乘法器，寄存器，运算放大器K p和K i，及模式判断模块，具体连接关系为：DAC的中点采样电压信号V sense(t mid)与系统预设的固定值V REF经过减法器得到误差e(n)，e(n)一方面给寄存器做输入，另一方面控制模式判断模块。模式判断模块输出两个信号V peak_d和状态state。状态信号state一分为二经过运算放大器，然后经过加法器求和。寄存器的输出e(n-1)与状态state的一路信号相乘并将结果给之后的减法器。求和之后的状态信号与误差e(n)相乘，然后依次经过减法器、加法器，最终得到控制信号V c(n)，此处控制信号V c(n)经过寄存器反馈给上一级加法器。输入信号为单输出DAC的中点采样电压信号V sense(t mid)输出信号是原边电流采样电阻R cs上峰值电压的数字值V peak_d，和控制信号V c(n)。比例控制的输出与输入误差信号成比例关系，积分控制的输出与输入误差信号的积分成比例关系。当系统仅有比例控制时，输出存在稳态误差。为了消除稳态误差，需要加入积分控制。PI控制器可以使系统在进入稳态后无稳态误差。根据输入信号单输出DAC的中点采样电压信号V sense(t mid)与系统预设的固定值V REF的误差系统预设的固定值V REF，比例和积分计算出控制量V c(n)，从而消除稳态误差，同时模式判断模块也会根据误差e(n)的大小直接给出原边电流采样电阻R cs上峰值电压的数字值V peak_d作为输出信号，表达式如下式(11)、(12)：
V c(n)＝V c(n-1)+K p·(e(n)-e(n-1))+K i·e(n)   (11)
e(n)＝V sense(t mid)-V REF         (12)
V c(n)代表本周期控制量，V c(n-1)代表前一周期控制量，e(n)代表本周期误差，e(n-1)代表前一周期误差，K p和K i分别为积分参数和微分参数，在全负载范围内是不唯一的，需要根据不同的模式设置不同的值。
本申请还提供一种原边反馈反激电源CCM模式下的控制系统。所述原边反馈反激电源包括变压器原边侧、变压器副边侧及辅助绕组，所述原边侧包括原边绕组、原边开关管及与所述原边开关管串联的原边电流采样电阻，所述副边侧包括副边绕组和副边整流管，所述系统包括：单输出DAC中点采样模块，在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)；数字控制模块，计算电压信号V sense(T mid)与预设的固定值V REF的误差e(n)，根据所述误差e(n)利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)，并根据所述误差e(n)得到所述原边电流采样电阻上的峰值电压的数字值V peak_d；电流检测模块，根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)；死区时间计算模块，根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d；及PWM驱动模块，根据所述死区时间t d和所述输入电压控制量V c(n)，产生原边占空比控制信号duty和副边占空比控制信号duty_SR；并根据所述原边占空比控制信号duty控制原边开关管的开关，根据所述副边占空比控制信号duty_SR控制副边整流管的开关。
在其中一个实施例中，所述单输出DAC中点采样模块包括数模转换器、三角波发生器、比较器CMP1、比较器CMP2、计数器和反馈量计算模块；所述辅助绕组上的电压信号V sense作为输入信号分别输入所述比较器CMP1的正端和CMP2的正端，所述三角波发生器输出的数字单斜波与所述数模转换器输出的模拟参考电压叠加后，得到单斜坡数字波的电压信号V ref_slope并输入所述比较器CMP1的负端，所述比较器CMP2的负端连接零电压，所述比较器CMP1输出反馈比较信号V ref_comp、所述比较器CMP2输出过零比较信号V zvs_comp至所述计数器，所述计数器根据所述反馈比较信号V ref_comp和过零比较信号V zvs_comp的高低电平变化，计数得到Δt r_half与T r的大小，其中Δt r_half为所述单斜坡数字波的电压信号V ref_slope从起始电压V initial位置上升到与辅助绕组上电压信号V sense相交所需要的总时间，T r为副边电流从峰值降低到最低点所需要的复位时间，所述反馈量计算模块根据Δt r_half与T r之间大小关系的不同，输出反馈信号V ref_initial至所述三角波发生器的输入端和数模转换器的输入端，调整下一周期的所述起始电压V initial的数字值，当辅助绕组上的电压信号V sense与单斜 坡数字波的电压信号V ref_slope相等时，将此刻单斜坡数字波的电压信号V ref_slope的值赋值给所述电压信号V sense(t mid)，作为本次开关周期内单输出DAC中点采样模块的输出信号输出。
在其中一个实施例中，所述电流检测模块包括单输入双输出数模转换器、比较器CMP3、比较器CMP4、原边电流时间计数模块、副边平均电流计算模块，所述单输入双输出数模转换器和副边平均电流计算模块接收所述数字控制模块输出的数字值V peak_d，所述比较器CMP3的正端和比较器CMP4的正端接收所述电压V cs，所述单输入双输出数模转换器的第一输出端输出的原边峰值电流对应于所述原边电流采样电阻上的电压模拟值V peak，并输出至所述比较器CMP3的负端，所述单输入双输出数模转换器的第二输出端输出V peak_half，V peak_half＝k·V peak，0＜k＜1，并输出至所述比较器CMP4的负端，所述比较器CMP3输出比较信号V cmp3至原边电流时间计数模块的第一计数器，所述比较器CMP4输出比较信号V cmp4至原边电流时间计数模块的第二计数器，所述原边电流时间计数模块根据比较信号V cmp3和比较信号V cmp4高低电平的变化，得出DCM情况下原边电流从零安培或者初始电流线性增加到峰值电流所需时间t a、CCM情况下原边电流从零安培或初始电流线性增加到峰值电流的时间t b，并输出给副边平均电流计算模块，所述副边平均电流计算模块将所述数字值V peak_d除以所述原边电流采样电阻的阻值，得到原边绕组电感峰值电流对应的数字量I peak_p，并与时间t a和t b一起代入I s(t mid)的表达式：
Figure PCTCN2018125640-appb-000021
其中N p和N s分别为变压器原、副边绕组匝数，得到CCM情况下的副边平均电流I s(t mid)并将其输出。
在其中一个实施例中，所述死区时间计算模块是根据如下各公式计算所述死区时间t d：
t d＝K 1+K 2+K 3+f(I s)
Figure PCTCN2018125640-appb-000022
Figure PCTCN2018125640-appb-000023
Figure PCTCN2018125640-appb-000024
Figure PCTCN2018125640-appb-000025
Figure PCTCN2018125640-appb-000026
n＝R ds；
以上各式中，U P为密勒平台电压，U g为副边整流管的栅极电压，R g为副边整流管的栅极电阻，Q g为副边整流管关断过程中栅极总耗散电荷量，Q gd为副边整流管关断过程中密勒效应阶段的栅极耗散电荷量，Q gs为副边整流管关断过程中U GS由密勒平台电压U P降至0阶段的门极耗散电荷量，I L为负载电流，U DS副边整流管的输入电压，C rss为副边整流管的反相传输电容，I S为副边电流，U X为实验测取量，U T为副边整流管的阈值电压，R ds为副边整流管的源漏电阻。
在其中一个实施例中，所述PWM驱动模块包括比较器、反相器、D触发器、或门及PWM驱动单元，所述比较器的正输入端输入所述死区时间t d，所述比较器的负输入端连接零电压，所述比较器的输出端连接所述反相器的输入端，所述反相器的输出端连接所述D触发器的D输入端，所述PWM驱动单元的输入信号为所述输入电压控制量V c(b)，所述PWM驱动单元的第一输出端输出原边占空比控制信号duty、第二输出端输出信号duty_SR1至所述D触发器的时钟控制端，所述D触发器的Q输出端连接所述或门的一个输入端、所述信号duty_SR1输入所述或门的另一个输入端，所述或门的输出端输出副边占空比控制信号duty_SR。
在其中一个实施例中，所述副边整流管是MOS管。
在其中一个实施例中，所述原边开关管是MOS管，所述原边电流采样电阻串联于所述原边开关管源极和地线之间。
本申请还提供一种原边反馈反激电源CCM模式下的控制方法，所述原边反馈反激电源包括变压器原边侧、变压器副边侧及辅助绕组，所述原边侧包括原边绕组、原边开关管及与所述原边开关管串联的原边电流采样电阻，所述副边侧包括副边绕组和副边整流管，所述方法包括：在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)；计算电压信号V sense(t mid)与预设的固定值V REF的误差e(n)，根据所述误差e(n)利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)，并根据所述误差e(n)得到所述原边电流采样电阻上的峰值电压的数字值V peak_d；根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均 电流I mid_p和副边平均电流I s(t mid)；根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d；PWM驱动模块根据所述死区时间t d和所述输入电压控制量，V c(n)产生原边占空比控制信号duty和副边占空比控制信号duty_SR；及根据所述原边占空比控制信号duty控制原边开关管的开关，根据所述副边占空比控制信号duty_SR控制副边整流管的开关。
在其中一个实施例中，所述在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(T mid)的步骤包括：
比较器CMP1的正端输入辅助绕组上的电压信号V sense，三角波发生器输出的数字单斜波与数模转换器输出的模拟参考电压叠加后，得到单斜坡数字波的电压信号V ref_slope并输入比较器CMP1的负端，比较器CMP1输出反馈比较信号V ref_comp；
比较器CMP1的正端输入辅助绕组上的电压信号V sense，负端输入零电压，比较器CMP2输出过零比较信号V zvs_comp；
根据所述反馈比较信号V ref_comp和过零比较信号V zvs_comp的高低电平变化，计数得到Δt r_half与T r的大小，其中Δt r_half为所述单斜坡数字波的电压信号V ref_slope从起始电压V initial位置上升到与辅助绕组上电压信号V sense相交所需要的总时间，T r为副边电流从峰值降低到最低点所需要的复位时间；
根据Δt r_half与T r之间大小关系的不同，输出反馈信号V ref_initial至所述三角波发生器的输入端和数模转换器的输入端，调整下一周期的所述起始电压V initial的数字值；及
当辅助绕组上的电压信号V sense与单斜坡数字波的电压信号V ref_slope相等时，将此刻单斜坡数字波的电压信号V ref_slope的值赋值给所述电压信号V sense(t mid)。
在其中一个实施例中，所述根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)的步骤包括：
所述比较器CMP3的正端和比较器CMP4的正端接收所述电压V cs；
将所述数字值V peak_d进行数模转换，得到原边峰值电流对应于所述原边电流采样电阻上的电压模拟值V peak，并输出至所述比较器CMP3的负端，且得到V peak_half，V peak_half＝k·V peak，0＜k＜1，并输出至所述比较器CMP4的负端；
根据所述比较器CMP3输出的比较信号V cmp3的高低电平变化、和所述比较器CMP4输出的比较信号V cmp4的高低电平变化，得出DCM情况下原边电流从零安培或者初始电流线性增加到峰值电流所需时间t a、CCM情况下原边电流从零安培或初始电流线性增加到峰值电流的时间t b；
将所述数字值V peak_d除以所述原边电流采样电阻的阻值，得到原边绕组电感峰值电流的数字量I peak_p；及
将数字量I peak_p、时间t a及t b一起代入I s(t mid)的表达式：
Figure PCTCN2018125640-appb-000027
其中N p和N s分别为变压器原、副边绕组匝数，得到CCM情况下的副边平均电流I s(t mid)。
在其中一个实施例中，所述根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d的步骤，是根据如下各公式计算所述死区时间t d：
t d＝K 1+K 2+K 3+f(I s)
Figure PCTCN2018125640-appb-000028
Figure PCTCN2018125640-appb-000029
Figure PCTCN2018125640-appb-000030
Figure PCTCN2018125640-appb-000031
Figure PCTCN2018125640-appb-000032
n＝R ds；
以上各式中，U P为密勒平台电压，U g为副边整流管的栅极电压，R g为副边整流管的栅极电阻，Q g为副边整流管关断过程中栅极总耗散电荷量，Q gd为副边整流管关断过程中 密勒效应阶段的栅极耗散电荷量，Q gs为副边整流管关断过程中U GS由密勒平台电压U P降至0阶段的门极耗散电荷量，I L为负载电流，U DS副边整流管的输入电压，C rss为副边整流管的反相传输电容，I s为副边电流，U X为实验测取量，U T为副边整流管的阈值电压，R ds为副边整流管的源漏电阻。

Claims (17)

  1. 一种原边反馈反激电源CCM模式下的死区时间自动优化系统，包括单输出DAC中点采样模块、数字控制模块、电流检测模块、死区时间计算模块和PWM驱动模块构成的控制系统，所述控制系统与受控的同步整流原边反馈反激式变换器主拓扑形成闭环；单输出DAC中点采样模块在副边电流复位时间T r的中点时刻，即T r/2时刻采样辅助绕组上的电压信号V sense(t mid)输出给数字控制模块，数字控制模块计算电压信号V sense(t mid)与系统预设的固定值V REF的误差e(n)并利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)输出给PWM驱动模块，同时，数字控制模块根据误差e(n)大小给出原边电流采样电阻R cs上的峰值电压的数字值V peak_d，该数字值V peak_d与原边电流采样电阻R cs两端的电压V cs一起输出给电流检测模块，电流检测模块使用纯数字的方式，通过DAC间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)并将副边平均电流I s(t mid)作为输出信号输出给死区时间计算模块计算出副边整流管SR关断到原边开关管SW开启之间合理的死区时间t d，PWM驱动模块在死区时间计算模块输出的死区时间t d和数字控制模块输出的控制量V c(n)的共同控制下，产生占空比控制信号duty和duty_SR，分别控制原边开关管SW和副边同步整流管SR的开关，实现对同步整流原边反馈反激式电源CCM模式下死区时间的自动优化。
  2. 根据权利要求1所述的原边反馈反激电源CCM模式下的死区时间自动优化系统，其特征在于，所述单输出DAC中点采样模块用于在副边电流复位时间中点t mid，采样得到辅助绕组上的电压信号V sense(t mid)，包括数模转换器DAC、三角波发生器、比较器CMP1、比较器CMP2、计数器和反馈量计算模块；辅助绕组上的电压信号V sense作为输入信号分别连接比较器CMP1和CMP2的正端，比较器CMP1的负端连接三角波发生器输出的数字单斜波与DAC输出的模拟参考电压两者叠加后得到的单斜坡数字波的电压信号V ref_slope，比较器CMP2的负端连接零电压，比较器CMP1和CMP2分别输出反馈比较信号V ref_comp和零比较信号V zvs_comp均连接至计数器，计数器根据反馈比较信号V ref_comp和过零比较信号V zvs_comp的高低电平变化，计数得到Δt r_half与T r的大小，Δt r_half为单斜坡数字波V ref_slope从起始电压V initial位置上升到与辅助绕组上电压信号V sense相交所需要的总时间，T r为副边 电流从峰值降低到最低点所需要的复位时间，反馈量计算模块输出反馈信号V ref_initial连接三角波发生器和DAC的输入端，根据Δt r_half与T r之间大小关系的不同，调整下一周期的单斜坡数字波起始电压V initial的数字值，当辅助绕组上的电压信号V sense与单斜坡数字波的电压信号V ref_slope相等时，将此刻单斜坡数字波的电压信号V ref_slope的值赋值给中点电压信号V sense(t mid)，作为本次开关周期内单输出DAC中点采样模块的输出信号输出。
  3. 根据权利要求1所述的原边反馈反激电源CCM模式下的死区时间自动优化系统，其特征在于：所述数字控制模块为数字PI控制模块结构，其核心是PI控制，即比例积分控制，包括加法器、减法器、乘法器、寄存器以及运算放大器K p和K i和模式判断模块，数字控制模块的输入信号为单输出DAC的中点采样电压信号V sense(t mid)，数字控制模块的输出信号是原边电流采样电阻R cs上峰值电压的数字值V peak_d和控制量V c(n)；单输出DAC的中点采样电压信号V sense(t mid)与系统预设的固定值V REF的误差e(n)大小，比例和积分计算出控制量V c(n)输出，同时模式判断模块也会根据误差e(n)大小给出原边电流采样电阻R cs上峰值电压的数字值V peak_d作为输出信号。
  4. 根据权利要求1所述的原边反馈反激电源CCM模式下的死区时间自动优化系统，其特征在于：所述电流检测模块包括一个单输入双输出的DAC和两个比较器CMP3和CMP4以及原边电流时间计数模块和副边平均电流计算模块，数字控制模块输出的原边电流采样电阻R cs上的峰值电压的数字值V peak_d分别连接DAC和副边平均电流计算模块，比较器CMP3的正端连接原边电流采样电阻R cs两端的电压V cs，负端连接DAC输出的原边峰值电流对应于原边电流采样电阻上的电压模拟值V peak，比较器CMP4的正端连接原边电流采样电阻R cs两端的电压V cs，负端连接原边峰值电流的k倍对应于原边电流采样电阻上的电压模拟值V peak_half，V peak_half＝k·V peak，0＜k＜1，比较器CMP3和比较器CMP4分别输出比较信号V cmp3和V cmp4均连接至原边电流时间计数模块，原边电流时间计数模块包括两个计数器，该两个计数器的输入信号分别为比较器CMP3和CMP4的输出信号V cmp3和V cmp4，根据V cmp3和V cmp4高低电平的变化，得出DCM情况下原边电流从零安培或者初始电流线性增加到峰值电流所需时间t a，CCM情况下原边电流从零安培或初始电流线性增加到峰值电流 的时间t b，输出给副边平均电流计算模块，副边平均电流计算模块根据输入的时间信号t a和t b，以及数字控制模块输出的原边电流采样电阻R cs上的峰值电压的数字值V peak_d，将V peak_d除以原边电流采样电阻R cs的阻值，推出原边绕组电感峰值电流I peak_p对应的数字量，并代入I s(t mid)的表达式：
    Figure PCTCN2018125640-appb-100001
    其中N p和N s分别为变压器原副边匝数，即得CCM情况下的副边平均电流I s(t mid)并将其输出。
  5. 根据权利要求1所述的原边反馈反激电源CCM模式下的死区时间自动优化系统，其特征在于：所述死区时间计算模块用于根据电流检测模块输出的副边平均电流I s(t mid)运用包括加法器、乘法器、除法器构成的计算链计算出副边整流管SR关断到原边开关管SW开启之间合理的死区时间t d：
    t d＝K 1+K 2+K 3+f(I s)
    Figure PCTCN2018125640-appb-100002
    Figure PCTCN2018125640-appb-100003
    Figure PCTCN2018125640-appb-100004
    Figure PCTCN2018125640-appb-100005
    Figure PCTCN2018125640-appb-100006
    n＝R ds；
    上式中，U P为密勒平台电压，U g为副边整流管的栅极电压，R g为副边整流管的栅极电阻，Q g为副边整流管关断过程中栅极总耗散电荷量，Q gd为副边整流管关断过程中密勒效应阶段的栅极耗散电荷量，Q gs为副边整流管关断过程中U GS由密勒平台电压U P降至0阶段的门极耗散电荷量，I L为负载电流，U DS副边整流管的输入电压，C rss为副边整流管的反相传输电容，I s为副边电流，U X为实验测取量，U T为副边整流管的阈值电压，R ds为副边整流管的源漏电阻。
  6. 根据权利要求1所述的原边反馈反激电源CCM模式下的死区时间自动优化系统，其特征在于：所述PWM驱动模块包括一个含有RS触发器，比较器，数模转换器DAC和驱 动电路的PWM驱动单元和一个包括比较器、反相器、D触发器和或门构成的逻辑电路，PWM驱动单元的输入信号为数字控制模块输出的控制量V c(n)，PWM驱动单元的输出为原边开关管占空比控制信号duty和副边同步整流管占空比控制信号duty_SR1，其中，原边开关管控制信号duty作为输出信号直接控制原边开关管，而产生的副边整流管控制信号duty_SR1连接D触发器的时钟控制端，D触发器的D输入端连接反相器的输出端，反相器的输入端连接比较器的输出端，比较器的正输入端连接死区时间计算模块输出的死区时间t d，比较器的负输入端连接零电压，D触发器的Q输出端和PWM驱动单元输出的副边同步整流管占空比控制信号duty_SR1分别连接或门的两个输入端，或门输出副边同步整流管占空比控制信号duty_SR控制副边同步整流管。
  7. 一种原边反馈反激电源CCM模式下的控制系统，所述原边反馈反激电源包括变压器原边侧、变压器副边侧及辅助绕组，所述原边侧包括原边绕组、原边开关管及与所述原边开关管串联的原边电流采样电阻，所述副边侧包括副边绕组和副边整流管，所述系统包括：
    单输出DAC中点采样模块，在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)；
    数字控制模块，计算电压信号V sense(t mid)与预设的固定值V REF的误差e(n)，根据所述误差e(n)利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)，并根据所述误差e(n)得到所述原边电流采样电阻上的峰值电压的数字值V peak_d；
    电流检测模块，根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)；
    死区时间计算模块，根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d；及
    PWM驱动模块，根据所述死区时间t d和所述输入电压控制量V c(n)，产生原边占空比控制信号duty和副边占空比控制信号duty_SR；并根据所述原边占空比控制信号duty控制原边开关管的开关，根据所述副边占空比控制信号duty_SR控制副边整流管的开关。
  8. 根据权利要求7所述的系统，其特征在于，所述单输出DAC中点采样模块包括数模转换器、三角波发生器、比较器CMP1、比较器CMP2、计数器和反馈量计算模块；所述辅助绕组上的电压信号V sense作为输入信号分别输入所述比较器CMP1的正端和CMP2的正端，所述三角波发生器输出的数字单斜波与所述数模转换器输出的模拟参考电压叠加后，得到单斜坡数字波的电压信号V ref_slope并输入所述比较器CMP1的负端，所述比较器CMP2 的负端连接零电压，所述比较器CMP1输出反馈比较信号V ref_comp、所述比较器CMP2输出过零比较信号V zvs_comp至所述计数器，所述计数器根据所述反馈比较信号V ref_comp和过零比较信号V zvs_comp的高低电平变化，计数得到Δt r_half与T r的大小，其中Δt r_half为所述单斜坡数字波的电压信号V ref_slope从起始电压V initial位置上升到与辅助绕组上电压信号V sense相交所需要的总时间，T r为副边电流从峰值降低到最低点所需要的复位时间，所述反馈量计算模块根据Δt r_half与T r之间大小关系的不同，输出反馈信号V ref_initial至所述三角波发生器的输入端和数模转换器的输入端，调整下一周期的所述起始电压V initial的数字值，当辅助绕组上的电压信号V sense与单斜坡数字波的电压信号V ref_slope相等时，将此刻单斜坡数字波的电压信号V ref_slope的值赋值给所述电压信号V sense(t mid)，作为本次开关周期内单输出DAC中点采样模块的输出信号输出。
  9. 根据权利要求7所述的系统，其特征在于，所述电流检测模块包括单输入双输出数模转换器、比较器CMP3、比较器CMP4、原边电流时间计数模块、副边平均电流计算模块，所述单输入双输出数模转换器和副边平均电流计算模块接收所述数字控制模块输出的数字值V peak_d，所述比较器CMP3的正端和比较器CMP4的正端接收所述电压V cs，所述单输入双输出数模转换器的第一输出端输出的原边峰值电流对应于所述原边电流采样电阻上的电压模拟值V peak，并输出至所述比较器CMP3的负端，所述单输入双输出数模转换器的第二输出端输出V peak_half，V peak_half＝k·V peak，0＜k＜1,并输出至所述比较器CMP4的负端，所述比较器CMP3输出比较信号V cmp3至原边电流时间计数模块的第一计数器，所述比较器CMP4输出比较信号V cmp4至原边电流时间计数模块的第二计数器，所述原边电流时间计数模块根据比较信号V cmp3和比较信号V cmp4高低电平的变化，得出DCM情况下原边电流从零安培或者初始电流线性增加到峰值电流所需时间t a、CCM情况下原边电流从零安培或初始电流线性增加到峰值电流的时间t b，并输出给副边平均电流计算模块，所述副边平均电流计算模块将所述数字值V peak_d除以所述原边电流采样电阻的阻值，得到原边绕组电感峰值电流对应的数字量I peak_p，并与时间t a和t b一起代入I s(t mid)的表达式：
    Figure PCTCN2018125640-appb-100007
    其中N p和N s分别为变压器原、副边绕组匝数，得到CCM情况下的副边平均电流I s(t mid)并将其输出。
  10. 根据权利要求7所述的系统，其特征在于，所述死区时间计算模块是根据如下各公式计算所述死区时间t d：
    t d＝K 1+K 2+K 3+f(I s)
    Figure PCTCN2018125640-appb-100008
    Figure PCTCN2018125640-appb-100009
    Figure PCTCN2018125640-appb-100010
    Figure PCTCN2018125640-appb-100011
    Figure PCTCN2018125640-appb-100012
    n＝R ds；
    以上各式中，U P为密勒平台电压，U g为副边整流管的栅极电压，R g为副边整流管的栅极电阻，Q g为副边整流管关断过程中栅极总耗散电荷量，Q gd为副边整流管关断过程中密勒效应阶段的栅极耗散电荷量，Q gs为副边整流管关断过程中U GS由密勒平台电压U P降至0阶段的门极耗散电荷量，I L为负载电流，U DS副边整流管的输入电压，C rss为副边整流管的反相传输电容，I s为副边电流，U X为实验测取量，U T为副边整流管的阈值电压，R ds为副边整流管的源漏电阻。
  11. 根据权利要求7所述的系统，其特征在于，所述PWM驱动模块包括比较器、反相器、D触发器、或门及PWM驱动单元，所述比较器的正输入端输入所述死区时间t d，所述比较器的负输入端连接零电压，所述比较器的输出端连接所述反相器的输入端，所述反相器的输出端连接所述D触发器的D输入端，所述PWM驱动单元的输入信号为所述输入电压控制量V c(n)，所述PWM驱动单元的第一输出端输出原边占空比控制信号duty、第二输出端输出信号duty_SR1至所述D触发器的时钟控制端，所述D触发器的Q输出端连接所述或门的一个输入端、所述信号duty_SR1输入所述或门的另一个输入端，所述或门的输出端输出副边占空比控制信号duty_SR。
  12. 根据权利要求7所述的系统，其特征在于，所述副边整流管是MOS管。
  13. 根据权利要求7所述的系统，其特征在于，所述原边开关管是MOS管，所述原边电流采样电阻串联于所述原边开关管源极和地线之间。
  14. 一种原边反馈反激电源CCM模式下的控制方法，所述原边反馈反激电源包括变压器原边侧、变压器副边侧及辅助绕组，所述原边侧包括原边绕组、原边开关管及与所述原边开关管串联的原边电流采样电阻，所述副边侧包括副边绕组和副边整流管，所述方法包括：
    在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)；
    计算电压信号V sense(t mid)与预设的固定值V REF的误差e(n)，根据所述误差e(n)利用比例和积分计算出PWM驱动模块的输入电压控制量V c(n)，并根据所述误差e(n)得到所述原边电流采样电阻上的峰值电压的数字值V peak_d；
    根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)；
    根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d；
    PWM驱动模块根据所述死区时间t d和所述输入电压控制量，V c(n)产生原边占空比控制信号duty和副边占空比控制信号duty_SR；及
    根据所述原边占空比控制信号duty控制原边开关管的开关，根据所述副边占空比控制信号duty_SR控制副边整流管的开关。
  15. 根据权利要求14所述的方法，其特征在于，所述在副边电流复位时间T r的中点时刻T r/2采样所述辅助绕组上的电压信号V sense(t mid)的步骤包括：
    比较器CMP1的正端输入辅助绕组上的电压信号V sense，三角波发生器输出的数字单斜波与数模转换器输出的模拟参考电压叠加后，得到单斜坡数字波的电压信号V ref_slope并输入比较器CMP1的负端，比较器CMP1输出反馈比较信号V ref_comp；
    比较器CMP1的正端输入辅助绕组上的电压信号V sense，负端输入零电压，比较器CMP2输出过零比较信号V zvs_comp；
    根据所述反馈比较信号V ref_comp和过零比较信号V zvs_comp的高低电平变化，计数得到Δt r_half与T r的大小，其中Δt r_half为所述单斜坡数字波的电压信号V ref_slope从起始电压V initial位置上升到与辅助绕组上电压信号V sense相交所需要的总时间，T r为副边电流从峰值 降低到最低点所需要的复位时间；
    根据Δt r_half与T r之间大小关系的不同，输出反馈信号V ref_initial至所述三角波发生器的输入端和数模转换器的输入端，调整下一周期的所述起始电压V initial的数字值；及
    当辅助绕组上的电压信号V sense与单斜坡数字波的电压信号V ref_slope相等时，将此刻单斜坡数字波的电压信号V ref_slope的值赋值给所述电压信号V sense(t mid)。
  16. 根据权利要求14所述的方法，其特征在于，所述根据所述数字值V peak_d和所述原边电流采样电阻两端的电压V cs，通过数模转换间接采样并推算得到CCM情况下原边平均电流I mid_p和副边平均电流I s(t mid)的步骤包括：
    所述比较器CMP3的正端和比较器CMP4的正端接收所述电压V cs；
    将所述数字值V peak_d进行数模转换，得到原边峰值电流对应于所述原边电流采样电阻上的电压模拟值V peak，并输出至所述比较器CMP3的负端，且得到V peak_half，V peak_half＝k·V peak，0＜k＜1，并输出至所述比较器CMP4的负端；
    根据所述比较器CMP3输出的比较信号V cmp3的高低电平变化、和所述比较器CMP4输出的比较信号V cmp4的高低电平变化，得出DCM情况下原边电流从零安培或者初始电流线性增加到峰值电流所需时间t a、CCM情况下原边电流从零安培或初始电流线性增加到峰值电流的时间t b；
    将所述数字值V peak_d除以所述原边电流采样电阻的阻值，得到原边绕组电感峰值电流的数字量I peak_p；及
    将数字量I peak_p、时间t a及t b一起代入I s(t mid)的表达式：
    Figure PCTCN2018125640-appb-100013
    其中N p和N s分别为变压器原、副边绕组匝数，得到CCM情况下的副边平均电流I s(t mid)。
  17. 根据权利要求14所述的方法，其特征在于，所述根据所述副边平均电流I s(t mid)计算所述副边整流管关断到原边开关管开启之间的死区时间t d的步骤，是根据如下各公式 计算所述死区时间t d：
    t d＝K 1+K 2+K 3+f(I s)
    Figure PCTCN2018125640-appb-100014
    Figure PCTCN2018125640-appb-100015
    Figure PCTCN2018125640-appb-100016
    Figure PCTCN2018125640-appb-100017
    Figure PCTCN2018125640-appb-100018
    n＝R ds；
    以上各式中，U P为密勒平台电压，U g为副边整流管的栅极电压，R g为副边整流管的栅极电阻，Q g为副边整流管关断过程中栅极总耗散电荷量，Q gd为副边整流管关断过程中密勒效应阶段的栅极耗散电荷量，Q gs为副边整流管关断过程中U GS由密勒平台电压U P降至0阶段的门极耗散电荷量，I L为负载电流，U DS副边整流管的输入电压，C rss为副边整流管的反相传输电容，I s为副边电流，U X为实验测取量，U T为副边整流管的阈值电压，R ds为副边整流管的源漏电阻。
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