WO2019127692A1

WO2019127692A1 - Coa type array substrate and display panel

Info

Publication number: WO2019127692A1
Application number: PCT/CN2018/072866
Authority: WO
Inventors: 甘启明
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2017-12-26
Filing date: 2018-01-16
Publication date: 2019-07-04
Also published as: CN108121124B; CN108121124A

Abstract

A color filter on array (COA) type array substrate, comprising: a thin film transistor array substrate, a first insulating layer (250), a color resist layer (260), a second insulating layer (270), and an electrode layer; a first opening (261) is internally provided with a first through hole (271) and a second through hole (272) that are separated from each other; the first through hole (271) penetrates the first insulating layer (250) and the second insulating layer (270) and reaches a drain electrode of a main thin film transistor; and the second through hole (272) penetrates the first insulating layer (250), the second insulating layer (270) and part of the thin film transistor array substrate and reaches a common electrode line (222); the COA type array substrate further comprises an elevated layer (262), wherein the elevated layer (262) at least elevates the height of the second insulating layer (270) in the first opening (261) so as to prevent a first connection electrode (283) and second connection electrode (284) from short circuiting. A display panel, which likewise has the advantage of preventing the first connection electrode (283) and second connection electrode (284) from short circuiting.

Description

COA type array substrate and display panel

The present application claims priority to the filing date of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the present disclosure.

Technical field

The present invention relates to the field of display technologies, and in particular, to a COA type array substrate and a display panel.

Background technique

With the development of technology, the application of liquid crystal display panels is increasing. In order to achieve better color display of the liquid crystal display panel, the current liquid crystal display panel adds a color resist layer on the array substrate, thereby realizing RGB three primary colors on the array substrate, thereby avoiding the array substrate and the filter substrate. The alignment operation allows the liquid crystal display device to perform a full color display better. The above technique is called COA (Color Filter on Array) technology.

For the COA type array substrate, in order to improve the color distortion in the large viewing angle display mode, the prior art adopts the 3T design, and in the 3T pixel structure design, one pixel structure is divided into two parts of the main pixel area and the sub-pixel area, and The shared thin film transistor is increased to lower the voltage of the sub-pixel region, thereby controlling the difference in liquid crystal rotation between the main pixel region and the sub-pixel region to improve the phenomenon of color distortion at a wide viewing angle.

Generally, in the array substrate of the above 3T design, referring to FIG. 1 to FIG. 4, each pixel unit PX includes: a main pixel region and a sub-pixel region, the main pixel region having a main thin film transistor TFT_m, the second The pixel region has a sub-thin film transistor TFT_s and a shared thin film transistor TFT_share; wherein the main pixel region further has a main pixel electrode 181 for forming a main liquid crystal capacitor Cls_m and a sub-pixel region between the common electrode and the common electrode Com on the filter substrate. There is also a sub-pixel electrode 182 for forming a sub-liquid crystal capacitance Cls_s with the common electrode Com on the filter substrate. The gate of the main thin film transistor TFT_m and the gate of the sub-thin film transistor TFT_s are connected to the same scan line SL; the source of the main thin film transistor TFT_m and the source of the sub-thin film transistor TFT_s are connected to the same data line. DL, the drain of the main thin film transistor TFT_m is connected to the main pixel electrode 181 of the main pixel region, and the drain of the sub-thin film transistor TFT_s is connected to the sub-pixel electrode 182 of the sub-pixel region, thereby respectively controlling the main pixel region and the second The display of the pixel area. The source of the shared thin film transistor TFT_share is connected to the common electrode line 122, the drain of the shared thin film transistor TFT_share is electrically connected to the sub-pixel electrode 182, the gate of the shared thin film transistor TFT_share and the main thin film transistor TFT_m, The scan lines SL connected to the sub-thin film transistor TFT_s are electrically connected.

In the specific fabrication process of the COA type array substrate using the above 3T design, the scan line SL, the gate electrode and the common electrode line 122 all belong to the first metal layer, and the first metal layer is formed on the base substrate 110. The data line DL, the source and drain of the main thin film transistor TFT_m, the source and drain of the sub-thin film transistor TFT_s, and the source and drain of the shared thin film transistor TFT_share belong to the second metal layer, and are formed on the first metal layer. A gate insulating layer 130 is disposed between the second metal layer and the first metal layer. The first insulating layer 150 is located on the second metal layer, and after the second metal layer is formed, the color resist layer 160 is located on the first insulating layer 150, after the first insulating layer 150, and the second insulating layer 170 is located in the color. The resistive layer 160 is formed behind the color resist layer 160, and the main pixel electrode 181 and the sub-pixel electrode 182 belong to the third metal layer, and the third metal layer is an ITO transparent conductive layer formed on the second insulating layer 170. after that. In order to connect the pixel electrode and the drain, and the shared thin film transistor TFT_share is electrically connected to the common electrode line 122, and limited by the size of the pixel unit and the limitation of the exposure process, the design of the original three vias on the color resist layer 160 is changed to A large opening 161 and a small opening, that is, two of the via holes on the color resist layer 160 are merged into a large opening 161, specifically a via and corresponding to the main thin film transistor TFT_m on the color resist layer 160. The vias of the shared thin film transistor TFT_share are merged into one large opening 161, and the remaining one is an opening similar to the via. Thereafter, a second insulating layer 170 is formed and the second insulating layer 170 is filled into the large opening 161, and then two via

holes

171, 172 are diced on the first insulating layer 150 and the second insulating layer 170, the two

Holes

171, 172 pass through the opening 161. Thereafter, an ITO transparent conductive layer is deposited, and then exposed and developed to form a main pixel electrode 181, a sub-pixel electrode 182, and

connection electrodes

183, 184. The

connection electrodes

183, 184 are respectively located in the two via

holes

171, 172, and the connection electrode 183 The drain for the main thin film transistor TFT_m is electrically connected to the main pixel electrode 181, and the source electrode for the shared thin film transistor TFT_share is electrically connected to the common electrode line 122. However, since the ground at the opening 161 of the color resist layer 160 is different, some terrains have a high topography, and after coating the photoresist, there may be residual photoresist after exposure, especially in a low-lying area, which may result in The ITO transparent conductive layer remains, so that the connection electrode 183 in the corresponding main thin film transistor TFT_m via 171 and the connection electrode 184 in the corresponding shared thin film transistor TFT_share via 172 may be short-circuited, thereby causing the main pixel electrode 181 and the common electrode line 122 to be short-circuited. A dark spot is formed, which affects the lighting of the main pixel electrode 181, thereby affecting the display of the display panel.

Summary of the invention

A technical problem to be solved by the embodiments of the present invention is to provide a COA type array substrate and a display panel. It can effectively improve the short circuit of the main thin film transistor and the shared thin film transistor.

In order to solve the above technical problem, the first aspect of the present invention provides a COA type array substrate, including:

A thin film transistor array substrate comprising:

a plurality of scan lines extending in a first direction;

a plurality of data lines extending in a second direction perpendicular to the first direction;

a plurality of common electrode lines for providing a common voltage, the common electrode lines being in the same metal layer as the scan lines;

a plurality of thin film transistors each comprising a main thin film transistor, a sub thin film transistor, and a shared thin film transistor;

a first insulating layer on the thin film transistor array substrate;

a color resist layer on the first insulating layer, wherein the color resist layer forms a plurality of first openings, each of the first openings extending from above the drain of the main thin film transistor to above the source of the shared thin film transistor ;

a second insulating layer formed on the color resist layer and the first insulating layer, and the second insulating layer is filled into the first opening;

An electrode layer formed on the second insulating layer, the electrode layer comprising a plurality of pixel electrodes, each pixel electrode being disposed corresponding to a group of thin film transistors, each of the pixel electrodes including a main pixel electrode and a sub-pixel electrode, the main film The drain of the transistor is electrically connected to the corresponding main pixel electrode, the drain of the sub-thin film transistor is electrically connected to the corresponding sub-pixel electrode, and the drain and the source of the shared thin film transistor are respectively corresponding to the corresponding a pixel electrode and a common electrode line are electrically connected; wherein

a first via hole and a second via hole separated from each other are disposed in the first opening, and the first via hole penetrates the first insulating layer and the second insulating layer to reach a drain of the main thin film transistor, the second pass The hole penetrates the first insulating layer, the second insulating layer, and the partial thin film transistor array substrate reaches the common electrode line, the electrode layer further includes a first connecting electrode and a second connecting electrode, wherein the first connecting electrode is located in the first via hole Connecting the drain of the main thin film transistor and the main pixel electrode, wherein the second connection electrode is located in the second via hole to connect the drain of the shared thin film transistor and the common electrode line; wherein the COA type array substrate further includes The upper layer of the pad, the pad upper layer at least raising the height of the second insulating layer in the first opening for preventing the first connection electrode and the second connection electrode from being short-circuited.

The upper layer of the pad is formed by extending a lower edge of the first opening toward the inside of the first opening, and the upper layer of the pad is integrally formed with the color resist layer.

Wherein the upper layer of the pad is in the same layer as the data line and is made of the same metal, and the projection of the pad in the horizontal plane extends from the lower edge of the first opening toward the inside of the first opening.

The gates of the same group of thin film transistors are connected to the same scan line, and the scan lines are located between the main pixel electrode and the sub-pixel electrode, and the first opening and the common electrode line are located at a position of the scan line close to the main pixel electrode. On the side, the first opening extends from the upper direction scanning line direction of the common electrode line to the gap area between the common electrode line and the scanning line.

Wherein the first opening comprises an opening first portion and an opening second portion, the opening first portion overlapping the common electrode line, the opening second portion being staggered from the common electrode line, and the opening second portion being located The lower side of the first portion of the opening, the projection of the level in the horizontal plane is at least partially located in the second portion of the opening.

Wherein the projection of the horizontal plane extends inwardly into the first portion of the opening.

Wherein the projection of the pad in the horizontal plane is located between the first connection electrode and the second connection electrode.

Wherein the source of the main thin film transistor and the source of the sub-thin film transistor of the same group of thin film transistors are electrically connected to the same data line, the gate of the main thin film transistor, the gate of the sub-thin film transistor, and the The gate of the shared thin film transistor is electrically connected to the same scan line.

Wherein, the main thin film transistor and the sub-thin film transistor share the same source and share the same gate.

A second aspect of the present invention provides a display panel including the above COA type array substrate.

Embodiments of the present invention have the following beneficial effects:

Since the COA type array substrate includes a pad high layer, the pad upper layer at least raises the height of the second insulating layer in the first opening, and can block the metal on both sides of the padded second insulating layer, thereby preventing the padding from being high. The metal on both sides of the second insulating layer is short-circuited, so that the first connection electrode and the second connection electrode can be prevented from being short-circuited.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic view of a prior art display panel;

2 is a schematic top view of a pixel unit of the prior art;

Figure 3 is a cross-sectional view of the ee line of Figure 2;

4 is an electrical connection diagram of a main thin film transistor, a sub-thin film transistor, and a shared thin film transistor in a pixel unit;

5 is a schematic diagram of a pixel unit in a COA type array substrate according to a first embodiment of the present invention;

Figure 6 is a cross-sectional view taken along line EE of Figure 5;

7 is a schematic diagram of a pixel unit in a COA type array substrate in a second embodiment of the present invention;

Figure 8 is a cross-sectional view taken along line EE of Figure 7.

Detailed ways

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The terms "comprising" and "having", and any variations thereof, appearing in the specification, the claims, and the drawings are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or alternatively Other steps or units inherent to these processes, methods, products or equipment. Moreover, the terms "first," "second," and "third," etc. are used to distinguish different objects, and are not intended to describe a particular order.

First embodiment

The embodiment of the present invention provides a COA type array substrate. Referring to FIG. 5 and FIG. 6, the COA type array substrate includes a thin film transistor array substrate, a first insulating layer 250, a color resist layer 260, a second insulating layer 270, and an electrode. Floor.

In this embodiment, the thin film transistor array substrate includes a base substrate 210, a plurality of scan lines SL, a plurality of data lines DL, a plurality of common electrode lines 222, and a plurality of sets of thin film transistors.

In this embodiment, the base substrate 210 may be a glass substrate, or may be a rigid plastic substrate or a flexible plastic substrate. The substrate substrate 210 is transparent, and light can penetrate through.

In this embodiment, a plurality of the scan lines SL are formed on the base substrate 210, and an insulating layer may or may not be disposed between the scan lines SL and the base substrate 210. . In the present embodiment, the plurality of scan lines SL extend in the first direction, and the scan lines SL and the scan lines SL are parallel to each other.

In this embodiment, the plurality of the common electrode lines 222 and the scan lines SL are located in the same metal layer. Here, the metal layer where the scan lines SL and the common electrode lines 222 are located is referred to as a first metal layer. The scan line SL and the common electrode line 222 are electrically insulated from each other. The common electrode line 222 is for providing a common voltage.

In this embodiment, the data line DL is located above the first metal layer, the data line DL is in the second metal layer, and the gate insulation is at least spaced between the first metal layer and the second metal layer. Layer 230. In this embodiment, the plurality of data lines DL extend in the second direction, the second direction and the first direction are perpendicular to each other, and the data lines DL and the data lines DL are parallel to each other.

In this embodiment, a plurality of thin film transistors are formed on the base substrate 210. Each of the thin film transistors includes a main thin film transistor TFT_m, a sub-thin film transistor TFT_s, and a shared thin film transistor TFT_share, wherein each thin film transistor includes a source and a drain. And the gate, that is, the main thin film transistor TFT_m, the sub-thin film transistor TFT_s, and the shared thin film transistor TFT_share, each include a source, a drain, and a gate. The gate is located in the first metal layer and is electrically connected to the corresponding scan line SL, and the source and the drain are located in the second metal layer. In this embodiment, the gates of the main thin film transistor TFT_m, the sub-thin film transistor TFT_s, and the shared thin film transistor TFT_share in each group of thin film transistors are connected to the same scan line SL, and the main thin film transistor TFT_m and the sub-thin film transistor in each group of thin film transistors are connected. The source of the TFT_s is connected to the same data line DL. In this embodiment, the main thin film transistor TFT_m and the sub-thin film transistor TFT_s share one source, and the drain of the shared thin film transistor TFT_share is the same as the same group. The drain of the thin film transistor TFT_s is electrically connected, and the source of the shared thin film transistor TFT_share is electrically connected to the corresponding common electrode line 222. In this embodiment, the main thin film transistor TFT_m and the sub-thin film transistor TFT_s of each group of thin film transistors share one gate, and the gates shared by the main thin film transistor TFT_m and the sub-thin film transistor TFT_s and the shared thin film transistor TFT_share in the same group The gates are electrically connected and share the same metal, except that the gates of the two are located in different regions of the common metal. In this embodiment, the gates of the main thin film transistor TFT_m, the sub-thin film transistor TFT_s, and the shared thin film transistor TFT_share in the same group are all located on the same side of the scan line SL connected thereto, which is the lower side of the scan line SL in this embodiment. .

In this embodiment, the first insulating layer 250 is located on the thin film transistor array substrate. Specifically, the first insulating layer 250 is located above the second metal layer. In this embodiment, the first insulating layer 250 is an inorganic insulating layer.

In this embodiment, a color resist layer 260 is formed on the first insulating layer 250, and the color resist layer 260 includes a plurality of red color resists, a plurality of green color resists, and a plurality of blue color resists, and the like. A plurality of first openings 261 are formed on the resist layer 260. The first openings 261 are a large opening, and the first openings 261 are square, and are rectangular here, and each of the first openings 261 is disposed in each Above the group of thin film transistors, the first opening 261 extends from above the drain of the main thin film transistor TFT_m to the source of the shared thin film transistor TFT_share. This arrangement facilitates process simplification. In this embodiment, the first opening 261 is disposed corresponding to a group of thin film transistors, and the first opening 261 is located at a side of the scan line SL electrically connected to the gate of the group of thin film transistors, where is scanning On the upper side of the line SL, the gate of the group of thin film transistors is located on the other side of the scanning line SL to which it is electrically connected, here the lower side of the scanning line SL.

In the embodiment, the second insulating layer 270 is formed on the color resist layer 260 and the first insulating layer 250, and the second insulating layer 270 is filled into the first opening 261, thereby being in the first opening 261. The second insulating layer 270 is disposed adjacent to the first insulating layer 250. In this embodiment, the second insulating layer 270 is an inorganic insulating layer.

In this embodiment, the electrode layer is formed on the second insulating layer 270, the electrode layer includes a plurality of pixel electrodes, each pixel electrode is disposed corresponding to a group of thin film transistors, and each pixel electrode includes a main pixel electrode. 281 and the sub-pixel electrode 282. In this embodiment, the main pixel electrode 281 is located on the upper side of the scan line SL electrically connected to the set of thin film transistors, and the sub-pixel electrode 282 is electrically connected to the set of thin film transistors. The lower side of the scan line SL (see Figure 5). In this embodiment, the drain of the main thin film transistor TFT_m is electrically connected to the corresponding main pixel electrode 281, and the drain of the sub-thin film transistor TFT_s is electrically connected to the corresponding sub-pixel electrode 282, the shared thin film The drain of the transistor TFT_share is electrically connected to the corresponding sub-pixel electrode 282, and the source thereof is electrically connected to the common electrode line 222. In this embodiment, the drain of the sub-thin film transistor TFT_s is integrated with the drain of the shared thin film transistor TFT_share, and the drain of the sub-thin film transistor TFT_s and the shared thin film transistor TFT_share are in FIG. The drains are connected together by a large metal.

In order to realize the electrical connection between the main pixel electrode 281 and the drain of the main thin film transistor TFT_m, the source of the shared thin film transistor TFT_share is electrically connected to the common electrode line 222. In this embodiment, the first opening 261 is provided separately from each other. The first via 271 and the second via 272 pass through the first insulating layer 250 and the second insulating layer 270 to reach the drain of the main thin film transistor TFT_m, and the second via 272 penetrates the first The insulating layer 250, the second insulating layer 270, and the partial thin film transistor array substrate reach the common electrode line 222. Specifically, the second via 272 penetrates at least the first insulating layer 250, the second insulating layer 270, and the gate insulating layer 230, and The second via 272 is next to the source of the shared thin film transistor TFT_share. In this embodiment, the electrode layer further includes a first connection electrode 283 and a second connection electrode 284. The first connection electrode 283 is located in the first via 271 to connect the drain of the main thin film transistor TFT_m with the The main pixel electrode 281 is located in the second via 272 to connect the source of the shared thin film transistor TFT_share and the common electrode line 222. In this embodiment, the first connection electrode 283, the second connection electrode 284, the main pixel electrode 281, and the sub-pixel electrode 282 are formed of the same metal layer, and may be referred to herein as a third metal layer.

In the embodiment, the COA type array substrate further includes a pad high layer 262. In the embodiment, the pad high layer 262 and the data line are used to prevent the first connection electrode 283 and the second connection electrode 284 from being short-circuited. The DL is parallel, of course, in other embodiments of the invention the upper layer of the pad may also not be parallel to the data line. The pad high layer 262 at least raises the height of the second insulating layer 270 in the first opening 261 for improving the short circuit of the first connection electrode 283 and the second connection electrode 284. Therefore, since the pad high layer 262 raises the height of the second insulating layer 270 thereon, the third metal layer on both sides of the padned second insulating layer 270 can be blocked, so that the padded second insulating layer 270 can be prevented. The metal on both sides is short-circuited, so that the first connection electrode 283 and the second connection electrode 284 can be prevented from being short-circuited. Preferably, in the present embodiment, the projection upper layer 262 is located between the first connection electrode 283 and the second connection electrode 284 at a horizontal plane.

In the present embodiment, in the same group of thin film transistors, the common electrode line 222 electrically connected to the shared thin film transistor TFT_share is located on the side of the scan line SL electrically connected thereto away from the sub-pixel electrode 282, that is, the side away from the gate. In the present embodiment, the upper side of the scan line SL, and the common electrode line 222 and the scan line SL have a gap, and the first opening 261 extends from the upper direction of the common electrode line 222 to the scan line SL to a region between the common electrode line 222 and the scan line SL, that is, a region extending to a gap between the common electrode line 222 and the scan line SL, the projection of the common electrode line 222 and the first opening 261 at a horizontal plane is large Portions are overlapped, and the overlapped first opening 261 portion may be referred to as an opening first portion 261a, and the first opening 261 region located in the gap region between the common electrode line 222 and the scan line SL does not overlap with the common electrode line 222. The portion of the non-overlapping first opening 261 may be referred to as an opening second portion 261b, where the opening first portion 261a and the opening second portion 261b constitute a first opening 261, and the first portion 261 is opened in FIG. a is located at one end of the first opening 261 away from the scanning line SL, which is an upper end in the drawing, and the opening second portion 261b is located at one end of the first opening 261 near the scanning line SL, which is a lower end in the drawing. In the present embodiment, the first insulating layer 250, the gate insulating layer 230, and the common electrode line 222 are present under the opening first portion 261a. The second insulating layer 270 is present inside the opening first portion 261a, and below the opening second portion 261b. There is a first insulating layer 250, a gate insulating layer 230, and a second insulating layer 270 exists inside the opening second portion 261b. It can be seen that the lower second portion 261b of the opening has less common electrode lines 222 below the opening first portion 261a. The area of the opening second portion 261b is lower than the area of the opening first portion 261a. When the second insulating layer 270 is formed, the second insulating layer 270 in the opening second portion 261b has a lower potential than the opening first portion 261a. The topography of the second insulating layer 270 is in the lowest potential in the present embodiment in which the second insulating layer 270 in the opening second portion 261 is at the top potential. Thereafter, after depositing the third metal layer, subsequent exposure and development, due to the relatively low potential of the second insulating layer 270 in the second portion 261b of the opening, the photoresist exposure here is incomplete, resulting in the second portion of the opening. The photoresist above 261b has a high probability of residual, resulting in a large probability that the third metal layer under the photoresist will remain, resulting in the remaining third metal layer portion will be the first connection electrode 283 and The second connection electrode 284 is short-circuited. In this embodiment, the pad high layer 262 is formed by the color resist layer 260 extending toward the inside of the first opening 261. One of the first openings 261 has at least one pad high layer 262, which in this embodiment is a pad high layer 262. . Specifically, the pad high layer 262 is formed by extending a lower edge of the first opening 261 toward the inside of the first opening 261. Preferably, the pad high layer 262 is located at the first connection electrode 283 and the second connection electrode 284. Between the upper layer 262 and the color resist layer, the upper layer 262 of the pad is raised by the second insulating layer 270, so that the second portion 261b is opened in the second portion 261b. The second insulating layer 270 on the left side of the pad high layer 262 and the second insulating layer 270 on the right side of the pad high layer 262 are lower than the second insulating layer 270 above the pad high layer 262, so that even when the third metal layer is exposed and developed, even The presence of metal residue is also located on the left or right side of the upper layer 262 of the pad, and there is no upper layer 262 above the pad, thereby blocking the first connection electrode 283 on the left side of the pad high layer 262 and the second connection electrode 284 on the right side of the pad upper layer 262. Short circuit. Preferably, the pad high layer 262 is located at an intermediate position between the first connection electrode 283 and the second connection electrode 284, for example, at an intermediate position of the lower edge of the first opening. In this embodiment, the pad high-rise 262 may extend from the opening second portion 261b to the opening first portion 261a, and the end of the pad-up layer 262 extending inward overlaps the projection of the common electrode line 222 in the horizontal plane. Of course, the pad upper layer 262 may also not extend to the opening first portion 261a.

In addition, referring to FIG. 5, in order to realize the electrical connection between the sub-thin film transistor TFT_s and the sub-pixel electrode 282, in the embodiment, the first insulating layer 250, the color resist layer 260, and the second insulating layer 270 are provided. a third via 273, the electrode layer further includes a third connection electrode 285, the third connection electrode 285 being located in the third via 273 to connect the drain of the sub-thin film transistor TFT_s with the sub-pixel electrode 282, the shared film The drain of the transistor TFT_share and the sub-pixel electrode 282. In this embodiment, the portion of the third via 273 located in the color resist layer 260 and the portion of the third via 273 located in the first insulating layer 250 and the second insulating layer 270 may be formed in one process or may be divided into A plurality of steps are formed, and when formed in a plurality of steps, the portion of the third via 273 located in the color resist layer 260 at this time may be referred to as a second opening.

In addition, an embodiment of the present invention further provides a display panel, which includes the COA type array substrate described above. In addition, in an embodiment of the invention, the display panel further includes a filter substrate, the filter substrate is located above the COA type array substrate, and the filter substrate is provided with a common electrode. A liquid crystal layer is disposed between the COA type array substrate and the filter substrate. In this embodiment, the main pixel electrode and the common electrode on the filter substrate form a main liquid crystal capacitor, the main pixel electrode and the common electrode line form a main storage capacitor, and the sub-pixel electrode and the common electrode on the filter substrate form a sub-liquid crystal capacitor The sub-pixel electrode and the common electrode line form a secondary storage capacitor.

Second embodiment

7 is a schematic view of a COA type array substrate according to a second embodiment of the present invention. The schematic diagram of FIG. 7 is similar to the schematic diagram of FIG. 5, and thus the same component symbols represent the same components. The main difference between this embodiment and the first embodiment is the position of the upper layer of the pad.

Referring to FIG. 7 and FIG. 8 , in the embodiment, the material of the high-rise layer 362 is made of a metal material, and the high-rise layer 362 of the pad is located on the second metal layer, that is, the high-rise layer 362 of the pad is located on the same layer as the data line DL. And the data line DL is made of the same metal. In this embodiment, the pad high layer 362 is located below the first insulating layer 250, and the pad high layer 362 heights the height of a portion of the first insulating layer 250 and a portion of the second insulating layer 270 in the opening first portion 261a. The pad high layer 362 is located between the first connection electrode 283 and the second connection electrode 284. Also, since the first insulating layer 250 and the second insulating layer 270 on the pad high-rise 362 are padded, it is possible to prevent a short circuit between the first connection electrode 283 and the second connection electrode 284. In the present embodiment, in the projection of the horizontal plane, the pad high-rise 362 extends from the lower edge of the first opening 261 toward the inside of the first opening 261, and the projections of the pad high-rise 362 and the opening first portion 261a in the horizontal plane overlap. In addition, in this embodiment, in the projection of the horizontal plane, the pad high-rise 362 may further extend downward beyond the lower edge of the first opening 261, that is, the pad high-rise 362 further exists in the scanning line SL and the An area between openings 261.

It should be noted that the various embodiments in the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments are mutually referred to. can. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

Claims

A COA type array substrate, comprising:

A thin film transistor array substrate comprising:

a plurality of scan lines extending in a first direction;

a plurality of data lines extending in a second direction perpendicular to the first direction;

a plurality of common electrode lines for providing a common voltage, the common electrode lines being in the same metal layer as the scan lines;

a plurality of thin film transistors each comprising a main thin film transistor, a sub thin film transistor, and a shared thin film transistor;

a first insulating layer on the thin film transistor array substrate;

a color resist layer on the first insulating layer, wherein the color resist layer forms a plurality of first openings, each of the first openings extending from above the drain of the main thin film transistor to above the source of the shared thin film transistor ;

a second insulating layer formed on the color resist layer and the first insulating layer, and the second insulating layer is filled into the first opening;

An electrode layer formed on the second insulating layer, the electrode layer comprising a plurality of pixel electrodes, each pixel electrode being disposed corresponding to a group of thin film transistors, each of the pixel electrodes including a main pixel electrode and a sub-pixel electrode, the main film The drain of the transistor is electrically connected to the corresponding main pixel electrode, the drain of the sub-thin film transistor is electrically connected to the corresponding sub-pixel electrode, and the drain and the source of the shared thin film transistor are respectively corresponding to the corresponding a pixel electrode and a common electrode line are electrically connected; wherein

a first via hole and a second via hole separated from each other are disposed in the first opening, and the first via hole penetrates the first insulating layer and the second insulating layer to reach a drain of the main thin film transistor, the second pass The hole penetrates the first insulating layer, the second insulating layer, and the partial thin film transistor array substrate reaches the common electrode line, the electrode layer further includes a first connecting electrode and a second connecting electrode, wherein the first connecting electrode is located in the first via hole Connecting the drain of the main thin film transistor and the main pixel electrode, wherein the second connection electrode is located in the second via hole to connect the drain of the shared thin film transistor and the common electrode line; wherein the COA type array substrate further includes The upper layer of the pad, the pad upper layer at least raising the height of the second insulating layer in the first opening for preventing the first connection electrode and the second connection electrode from being short-circuited.
The COA type array substrate according to claim 1, wherein the upper layer of the pad is formed by extending a lower edge of the first opening toward the inside of the first opening, and the upper layer of the pad is integrally formed with the color resist layer.
The COA type array substrate according to claim 1, wherein the upper layer of the pad is in the same layer as the data line and is made of the same metal, and the projection of the pad in the horizontal plane is first from the lower edge of the first opening. The inside of the opening extends.
The COA type array substrate according to claim 1, wherein gates of the same group of thin film transistors are connected to a same scan line, and the scan lines are located between the main pixel electrode and the sub-pixel electrode, the first opening, the common The electrode line is located on a side of the scan line adjacent to the main pixel electrode, and the first opening extends from an upper direction of the common electrode line to a gap region between the common electrode line and the scan line.
The COA type array substrate according to claim 4, wherein the first opening comprises an opening first portion and an opening second portion, the opening first portion overlapping the common electrode line, and the opening second portion is The common electrode lines are staggered, and the second portion of the opening is located on the underside of the first portion of the opening, and the projection of the pad in the horizontal plane is at least partially located in the second portion of the opening.
The COA type array substrate of claim 5, wherein the projection of the horizontal plane extends inwardly into the first portion of the opening in a horizontal plane.
The COA type array substrate according to claim 2, wherein the gates of the same group of thin film transistors are connected to the same scan line, and the scan lines are located between the main pixel electrode and the sub-pixel electrode, the first opening, the common The electrode line is located on a side of the scan line adjacent to the main pixel electrode, and the first opening extends from an upper direction of the common electrode line to a gap region between the common electrode line and the scan line.
The COA type array substrate according to claim 3, wherein the gates of the same group of thin film transistors are connected to the same scan line, and the scan lines are located between the main pixel electrode and the sub-pixel electrode, the first opening, the common The electrode line is located on a side of the scan line adjacent to the main pixel electrode, and the first opening extends from an upper direction of the common electrode line to a gap region between the common electrode line and the scan line.
The COA type array substrate according to claim 1, wherein the projection of the pad in a horizontal plane is located between the first connection electrode and the second connection electrode.
The COA type array substrate according to claim 2, wherein the projection of the pad in a horizontal plane is located between the first connection electrode and the second connection electrode.
The COA type array substrate according to claim 3, wherein the projection of the pad in a horizontal plane is located between the first connection electrode and the second connection electrode.
The COA type array substrate according to claim 1, wherein a source of the main thin film transistor and a source of the sub-thin film transistor of the same group of thin film transistors are electrically connected to a same data line, a gate of the main thin film transistor The gate of the sub-thin film transistor and the gate of the shared thin film transistor are electrically connected to the same scan line.
The COA type array substrate according to claim 12, wherein the main thin film transistor and the sub-thin film transistor share the same source and share the same gate.
The COA type array substrate according to claim 2, wherein a source of the main thin film transistor and a source of the sub-thin film transistor of the same group of thin film transistors are electrically connected to a same data line, a gate of the main thin film transistor The gate of the sub-thin film transistor and the gate of the shared thin film transistor are electrically connected to the same scan line.
A display panel, comprising a COA type array substrate, the COA type array substrate comprising:

A thin film transistor array substrate comprising:

a plurality of scan lines extending in a first direction;

a plurality of data lines extending in a second direction perpendicular to the first direction;

a plurality of common electrode lines for providing a common voltage, the common electrode lines being in the same metal layer as the scan lines;

a plurality of thin film transistors each comprising a main thin film transistor, a sub thin film transistor, and a shared thin film transistor;

a first insulating layer on the thin film transistor array substrate;

a color resist layer on the first insulating layer, wherein the color resist layer forms a plurality of first openings, each of the first openings extending from above the drain of the main thin film transistor to above the source of the shared thin film transistor ;

a second insulating layer formed on the color resist layer and the first insulating layer, and the second insulating layer is filled into the first opening;

An electrode layer formed on the second insulating layer, the electrode layer comprising a plurality of pixel electrodes, each pixel electrode being disposed corresponding to a group of thin film transistors, each of the pixel electrodes including a main pixel electrode and a sub-pixel electrode, the main film The drain of the transistor is electrically connected to the corresponding main pixel electrode, the drain of the sub-thin film transistor is electrically connected to the corresponding sub-pixel electrode, and the drain and the source of the shared thin film transistor are respectively corresponding to the corresponding a pixel electrode and a common electrode line are electrically connected; wherein

a first via hole and a second via hole separated from each other are disposed in the first opening, and the first via hole penetrates the first insulating layer and the second insulating layer to reach a drain of the main thin film transistor, the second pass The hole penetrates the first insulating layer, the second insulating layer, and the partial thin film transistor array substrate reaches the common electrode line, the electrode layer further includes a first connecting electrode and a second connecting electrode, wherein the first connecting electrode is located in the first via hole Connecting the drain of the main thin film transistor and the main pixel electrode, wherein the second connection electrode is located in the second via hole to connect the drain of the shared thin film transistor and the common electrode line; wherein the COA type array substrate further includes The upper layer of the pad, the pad upper layer at least raising the height of the second insulating layer in the first opening for preventing the first connection electrode and the second connection electrode from being short-circuited.
The display panel according to claim 15, wherein the upper layer of the pad is formed by extending a lower edge of the first opening toward the inside of the first opening, and the upper layer of the pad is integrally formed with the color resist layer.
The display panel according to claim 15, wherein said upper layer of said pad is in the same layer as said data line and is made of the same metal, and projection of said high layer on said horizontal surface from said lower edge of said first opening to said first opening extend.
The display panel according to claim 15, wherein the gates of the same group of thin film transistors are connected to the same scan line, and the scan lines are located between the main pixel electrode and the sub-pixel electrode, the first opening and the common electrode line. Located at a side of the scan line adjacent to the main pixel electrode, the first opening extends from a direction of the upper direction of the common electrode line to a gap region between the common electrode line and the scan line.
The display panel according to claim 15, wherein the projection of the pad in a horizontal plane is located between the first connection electrode and the second connection electrode.
The display panel according to claim 15, wherein the source of the main thin film transistor and the source of the sub-thin film transistor of the same group of thin film transistors are electrically connected to the same data line, the gate of the main thin film transistor, The gate of the thin film transistor and the gate of the shared thin film transistor are electrically connected to the same scan line.