WO2019127537A1 - 宽频带低相噪频综电路及电子设备 - Google Patents

宽频带低相噪频综电路及电子设备 Download PDF

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Publication number
WO2019127537A1
WO2019127537A1 PCT/CN2017/120272 CN2017120272W WO2019127537A1 WO 2019127537 A1 WO2019127537 A1 WO 2019127537A1 CN 2017120272 W CN2017120272 W CN 2017120272W WO 2019127537 A1 WO2019127537 A1 WO 2019127537A1
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circuit
frequency
capacitor
oscillating
phase
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PCT/CN2017/120272
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English (en)
French (fr)
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胡孔一
崔建伟
覃志华
孙建平
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海能达通信股份有限公司
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Priority to PCT/CN2017/120272 priority Critical patent/WO2019127537A1/zh
Publication of WO2019127537A1 publication Critical patent/WO2019127537A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a broadband low phase noise frequency synthesizing circuit and an electronic device.
  • the phase-locked loop technology is applied in the communication system to generate a variable local oscillator signal or a circuit clock signal.
  • the phase-locked loop technology has lower spurs and higher harmonic rejection than the frequency multiplication/mixing technique, and works more than direct digital frequency synthesis technology. It has high frequency, low power consumption, flexible application and wide frequency range, and is widely used in RF communication systems, becoming the mainstream frequency synthesis technology.
  • a phase-locked loop chip is used to carry a passive loop filter to obtain low phase noise, good loop stability, and low cost, but the synthesized frequency band is limited by the output pump voltage of the phase-locked loop chip, and a wide-band frequency output cannot be obtained. Therefore, it can only be applied to narrowband communication systems.
  • Wideband frequency synthesis often uses an active loop filter scheme to achieve wide coverage bandwidth, that is, the op amp circuit is used to amplify the pump voltage of the phase-locked loop chip to improve the tuning voltage range of the voltage-controlled oscillator, but the active loop filter will Introducing additional noise to deteriorate the phase noise of the frequency synthesizer circuit.
  • the low noise and high tuning voltage voltage controlled oscillator is difficult to obtain, the PCB area is increased, and the cost is high. Therefore, it can only be applied to a fixed communication system with low broadband phase noise requirements.
  • Low-noise, wide-band frequency integrated circuits for broadband private network communication systems have become a strong demand in the industry.
  • the technical problem to be solved by the present invention is to provide a broadband low phase noise frequency synthesizing circuit and an electronic device to meet the requirements of a broadband private network communication system.
  • a technical solution adopted by the present invention is to provide a broadband low phase noise frequency synthesizing circuit, and the frequency synthesizing circuit includes:
  • An oscillating circuit connected to the back end circuit, for outputting a first oscillating frequency and a second oscillating frequency different from the first oscillating frequency to the back end circuit;
  • a feedback circuit connected to the oscillating circuit, for feeding back the first oscillating frequency and the second oscillating frequency output by the oscillating circuit to the phase detecting circuit;
  • the phase-detecting circuit is connected to the feedback circuit for storing a reference frequency and receiving the first oscillating frequency and the second oscillating frequency from the feedback circuit, and the first oscillating frequency or the Comparing the second oscillation frequency with the reference frequency, outputting an adjustment signal when the first oscillation frequency or the second oscillation frequency does not coincide with the reference frequency; at the first oscillation frequency or the second Outputting a lock signal when the oscillation frequency is consistent with the reference frequency; and
  • a loop filter circuit connected to the phase discriminating circuit and the oscillating circuit, configured to receive the adjustment signal from the phase phasing circuit and convert the signal into a voltage signal, and then provide the oscillating circuit to adjust the oscillating circuit output
  • the first oscillation frequency or the second oscillation frequency the loop filter circuit further receives the phase lock signal from the phase discrimination circuit and converts it into a voltage signal, and then supplies the signal to the oscillation circuit to control the oscillation
  • the circuit outputs the first oscillating frequency or the second oscillating frequency to a back end circuit.
  • an electronic device which includes a broadband low phase noise frequency synthesizing circuit, and the frequency synthesizing circuit includes:
  • An oscillating circuit connected to the back end circuit, for outputting a first oscillating frequency and a second oscillating frequency different from the first oscillating frequency to the back end circuit;
  • a feedback circuit connected to the oscillating circuit, for feeding back the first oscillating frequency and the second oscillating frequency output by the oscillating circuit to the phase detecting circuit;
  • the phase-detecting circuit is connected to the feedback circuit for storing a reference frequency and receiving the first oscillating frequency and the second oscillating frequency from the feedback circuit, and the first oscillating frequency or the Comparing the second oscillation frequency with the reference frequency, outputting an adjustment signal when the first oscillation frequency or the second oscillation frequency does not coincide with the reference frequency; at the first oscillation frequency or the second Outputting a lock signal when the oscillation frequency is consistent with the reference frequency; and
  • a loop filter circuit connected to the phase discriminating circuit and the oscillating circuit, configured to receive the adjustment signal from the phase phasing circuit and convert the signal into a voltage signal, and then provide the oscillating circuit to adjust the oscillating circuit output
  • the first oscillation frequency or the second oscillation frequency the loop filter circuit further receives the phase lock signal from the phase discrimination circuit and converts it into a voltage signal, and then supplies the signal to the oscillation circuit to control the oscillation
  • the circuit outputs the first oscillating frequency or the second oscillating frequency to a back end circuit.
  • the broadband low phase noise frequency synthesizing circuit of the present invention outputs a first oscillation frequency and a second different from the first oscillation frequency by the oscillation circuit.
  • the loop filter circuit controls the oscillating circuit to achieve broadband low phase noise to meet the requirements of a broadband private network communication system.
  • 1 is a circuit diagram of a conventional frequency synthesizing circuit
  • FIG. 2 is a circuit diagram of a broadband low phase noise frequency synthesizing circuit of the present invention
  • Figure 3 is a circuit diagram of the oscillation circuit of Figure 2;
  • Figure 4 is an equivalent circuit diagram of Figure 3;
  • FIG. 5 is a schematic diagram of simulation waveforms of the broadband low phase noise frequency synthesizing circuit of the present invention.
  • Fig. 6 is a schematic structural view of an electronic device of the present invention.
  • FIG. 1 is a circuit diagram of a conventional frequency synthesizer circuit. It can be seen from FIG. 1 that the prior art realizes wide-band coverage by adopting an active loop filter to increase the range of the control voltage CV, specifically, the mainstream pump voltage using the phase-locked loop chip pin CP generally does not exceed 5V, and adopts low noise.
  • the op amp and the RC network form a loop to achieve voltage amplification, which is provided to the high-tuning voltage-controlled oscillator for broadband purposes.
  • the working principle is to use a low-noise op amp to amplify the phase error signal output from the phase detector and improve the tuning voltage range.
  • FIG. 2 and FIG. 3 are circuit diagrams of the broadband low phase noise frequency synthesizing circuit of the present invention.
  • the frequency synthesizing circuit includes an oscillating circuit 10, and is connected to the back end circuit 20 for outputting a first oscillating frequency f1 and a second oscillating frequency f2 different from the first oscillating frequency f1 to the back end circuit 20;
  • the feedback circuit 30 is connected to the oscillating circuit 10 for feeding back the first oscillating frequency f1 and the second oscillating frequency f2 outputted by the oscillating circuit 10 to the phase detecting circuit 40;
  • the phase-detecting circuit 40 is connected to the feedback circuit 30 for storing a reference frequency f and receiving the first oscillation frequency f1 and the second oscillation frequency f2 from the feedback circuit 30, and the An oscillation frequency f1 or the second oscillation frequency f2 is compared with the reference frequency f, and when the first oscillation frequency f1 or the second oscillation frequency f2 does not coincide with the reference frequency f, an adjustment signal is output; Outputting a lock signal when the first oscillation frequency f1 or the second oscillation frequency f2 coincides with the reference frequency f;
  • the loop filter circuit 50 is connected to the phase discriminating circuit 40 and the oscillating circuit 10 for receiving the adjustment signal from the phase acknowledging circuit 40 and converting it into a voltage signal, and then providing the oscillating circuit 10 to adjust The first oscillating frequency f1 or the second oscillating frequency f2 output by the oscillating circuit 10, the loop filter circuit 50 further receives the phase lock signal from the phase acknowledging circuit 40 and converts it into a voltage signal and supplies it to the
  • the oscillating circuit 10 controls the oscillating circuit 10 to output the first oscillating frequency f1 or the second oscillating frequency f2 to the back end circuit 20.
  • the phase-detecting circuit 40 is a phase-detecting loop chip 41, and the feedback circuit 30 is a low-pass filter.
  • the first oscillating frequency f1 output by the oscillating circuit 10 is smaller than the second oscillating frequency f2, and The tuning voltage of the oscillating circuit 10 does not exceed the pump voltage of the phase sensing chip.
  • the oscillating circuit 10 includes a first varactor diode VC1 and a second varactor diode VC2, first to fourth capacitors C1-C4, a switching diode D1, a first inductor L1, and a second inductor L2, and a controllable switch.
  • the cathode of the first varactor VC1 is connected to the cathode of the second varactor VC2 and the loop filter circuit 50, the anode of the second varactor VC2 Grounding, the anode of the first varactor diode VC1 is grounded via the first inductor L1, and the anode of the first varactor diode VC1 is further connected to the switch via the first capacitor C1 and the switching capacitor Cs.
  • An anode of the diode D1, a cathode of the switching diode D1 is grounded, a first end of the second inductor L2 is connected to a node between the first capacitor C1 and the switching capacitor Cs, and the second inductor L2 The second end is grounded, and the first end of the second inductor L2 is sequentially grounded through the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, and the control end of the controllable switch T1 is connected.
  • a section between the second capacitor C2 and the third capacitor C3 Said controllable switch T1 via a first end of the load resistor RL is grounded, the controllable switch T1 is connected to a second end of the third capacitor between the node and the fourth capacitor C4 C3.
  • the loop filter circuit 50 includes fifth to seventh capacitors C5-C7, a third inductor L3, and a fourth inductor L4, and the first end of the fifth capacitor C5 is connected to the phase-sensing ring chip 41.
  • a first pin 1 a second end of the fifth capacitor C5 is grounded, and a first end of the fifth capacitor C5 is grounded through the third inductor L3 and the sixth capacitor C6 in sequence, the fifth capacitor
  • the first end of C5 is also grounded through the fourth inductor L4 and the seventh capacitor C7 in sequence, and the node between the fourth inductor L4 and the seventh capacitor C7 is connected to the oscillating circuit 10.
  • the broadband low phase noise frequency synthesizing circuit uses a passive loop filter circuit to have no amplification function for the pump voltage outputted by the phase detector circuit, that is, the control voltage range of the oscillation circuit 10 is affected by the phase detection loop chip 41 of the phase discrimination circuit 40.
  • the voltage is limited, and is lower than the pump voltage range of the phase-detecting loop chip 41.
  • the passive loop filter circuit cannot widen the control voltage range, but has good noise performance, application frequency bandwidth, easy implementation, high reliability, etc. The system is widely used.
  • the wideband low phase noise frequency synthesizing circuit uses a low control voltage range wideband oscillating circuit, and the oscillating circuit 10 has two working modes, a high frequency working mode and a low frequency working mode, and the tuning voltage range of each mode is not Exceeding the pump voltage of the phase-detecting loop chip 41 of the phase-detecting circuit 40, the two modes are freely switched by the switching diode D1, and when the switching diode D1 is turned off, the oscillation circuit 10 outputs the operation of the first mode.
  • the frequency that is, the first oscillation frequency f1
  • the oscillation circuit 10 outputs the operating frequency of the second medium mode, that is, the second oscillation frequency f2, thereby achieving the broadband purpose. Since the other active devices are not introduced, the phase noise of the wideband low phase noise frequency synthesizing circuit is very low, and the locking time is narrower than the active loop filter circuit, which can satisfy the wideband private network.
  • FIG. 4 is an equivalent circuit diagram of an oscillation circuit of the broadband low phase noise frequency synthesizing circuit of the present invention.
  • the wideband low phase noise frequency synthesizing circuit of the present invention uses a switching diode D1 to change the core parameters of the oscillating circuit 10 to achieve frequency conversion.
  • the switching diode D1 is turned off, the The switching capacitor Cs is not connected to the oscillating circuit 10, and the oscillating circuit 10 outputs the first oscillating frequency f1, and the first oscillating frequency f1 satisfies the formula:
  • the oscillating circuit 10 outputs the first oscillating frequency f1 and the second oscillating frequency f2 of different frequencies to achieve the effect of widening the frequency band.
  • C1, C2, C3, and C4 are respectively a capacitance value of the first capacitor C1, a capacitance value of the second capacitor C2, a capacitance value of the third capacitor C3, and a capacitance value of the fourth capacitor C4.
  • L is the inductance value of the second inductor L2
  • CT is the capacitance value of the tuning capacitor
  • Cs is the capacitance value of the switching capacitor. It can be seen from the above formula that Cs is a fixed constant and does not change the trend between the oscillation frequency f and the tuning capacitance CT, that is, Cs only changes the initial point of the oscillation frequency without changing the trend, that is, there are two different modes. , high frequency mode and low frequency mode or high frequency state and low frequency state.
  • FIG. 5 is a schematic diagram of simulation waveforms of the broadband low phase noise frequency synthesizing circuit of the present invention.
  • the EDA simulation software ADS is used to simulate the oscillation circuit.
  • the simulation results show that the oscillation circuit has two working states, high frequency state and low frequency state, and the control voltage CV curve and voltage control sensitivity KV curve of the two states have the same trend.
  • the frequency synthesis is greater than 50%, and the frequency range of the low frequency mode changes due to the value of the switching capacitor Cs.
  • the larger the value of the Cs connected to the switching capacitor the low frequency mode
  • the less overlapping frequency with the high frequency mode, even without overlap, the frequency coverage of the oscillating circuit is the high frequency mode coverage frequency range plus the low frequency frequency coverage minus the overlap range.
  • FIG. 6 is a schematic structural diagram of an electronic device of the present invention.
  • the electronic device includes the above-mentioned broadband low phase noise frequency synthesizing circuit, and the electronic device is a terminal product, and other devices and functions in the electronic device are the same as those of the existing electronic device, and Let me repeat.
  • the radio frequency bandwidth of the electronic device is 320MHz-475MHz, covering 155MHz bandwidth
  • the frequency generation circuit index reaches the index requirement
  • the intermediate frequency is 73.35MHz
  • the receiving frequency generating circuit covers the frequency range of 393.35MHz-548.35MHz, and the relative bandwidth.
  • the program reached the design goal, as shown in Table 1:
  • the data in Table 2 below shows that the two modes of the wideband low phase noise synthesizing circuit, namely the low frequency mode and the high frequency mode, complete 33% frequency coverage within the control voltage CV range of 0.8-3.8V, and The two modes have good consistency.
  • the control voltage CV tuning range of both modes is within 0.8-3.8V, and the open-loop phase noise index is ⁇ -128dBc/Hz@50K ⁇ -140dBc/Hz@200k ⁇ -155dBc/Hz@ 1M, meet the requirements of open-loop established indicators, the closed-loop control voltage CV range is 0.8-3.8V, the full-band phase noise index ⁇ -127dBc/Hz@50K ⁇ -140dBc/Hz@200k ⁇ -155dBc/Hz@1M, as specified As shown in Tables 3 and 4, the machine is evaluated according to the requirements of the established indicators.
  • the broadband low phase noise frequency synthesizing circuit outputs a first oscillation frequency and a second oscillation frequency different from the first oscillation frequency by the oscillation circuit, and the first and second oscillations are performed by the feedback circuit a frequency is provided to the phase discrimination circuit, the phase discrimination circuit is configured to control the oscillation circuit by the loop filter circuit according to the comparison of the first and second oscillation frequencies with a reference frequency, thereby implementing a broadband low phase
  • the purpose of noise is to meet the needs of broadband private network communication systems.

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Abstract

一种宽频带低相噪频综电路及电子设备。频综电路包括振荡电路（10）输出第一及第二振荡频率；反馈电路（30）将第一及第二振荡频率反馈给鉴相电路（40）；鉴相电路（40）将第一或第二振荡频率与参考频率进行比较，在不一致时，输出调整信号；在一致时，输出锁定信号；环路滤波电路（50）将调整信号转换为电压信号后提供给振荡电路（10），以调整第一或第二振荡频率，还将锁相信号转换为电压信号后提供给振荡电路（10），以控制第一或第二振荡频率输出给后端电路（20）。

Description

宽频带低相噪频综电路及电子设备 【技术领域】
本发明涉及通信技术领域，特别是涉及一种宽频带低相噪频综电路及电子设备。
【背景技术】
锁相环技术应用在通信系统中，可产生可变本振信号或电路时钟信号，锁相环技术较倍频/混频技术具有低杂散、谐波抑制高，较直接数字频率合成技术工作频率高、功耗低，且应用灵活方便、频率范围宽，而被广泛应用于射频通信系统中，成为主流的频率合成技术。通常采用锁相环芯片搭载无源环路滤波器可获得较低的相位噪声、环路稳定性好、成本低，但合成频带受锁相环芯片输出泵电压限制，不能获得宽频带频率输出，因此只能应用于窄带通信系统。宽带频率合成常采用有源环路滤波器方案来实现拓宽覆盖带宽，即采用运放电路放大锁相环芯片的泵电压，提高压控振荡器的调谐电压范围，但是有源环路滤波器会引入额外噪声而恶化频综电路的相位噪声，此外低噪声高调谐电压压控振荡器不易获取、PCB面积增加、成本高，因此只能适用于宽频带相噪要求较低的固定通信系统，目前应用于宽频带专网通信系统的低噪声、宽频带频率综合电路已成为业界的强烈需求。
【发明内容】
本发明主要解决的技术问题是提供一种宽频带低相噪频综电路及电子设备，以满足宽频带专网通信系统的需求。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种宽频带低相噪频综电路，所述频综电路包括：
振荡电路，连接后端电路，用于输出第一振荡频率及与所述第一振荡频率不同的第二振荡频率给所述后端电路；
反馈电路，连接所述振荡电路，用于将所述振荡电路输出的第一振荡频率及第二振荡频率反馈给鉴相电路；
所述鉴相电路，连接所述反馈电路，用于存储一参考频率及从所述反馈电 路接收所述第一振荡频率及所述第二振荡频率，并将所述第一振荡频率或所述第二振荡频率与所述参考频率进行比较，在所述第一振荡频率或所述第二振荡频率与所述参考频率不一致时，输出调整信号；在所述第一振荡频率或所述第二振荡频率与所述参考频率一致时，输出锁定信号；及
环路滤波电路，连接所述鉴相电路及所述振荡电路，用于从所述鉴相电路接收所述调整信号并转换为电压信号后提供给所述振荡电路，以调整所述振荡电路输出的第一振荡频率或所述第二振荡频率，所述环路滤波电路还从所述鉴相电路接收所述锁相信号并转换为电压信号后提供给所述振荡电路，以控制所述振荡电路将所述第一振荡频率或所述第二振荡频率输出给后端电路。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种电子设备，所述电子设备包括宽频带低相噪频综电路，所述频综电路包括：
振荡电路，连接后端电路，用于输出第一振荡频率及与所述第一振荡频率不同的第二振荡频率给所述后端电路；
反馈电路，连接所述振荡电路，用于将所述振荡电路输出的第一振荡频率及第二振荡频率反馈给鉴相电路；
所述鉴相电路，连接所述反馈电路，用于存储一参考频率及从所述反馈电路接收所述第一振荡频率及所述第二振荡频率，并将所述第一振荡频率或所述第二振荡频率与所述参考频率进行比较，在所述第一振荡频率或所述第二振荡频率与所述参考频率不一致时，输出调整信号；在所述第一振荡频率或所述第二振荡频率与所述参考频率一致时，输出锁定信号；及
环路滤波电路，连接所述鉴相电路及所述振荡电路，用于从所述鉴相电路接收所述调整信号并转换为电压信号后提供给所述振荡电路，以调整所述振荡电路输出的第一振荡频率或所述第二振荡频率，所述环路滤波电路还从所述鉴相电路接收所述锁相信号并转换为电压信号后提供给所述振荡电路，以控制所述振荡电路将所述第一振荡频率或所述第二振荡频率输出给后端电路。
本发明的有益效果是：区别于现有技术的情况，本发明的所述宽频带低相噪频综电路通过所述振荡电路输出第一振荡频率及与所述第一振荡频率不同的第二振荡频率，并通过所述反馈电路将所述第一及第二振荡频率提供给所述鉴相电路，所述鉴相电路根据所述第一及第二振荡频率与参考频率的比较以通过所述环路滤波电路控制所述振荡电路，以此实现宽频带低相噪的目的，以满足宽频带专网通信系统的需求。
【附图说明】
图1是现有的频综电路的电路示意图；
图2是本发明宽频带低相噪频综电路的电路示意图；
图3是图2中的振荡电路的电路示意图；
图4是图3的等效电路图；
图5是本发明的宽频带低相噪频综电路的仿真波形示意图；
图6是本发明电子设备的结构示意图。
【具体实施方式】
请参阅图1，是现有的频综电路的电路示意图。从图1中可以看出现有技术实现宽频覆盖通过采用有源环路滤波器来提升控制电压CV的范围，具体为利用锁相环芯片引脚CP的主流泵电压一般不超过5V，采用低噪声运放与RC网络构成环路实现电压放大，提供给高调谐压控振荡器以实现宽频带目的，其工作原理为采用低噪声运放来放大鉴相器输出的相位误差信号，提升调谐电压范围，并通过接入高调谐电压及低噪声的压控振荡器达到宽频带频率合成的效果，然而由运放和RC网络构成的有源环路滤波器会引入额外噪声，为了降低噪声，一般采用低噪声运放，但是低噪声运放价格昂贵，而且运放提高了压控振荡器的调谐电压范围，导致低频端与高频端压差扩大，跳频锁定时间会增加，因此还需要使用低相噪高调谐的压控振荡器，因为有源运放供电电压高于调谐电压，因此手持设备要实现宽频带需要额外设计电源升压电路及外围电路，这些将使得电路设计复杂、占用空间、增加成本，而且降低了频综系统的可靠性。
请参阅图2及图3，是本发明的宽频带低相噪频综电路的电路示意图。所述频综电路包括振荡电路10，连接后端电路20，用于输出第一振荡频率f1及与所述第一振荡频率f1不同的第二振荡频率f2给所述后端电路20；
反馈电路30，连接所述振荡电路10，用于将所述振荡电路10输出的第一振荡频率f1及第二振荡频率f2反馈给鉴相电路40；
所述鉴相电路40，连接所述反馈电路30，用于存储一参考频率f及从所述反馈电路30接收所述第一振荡频率f1及所述第二振荡频率f2，并将所述第一振荡频率f1或所述第二振荡频率f2与所述参考频率f进行比较，在所述第一振荡频率f1或所述第二振荡频率f2与所述参考频率f不一致时，输出调整信号；在 所述第一振荡频率f1或所述第二振荡频率f2与所述参考频率f一致时，输出锁定信号；及
环路滤波电路50，连接所述鉴相电路40及所述振荡电路10，用于从所述鉴相电路40接收所述调整信号并转换为电压信号后提供给所述振荡电路10，以调整所述振荡电路10输出的第一振荡频率f1或所述第二振荡频率f2，所述环路滤波电路50还从所述鉴相电路40接收所述锁相信号并转换为电压信号后提供给所述振荡电路10，以控制所述振荡电路10将所述第一振荡频率f1或所述第二振荡频率f2输出给后端电路20。
其中，所述鉴相电路40为一鉴相环芯片41，所述反馈电路30为一低通滤波器，所述振荡电路10输出的第一振荡频率f1小于所述第二振荡频率f2，且所述振荡电路10的调谐电压不超过所述鉴相芯片的泵电压。
具体地，所述振荡电路10包括第一变容二极管VC1及第二变容二极管VC2、第一至第四电容C1-C4、切换二极管D1、第一电感L1及第二电感L2、可控开关T1、切换电容Cs及负载电阻RL，所述第一变容二极管VC1的阴极连接所述第二变容二极管VC2的阴极及所述环路滤波电路50，所述第二变容二极管VC2的阳极接地，所述第一变容二极管VC1的阳极经所述第一电感L1接地，所述第一变容二极管VC1的阳极还依次经所述第一电容C1及所述切换电容Cs连接所述切换二极管D1的阳极，所述切换二极管D1的阴极接地，所述第二电感L2的第一端连接在所述第一电容C1与所述切换电容Cs之间的节点，所述第二电感L2的第二端接地，所述第二电感L2的第一端还依次经过所述第二电容C2、所述第三电容C3及所述第四电容C4接地，所述可控开关T1的控制端连接在所述第二电容C2与所述第三电容C3之间的节点，所述可控开关T1的第一端经所述负载电阻RL接地，所述可控开关T1的第二端连接在所述第三电容C3与所述第四电容C4之间的节点。
具体地，所述环路滤波电路50包括第五至第七电容C5-C7、第三电感L3及第四电感L4，所述第五电容C5的第一端连接所述鉴相环芯片41的第一引脚1，所述第五电容C5的第二端接地，所述第五电容C5的第一端依次经所述第三电感L3及所述第六电容C6接地，所述第五电容C5的第一端还依次经所述第四电感L4及所述第七电容C7接地，所述第四电感L4与所述第七电容C7之间的节点连接所述振荡电路10。
所述宽频带低相噪频综电路使用无源环路滤波电路对鉴相电路输出的泵电 压没有放大功能，即所述振荡电路10的控制电压范围受鉴相电路40中鉴相环芯片41电压限制，且低于鉴相环芯片41的泵电压范围，无源环路滤波电路虽不能拓宽控制电压范围，但是具有良好的噪声性能、应用频带宽、易实现、可靠性高等优势，被窄带系统广泛应用。所述宽频带低相噪频综电路使用低控制电压范围宽频带振荡电路，所述振荡电路10存在两种工作模式，高频工作模式与低频工作模式，且每个模式的调谐电压范围均不超过所述鉴相电路40的鉴相环芯片41的泵电压，两种模式通过所述切换二极管D1自由切换，当所述切换二极管D1截止时，所述振荡电路10输出第一种模式的工作频率，即第一振荡频率f1，当所述切换二极管D1导通时，所述振荡电路10输出第二中模式的工作频率，即第二振荡频率f2，以此实现宽频带目的。因没有引入其他有源器件，因此所述宽频带低相噪频综电路的相位噪声非常低，因调谐电压范围窄，锁定时间较有源环路滤波电路具有突出优势，能够满足宽频带专网通信系统的需求。
请参阅图4，是本发明的宽频带低相噪频综电路的振荡电路的等效电路图。根据图2至图4可以得出本发明宽频带低相噪频综电路使用了一个切换二极管D1改变所述振荡电路10的核心参数实现了频率转换，当所述切换二极管D1截止时，所述切换电容Cs未接入所述振荡电路10，所述振荡电路10输出所述第一振荡频率f1，所述第一振荡频率f1满足公式：
Figure PCTCN2017120272-appb-000001
当所述切换二极管D1导通时，所述切换电容Cs接入所述振荡电路10，所述振荡电路10输出第二振荡频率f2，所述第二振荡频率f2满足公式：
Figure PCTCN2017120272-appb-000002
所述振荡电路10输出不同频率的所述第一振荡频率f1及所述第二振荡频率f2，实现了拓宽频带的效果。
其中，C1、C2、C3、C4分别为所述第一电容C1的电容值、所述第二电容C2的电容值、所述第三电容C3的电容值及所述第四电容C4的电容值，L为所述第二电感L2的电感值，CT为调谐电容的电容值，Cs为所述切换电容的电容值。从上述公式中可以看出，Cs为固定常数，不改变振荡频率f与调谐电容CT 之间的变化趋势，即Cs只改变振荡频率的初始点而不改变变化趋势，即存在两种不同的模式，高频模式与低频模式或高频状态与低频状态。
请参阅图5，是本发明的宽频带低相噪频综电路的仿真波形示意图。采用EDA仿真软件ADS对振荡电路进行仿真，仿真结果表明，所述振荡电路存在两种工作状态，高频状态与低频状态，且两种状态的控制电压CV曲线及压控灵敏度KV曲线变化趋势相同，在所述控制电压范围0-5V内，实现带宽大于50％频率合成，低频模式频率范围因接入所述切换电容Cs的值而变化，接入所述切换电容Cs值越大，低频模式与高频模式的重叠频率越少，甚至可以无重叠，所述振荡电路的频率覆盖范围为高频模式覆盖频率范围加上低频频率覆盖范围减去重叠范围。
请参阅图6，是本发明的电子设备的结构示意图。其中，所述电子设备包括上述的宽频带低相噪频综电路，所述电子设备为终端产品，所述电子设备中的其他器件及功能与现有电子设备的器件及功能相同，在此不再赘述。
将所述宽频带低相噪频综电路应用在所述电子设备中，并对所述电子设备进行整机评估，验证了所述电子设备能够满足对频综电路的指标要求。具体描述如下：所述电子设备的射频带宽为320MHz-475MHz，覆盖155MHz带宽，频率产生电路指标达成指标要求，中频为73.35MHz，故接收频率产生电路覆盖频率范围为393.35MHz-548.35MHz，相对带宽约33％，方案达成设计目标，如表1所示：
Figure PCTCN2017120272-appb-000003
表1
下面表2的数据表明，所述宽频带低相噪频综电路的两个模式，即低频模式与高频模式，在所述控制电压CV范围0.8-3.8V内，完成33％频率覆盖，且两种模式一致性较好，两种模式的控制电压CV调谐范围均在0.8-3.8V内，开环相噪指标<-128dBc/Hz@50K<-140dBc/Hz@200k<-155dBc/Hz@1M，满足开环既定指标要求，闭环后控制电压CV范围为0.8-3.8V，全频段相噪指标 <-127dBc/Hz@50K<-140dBc/Hz@200k<-155dBc/Hz@1M，具体如表3及表4所示，满足既定指标要求，整机完成评估。
Figure PCTCN2017120272-appb-000004
表2
Figure PCTCN2017120272-appb-000005
表3
Figure PCTCN2017120272-appb-000006
表4
所述宽频带低相噪频综电路通过所述振荡电路输出第一振荡频率及与所述 第一振荡频率不同的第二振荡频率，并通过所述反馈电路将所述第一及第二振荡频率提供给所述鉴相电路，所述鉴相电路根据所述第一及第二振荡频率与参考频率的比较以通过所述环路滤波电路控制所述振荡电路，以此实现宽频带低相噪的目的，以满足宽频带专网通信系统的需求。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种宽频带低相噪频综电路，其中，所述频综电路包括：
    振荡电路，连接后端电路，用于输出第一振荡频率及与所述第一振荡频率不同的第二振荡频率给所述后端电路；
    反馈电路，连接所述振荡电路，用于将所述振荡电路输出的第一振荡频率及第二振荡频率反馈给鉴相电路；
    所述鉴相电路，连接所述反馈电路，用于存储一参考频率及从所述反馈电路接收所述第一振荡频率及所述第二振荡频率，并将所述第一振荡频率或所述第二振荡频率与所述参考频率进行比较，在所述第一振荡频率或所述第二振荡频率与所述参考频率不一致时，输出调整信号；在所述第一振荡频率或所述第二振荡频率与所述参考频率一致时，输出锁定信号；及
    环路滤波电路，连接所述鉴相电路及所述振荡电路，用于从所述鉴相电路接收所述调整信号并转换为电压信号后提供给所述振荡电路，以调整所述振荡电路输出的第一振荡频率或所述第二振荡频率，所述环路滤波电路还从所述鉴相电路接收所述锁相信号并转换为电压信号后提供给所述振荡电路，以控制所述振荡电路将所述第一振荡频率或所述第二振荡频率输出给后端电路。
  2. 根据权利要求1所述的宽频带低相噪频综电路，其中，所述鉴相电路为一鉴相环芯片，所述反馈电路为一低通滤波器，所述振荡电路输出的第一振荡频率小于所述第二振荡频率，且所述振荡电路的调谐电压不超过所述鉴相芯片的泵电压。
  3. 根据权利要求2所述的宽频带低相噪频综电路，其中，所述振荡电路包括第一及第二变容二极管、第一至第四电容、切换二极管、第一及第二电感、可控开关、切换电容及负载电阻，所述第一变容二极管的阴极连接所述第二变容二极管的阴极及所述环路滤波电路，所述第二变容二极管的阳极接地，所述第一变容二极管的阳极经所述第一电感接地，所述第一变容二极管的阳极还依次经所述第一电容及所述切换电容连接所述切换二极管的阳极，所述切换二极管的阴极接地，所述第二电感的第一端连接在所述第一电容与所述切换电容之间的节点，所述第二电感的第二端接地，所述第二电感的第一端还依次经过所述第二电容、所述第三电容及所述第四电容接地，所述可控开关的控制端连接在所述第二电容与所述第三电容之间的节点，所述可控开关的第一端经所述负 载电阻接地，所述可控开关的第二端连接在所述第三电容与所述第四电容之间的节点。
  4. 根据权利要求3所述的宽频带低相噪频综电路，其中，所述环路滤波电路包括第五至第七电容、第三电感及第四电感，所述第五电容的第一端连接所述鉴相环芯片的第一引脚，所述第五电容的第二端接地，所述第五电容的第一端依次经所述第三电感及所述第六电容接地，所述第五电容的第一端还依次经所述第四电感及所述第七电容接地，所述第四电感与所述第七电容之间的节点连接所述振荡电路。
  5. 根据权利要求3所述的宽频带低相噪频综电路，其中，所述第一振荡频率满足公式：
    Figure PCTCN2017120272-appb-100001
    所述第二振荡频率满足公式：
    Figure PCTCN2017120272-appb-100002
    其中，C1、C2、C3、C4分别为所述第一电容的电容值、所述第二电容的电容值、所述第三电容的电容值及所述第四电容的电容值，L为所述第二电感的电感值，CT为调谐电容的电容值，Cs为所述切换电容的电容值。
  6. 一种电子设备，其中，所述电子设备包括宽频带低相噪频综电路，所述频综电路包括：
    振荡电路，连接后端电路，用于输出第一振荡频率及与所述第一振荡频率不同的第二振荡频率给所述后端电路；
    反馈电路，连接所述振荡电路，用于将所述振荡电路输出的第一振荡频率及第二振荡频率反馈给鉴相电路；
    所述鉴相电路，连接所述反馈电路，用于存储一参考频率及从所述反馈电路接收所述第一振荡频率及所述第二振荡频率，并将所述第一振荡频率或所述第二振荡频率与所述参考频率进行比较，在所述第一振荡频率或所述第二振荡频率与所述参考频率不一致时，输出调整信号；在所述第一振荡频率或所述第二振荡频率与所述参考频率一致时，输出锁定信号；及
    环路滤波电路，连接所述鉴相电路及所述振荡电路，用于从所述鉴相电路接收所述调整信号并转换为电压信号后提供给所述振荡电路，以调整所述振荡 电路输出的第一振荡频率或所述第二振荡频率，所述环路滤波电路还从所述鉴相电路接收所述锁相信号并转换为电压信号后提供给所述振荡电路，以控制所述振荡电路将所述第一振荡频率或所述第二振荡频率输出给后端电路。
  7. 根据权利要求6所述的电子设备，其中，所述鉴相电路为一鉴相环芯片，所述反馈电路为一低通滤波器，所述振荡电路输出的第一振荡频率小于所述第二振荡频率，且所述振荡电路的调谐电压不超过所述鉴相芯片的泵电压。
  8. 根据权利要求7所述的电子设备，其中，所述振荡电路包括第一及第二变容二极管、第一至第四电容、切换二极管、第一及第二电感、可控开关、切换电容及负载电阻，所述第一变容二极管的阴极连接所述第二变容二极管的阴极及所述环路滤波电路，所述第二变容二极管的阳极接地，所述第一变容二极管的阳极经所述第一电感接地，所述第一变容二极管的阳极还依次经所述第一电容及所述切换电容连接所述切换二极管的阳极，所述切换二极管的阴极接地，所述第二电感的第一端连接在所述第一电容与所述切换电容之间的节点，所述第二电感的第二端接地，所述第二电感的第一端还依次经过所述第二电容、所述第三电容及所述第四电容接地，所述可控开关的控制端连接在所述第二电容与所述第三电容之间的节点，所述可控开关的第一端经所述负载电阻接地，所述可控开关的第二端连接在所述第三电容与所述第四电容之间的节点。
  9. 根据权利要求8所述的电子设备，其中，所述环路滤波电路包括第五至第七电容、第三电感及第四电感，所述第五电容的第一端连接所述鉴相环芯片的第一引脚，所述第五电容的第二端接地，所述第五电容的第一端依次经所述第三电感及所述第六电容接地，所述第五电容的第一端还依次经所述第四电感及所述第七电容接地，所述第四电感与所述第七电容之间的节点连接所述振荡电路。
  10. 根据权利要求7所述的电子设备，其中，所述第一振荡频率满足公式：
    Figure PCTCN2017120272-appb-100003
    所述第二振荡频率满足公式：
    Figure PCTCN2017120272-appb-100004
    其中，C1、C2、C3、C4分别为所述第一电容的电容值、所述第二电容的电容值、所述第三电容的电容值及所述第四电容的电容值，L为所述第二电感的电 感值，CT为调谐电容的电容值，Cs为所述切换电容的电容值。
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