WO2019127313A1 - 节点电容的校准方法 - Google Patents

节点电容的校准方法 Download PDF

Info

Publication number
WO2019127313A1
WO2019127313A1 PCT/CN2017/119697 CN2017119697W WO2019127313A1 WO 2019127313 A1 WO2019127313 A1 WO 2019127313A1 CN 2017119697 W CN2017119697 W CN 2017119697W WO 2019127313 A1 WO2019127313 A1 WO 2019127313A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
capacitance
channel
output voltage
capacitor
Prior art date
Application number
PCT/CN2017/119697
Other languages
English (en)
French (fr)
Inventor
罗政
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2017/119697 priority Critical patent/WO2019127313A1/zh
Priority to CN201780002330.6A priority patent/CN110383226B/zh
Publication of WO2019127313A1 publication Critical patent/WO2019127313A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present application relates to the field of detection technologies, and in particular, to a method for calibrating a node capacitance.
  • a chip for transmitting and receiving multi-channel signals for detecting small capacitance changes (such as a capacitive touch chip) or a device usually requires a matrix capacitor as a signal transmission path, that is, a matrix capacitor plate as a chip or device test. Intermediary; therefore, the accuracy of the matrix capacitor plate itself directly affects the test results of the chip or device.
  • a matrix capacitor board There are currently two ways to make a matrix capacitor board. One is to use a small capacitance ceramic capacitor combined with a printed circuit board (PCB) to make a matrix capacitor board. The other is to use a PCB trace to simulate a flat capacitor node to make a PCB. Trace capacitance matrix board.
  • the PCB trace capacitance matrix board is affected by the PCB fabrication tolerance and the dielectric constant of the substrate, and the dielectric constant of the substrate has a great influence on the matrix capacitance.
  • the FR-4 substrate board has a dielectric constant generally ranging from Around 4.2-4.7, the deviation due to the dielectric constant can be as high as 10%. Therefore, it is generally preferred to use a ceramic capacitor in combination with a PCB to form a matrix capacitor plate.
  • the inventors have found that the prior art has at least the following problems: usually good commercial small-capacitance ceramic capacitors (several pF) have an accuracy of +/- 0.1 pF, while the industry provides a leading manufacturer of general-purpose ceramic capacitors in several pF The highest precision of a small capacitor is +/- 0.05 pF, but even so, if the deviation is still +/- 5% for 1 pF, the ceramic capacitor of this precision is very expensive. In addition, it is necessary to ensure the consistency of the capacitance of each node during the test.
  • the number of node capacitances of a matrix capacitor board with multiple transmission channels and multiple receiving channels is very large, and a large number of high-precision capacitors are selected by testing methods to form a large number of high-precision capacitors.
  • a matrix capacitor plate is very labor intensive.
  • the purpose of some embodiments of the present application is to provide a method for calibrating a node capacitance, which can obtain a calibration coefficient of a monolithic matrix capacitor plate by physically calibrating a small number of node capacitances, thereby quickly obtaining a high-precision matrix capacitor. board.
  • An embodiment of the present application provides a method for calibrating a node capacitance, comprising physically calibrating at least one transmission channel of a matrix capacitor plate and a node capacitance of at least one receiving channel to form a reference node capacitance; and transmitting to a matrix capacitor plate
  • the scanning voltage is applied to the channel, and the output voltage corresponding to each node capacitor is received from each receiving channel; and the calibration coefficient of each non-reference node capacitance is calculated according to the output voltage of each reference node capacitor and the output voltage of each non-reference node capacitor;
  • the node capacitance that is not physically calibrated in the capacitance matrix is a non-reference node capacitance.
  • the embodiment of the present application further provides a method for calibrating a node capacitance, comprising: providing a public board, wherein the public board is a matrix capacitor board calibrated according to the calibration method of the node capacitance described above; and each transmitting channel to the public board Applying another scan voltage, and receiving an output voltage corresponding to each node capacitor from each receiving channel; applying another scan voltage to each transmission channel of the matrix capacitor plate to be calibrated, and receiving an output voltage corresponding to each node capacitor from each receiving channel Calculating the capacitance of each node of the matrix capacitor plate to be calibrated according to the output voltage of each node capacitor in the public board, the calibration coefficient of each node capacitor in the public board, and the output voltage of each node capacitor of the matrix capacitor plate to be calibrated Calibration coefficient; where the calibration coefficient of each reference node capacitance in the public board is 1.
  • the embodiment of the present application forms a reference node capacitance by physically calibrating at least one transmission channel on the matrix capacitor plate and the node capacitance on at least one receiving channel, so that each non-accuracy can be calculated according to the reference node capacitance.
  • the calibration coefficient of the reference node capacitance that is, the physical calibration of the node capacitance is obtained, the calibration coefficient of the entire matrix capacitor plate is obtained, and the matrix capacitor plate is quickly calibrated; thereby obtaining a high precision Matrix capacitor plate.
  • the obtained high-precision matrix capacitor plate can be used as a common plate to obtain calibration coefficients of other uncalibrated matrix capacitor plates, so that a plurality of uncalibrated matrix capacitor plates can be quickly calibrated to exactly the same accuracy as the public board.
  • a calibration coefficient of each non-reference node capacitance is calculated according to an output voltage of each reference node capacitance and an output voltage of each non-reference node capacitance, and specifically includes: selecting a non-reference node for each non-reference node capacitance to be calibrated Three associated node capacitances of the capacitor; wherein three associated node capacitances and non-reference node capacitances are arranged in a rectangular shape, and each associated node capacitance is a reference node capacitance or a calibrated non-reference node capacitance; according to three associated node capacitances
  • the output voltage and the output voltage of the non-reference node capacitor calculate the calibration factor for the non-reference node capacitance.
  • This embodiment provides a specific calculation method of the calibration coefficients of the non-reference node capacitances.
  • Vout(i,j) is the output voltage of the non-reference node capacitor on the ith transmit channel and the jth receive channel
  • Vout(k,j) is the kth transmit channel and the jth receive channel
  • the output voltage of the associated node capacitor, Vout(i,m) is the output voltage of the ith transmission channel, the associated node capacitor on the mth receive channel
  • Vout(k,m) is the kth transmission channel, the mth strip
  • This embodiment provides a calculation formula for the calibration coefficient of the non-reference node capacitance.
  • the three associated node capacitances are the reference node capacitances.
  • the three associated node capacitances are all reference node capacitances, so that the calibration result can be more accurate.
  • the preset accuracy requirement is: the range of the deviation percentage of the reference capacitor is (-f1, f1), and f1 is the maximum deviation percentage of the reference capacitor.
  • the percentage deviation of all the reference capacitors on the matrix capacitor board is (0, f1), or the deviation percentage of all the reference capacitors on the matrix capacitor board is (-f1, 0).
  • the reference capacitance biased in one direction is selected, and the overall deviation can be further reduced.
  • the maximum deviation percentage f1 has a value of 1%.
  • This embodiment provides a specific calculation formula for obtaining the calibration coefficient of the node capacitance of the matrix capacitor plate to be calibrated by using the public board.
  • FIG. 1 is a schematic view of a matrix capacitor plate in a first embodiment according to the present application.
  • FIG. 2 is a specific flowchart of a method for calibrating a node capacitance according to a first embodiment of the present application
  • FIG. 3 is a specific flowchart of a method for calibrating a node capacitance according to a second embodiment of the present application
  • FIG. 4 is a circuit configuration diagram of a capacitance detecting model in a second embodiment of the present application.
  • FIG. 5 is a schematic diagram of any two transmission channels and any two receiving channels on a matrix capacitor plate according to a second embodiment of the present application
  • FIG. 6 is a specific flowchart of a method of calibrating a node capacitance according to a third embodiment of the present application.
  • the first embodiment of the present application relates to a method for calibrating a node capacitance, which is applied to calibrate a node capacitance on a matrix capacitor plate.
  • a capacitor matrix on a matrix capacitor plate may be disposed on a substrate or Two opposite substrates (the substrate of the matrix capacitor plate are not illustrated in FIG.
  • TX channels transmission channels
  • RX channels receiving channels
  • TX channels transmission channels
  • RX channels receiving channels
  • TX channels transmission channels
  • RX channels receiving channels
  • intersections of the TX channels and the RX channels There is a node capacitor, one plate of the node capacitor is connected to the TX channel forming the node capacitance, and the other plate of the node capacitor is connected to the RX channel forming the node capacitance; wherein only five TX channels are schematically shown in the figure TX0 to TX4 and 5 RX channels RX0 to RX4 form a 25-node capacitor; however, the illustration is merely illustrative, and the number of TX channels and RX channels of the actual matrix capacitor plate is set as needed.
  • Step 101 Physically calibrate the node capacitances of the at least one transmission channel of the matrix capacitor plate and the at least one receiving channel to form a reference node capacitance, and the node capacitances other than the reference node capacitance are used as non-reference node capacitances.
  • Step 102 applying a scan voltage to each transmission channel of the matrix capacitor plate, and receiving an output voltage corresponding to each node capacitor from each receiving channel.
  • Step 103 Calculate a calibration coefficient of each non-reference node capacitance according to an output voltage of each reference node capacitance and an output voltage of each non-reference node capacitance.
  • the present embodiment forms a reference node capacitance by physically calibrating the node capacitances of at least one transmission channel and at least one receiving channel on the matrix capacitor plate, so that each non-reference can be calculated according to the reference node capacitance.
  • the calibration coefficient of the node capacitance that is, the physical calibration of the node capacitance is obtained, the calibration coefficient of the whole matrix capacitor plate is obtained, and the matrix capacitor plate is quickly calibrated; thereby obtaining a high precision matrix quickly.
  • the second embodiment of the present application relates to a method for calibrating a node capacitance.
  • the present embodiment is a refinement based on the first embodiment.
  • the main refinement is that the steps in the first embodiment are described in detail.
  • Step 201 is similar to step 102; step 203 includes sub-step 2031 and sub-step 2032.
  • Step 201 Replace the node capacitance of the at least one transmission channel of the matrix capacitor plate and the node capacitance of the at least one receiving channel with a reference capacitance that meets a preset accuracy requirement.
  • At least one TX channel and at least one RX channel of the matrix capacitor plate are first selected as a reference line, and then the node capacitance on the reference line is replaced with a reference capacitance satisfying a preset accuracy requirement to form a reference node capacitance;
  • a preset accuracy requirement is: the range of the deviation percentage of the reference capacitor is (-f1, f1), and f1 is the maximum deviation percentage of the reference capacitor.
  • the specific value of f1 can be set according to the accuracy, and the higher the required precision, the smaller the value of f1. It should be noted that, in the preset accuracy requirement of the embodiment, the range of the deviation percentage of the reference capacitance is symmetric with respect to zero (that is, the absolute values of the maximum deviation percentage and the minimum deviation percentage are both f1), but not limited thereto.
  • the reference capacitance that satisfies the preset accuracy requirement is selected in the ordinary precision capacitor by the precision LCR meter test, for example, the Agilent E4980A LCR meter (not limited to this) to obtain the required high precision capacitor.
  • the range of deviations of all the reference capacitors on the matrix capacitor board is (0, f1), or the range of deviations of all the reference capacitors on the matrix capacitor board is (-f1, 0). That is, the reference capacitances offset in the same direction are selected, so that the deviation percentage of all the reference capacitances can be in the range of (0, f1) or (-f1, 0), which can further reduce the overall deviation.
  • Cx is the standard capacitance value of the reference capacitor
  • the capacitance value of the reference capacitor is in the range of (Cx, (1+f1)Cx) or ((1-f1)Cx, Cx).
  • the value of the maximum deviation percentage f1 is selected to be 1%.
  • Step 202 applying a scan voltage to each transmission channel of the matrix capacitor plate, and receiving an output voltage corresponding to each node capacitor from each receiving channel.
  • Step 203 calculating a calibration coefficient of each non-reference node capacitance according to an output voltage of each reference node capacitance and an output voltage of each non-reference node capacitance, specifically including:
  • Sub-step 2031 for each non-reference node capacitance to be calibrated, three associated node capacitances of the non-reference node capacitance are selected.
  • the three associated node capacitors and the non-reference node capacitors are arranged in a rectangular shape, and each associated node capacitance is a reference node capacitance.
  • Sub-step 2032 calculates a calibration coefficient of the non-reference node capacitance based on the output voltage of the three associated node capacitances and the output voltage of the non-reference node capacitance.
  • the solution in this embodiment is to use a set of four node capacitors, one of which is a non-reference node capacitor to be calibrated, and the other three are reference node capacitances, thereby calculating the non-reference node to be calibrated. capacitance.
  • the following is a description of why the non-reference node capacitance to be calibrated in the group can be calculated by using the above scheme.
  • a scan voltage Vin is applied to each TX channel of the matrix capacitor plate, and Vin(i) represents a scan voltage applied to the i-th TX channel, so that the output voltage Vout corresponding to each node capacitance can be received from the RX channel.
  • the scan voltage Vin(i) enters the i-th TX channel, passes through the i-th TX channel on the matrix capacitor plate, and the node capacitance Cx(i,j) on the j-th RX channel, after the j-th RX channel
  • the output voltage Vout(i,j) is generated, and the process can be equivalent to: after the scan voltage Vin(i) is input to the capacitance detection model shown in FIG. 4, the output voltage Vout(i, j) is generated.
  • the capacitance detection model includes a node capacitance Cx(i,j), an operational amplifier 1, and a resistance R of the capacitance detection model.
  • One end of the node capacitance Cx(i,j) is used to receive the scan voltage Vin(i), and the node capacitance Cx(i, The other end of j) is connected to the negative input terminal of the operational amplifier 1, and the forward input terminal of the operational amplifier 1 is grounded. Both ends of the resistor R are respectively connected to the negative input terminal of the operational amplifier 1 and the output terminal of the operational amplifier 1.
  • the voltage applied to the xth TX channel is represented by Vin(x), and H2(x, y) represents the transfer function of the uncalibrated node capacitance at the intersection of the xth TX channel and the yth RX channel, H2cal(x) , y) represents the transfer function of the calibrated node capacitance at the intersection of the xth TX channel and the yth RX channel, and H3(y) is the transfer function of the yth RX channel receiving loop; Vin(x) goes through the xth
  • the uncalibrated node capacitance formed by the strip TX channel and the yth RX channel is expressed as Vout(x, y) through the receiving loop, and the Vin(x) passes through the xth TX channel and the yth RX.
  • the calibrated node capacitance formed by the channel, and then the output voltage generated by the receiving loop is expressed as Vcal(x, y), and the following formula can be obtained:
  • Vout(x,y) Vin(x)*H2(x,y)*H3(y) Formula (1)
  • Vcal(x,y) Vin(x)*H2cal(x,y)*H3(y) Formula (2)
  • FIG. 5 is any two TX channels on the matrix capacitor plate (the i-th and K-th TX channels respectively) and any two RX channels (the j-th and m-th RX channels, respectively).
  • formula (2) you can get:
  • Vcal(i,j) Vin(i)*H2cal(i,j)*H3(j)
  • Vcal(k,j) Vin(k)*H2cal(k,j)*H3(j)
  • Vcal(i,m) Vin(i)*H2cal(i,m)*H3(m)
  • Vcal(k,m) Vin(k)*H2cal(k,m)*H3(m)
  • Equation (3) Since H2cal(i,j), H2cal(k,j), H2cal(i,m), H2cal(k,m) are equal to the transfer functions of the calibrated node capacitances, equation (3) can be obtained:
  • Vcal(i,j)/Vcal(k,j) Vcal(i,m)/Vcal(k,m) Formula (3)
  • the output voltage generated after the calibration of the fourth non-reference node capacitance can be obtained according to the above formula (3).
  • Vout(k,j)/Vcal(i,j) Vout(k,m)/Vout(i,m) modeling formula (4)
  • the calibration coefficient K(i,j) of the non-reference node capacitance Cx(i,j) can be expressed as:
  • the calibration coefficients of the non-reference nodes are stored in the corresponding microcontroller of the matrix capacitor plate; thereby being able to be based on the calibration coefficients of the non-reference node capacitances and at different scan voltages.
  • the output voltage of the non-reference node capacitor is calculated from the calibrated output voltage of the non-reference node capacitor.
  • the microcontroller can store the calibration coefficients of the capacitances of the nodes, and the calibration coefficient of each reference node is 1.
  • one TX channel and one RX channel are selected as the reference lines; however, it is not limited thereto, and multiple TX channels and multiple RX channels may be selected as the reference lines.
  • the selected three associated node capacitances are the reference node capacitances on the reference line, but it is not limited thereto. If the engineering error tolerance range is larger, the calibration may also be selected. The node capacitance on the subsequent non-reference line is calculated as the associated node capacitance.
  • This embodiment provides a specific method of calculating a calibration coefficient of a non-reference node capacitance with respect to the first embodiment.
  • the third embodiment of the present application relates to a method for calibrating a node capacitance for quickly acquiring calibration coefficients of an uncalibrated matrix capacitor plate.
  • the specific process of the node capacitance calibration method is shown in Figure 6.
  • step 301 a public board is provided.
  • the public board is a matrix capacitor board calibrated according to the calibration method of the node capacitance according to the first embodiment or the second embodiment.
  • Step 302 Apply another scan voltage to each transmission channel of the public board, and receive an output voltage corresponding to each node capacitance from each receiving channel.
  • a scan voltage is applied to each TX channel of the public board, and an output voltage corresponding to each node capacitor is received from each RX channel, and Vcom(i, j) is the i-th TX channel and the j-th RX on the public board.
  • the other scan voltage may be the same as or different from the scan voltage mentioned in step 102 or step 202 of the first or second embodiment.
  • Step 303 applying another scan voltage to each transmission channel of the matrix capacitor plate to be calibrated, and receiving an output voltage corresponding to each node capacitor from each receiving channel.
  • the other scan voltage Vin is applied to each TX channel of the matrix capacitor plate to be calibrated and the corresponding TX channel on the public board, and the output voltage corresponding to each node capacitor is received from each RX channel, V(i, j) is the output voltage of the node capacitance on the i-th TX channel and the j-th RX channel of the matrix capacitor plate to be calibrated.
  • the matrix capacitor plate to be calibrated is the same as the model of the public board, that is, the number of TX channels and the number of RX channels on the matrix capacitor plate to be calibrated correspond to the number of TX channels and the number of RX channels on the public board respectively. The same, therefore, the capacitance of each node on the matrix capacitor plate to be calibrated corresponds to the capacitance of each node on the matrix capacitor plate to be calibrated.
  • Step 304 Calculate the matrix capacitor plate to be calibrated according to the output voltage of each node capacitor in the public board, the calibration coefficient of each non-reference node capacitor in the public board, and the output voltage of each node capacitor of the matrix capacitor plate to be calibrated. The calibration factor for each node's capacitance.
  • the calibration coefficient P(i,j) of each node capacitance of the matrix capacitor plate to be calibrated is calculated according to the formula:
  • K(i,j) is the calibration coefficient of the node capacitance on the i-th transmission channel and the j-th reception channel on the public board
  • Vcom(i,j) is the i-th TX channel on the public board
  • V(i, j) is the output voltage of the node capacitor of the i-th TX channel and the j-th RX channel of the matrix capacitor plate to be calibrated;
  • the calibration coefficient of each reference node capacitance is 1.
  • the present embodiment forms a reference node capacitance by physically calibrating the node capacitances of at least one transmission channel and at least one receiving channel on the matrix capacitor plate, so that each non-reference can be calculated according to the reference node capacitance.
  • the calibration coefficient of the node capacitance that is, the physical calibration of the node capacitance is obtained, the calibration coefficient of the whole matrix capacitor plate is obtained, and the matrix capacitor plate is quickly calibrated; thereby obtaining a high precision matrix quickly.
  • the obtained high-precision matrix capacitor plate can be used as a common plate to obtain calibration coefficients of other uncalibrated matrix capacitor plates, so that a plurality of uncalibrated matrix capacitor plates can be quickly calibrated to exactly the same accuracy as the public board.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

一种节点电容的校准方法，包括：对矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容进行物理校准，以形成基准节点电容（101）；向矩阵电容板的各发送通道施加扫描电压，并从各接收通道接收各节点电容对应的输出电压（102）；根据各基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各非基准节点电容的校准系数（103）；其中，电容矩阵中未经物理校准的节点电容为非基准节点电容。采用该方法，能够通过对数量较少的节点电容的物理校准，获取整块矩阵电容板的校准系数，从而能够快速获取一块高精度的矩阵电容板。

Description

节点电容的校准方法 技术领域
本申请涉及检测技术领域，特别涉及一种节点电容的校准方法。
背景技术
目前，用于检测小电容变化的多通道信号发送和接收的芯片(比如电容触控芯片)或设备在测试时，通常需要矩阵电容来作为信号传输通路，即矩阵电容板作为芯片或设备的测试中介；因此，矩阵电容板本身的精度会直接影响芯片或设备的测试结果。
目前有两种方式来制作矩阵电容板，一是用小容值的陶瓷电容结合印刷电路板(Printed Circuit Board，PCB)制成矩阵电容板；二是用PCB走线模拟平板电容节点制成PCB走线电容矩阵板。其中，PCB走线电容矩阵板会受PCB制作公差和基板的介电常数影响，而基板的介电常数会对矩阵电容影响很大，例如，FR-4基材板，介电常数通常范围为4.2-4.7左右，此时因介电常数引起的偏差就可高达10％。因此，一般更倾向于采用陶瓷电容结合PCB制成矩阵电容板。
发明人发现现有技术至少存在以下问题：通常良好的商用的小容值的陶瓷电容(几个pF)的精度为+/-0.1pF,而业界提供通用陶瓷电容器的领先厂商在几个pF这种小电容的最高精度为+/-0.05pF,但是即使如此，此种偏差如果对于 1pF而言，偏差仍旧达到了+/-5％,且这种精度的陶瓷电容非常昂贵。另外，在测试时需要保证各节点电容的一致性，然而一块多发射通道和多接收通道的矩阵电容板的节点电容数量非常多，完全通过测试的方法来挑选出数量众多的高精度电容来构成一块矩阵电容板工作量非常大。
发明内容
本申请部分实施例的目的在于提供一种节点电容的校准方法，能够通过对数量较少的节点电容的物理校准，获取整块矩阵电容板的校准系数，从而能够快速获取一块高精度的矩阵电容板。
本申请实施例提供了一种节点电容的校准方法，包括对矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容进行物理校准，以形成基准节点电容；向矩阵电容板的各发送通道施加扫描电压，并从各接收通道接收各节点电容对应的输出电压；根据各基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各非基准节点电容的校准系数；其中，电容矩阵中未经物理校准的节点电容为非基准节点电容。
本申请实施例还提供了一种节点电容的校准方法，包括：提供一块公板，其中，公板为根据上述的节点电容的校准方法进行校准后的矩阵电容板；向公板的各发送通道施加另一扫描电压，并从各接收通道接收各节点电容对应的输出电压；向待校准的矩阵电容板的各发送通道施加另一扫描电压，并从各接收通道接收各节点电容对应的输出电压；根据公板中的各节点电容的输出电压、公板中各节点电容的校准系数以及待校准的矩阵电容板的各节点电容的输出电压，计算出待校准的矩阵电容板的各节点电容的校准系数；其中，公板中各基 准节点电容的校准系数为1。
本申请实施例相对于现有技术而言，通过对矩阵电容板上至少一条发送通道和至少一条接收通道上的节点电容的物理校准，形成基准节点电容，从而能够根据基准节点电容计算出各非基准节点电容的校准系数；即，实现了通过对数量较少的节点电容的物理校准，获取整块矩阵电容板的校准系数，实现对矩阵电容板的快速校准；从而能够快速获取一块高精度的矩阵电容板。并且，能够以获取的高精度的矩阵电容板作为公板，获取其他尚未校准的矩阵电容板的校准系数，从而能够将多个未校准的矩阵电容板快速校准到与公板完全一样的精度。
另外，对矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容进行物理校准，具体为：将矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容替换为满足预设精度要求的基准电容。本实施例提供了一种对矩阵电容板进行物理校准的具体方式。
另外，根据各基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各非基准节点电容的校准系数，具体包括：对于每个待校准的非基准节点电容，选定非基准节点电容的三个关联节点电容；其中，三个关联节点电容与非基准节点电容排列成矩形，且每个关联节点电容为基准节点电容或者为校准后的非基准节点电容；根据三个关联节点电容的输出电压和非基准节点电容的输出电压，计算出非基准节点电容的校准系数。本实施例提供了各非基准节点电容的校准系数的具体计算方式。
另外，非基准节点电容的校准系数K(i，j)的计算公式为：K(i，j)＝(Vout(k，j)*Vout(i，m))/(Vout(k，m)*Vout(i，j))。其中，Vout(i，j) 为第i条发送通道、第j条接收通道上的非基准节点电容的输出电压，Vout(k，j)为第k条发送通道、第j条接收通道上的关联节点电容的输出电压，Vout(i，m)为第i条发送通道、第m条接收通道上的关联节点电容的输出电压、Vout(k，m)为第k条发送通道、第m条接收通道上的关联节点电容的输出电压。本实施例提供了非基准节点电容的校准系数的计算公式。
另外，三个关联节点电容均为基准节点电容。本实施例设定三个关联节点电容均为基准节点电容，从而能够使校准结果更加准确。
另外，预设精度要求为：基准电容的偏差百分比的范围是(-f1，f1)，f1为基准电容的最大偏差百分比。本实施例提供了基准电容的选取方式。
另外，矩阵电容板板上所有的基准电容的偏差百分比的范围均是(0，f1)，或者矩阵电容板板上所有的基准电容的偏差百分比的范围均是(-f1，0)。本实施例选取往一个方向偏的基准电容，能够进一步减小整体偏差。
另外，最大偏差百分比f1的值为1％。
另外，待校准的矩阵电容板的各节点电容的校准系数的计算公式为：P(i，j)＝K(i，j)*Vcom(i，j)/V(i，j)；其中，K(i，j)为公板上的第i条发送通道、第j条接收通道上的节点电容的校准系数，Vcom(i，j)为公板上的第i条发送通道、第j条接收通道上的节点电容的输出电压；V(i，j)为待校准的矩阵电容板的第i条发送通道、第j条接收通道上的节点电容的输出电压。本实施例提供了利用公板得到待校准的矩阵电容板的节点电容的校准系数的具体计算公式。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例中的矩阵电容板的示意图；
图2是根据本申请第一实施例中的节点电容的校准方法的具体流程图；
图3是根据本申请第二实施例中的节点电容的校准方法的具体流程图；
图4是根据本申请第二实施例中的电容检测模型的电路结构图；
图5是根据本申请第二实施例中的矩阵电容板上的任意两条发送通道和任意两条接收通道的示意图；
图6是根据本申请第三实施例中的节点电容的校准方法的具体流程图。
具体实施例
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种节点电容的校准方法，应用于对矩阵电容板上的节点电容进行校准，请参考图1，为一块矩阵电容板上的电容矩阵，其可以设置在一个基板或两个相对的基板上(图1中未示意出该矩阵电容板的基板)，其包括多条发送通道(TX通道)和多条接收通道(RX通道)，TX通道与RX通道的交点处设有节点电容，节点电容的一个极板连接到形成该节点电容的TX通道，节点电容的另一个极板连接到形成该节点电容的RX通道；其中，图中 仅示意性画出5条TX通道TX0至TX4和5条RX通道RX0至RX4，形成25个节点电容；然图中仅仅是示例性说明，实际的矩阵电容板的TX通道和RX通道的数目根据需要设定。
本实施例中的节点电容的校准方法的具体流程如图2所示。
步骤101，对矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容进行物理校准，以形成基准节点电容，除基准节点电容之外的其他节点电容作为非基准节点电容。
步骤102，向矩阵电容板的各发送通道施加扫描电压，并从各接收通道接收各节点电容对应的输出电压。
步骤103，根据各基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各非基准节点电容的校准系数。
本实施例相对于现有技术而言，通过对矩阵电容板上至少一条发送通道和至少一条接收通道上的节点电容的物理校准，形成基准节点电容，从而能够根据基准节点电容计算出各非基准节点电容的校准系数；即，实现了通过对数量较少的节点电容的物理校准，获取整块矩阵电容板的校准系数，实现对矩阵电容板的快速校准；从而能够快速获取一块高精度的矩阵电容板。
本申请第二实施例涉及一种节点电容的校准方法，本实施例是在第一实施例基础上的细化，主要细化之处在于：对第一实施例中的各步骤进行详细说明。
本实施例中的节点电容的校准方法的具体流程如图3所示。其中，步骤201为步骤101的具体化；步骤202与步骤102相似；步骤203包括子步骤2031和子步骤2032。
步骤201，将矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容替换为满足预设精度要求的基准电容。
具体而言，先选定矩阵电容板的至少一条TX通道和至少一条RX通道作为基准线，然后将基准线上的节点电容替换为满足预设精度要求的基准电容，以形成基准节点电容；如图1所示的矩阵电容板，若将一条TX通道和一条RX通道作为基准线，则需要以9个满足预设精度要求的基准电容替换基准线上的节点电容，从而形成基准节点电容。其中，预设精度要求为：基准电容的偏差百分比的范围是(-f1，f1)，f1为基准电容的最大偏差百分比。其中，f1的具体数值可以根据精度需要设定，要求的精度越高，f1的值越小。需要说明的是，本实施例的预设精度要求中，基准电容的偏差百分比的范围关于零对称(即最大偏差百分比和最小偏差百分比的绝对值都是f1)，然并不以此为限。
其中，满足预设精度要求的基准电容的选取方式为，在普通精度的电容中，通过精度LCR表测试，例如安捷伦E4980A LCR表(然不限于此)，来获取所需的高精度电容。
较佳的，选取矩阵电容板板上所有的基准电容的偏差百分比的范围均是(0，f1)，或者矩阵电容板板上所有的基准电容的偏差百分比的范围均是(-f1，0)，即，选取往同一个方向偏的基准电容，从而可以使所有的基准电容的偏差百分比的范围为(0，f1)或(-f1，0)，能够进一步减小整体偏差。其中，若以Cx为基准电容的标准电容值，则基准电容的电容值在(Cx，(1+f1)Cx)范围内，或((1-f1)Cx，Cx)范围内。本实施例中，选取最大偏差百分比f1的值为1％。
步骤202，向矩阵电容板的各发送通道施加扫描电压，并从各接收通道接收各节点电容对应的输出电压。
步骤203，根据各基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各非基准节点电容的校准系数，具体包括：
子步骤2031，对于每个待校准的非基准节点电容，选定非基准节点电容的三个关联节点电容。其中，三个关联节点电容与非基准节点电容排列成矩形，且每个关联节点电容为基准节点电容。
子步骤2032，根据三个关联节点电容的输出电压和非基准节点电容的输出电压，计算出非基准节点电容的校准系数。
以下是对步骤202和步骤203进行的具体分析。
本实施例中，为了计算出待校准的非基准节点电容，需选定三个关联节点电容。即，本实施例中的方案是，以四个节点电容为一组，其中一个是待校准的非基准节点电容，其余三个是基准节点电容，以此来计算出该待校准的非基准节点电容。以下首先对为何可以采用上述方案计算出该组中的该待校准的非基准节点电容进行说明。
向矩阵电容板的各TX通道施加扫描电压Vin，Vin(i)表示对第i条TX通道施加的扫描电压，从而可以从RX通道接收各节点电容对应的输出电压Vout。其中，扫描电压Vin(i)进入第i条TX通道，经过矩阵电容板上的第i条TX通道、第j条RX通道上的节点电容Cx(i，j)后，在第j条RX通道产生输出电压Vout(i，j)，该过程可以等效为：扫描电压Vin(i)输入图4所示的电容检测模型后，产生输出电压Vout(i，j)。电容检测模型包括节点电容Cx(i，j)，运算放大器1、电容检测模型的电阻R，节点电容Cx(i，j)的一端用于接收扫描电压Vin(i)，节点电容Cx(i，j)的另一端连接于运算放大器1的负向输入端，运算放大器1的正向输入端接地，电阻R的两端分别 连接于运算放大器1的负向输入端和运算放大器1的输出端。
以Vin(x)表示对第x条TX通道施加的扫描电压，H2(x，y)表示第x条TX通道、第y条RX通道交点处的未经校准节点电容的传递函数，H2cal(x，y)表示第x条TX通道、第y条RX通道交点处的校准后的节点电容的传递函数，H3(y)为第y条RX通道接收回路的传递函数；Vin(x)经过第x条TX通道、第y条RX通道形成的未校准的节点电容，再经过接收回路所产生的输出电压表示为Vout(x，y)，Vin(x)经过第x条TX通道、第y条RX通道形成的校准后的节点电容，再经过接收回路所产生的输出电压表示为Vcal(x，y)，可以得到如下的公式：
Vout(x，y)＝Vin(x)*H2(x，y)*H3(y)公式(1)
Vcal(x，y)＝Vin(x)*H2cal(x，y)*H3(y)公式(2)
请参考图5，为矩阵电容板上的任意两条TX通道(分别为第i条和第K条TX通道)和任意两条RX通道(分别为第j条和第m条RX通道)，形成有四个节点电容Cx(i，j)、Cx(i，m)、Cx(k，j)以及Cx(k，m)。根据公式(2)可以得到：
Vcal(i，j)＝Vin(i)*H2cal(i，j)*H3(j)
Vcal(k，j)＝Vin(k)*H2cal(k，j)*H3(j)
Vcal(i，m)＝Vin(i)*H2cal(i，m)*H3(m)
Vcal(k，m)＝Vin(k)*H2cal(k，m)*H3(m)
由于H2cal(i，j)、H2cal(k，j)、H2cal(i，m)、H2cal(k，m)为校准后的节点电容的传递函数均相等，从而可以得到公式(3)：
Vcal(i，j)/Vcal(k，j)＝Vcal(i，m)/Vcal(k，m)公式(3)
由上可知，若四个节点电容中的任意三个为基准节点电容，则第四个非基准节点电容校准后所产生的输出电压可以根据上述公式(3)求出。
因此，只需在TX通道和RX通道中各构造至少一条通过物理校准形成的基准线，便能够满足选定的三个关联节点电容均为基准节点电容，与非基准节点电容排列成矩形，从而可以利用上述公式(3)对非基准节点电容进行校准。
本实施例中，以图5中设定第k条TX通道和第m条RX通道为基准线为例，则四个节点电容中，Cx(i，m)、Cx(k，j)以及Cx(k，m)为基准节点电容，Cx(i，j)为非基准节点电容，下面介绍如何计算非基准节点电容Cx(i，j)的校准系数。
基于上述公式(3)，提出如下的建模公式(4)：
Vout(k，j)/Vcal(i，j)＝Vout(k，m)/Vout(i，m)建模公式(4)
非基准节点电容Cx(i，j)的校准系数K(i，j)可以表示为：
K(i，j)＝Vcal(i，j)/Vout(i，j)公式(5)
结合建模公式(4)与公式(5)，可以得到校准系数K(i，j)为：K(i，j)＝(Vout(k，j)*Vout(i，m)/(Vout(k，m)*Vout(i，j))公式(6)
本实施例中，各非基准节点被校准后，各非基准节点的校准系数会存储在该矩阵电容板对应的微控制器中；从而能够根据非基准节点电容的校准系数与在不同扫描电压下非基准节点电容的输出电压，计算非基准节点电容的校准后的输出电压。其中，微控制器可以存储各节点电容的校准系数，且各基准节点的校准系数是1。
需要强调的是，本实施例中选定一条TX通道和一条RX通道作为基准线；然不限于此，也可以选择多条TX通道和多条RX通道作为基准线。
还需要说明的是，本实施例中，选取的三个关联节点电容均为基准线上的基准节点电容，然不限于此，若工程上的误差容许范围较大一些的话，也可以选择经校准后的非基准线上的节点电容作为关联节点电容进行计算。
本实施例相对于第一实施例而言，提供了计算非基准节点电容的校准系数的具体方法。
本申请第三实施例涉及一种节点电容的校准方法，用于快速获取未校准的矩阵电容板的校准系数。节点电容的校准方法的具体流程如图6所示。
步骤301，提供一块公板。
具体而言，公板为根据第一实施例或第二实施例的节点电容的校准方法进行校准后的矩阵电容板。
步骤302，向公板的各发送通道施加另一扫描电压，并从各接收通道接收各节点电容对应的输出电压。
具体而言，向公板的各TX通道施加扫描电压，并从各RX通道接收各节点电容对应的输出电压，Vcom(i，j)为公板上的第i条TX通道、第j条RX通道上的节点电容的输出电压。其中，该另一扫描电压可以与第一或第二实施例的步骤102或步骤202中提到的扫描电压可以相同，也可以不同。
步骤303，向待校准的矩阵电容板的各发送通道施加另一扫描电压，并从各接收通道接收各节点电容对应的输出电压。
具体而言，向待校准的矩阵电容板的各TX通道与公板上对应的各TX通道施加该另一扫描电压Vin，并从各RX通道接收各节点电容对应的输出电压，V(i，j)为待校准的矩阵电容板的第i条TX通道、第j条RX通道上的节点电容的输出电压。需要说明的是，待校准的矩阵电容板与该公板的型号相同， 即待校准的矩阵电容板上的TX通道数目、RX通道数目与该公板上的TX通道数目、RX通道数目分别对应相同，因此，待校准的矩阵电容板上的各节点电容与待校准的矩阵电容板上的各节点电容分别对应。
步骤304，根据公板中的各节点电容的输出电压、公板中各非基准节点电容的校准系数以及待校准的矩阵电容板的各节点电容的输出电压，计算出待校准的矩阵电容板的各节点电容的校准系数。
具体而言，根据公式计算待校准的矩阵电容板的各节点电容的校准系数P(i，j)：
P(i，j)＝K(i，j)*Vcom(i，j)/V(i，j)
其中，K(i，j)为公板上的第i条发送通道、第j条接收通道上的节点电容的校准系数，Vcom(i，j)为公板上的第i条TX通道、第j条RX通道上的节点电容的输出电压；V(i，j)为待校准的矩阵电容板的第i条TX通道、第j条RX通道上的节点电容的输出电压；其中，公板中各基准节点电容的校准系数为1。
本实施例相对于现有技术而言，通过对矩阵电容板上至少一条发送通道和至少一条接收通道上的节点电容的物理校准，形成基准节点电容，从而能够根据基准节点电容计算出各非基准节点电容的校准系数；即，实现了通过对数量较少的节点电容的物理校准，获取整块矩阵电容板的校准系数，实现对矩阵电容板的快速校准；从而能够快速获取一块高精度的矩阵电容板。并且，能够以获取的高精度的矩阵电容板作为公板，获取其他尚未校准的矩阵电容板的校准系数，从而能够将多个未校准的矩阵电容板快速校准到与公板完全一样的精度。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种节点电容的校准方法，其特征在于，包括：
    对矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容进行物理校准，以形成基准节点电容；
    向所述矩阵电容板的各所述发送通道施加扫描电压，并从各所述接收通道接收各所述节点电容对应的输出电压；
    根据各所述基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各所述非基准节点电容的校准系数；其中，所述电容矩阵中未经物理校准的节点电容为所述非基准节点电容。
  2. 如权利要求1所述的节点电容的校准方法，其特征在于，所述对矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容进行物理校准，具体为：
    将所述矩阵电容板的至少一条发送通道和至少一条接收通道上的节点电容替换为满足预设精度要求的基准电容。
  3. 如权利要求1所述的节点电容的校准方法，其特征在于，所述根据各所述基准节点电容的输出电压和各非基准节点电容的输出电压，计算出各所述非基准节点电容的校准系数，具体包括：
    对于每个待校准的所述非基准节点电容，选定所述非基准节点电容的三个关联节点电容；其中，三个所述关联节点电容与所述非基准节点电容排列成矩形，且每个所述关联节点电容为所述基准节点电容或者为校准后的所述非基准节点电容；
    根据三个所述关联节点电容的输出电压和所述非基准节点电容的输出电压，计算出所述非基准节点电容的校准系数。
  4. 如权利要求3所述的节点电容的校准方法，其特征在于，所述非基准节点电容的校准系数K(i，j)的计算公式为：
    K(i，j)＝(Vout(k，j)*Vout(i，m))/(Vout(k，m)*Vout(i，j))。
    其中，Vout(i，j)为第i条发送通道、第j条接收通道上的所述非基准节点电容的输出电压，Vout(k，j)为第k条发送通道、第j条接收通道上的所述关联节点电容的输出电压，Vout(i，m)为第i条发送通道、第m条接收通道上的所述关联节点电容的输出电压、Vout(k，m)为第k条发送通道、第m条接收通道上的所述关联节点电容的输出电压。
  5. 如权利要求3所述的节点电容的校准方法，其特征在于，三个所述关联节点电容均为所述基准节点电容。
  6. 如权利要求2所述的节点电容的校准方法，其特征在于，所述预设精度要求为：所述基准电容的偏差百分比的范围是(-f1，f1)，f1为所述基准电容的最大偏差百分比。
  7. 如权利要求6所述的节点电容的校准方法，其特征在于，所述矩阵电容板上所有的所述基准电容的偏差百分比的范围均是(0，f1)，或者所述矩阵电容板板上所有的所述基准电容的偏差百分比的范围均是(-f1，0)。
  8. 如权利要求6所述的节点电容的校准方法，其特征在于，所述最大偏差百分比f1的值为1％。
  9. 一种节点电容的校准方法，其特征在于，包括：
    提供一块公板，其中，所述公板为根据权利要求1至8中任一项所述的节点电容的校准方法进行校准后的矩阵电容板；
    向所述公板的各发送通道施加另一扫描电压，并从各接收通道接收各节点电容对应的输出电压；
    向待校准的矩阵电容板的各发送通道施加所述另一扫描电压，并从各接收通道接收各节点电容对应的输出电压；
    根据所述公板中的各节点电容的输出电压、所述公板中各所述节点电容的校准系数以及待校准的所述矩阵电容板的各节点电容的输出电压，计算出待校准的所述矩阵电容板的各节点电容的校准系数；其中，所述公板中各所述基准节点电容的校准系数为1。
  10. 如权利要求9所述的节点电容的校准方法，其特征在于，待校准的所述矩阵电容板的各节点电容的校准系数的计算公式为：
    P(i，j)＝K(i，j)*Vcom(i，j)/V(i，j)；
    其中，K(i，j)为所述公板上的第i条发送通道、第j条接收通道上的节点电容的校准系数，Vcom(i，j)为所述公板上的第i条发送通道、第j条接收通道上的节点电容的输出电压；V(i，j)为待校准的所述矩阵电容板的第i条发送通道、第j条接收通道上的节点电容的输出电压。
PCT/CN2017/119697 2017-12-29 2017-12-29 节点电容的校准方法 WO2019127313A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/119697 WO2019127313A1 (zh) 2017-12-29 2017-12-29 节点电容的校准方法
CN201780002330.6A CN110383226B (zh) 2017-12-29 2017-12-29 节点电容的校准方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/119697 WO2019127313A1 (zh) 2017-12-29 2017-12-29 节点电容的校准方法

Publications (1)

Publication Number Publication Date
WO2019127313A1 true WO2019127313A1 (zh) 2019-07-04

Family

ID=67062865

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/119697 WO2019127313A1 (zh) 2017-12-29 2017-12-29 节点电容的校准方法

Country Status (2)

Country Link
CN (1) CN110383226B (zh)
WO (1) WO2019127313A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1576862A (zh) * 2003-07-29 2005-02-09 阿尔卑斯电气株式会社 电容检测电路及其检测方法以及指纹传感器
CN103018594A (zh) * 2012-11-30 2013-04-03 深圳市汇顶科技股份有限公司 一种电容式触摸屏的测试方法、系统及电子设备
US20130201146A1 (en) * 2010-01-04 2013-08-08 Plastic Logic Limited Touch-sensing systems
CN103543888A (zh) * 2012-07-16 2014-01-29 联咏科技股份有限公司 电容式触控装置及其感测方法
CN103983867A (zh) * 2014-04-23 2014-08-13 深圳市立德通讯器材有限公司 用于触摸、显示屏一体化屏幕的测试方法
CN104655935A (zh) * 2015-02-12 2015-05-27 深圳市精智达技术有限公司 节点电容的测试方法及装置
CN104834418A (zh) * 2014-02-04 2015-08-12 商升特公司 触摸面板校准系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2419950A (en) * 2004-11-09 2006-05-10 Sharp Kk Capacitance measuring apparatus for LCD touch screen
JP2013246557A (ja) * 2012-05-24 2013-12-09 Asahi Kasei Electronics Co Ltd タッチセンサの信号処理回路、およびタッチセンサ
US9007334B2 (en) * 2012-06-07 2015-04-14 Texas Instruments Incorporated Baseline capacitance calibration
KR20140086477A (ko) * 2012-12-28 2014-07-08 삼성전기주식회사 터치 감지 장치
KR20150017123A (ko) * 2013-08-06 2015-02-16 삼성디스플레이 주식회사 터치 센서 및 그의 구동방법
KR101580381B1 (ko) * 2014-01-03 2015-12-28 삼성전기주식회사 터치 스크린 장치 및 그 제어 방법
CN107238788B (zh) * 2016-03-29 2019-12-27 深圳市汇顶科技股份有限公司 基于矩阵电容板的触控芯片测试系统及其测试方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1576862A (zh) * 2003-07-29 2005-02-09 阿尔卑斯电气株式会社 电容检测电路及其检测方法以及指纹传感器
US20130201146A1 (en) * 2010-01-04 2013-08-08 Plastic Logic Limited Touch-sensing systems
CN103543888A (zh) * 2012-07-16 2014-01-29 联咏科技股份有限公司 电容式触控装置及其感测方法
CN103018594A (zh) * 2012-11-30 2013-04-03 深圳市汇顶科技股份有限公司 一种电容式触摸屏的测试方法、系统及电子设备
CN104834418A (zh) * 2014-02-04 2015-08-12 商升特公司 触摸面板校准系统
CN103983867A (zh) * 2014-04-23 2014-08-13 深圳市立德通讯器材有限公司 用于触摸、显示屏一体化屏幕的测试方法
CN104655935A (zh) * 2015-02-12 2015-05-27 深圳市精智达技术有限公司 节点电容的测试方法及装置

Also Published As

Publication number Publication date
CN110383226A (zh) 2019-10-25
CN110383226B (zh) 2023-01-31

Similar Documents

Publication Publication Date Title
US6838885B2 (en) Method of correcting measurement error and electronic component characteristic measurement apparatus
CA2921479C (en) Method for calibrating a test setup
CN107076789B (zh) 测量和确定噪声参数的系统和方法
CN101957243B (zh) 一种高精度温度测量装置及测量方法
CN107238788B (zh) 基于矩阵电容板的触控芯片测试系统及其测试方法
US9922888B2 (en) General four-port on-wafer high frequency de-embedding method
CN106501743B (zh) 一种数字示波器精度校准方法及装置
US5734268A (en) Calibration and measurment technique and apparatus for same
JP2010160000A (ja) インピーダンス測定方法
CN104236448B (zh) 电子式标准模拟应变量校准器的校准方法
CN110716120B (zh) 芯片自动测试设备的通道延时偏差的校准方法
WO2019127313A1 (zh) 节点电容的校准方法
EP1455197A2 (en) Calibration method and apparatus
US20130285679A1 (en) On-Chip Resistor Calibration in Semiconductor Devices
CN112286275A (zh) 一种有源电容分压器的补偿方法及装置
CN113702710A (zh) 电阻测试电路及电阻测试方法
US8451021B1 (en) Calibrating on-chip resistors via a daisy chain scheme
CN103063949A (zh) 一种电容失配检测电路及方法
CN110244128A (zh) 热电阻四线制实时测量电路及其实现方法
US10534476B2 (en) Compensation method for an induced amount in a touch sensor and touch panel thereof
CN106289043A (zh) 一种电容式距离测量方法、装置及其定标方法
CN112816752B (zh) 电容互感器温度补偿方法及设备
CN105471454A (zh) 用于射频信号源的自校正装置以及射频信号的校正系统
Bonse et al. A new two-dimensional capacitive position transducer
CN207636754U (zh) 电力仪表校准系统

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17936116

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17936116

Country of ref document: EP

Kind code of ref document: A1