WO2019114348A1 - 像素电路及其驱动方法、显示面板及电子设备 - Google Patents

像素电路及其驱动方法、显示面板及电子设备 Download PDF

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Publication number
WO2019114348A1
WO2019114348A1 PCT/CN2018/105748 CN2018105748W WO2019114348A1 WO 2019114348 A1 WO2019114348 A1 WO 2019114348A1 CN 2018105748 W CN2018105748 W CN 2018105748W WO 2019114348 A1 WO2019114348 A1 WO 2019114348A1
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Prior art keywords
circuit
voltage
control
driving
transistor
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PCT/CN2018/105748
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English (en)
French (fr)
Inventor
王峥
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/337,042 priority Critical patent/US11527199B2/en
Priority to EP18857412.3A priority patent/EP3726517A4/en
Publication of WO2019114348A1 publication Critical patent/WO2019114348A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage

Definitions

  • the present disclosure relates to a pixel circuit and a driving method thereof, a display panel, and an electronic device.
  • Organic Light Emitting Diode (OLED) display devices are gradually gaining popularity due to their wide viewing angle, high contrast ratio, fast response speed, and higher brightness and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, the organic light emitting diode (OLED) can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • the pixel circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix (AM) driving and a passive matrix (PM) driving according to whether or not a switching component is introduced in each pixel circuit.
  • AM active matrix
  • PM passive matrix
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By controlling the driving of the thin film transistor and the storage capacitor, the current flowing through the OLED is controlled, so that the OLED is required according to the needs. Glowing.
  • AMOLED Compared with PMOLED, AMOLED requires less drive current, lower power consumption and longer life, which can meet the needs of large-size display with high resolution and multiple gray scales. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reduction, power consumption and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a memory circuit, a discharge control circuit, a memory control circuit, and a data writing circuit.
  • the driving circuit includes a control end, a first end and a second end, and is configured to control a driving current for driving the light emitting element to emit light, and the first end of the driving circuit is configured to receive the first voltage from the first voltage end;
  • the storage circuit is coupled to a control end of the drive circuit;
  • the discharge control circuit is coupled to the storage circuit and a control end of the drive circuit, and is configured to control a voltage value across the storage circuit, and a control Discharging a second end of the drive circuit;
  • the memory control circuit is coupled to the control terminal of the drive circuit, the first end of the drive circuit, and the memory circuit, and configured to control the memory circuit to store the drive a voltage at a second end of the circuit;
  • the data write circuit is coupled to the memory circuit, the data signal input terminal, the first control signal terminal, and
  • the driving circuit includes a driving transistor; a control electrode of the driving transistor is connected to the memory circuit, and a first electrode of the driving transistor is connected to the light emitting device At one end, the second pole of the driving transistor is connected to the first voltage terminal, and the second end of the light emitting component is connected to the second voltage terminal.
  • the data writing circuit includes a first transistor; a control electrode of the first transistor is connected to the first control signal terminal to receive the first control signal, A first pole of the first transistor is coupled to the memory circuit, and a second pole of the first transistor is coupled to the data signal input terminal to receive the data voltage.
  • the storage circuit includes a storage capacitor; a first end of the storage capacitor is connected to a control electrode of the driving transistor, and a second end of the storage capacitor is connected to the The first pole of the first transistor.
  • the memory control circuit includes a second transistor; a control electrode of the second transistor is coupled to the second control signal terminal to receive a second control signal, the second transistor The first pole is connected to the first pole of the driving transistor, and the second pole of the second transistor is connected to the first end of the storage capacitor.
  • the discharge control circuit includes a third transistor and a fourth transistor; and a control electrode of the third transistor is connected to the third control signal terminal to receive the third control signal.
  • a first pole of the third transistor is connected to the first voltage end, a second pole of the third transistor is connected to a second end of the storage capacitor; and a control pole of the fourth transistor is connected to the third control signal Receiving the third control signal, the first pole of the fourth transistor is connected to the first voltage end, and the second pole of the fourth transistor is connected to the first end of the storage capacitor.
  • At least one embodiment of the present disclosure further provides a display panel including a plurality of pixel units arranged in an array, wherein the pixel units each include a pixel circuit and a light emitting element provided by any of the embodiments of the present disclosure.
  • a display panel further includes a plurality of scan lines.
  • the plurality of pixel units are arranged in a plurality of rows, the first control signal end of the data writing circuit of the pixel circuit of the nth row pixel unit is connected to the nth row scan line, and the storage control circuit of the pixel circuit of the nth row pixel unit Connected to the n-1th row scan line, the discharge control circuit of the pixel circuit of the nth row of pixel cells is connected to the n-2th row scan line; the n-1th row scan line is also connected to the n-1th row of pixels a first control signal end of the data writing circuit of the pixel circuit of the unit is connected; the n-2th scanning line is further connected to the first control signal end of the data writing circuit of the pixel circuit of the pixel unit of the n-2th row A connection; wherein n is an integer greater than 3.
  • the light emitting element is an organic light emitting diode.
  • a display panel provided by an embodiment of the present disclosure further includes a voltage generating circuit.
  • the voltage generating circuit is coupled to the first voltage terminal and/or the second voltage terminal, and configured to correspondingly change a first voltage provided by the first voltage terminal and/or a second voltage terminal provided The size of the two voltages.
  • At least one embodiment of the present disclosure further provides an electronic device, including the display panel provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a driving method of a pixel circuit, comprising: controlling, by the discharge control circuit, discharging of a second end of the driving circuit, such that a voltage of a second end of the driving circuit is based on the driving circuit Threshold voltage; controlling, by the memory control circuit, the memory circuit to store the threshold voltage; writing, by the data write circuit, a data voltage to the memory circuit, based on a data voltage and a location stored by the memory circuit The threshold voltage is controlled to control the driving circuit to be turned on to drive the light emitting element to emit light.
  • each lighting period of the light emitting element includes three stages, and the driving method includes: controlling, in the first stage, the discharging control circuit to be turned on. Controlling the second end of the driving circuit to discharge to the first voltage terminal until the voltage of the second end of the driving circuit reaches a threshold voltage; in the second phase, controlling the storage control circuit to be turned on The threshold voltage is stored in the storage circuit; in the third stage, the first control signal terminal inputs the first control signal to control the data write circuit to be turned on, and the first end of the storage capacitor is coupled For the sum of the data voltage and the threshold voltage, the driving circuit is turned on, and the light emitting element emits light.
  • a driving method of a pixel circuit further includes: changing, in the first stage, the first voltage to control a second end of the driving circuit to discharge the first voltage end At the third stage, the first voltage is again changed to allow the drive circuit to be turned on to drive the light emitting element to emit light.
  • a second end of the light emitting element is connected to a second voltage terminal to receive a second voltage
  • the driving method further includes: in the first stage, Changing the first voltage and the second voltage to control a second end of the driving circuit to discharge to the first voltage terminal; in the third phase, changing the first voltage and the first Two voltages are provided to allow the drive circuit to be turned on to drive the light emitting element to emit light.
  • 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit
  • FIG. 2A is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • 2B is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure.
  • 3A is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 2A;
  • 3B is a circuit diagram showing another specific implementation example of the pixel circuit shown in FIG. 2A;
  • 3C is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 2B;
  • FIG. 4 is a timing diagram of signals of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5A is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5B is a schematic diagram of another display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • the driving current of the OLED is generally related to the threshold voltage of a driving TFT (Thin Film Transistor), and the TFT fabricated by the a-Si (Amorphous Silicon) process has a problem of threshold voltage drift. That is, when a voltage is applied to the gate and source of the TFT, the threshold voltage of the TFT is gradually increased, and the current flowing through the TFT is gradually attenuated, which directly affects the brightness and lifetime of the OLED to which it is connected.
  • 1A and 1B are schematic views showing two 2T1C pixel circuits, respectively.
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1, for example, the source is connected to the data line to receive the data signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to The first voltage terminal receives the first voltage Vdd (high voltage), the drain is connected to the positive terminal of the light emitting element (here, the OLED); one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0 The other end is connected to the source of the driving transistor N0 and the first voltage terminal; the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Scan1 is applied through the scan line to turn on the switching transistor T0
  • the data signal Vdata fed through the data line by the data driving circuit charges the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs.
  • the stored data signal Vdata controls the degree of conduction of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection mode thereof is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 1B with respect to FIG. 1A includes that the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the drain of the driving transistor N0, and the driving transistor The source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • the switching transistor T0 is not limited to the N-type transistor, and may be a P-type transistor as needed, thereby controlling the polarity of the scan signal Scan1 that is turned on or off accordingly. Change it.
  • the driving transistor N0 has a large duty ratio, which will aggravate the drift of the threshold voltage of the driving transistor N0, so that the current flowing through the driving transistor N0 gradually becomes lower, affecting the OLED. Display brightness.
  • An embodiment of the present disclosure provides a pixel circuit including a driving circuit, a storage circuit, a discharge control circuit, a storage control circuit, and a data writing circuit.
  • the driving circuit includes a control end, a first end and a second end, and is configured to control a driving current for driving the light emitting element to emit light, the first end of the driving circuit is configured to receive the first voltage from the first voltage end; the storage circuit and the driving circuit The control terminal is connected; the discharge control circuit is connected to the storage circuit and the control end of the drive circuit, and is configured to control the voltage value at both ends of the storage circuit and to control the discharge of the second end of the drive circuit; the control terminal and the drive end of the drive circuit and the drive The second end of the circuit and the storage circuit are connected, and configured to control the storage circuit to store the voltage of the second end of the driving circuit; the data writing circuit is connected with the storage circuit, the data signal input end, the first control signal end, and the discharge control circuit, and is configured For controlling the first control signal input at the first control
  • the pixel circuit provided by the above embodiment of the present disclosure can eliminate the influence of the threshold voltage of the driving circuit in the pixel circuit on the driving current, thereby improving the display effect of the light emitting element and prolonging the service life of the light emitting element.
  • a pixel circuit, a driving method thereof, a display panel, and an electronic device of an embodiment of the present disclosure are described below with reference to the accompanying drawings. It should be noted that the same reference numerals will be used in the different drawings to refer to the same elements that have been described.
  • Embodiments of the present disclosure provide a pixel circuit 100 that is used to, for example, drive a light-emitting element in a sub-pixel of a display panel to emit light.
  • the display panel is prepared by, for example, a glass substrate.
  • the specific structure and the preparation process may be the conventional methods in the art, which are not described in detail herein, and the embodiments of the present disclosure are not limited thereto.
  • the illuminating element may be an OLED or a QLED (Quantum Dot Light Emitting Diodes) or the like
  • the corresponding display panel is an OLED display panel or a QLED display panel.
  • the OLED is taken as an example, and the corresponding description is also applicable to the QLED.
  • the pixel circuit 100 provided by the embodiment of the present disclosure includes a driving circuit 10, a storage circuit 20, a discharge control circuit 30, a storage control circuit 40, and a data writing circuit 50.
  • the driving circuit 10 includes a control terminal 130 (first node A), a first terminal 110 and a second terminal 120 (second node B), for example, connected to a light emitting element (here, an OLED), a first voltage terminal VDD, and The first end 110 of the drive circuit 10 is configured to receive a first voltage from the first voltage terminal VDD, configured to control a drive current that drives the illumination element to emit light.
  • the driving circuit 100 may supply a driving current to the light emitting element to drive the light emitting element to emit light, and may emit light according to a desired "grayscale".
  • the memory circuit 20 is coupled to the control terminal 130 (first node A) of the driver circuit 10 and is configured to store the data voltage and/or threshold voltage written by the data write circuit 50.
  • memory circuit 20 can store the data voltage and/or threshold voltage and control drive circuit 10 using the stored data voltage and/or threshold voltage.
  • the storage circuit 20 includes a storage capacitor
  • the storage circuit 20 can store the data voltage written by the data write circuit 50 and the threshold voltage in the storage capacitor, so that the stored data voltage and the stored data voltage can be utilized, for example, in the light-emitting phase.
  • the threshold voltage controls the drive circuit 10.
  • the discharge control circuit 30 is connected to the storage circuit 20 (third node C) and the control terminal 130 (first node A) of the drive circuit 10, and is configured to control the voltage value across the storage circuit 20, and to control the second of the drive circuit 10. End discharge.
  • the discharge control circuit 30 is further connected to the first voltage terminal VDD and the third control signal terminal (not shown), and is configured to be provided in response to the third control signal terminal.
  • a third control signal that connects the first node A and the third node C with the first voltage terminal VDD (eg, a first voltage that provides a low level (eg, 0V (volts) or ground voltage) at this time, thereby causing
  • the second terminal 120 of the driver circuit eg, a high level during the last illumination period discharges to the first voltage terminal VDD.
  • the drive circuit 10 is implemented as a drive transistor, it is turned off when the voltage of the second node B is discharged to the threshold voltage of the drive transistor.
  • the storage control circuit 40 is connected to the control terminal 130 (first node A) of the drive circuit 10, the second terminal 120 (second node B) of the drive circuit 10, and the storage circuit 20, and is configured to control the storage circuit 20 to store the drive circuit 10.
  • the voltage after discharge is further connected to a second control signal terminal (not shown) and configured to be turned on under the control of the second control signal provided at the second control signal terminal to discharge the driving circuit 10.
  • the voltage i.e., the voltage of the second node B
  • the voltage i.e., the voltage of the second node B
  • the data writing circuit 50 is connected to the storage circuit 20, the data signal input terminal DATA, the first control signal terminal Gn, and the discharge control circuit 30, and is configured to be under the control of the first control signal input by the first control signal terminal Gn.
  • the data voltage Vdata (not shown) is written to the memory circuit 20 to store the data voltage in the memory circuit 20, and the control driver circuit 10 is turned on to drive the light-emitting element to emit light.
  • the data write circuit 50 can be turned on in response to the first control signal provided by the first control signal terminal Gn, so that the data voltage can be written to the control terminal 130 (first node A) of the drive circuit 10, and the data voltage is applied.
  • Vdata is stored in the above-described storage circuit 20 to generate a drive current for driving the light-emitting element to emit light based on the data voltage Vdata.
  • the magnitude of the data voltage Vdata determines the luminance of the pixel unit (ie, the grayscale used for display).
  • a pixel circuit 100' is also provided.
  • the structure of the pixel circuit 100' is similar to that of the pixel circuit 100 shown in FIG. 2A, and will not be described herein again.
  • the difference is that the discharge control circuit 30 included in the pixel circuit 100' can also be combined with the initial voltage terminal Vinit and the
  • the three control signal terminals are connected and configured to respond to the third control signal provided by the third control signal terminal to connect the first node A and the third node C with the initial voltage terminal Vinit (eg, provide low
  • the initial voltage of the level eg, 0V or ground
  • the second terminal 120 of the driver circuit eg, a high level during the last illumination period discharges to the initial voltage terminal Vinit.
  • the first node A, the second node B, and the third node C do not represent the actually existing components, but represent the convergence points of the related circuit connections in the circuit diagram, so as to describe .
  • the pixel circuit provided by the above embodiment of the present disclosure can eliminate the influence of the threshold voltage drift of the driving circuit in the pixel circuit on the driving current of the light emitting element, thereby improving the display effect of the light emitting element and prolonging the service life of the light emitting element.
  • the pixel circuit 100 shown in FIG. 2A may be embodied as the pixel circuit structure shown in FIG. 3A.
  • the pixel circuit 100 includes a driving transistor DRT and first to fourth transistors T1, T2, T3, T4 and includes a storage capacitor Cst and a light emitting element (ie, an OLED).
  • the first to fourth transistors T1, T2, T3, and T4 are used as switching transistors.
  • the light-emitting elements may be of various types, such as top emission, bottom emission, etc., and may emit red, green, blue, or white light, etc., which is not limited by the embodiments of the present disclosure.
  • each of the switching transistors may employ an N-type transistor
  • the driving transistor DRT may employ a P-type transistor.
  • the N-type transistor is turned on in response to the high-level signal, turned off in response to the low-level signal
  • the P-type transistor is turned on in response to the low-level signal, and turned off in response to the high-level signal, the following embodiment being the same ,No longer.
  • the drive circuit 10 includes a drive transistor DRT.
  • the control terminal (ie, the gate) of the driving transistor DRT is connected to the memory circuit 10 as the control terminal 130 of the driving circuit 10.
  • the first electrode of the driving transistor DRT is connected as the first terminal 120 of the driving circuit 10 to the first end of the light emitting device, and the driving transistor
  • the second pole of the DRT is connected to the first voltage terminal VDD as the first terminal 110 of the driving circuit 10, wherein the second end of the light emitting element is connected to the second voltage terminal VEE to receive the second voltage.
  • the data write circuit 50 includes a first transistor T1.
  • the control electrode of the first transistor T1 is connected to the first control signal terminal Gn to receive the first control signal, the first electrode of the first transistor T1 is connected to the storage circuit 20 (third node C), and the second pole of the first transistor T1 is connected to the data.
  • the signal input terminal DATA receives the data voltage.
  • the memory circuit 20 includes a storage capacitor Cst.
  • the first end of the storage capacitor Cst is connected to the control electrode (first node A) of the driving transistor T1, and the second end of the storage capacitor Cst is connected to the first pole (third node C) of the first transistor T1.
  • the memory control circuit 40 includes a second transistor T2, the control electrode of the second transistor T2 is coupled to the second control signal terminal Gn-1 to receive the second control signal, and the first electrode of the second transistor T2 is coupled to the first electrode of the driving transistor DRT ( The second node B), the second pole of the second transistor T2 is connected to the first end of the storage capacitor Cst.
  • the discharge control circuit 30 includes a third transistor T3 and a fourth transistor T4.
  • the control electrode of the third transistor T3 is connected to the third control signal terminal Gn-2 to receive the third control signal, the first electrode of the third transistor T3 is connected to the first voltage terminal VDD, and the second electrode of the third transistor T3 is connected to the storage capacitor Cst.
  • the control electrode of the fourth transistor T4 is connected to the third control signal terminal Gn-2 to receive the third control signal, the first electrode of the fourth transistor T4 is connected to the first voltage terminal VDD, and the second electrode of the fourth transistor T4 is connected to the storage capacitor Cst.
  • T1, T2, T3, and T4 are all N-type transistors.
  • each lighting period of the light emitting element includes three stages.
  • the first voltage terminal VDD provides a first voltage Vdd
  • the first voltage Vdd is a low level (eg, the low level is 0V or a ground voltage)
  • the third control signal terminal Gn-2 is input.
  • the three control signals are controlled to turn on the third transistor T3 and the fourth transistor T4, and the first pole of the control driving transistor DRT is discharged to the first voltage terminal VDD until the voltage of the first pole of the driving transistor DRT reaches the threshold voltage Vth.
  • the second control signal terminal Gn-1 inputs a second control signal to control the second transistor T2 to be turned on, and stores the threshold voltage Vth to the storage capacitor Cst.
  • the first control signal terminal Gn inputs the first control signal to control the first transistor T1 to be turned on, the first end of the storage capacitor Cst is coupled to the sum of the data voltage and the threshold voltage Vdata+Vth, and the driving transistor DRT is turned on.
  • the light-emitting element starts to emit light.
  • the voltage of the first pole of the driving transistor DRT reaches the threshold voltage Vth, and the input of the data signal input terminal
  • the data voltage is Vdata; for example, when the first voltage Vdd supplied from the first voltage terminal VDD is not 0 (for example, ⁇ ), the voltage of the first pole of the driving transistor DRT reaches the threshold voltage Vth+ ⁇ (ie, the driving is satisfied)
  • the voltage difference between the first pole and the gate of the transistor DRT reaches the threshold voltage Vth), and the magnitude of the data voltage input at the input end of the data signal is Vdata- ⁇ , so that the voltage of the gate of the driving transistor can be guaranteed to be Vdata+Vth.
  • the first voltage provided by the first voltage terminal VDD and the second voltage provided by the second voltage terminal VEE are changed such that the control terminal of the driving circuit can discharge to the first voltage terminal VDD.
  • the drive transistor is implemented as an N-type transistor, it is charged.
  • the first voltage is changed from a high level to a low level, and the second voltage is changed from a low level to a high level.
  • the first voltage is kept at a low level, and the first voltage is maintained.
  • the second level is a high level; in the third phase, the first voltage is changed from a low level in the second stage to a high level, and the second voltage is changed from a high level in the second stage to a low level.
  • Level Level.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • the examples of the embodiments of the present disclosure are exemplified by a thin film transistor.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the first voltage terminal VDD, the second voltage terminal VEE, the first control signal terminal Gn, the second control signal terminal Gn-1, and the third control signal terminal Gn- can be used in each illumination period of the light emitting element.
  • 2 and the data signal input terminal DATA respectively provide the signal timing shown in FIG. 4 to control the light-emitting element to emit light.
  • the third control signal terminal Gn-2 is input with a high level, and the third transistor T3 and the fourth transistor T4 are turned on, and the first voltage terminal VDD is input.
  • the first voltage Vdd changes from a high level to a low level (for example, the low level is 0V or ground)
  • the second voltage input from the second voltage terminal VEE changes from a low level to a high level
  • the first node A and the third node C are connected to the first voltage terminal VDD, and are at a low level.
  • the second electrode (eg, the drain) of the driving transistor DRT is short-circuited with the gate, and the driving transistor DRT becomes a diode structure due to the previous light emission.
  • the first pole (eg, the source) of the period driving transistor DRT is at a high level, so the first pole of the driving transistor DRT is discharged to the first voltage terminal VDD until the voltage difference between the first pole and the gate of the driving transistor DRT reaches Until the threshold voltage Vth, for example, when the first voltage supplied from the first voltage terminal VDD is 0V, the voltage of the second node B reaches the threshold voltage Vth.
  • the second control signal terminal Gn-1 is input to the high level, the second transistor T2 is turned on, the second node B is turned on with the first node A, and the voltage of the second node B is The threshold voltage Vth is stored to the first end of the storage capacitor Cst, that is, the first node A.
  • the first control signal terminal Gn inputs a high level
  • the first transistor T1 is turned on
  • the first voltage input from the first voltage terminal VDD changes from a low level to a high level
  • a second The second voltage input from the voltage terminal VEE changes from a high level to a low level
  • the second end of the storage capacitor Cst writes a data voltage Vdata
  • the first end of the storage capacitor Cst is coupled to a sum of the data voltage and the threshold voltage Vdata+Vth That is, the voltage of the first node A is Vdata+Vth
  • the driving transistor DRT is turned on, and the light emitting element starts to emit light.
  • the first voltage charges the second node B through the driving transistor DRT, and the voltage of the second node B is charged to the first voltage Vdd.
  • the value of the driving current I OLED flowing through the light emitting element can be obtained according to the following formula:
  • I OLED 1/2*K(Vgs-Vth) ⁇ 2
  • Vgs is the voltage between the gate and the source of the driving transistor DRT, that is, the voltage between the first node A and the second node B.
  • Vgs-Vth Vdata+Vth-Vdd-Vth
  • the light-emitting element when the light-emitting element emits light, its current I is related to the data voltage Vdata and the first voltage Vdd, and is no longer related to the threshold voltage Vth of the driving transistor DRT, so that the threshold voltage of the driving transistor can be eliminated to the light-emitting element.
  • the influence of the driving current can improve the display effect of the light-emitting element and prolong the service life of the light-emitting element.
  • the pixel circuit provided by the embodiment of the present disclosure controls the second end discharge of the drive circuit 10 by the storage circuit 20 connected to the drive circuit 10, and the discharge control circuit 30 connected to the storage circuit 20, and is controlled by the storage control circuit 40.
  • the storage circuit 20 stores the voltage after the discharge of the drive circuit 10, and finally, when the data write circuit 50 writes the data voltage, the drive circuit 10 can be turned on by the data voltage and the voltage stored in the storage circuit 20.
  • the driving circuit 10 drives the light emitting element to emit light
  • the voltage of the control terminal of the driving circuit 10 can reach the sum of the data voltage and the stored threshold voltage, so that the current of the light emitting element is not related to the threshold voltage of the driving circuit 10, thereby being able to avoid
  • the influence of the change in the threshold voltage of the drive circuit 10 on the drive current of the light-emitting element improves the light-emitting effect of the light-emitting element and prolongs the life of the light-emitting element.
  • Embodiments of the present disclosure include, but are not limited to, the configuration in FIG. 3A.
  • transistors in the pixel circuit 100 may also adopt N-type transistors.
  • the first pole can be the source and the second pole can be the drain.
  • the anode of the light-emitting element in the pixel circuit 100 is connected to the first voltage terminal VDD to receive the first voltage.
  • the anodes of the light-emitting elements can be electrically connected to the same voltage terminal (for example, a common voltage terminal), that is, by a common anode connection.
  • the driving transistor DRT when it adopts an N-type transistor, it can be fabricated by using an IGZO (Indium Gallium Zinc Oxide) preparation process, compared to the LTPS (Low Temperature Poly). Silicon, low temperature polysilicon) preparation process can effectively reduce the size of the drive transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly
  • the pixel circuit 100' shown in Fig. 2B can be embodied as the pixel circuit structure shown in Fig. 3C.
  • the structure of the pixel circuit is similar to that of the pixel circuit shown in FIG. 3A, except that the discharge control circuit 30 includes a first transistor of the third transistor T3 and the fourth transistor T4 connected to the initial voltage terminal. Vinit.
  • the initial voltage terminal Vinit provides a low level (for example, the low level is 0V or a ground voltage)
  • the third control signal terminal Gn-2 inputs a third control signal to control the third transistor T3 and the third
  • the four transistor T4 is turned on, and the first pole of the control driving transistor DRT is discharged to the initial voltage terminal Vinit until the voltage difference between the first pole and the gate of the driving transistor DRT reaches the threshold voltage Vth.
  • the working principle of the pixel circuit shown in FIG. 3B is similar to the working principle of the pixel circuit shown in FIG. 3A, except that the first node A to the third node C in the pixel circuit shown in FIG. 3A are The first stage is a process of discharging, and the first node A to the third node C in the pixel circuit shown in FIG. 3B are charging processes in the first stage.
  • the first stage is a process of discharging, and the first node A to the third node C in the pixel circuit shown in FIG. 3B are charging processes in the first stage.
  • the first node A and the third node C are charged to the second voltage Vss in the first stage, and the second node B is charged to Vss-Vth, so that in the second stage, Writing the voltage of the second node B with the threshold voltage Vth to the first node A, in the third stage, by the coupling of the capacitor, the data voltage Vdata can be written into the first node A, so that at this stage, the first The voltage of node A is Vdata+Vss-Vth.
  • the value of the driving current I OLED flowing through the light emitting element can be obtained according to the following formula:
  • I OLED 1/2*K(Vgs-Vth) ⁇ 2
  • the driving transistor DRT When the voltage of the first terminal of the storage capacitor Cst is Vdata+Vss-Vth, that is, the voltage of the gate (first node A) of the driving transistor DRT is Vdata+Vss-Vth, and the driving transistor DRT is turned on, at this time, the driving transistor is The voltage of one pole (source) is Vdd, which can be obtained by substituting it into the above formula:
  • Vgs-Vth Vdata+Vss-Vth-Vdd-Vth
  • the light emitting element when the light emitting element emits light, its current I is related to the data voltage Vdata, the first voltage Vdd and the second voltage Vss, and is no longer related to the threshold voltage Vth of the driving transistor DRT, so that the driving transistor can be eliminated.
  • the influence of the threshold voltage on the driving current of the light-emitting element can improve the display effect of the light-emitting element and prolong the service life of the light-emitting element.
  • the operation of the pixel circuit shown in FIG. 3C is similar to that of the pixel circuit shown in FIG. 3A, except that in the first stage, the first node A and the third node C are discharged through the initial voltage terminal Vinit. I will not repeat them here.
  • An embodiment of the present disclosure further provides a display panel including a plurality of pixel units arranged in an array.
  • the plurality of pixel units each include the pixel circuit 100 or the pixel circuit 100' and the light-emitting element L provided in the above embodiment.
  • FIG. 5A is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 1000 of the embodiment of the present disclosure includes a plurality of pixel units P arranged in an array.
  • the plurality of pixel units P each include the pixel circuit 100/100' and the light-emitting element L provided by the above-described embodiments of the present disclosure, for example, including the pixel circuit shown in Fig. 3A, Fig. 3B, or Fig. 3C.
  • the foregoing embodiment of the pixel circuit 100 To avoid redundancy, details are not described herein again.
  • the display panel 1000 also includes a plurality of scan lines.
  • the plurality of scan lines are driven by a gate drive circuit (not shown).
  • a plurality of pixel units are arranged in a plurality of rows, and a first control signal terminal Gn of the data writing circuit 50 of the pixel circuit 100 of the nth (n is an integer greater than 3) row pixel unit is connected to the nth row scanning line,
  • the memory control circuit 40 of the pixel circuit 100 of the n rows of pixel cells is connected to the n-1th row scanning line, and the discharge control circuit 30 of the pixel circuit 100 of the nth row of pixel cells is connected to the n-2th row of scanning lines.
  • the n-1th row scanning line is also connected to the first control signal terminal Gn of the data writing circuit 50 of the pixel circuit 100 of the pixel unit of the n-1th row.
  • the n-2th row scanning line is also connected to the first control signal terminal Gn of the data writing circuit 50 of the pixel circuit 100 of the pixel unit of the n-2th row. This simplifies the layout space around the display panel, enabling the development of high-resolution display panels.
  • the light emitting element L may be an organic light emitting diode or a quantum dot light emitting diode or the like
  • the corresponding display panel is an OLED display panel or a QLED display panel.
  • the OLED is taken as an example, and the corresponding description is also applicable to the QLED.
  • the display panel 1000 further includes a voltage generating circuit 200.
  • the voltage generating circuit 200 is coupled to the pixel circuit 100/100' in the pixel unit P, such as in a power management integrated circuit in the module driving circuitry.
  • the voltage generating circuit 200 is coupled to the first voltage terminal VDD and/or the second voltage terminal VEE of the pixel circuit 100/100' and configured to correspondingly change the first voltage and/or the second voltage provided by the first voltage terminal VDD. The magnitude of the second voltage provided by the voltage terminal VEE.
  • the voltage generating circuit 200 changes the first voltage and/or the second voltage, for example, controlling the first voltage to a low level and the second voltage to a high level to control the driving circuit 10.
  • the second terminal 120 discharges to the first voltage terminal VDD; in the third phase, the voltage generating circuit 200 changes the first voltage and the second voltage again, for example, controlling the first voltage to a high level and the second voltage to Low level to allow the drive circuit 10 to conduct to drive the light emitting elements to begin to emit light.
  • the following is the same as the embodiment, and will not be described again.
  • FIG. 5B is a schematic block diagram of another display panel according to an embodiment of the present disclosure.
  • the display panel 11 is disposed in the display device 1 and is electrically connected to the gate driver 12, the timing controller 13, and the data driver 14.
  • the display panel 11 includes a pixel unit P defined according to a plurality of scan lines GL and a plurality of data lines DL; a gate driver 12 for driving a plurality of scan lines GL; and a data driver 14 for driving a plurality of data lines DL;
  • the controller 13 is for processing the image data RGB input from the outside of the display device 1, supplying the processed image data RGB to the data driver 14, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14, to The gate driver 12 and the data driver 14 are controlled.
  • the display panel 11 includes a plurality of pixel units P including any of the pixel circuits 100 or pixel circuits 100' provided in the above embodiments.
  • a pixel circuit as shown in any of Figures 3A-3C is included.
  • the display panel 11 further includes a plurality of scanning lines GL and a plurality of data lines DL.
  • the plurality of scan lines are correspondingly connected to the pixel circuit 100 of each row of pixel units or the data write circuit 50 in the pixel circuit 100', the memory control circuit 30, and the discharge control circuit 40 to respectively provide a first control signal, and a second
  • the connection manner of the multiple scan lines can be referred to the related description of the example shown in FIG. 5A, and details are not described herein again.
  • the pixel unit P is disposed at an intersection area of the scanning line GL and the data line DL.
  • each pixel unit P is connected to three scanning lines GL (providing a first control signal, a second control signal, and a third control signal, respectively), a data line DL, and a first voltage for providing The first voltage line, the second voltage line for providing the second voltage, or further includes an initial voltage line (not shown) for providing an initial voltage.
  • the first voltage line or the second voltage line can be replaced with a corresponding common electrode (eg, a common anode or a common cathode). It should be noted that only a part of the pixel unit P, the scanning line GL, and the data line DL are shown in FIG. 5B. It should be noted that the following embodiments are the same as the above, and are not described again.
  • the plurality of pixel units P are arranged in a plurality of rows, and the first control signal terminal Gn of the data writing circuit 50 of each row of pixel units P is connected to the same scanning line GL, and the storage control of the pixel circuits of each row of pixel units P is performed.
  • the circuit 30 and the discharge control circuit 40 are respectively connected to the other two scanning lines GL to receive the first control signal and the second control signal.
  • the data line DL of each column is connected to the data write circuit 50 in the column of pixel circuits 10 to provide a data voltage.
  • the gate driver 12 supplies a plurality of strobe signals to the plurality of scan lines GL in accordance with a plurality of scan control signals GCS derived from the timing controller 13.
  • the plurality of strobe signals include a first control signal, a second control signal, and a third control signal. These signals are supplied to each of the pixel units P through a plurality of scanning lines GL.
  • the data driver 14 converts the digital image data RGB input from the timing controller 13 into a data signal in accordance with a plurality of data control signals DCS derived from the timing controller 13 using the reference gamma voltage.
  • the data driver 14 supplies the converted data signals to the plurality of data lines DL.
  • the timing controller 13 processes the externally input image data RGB to match the size and resolution of the display panel 11, and then supplies the processed image data to the data driver 14.
  • the timing controller 13 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using a synchronization signal (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device.
  • the timing controller 13 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14, respectively, for control of the gate driver 12 and the data driver 14.
  • the data driving device 14 may be connected to the plurality of data lines DL to provide the data voltage Vdata; and may also be connected to the plurality of first voltage lines, the plurality of second voltage lines, and/or the plurality of initial voltage lines to provide respectively The first voltage, the second voltage, and/or the initial voltage.
  • the gate driver 12 and the data driver 14 can be implemented as a semiconductor chip.
  • the display device 1 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display panel 1000 or the display panel 11 provided in this embodiment can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a virtual reality display device, and the like. Or in the part.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a virtual reality display device, and the like. Or in the part.
  • the display panel provided by the embodiment of the present disclosure has a good display effect and a high lifetime, and thus has high display performance.
  • FIG. 6 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.
  • the electronic device 10000 of the embodiment of the present disclosure includes the display panel 1000 provided by the above-described embodiments of the present disclosure, for example, including the display panel 1000 illustrated in FIG. 5A or the display panel 11 illustrated in FIG. 5B.
  • the electronic device 10000 refer to the embodiment of the foregoing display panel. To avoid redundancy, details are not described herein again.
  • the electronic device 10000 provided in this embodiment may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a virtual reality device, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a virtual reality device, and the like.
  • the electronic device provided by the embodiment of the present disclosure has a good display effect and a high lifetime, and thus has high performance.
  • Embodiments of the present disclosure also provide a driving method of a pixel circuit, which can be used to drive a pixel circuit provided by any of the embodiments of the present disclosure.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • the driving method of the pixel circuit shown in FIG. 3A will be described as an example.
  • the driving method includes steps S1-S3.
  • Step S1 controlling the discharge of the second end of the driving circuit by the discharge control circuit such that the voltage of the second end of the driving circuit is based on the threshold voltage of the driving circuit.
  • Step S2 controlling the storage circuit to store the threshold voltage through a storage control circuit.
  • Step S3 writing a data voltage to the storage circuit through the data writing circuit, and controlling the driving circuit to be turned on based on the data voltage stored by the storage circuit and the threshold voltage to drive the light emitting element to emit light.
  • the driving circuit 10 includes a driving transistor DRT, and a control electrode (ie, a gate) of the driving transistor DRT is connected to the memory circuit 20.
  • the first electrode of the driving transistor DRT is connected to the first end of the light emitting element, and the driving transistor DRT
  • the second pole is connected to the first voltage terminal VDD, wherein the second end of the light emitting element is connected to the second voltage terminal VEE.
  • the data writing circuit 50 includes a first transistor T1.
  • the control electrode of the first transistor T1 is connected to the first control signal terminal Gn.
  • the first electrode of the first transistor T1 is connected to the memory circuit 20, and the second electrode of the first transistor T1 is connected to the data signal.
  • Input DATA is connected to the first transistor T1.
  • the storage circuit 20 includes a storage capacitor Cst.
  • the first end of the storage capacitor Cst is connected to the control electrode of the driving transistor T1, and the second end of the storage capacitor Cst is connected to the first electrode of the first transistor T1.
  • the storage control circuit 40 includes a second transistor T2.
  • the control electrode of the second transistor T2 is connected to the second control signal terminal Gn-1.
  • the first electrode of the second transistor T2 is connected to the first electrode of the driving transistor DRT, and the second transistor T2 is The second pole is connected to the first end of the storage capacitor Cst.
  • the discharge control circuit 30 includes a third transistor T3 and a fourth transistor T4.
  • the control electrode of the third transistor T3 is connected to the third control signal terminal Gn-2, the first electrode of the third transistor T3 is connected to the first voltage terminal VDD, and the second electrode of the third transistor T3 is connected to the second terminal of the storage capacitor Cst.
  • the control electrode of the fourth transistor T4 is connected to the third control signal terminal Gn-2, the first electrode of the fourth transistor T4 is connected to the first voltage terminal VDD, and the second electrode of the fourth transistor T4 is connected to the first terminal of the storage capacitor Cst.
  • each of the light emitting periods of the light emitting element includes three stages.
  • control discharge control circuit 40 is turned on, and the second terminal 120 of the control drive circuit 10 is discharged to the first voltage terminal VDD until the voltage of the second terminal of the drive circuit 10 reaches the threshold voltage.
  • control storage control circuit 30 is turned on to store the threshold voltage in the memory circuit 20.
  • the first control signal terminal inputs a first control signal to control the data writing circuit 50 to be turned on, the first end of the storage circuit 20 is coupled to the sum of the data voltage and the threshold voltage, and the driving circuit 10 is turned on, and the light emitting element Glowing.
  • the driving method further includes: changing the first voltage in the first stage to control the second end 120 of the driving circuit 10 to discharge to the first voltage terminal VDD; in the third stage, changing the first time again A voltage is applied to allow the driving circuit to be turned on to drive the light emitting element to emit light.
  • the second end of the light emitting element is coupled to the second voltage terminal to receive the second voltage
  • the driving method further includes: changing the first voltage and the second voltage in the first stage to control the driving circuit 10
  • the second terminal 120 discharges to the first voltage terminal VDD (for example, when the driving transistor is implemented as an N-type transistor, for charging); in the third phase, the first voltage and the second voltage are changed again to allow the driving circuit 10 to conduct
  • the light-emitting element L is driven to emit light.
  • the first voltage is changed from a high level to a low level, and the second voltage is changed from a low level to a high level; in the third phase, the first voltage is applied The low voltage is changed from a low level in the first phase and the second phase to a high level, and the second voltage is changed from a high level in the first phase and the second phase to a low level.
  • the third control signal input by the third control signal terminal Gn-2 controls the third transistor T3 and the fourth transistor T4 to be turned on, and controls the first pole of the driving transistor DRT to the first voltage terminal VDD. Discharge until the voltage at the second end of the drive circuit 10 reaches the threshold voltage or until the voltage difference between the first pole and the gate of the drive transistor DRT reaches the threshold voltage Vth.
  • the voltage of the first pole of the driving transistor DRT reaches the threshold voltage Vth, and the data voltage input to the data signal input terminal is Vdata; for example, at the first voltage end
  • the first voltage supplied by VDD is not 0 (for example, ⁇ )
  • the voltage of the first pole of the driving transistor DRT reaches the threshold voltage Vth+ ⁇
  • the magnitude of the data voltage input at the input end of the data signal is Vdata- ⁇ . Therefore, it is possible to ensure that the voltage of the gate of the driving transistor is Vdata+Vth.
  • the second control signal input by the second control signal terminal Gn-1 controls the second transistor T2 to be turned on, and stores the threshold voltage Vth to the storage capacitor Cst.
  • the first control signal input by the first control signal terminal Gn controls the first transistor T1 to be turned on, and the first end of the storage capacitor Cst is coupled to the sum of the data voltage and the threshold voltage Vdata+Vth, and the driving transistor DRT is turned on.
  • the light-emitting element starts to emit light.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the first voltage terminal VDD, the second voltage terminal VEE, the first control signal terminal Gn, the second control signal terminal Gn-1, the third control signal terminal Gn-2, and the data may be used in each lighting period of the light emitting element.
  • the signal input terminal DATA respectively provides the signal timing shown in FIG. 4 to control the light-emitting element to emit light.
  • the third control signal terminal Gn-2 is input with a high level, and the third transistor T3 and the fourth transistor T4 are turned on, and the first voltage terminal VDD is input.
  • the first voltage changes from high to low
  • the second voltage input from the second voltage terminal VEE changes from low to high.
  • the first node A and the third node C are connected to the first voltage terminal VDD, being low level
  • the second pole (eg, the drain) of the driving transistor DRT is shorted to the gate, and the driving transistor DRT becomes a diode.
  • the first pole (eg, the source) of the driving transistor DRT is at a high level during the previous lighting period, so that the first pole of the driving transistor DRT discharges to the first voltage terminal VDD until the first pole of the driving transistor DRT
  • the voltage difference between the gate and the gate reaches the threshold voltage of the driving transistor DRT. For example, when the first voltage Vdd supplied from the first voltage terminal VDD is 0 V, the voltage of the second node B reaches the threshold voltage Vth.
  • the second control signal terminal Gn-1 is input to the high level, the second transistor T2 is turned on, the second node B is turned on with the first node A, and the threshold voltage Vth is stored to the storage capacitor.
  • the first control signal terminal Gn inputs a high level
  • the first transistor T1 is turned on
  • the first voltage Vdd input from the first voltage terminal VDD changes from low to high
  • the second voltage terminal VEE The input second voltage is changed from high to low
  • the second end of the storage capacitor Cst is written with the data voltage Vdata
  • the first end of the storage capacitor Cst is coupled to the sum of the data voltage and the threshold voltage Vdata+Vth, that is, the first node A
  • the driving transistor DRT is turned on, and the light emitting element starts to emit light.
  • the first voltage Vdd charges the second node B through the driving transistor DRT, and the voltage of the second node B is charged to the first voltage Vdd.
  • the value of the driving current I OLED flowing through the light emitting element can be obtained according to the following formula:
  • I OLED 1/2*K(Vgs-Vth) ⁇ 2
  • Vgs is the voltage between the gate and the source of the driving transistor DRT, that is, the voltage between the first node A and the second node B.
  • Vgs-Vth Vdata+Vth-Vdd-Vth
  • the discharge control circuit connected to the storage circuit controls the discharge of the drive circuit
  • the storage control circuit connected to the drive circuit controls the storage circuit to store the voltage after the discharge of the drive circuit
  • the driving circuit can be turned on by the data voltage and the voltage stored in the storage circuit, whereby when the driving circuit drives the light emitting element to emit light, the voltage of the control terminal of the driving circuit can reach the data voltage and the stored voltage.
  • the sum is such that the current of the light-emitting element is not related to the threshold voltage of the driving circuit, so that the influence of the variation of the threshold voltage of the driving circuit on the current of the light-emitting element can be avoided, the light-emitting effect of the light-emitting element can be improved, and the life of the light-emitting element can be prolonged.

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Abstract

一种像素电路(100,100 ')及其驱动方法、显示面板(1000)及电子设备(10000)。像素电路(100,100 ')包括驱动电路(10)、存储电路(20)、放电控制电路(30)、存储控制电路(40)和数据写入电路(50)。驱动电路(10)包括控制端(130)、第一端(110)和第二端(120)，配置为控制驱动发光元件(OLED)发光的驱动电流；存储电路(20)与驱动电路(10)的控制端(130)连接；放电控制电路(30)配置为控制存储电路(20)两端的电压值，以及控制驱动电路(10)的第二端(120)放电；存储控制电路(40)配置为控制存储电路(20)存储驱动电路(10)的电压；数据写入电路(50)配置为响应于第一控制信号端(Gn)输入的第一控制信号，将数据信号输入端(DATA)提供的数据电压(Vdata)写入到存储电路(20)以将数据电压(Vdata)存储在存储电路(20)，控制驱动电路(10)导通，以驱动发光元件(OLED)发光。可以改善发光元件(OLED)的发光效果，延长发光元件(OLED)的使用寿命。

Description

像素电路及其驱动方法、显示面板及电子设备
本申请要求于2017年12月13日递交的中国专利申请第201711332550.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及一种像素电路及其驱动方法、显示面板及电子设备。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素电路中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一实施例提供一种像素电路，包括驱动电路、存储电路、放 电控制电路、存储控制电路和数据写入电路。所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第一端配置为从第一电压端接收第一电压；所述存储电路与所述驱动电路的控制端连接；所述放电控制电路与所述存储电路以及所述驱动电路的控制端连接，且配置为控制所述存储电路两端的电压值，以及控制所述驱动电路的第二端放电；所述存储控制电路与所述驱动电路的控制端、所述驱动电路的第一端以及所述存储电路连接，且配置为控制所述存储电路存储所述驱动电路的第二端的电压；所述数据写入电路与所述存储电路、数据信号输入端、第一控制信号端以及所述放电控制电路连接，且配置为响应于所述第一控制信号端输入的第一控制信号，将所述数据信号输入端提供的所述数据电压写入到所述存储电路以将所述数据电压存储在所述存储电路，控制所述驱动电路导通，以驱动所述发光元件发光。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括驱动晶体管；所述驱动晶体管的控制极连接所述存储电路，所述驱动晶体管的第一极连接所述发光元件的第一端，所述驱动晶体管的第二极连接所述第一电压端，其中，所述发光元件的第二端连接第二电压端。
例如，在本公开一实施例提供的像素电路中，所述数据写入电路包括第一晶体管；所述第一晶体管的控制极连接所述第一控制信号端以接收所述第一控制信号，所述第一晶体管的第一极连接所述存储电路，所述第一晶体管的第二极连接所述数据信号输入端以接收所述数据电压。
例如，在本公开一实施例提供的像素电路中，所述存储电路包括存储电容；所述存储电容的第一端连接所述驱动晶体管的控制极，所述存储电容的第二端连接所述第一晶体管的第一极。
例如，在本公开一实施例提供的像素电路中，所述存储控制电路包括第二晶体管；所述第二晶体管的控制极连接第二控制信号端以接收第二控制信号，所述第二晶体管的第一极连接所述驱动晶体管的第一极，所述第二晶体管的第二极连接所述存储电容的第一端。
例如，在本公开一实施例提供的像素电路中，所述放电控制电路包括第三晶体管和第四晶体管；所述第三晶体管的控制极连接第三控制信号端以接 收第三控制信号，所述第三晶体管的第一极连接所述第一电压端，所述第三晶体管的第二极连接所述存储电容的第二端；所述第四晶体管的控制极连接所述第三控制信号端以接收所述第三控制信号，所述第四晶体管的第一极连接所述第一电压端，所述第四晶体管的第二极连接所述存储电容的第一端。
本公开至少一实施例还提供一种显示面板，包括阵列布置的多个像素单元，其中，所述像素单元每个包括本公开任一实施例提供的像素电路以及发光元件。
例如，本公开一实施例提供的显示面板，还包括多条扫描线。所述多个像素单元排列为多行，第n行像素单元的像素电路的数据写入电路的第一控制信号端连接到第n行扫描线，第n行像素单元的像素电路的存储控制电路连接到第n-1行扫描线，第n行像素单元的像素电路的放电控制电路连接到第n-2行扫描线；所述第n-1行扫描线还与第n-1行的像素单元的像素电路的数据写入电路的第一控制信号端连接；所述第n-2行扫描线还与第n-2行的像素单元的像素电路的数据写入电路的第一控制信号端连接；其中，n为大于3的整数。
例如，在本公开一实施例提供的显示面板中，所述发光元件为有机发光二极管。
例如，本公开一实施例提供的显示面板，还包括电压发生电路。所述电压发生电路与所述第一电压端和/或第二电压端连接，且配置为对应地改变所述第一电压端提供的第一电压和/或所述第二电压端提供的第二电压的大小。
本公开至少一实施例还提供一种电子设备，包括本公开任一实施例提供的显示面板。
本公开至少一实施例还提供一种像素电路的驱动方法，包括：通过所述放电控制电路控制所述驱动电路的第二端放电，使得所述驱动电路的第二端的电压基于所述驱动电路的阈值电压；通过所述存储控制电路控制所述存储电路存储所述阈值电压；通过所述数据写入电路将数据电压写入到所述存储电路，基于所述存储电路存储的数据电压和所述阈值电压，控制所述驱动电路导通，以驱动所述发光元件发光。
例如，在本公开一实施例提供的像素电路的驱动方法中，所述发光元件 的每个发光周期包括三个阶段，所述驱动方法包括：在第一阶段，控制所述放电控制电路导通，控制所述驱动电路的第二端向所述第一电压端放电，直至所述驱动电路的第二端的电压达到阈值电压为止；在第二阶段，控制所述存储控制电路导通，将所述阈值电压存储至所述存储电路中；在第三阶段，所述第一控制信号端输入所述第一控制信号以控制所述数据写入电路导通，所述存储电容的第一端耦合为所述数据电压与所述阈值电压之和，所述驱动电路导通，所述发光元件发光。
例如，本公开一实施例提供的像素电路的驱动方法，还包括：在所述第一阶段，改变所述第一电压，以控制所述驱动电路的第二端向所述第一电压端放电；在所述第三阶段，再次改变所述第一电压，以允许所述驱动电路导通以驱动所述发光元件发光。
例如，在本公开一实施例提供的像素电路的驱动方法中，所述发光元件的第二端连接第二电压端以接收第二电压，所述驱动方法还包括：在所述第一阶段，改变所述第一电压和所述第二电压，以控制所述驱动电路的第二端向所述第一电压端放电；在所述第三阶段，再次改变所述第一电压和所述第二电压，以允许所述驱动电路导通以驱动所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图；
图1B为另一种2T1C像素电路的示意图；
图2A为本公开一实施例提供的一种像素电路的结构示意图；
图2B为本公开一实施例提供的另一种像素电路的结构示意图；
图3A为图2A中所示的像素电路的一种具体实现示例的电路示意图；
图3B为图2A中所示的像素电路的另一种具体实现示例的电路示意图；
图3C为图2B中所示的像素电路的一种具体实现示例的电路示意图；
图4为本公开一实施例提供的一种像素电路的信号时序图；
图5A为本公开一实施例提供的一种显示面板的方框示意图；
图5B为本公开一实施例提供的另一种显示面板的示意图；
图6为本公开一实施例提供的一种电子设备的方框示意图；以及
图7为本公开一实施例提供的一种像素电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的实施例的限制。
在OLED显示面板中，由于子像素的OLED在电流的驱动作用下发光，因此OLED的电流稳定性非常重要，直接影响OLED的显示亮度。OLED的驱动电流一般与驱动TFT(Thin Film Transistor，薄膜晶体管)的阈值电压相关，而通过a-Si(Amorphous Silicon，非晶硅)工艺制作的TFT存在阈值电压漂移的问题。即，当有电压作用在TFT的栅源极时，TFT的阈值电压会逐 渐升高，流经TFT的电流会逐渐衰减，这会直接影响与其连接的OLED的亮度和寿命。图1A和图1B分别为示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1，例如源极连接到数据线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(高电压)，漏极连接到发光元件(这里为OLED)的正极端；存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端；OLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据线送入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到第一电压端以接收第一电压Vdd(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，根据需要也可以为P型晶体管，由此控制其导通或截止的扫描信号Scan1的极性进行相应地改变即可。
图1A和图1B所示的像素电路中，驱动晶体管N0具有较大的占空比，这将会加剧驱动晶体管N0的阈值电压的漂移，使得流经驱动晶体管N0的电流逐渐变低，影响OLED的显示亮度。
本公开一实施例提供了一种像素电路，包括驱动电路、存储电路、放电控制电路、存储控制电路和数据写入电路。驱动电路包括控制端、第一端和第二端，且配置为控制驱动发光元件发光的驱动电流，驱动电路的第一端配置为从第一电压端接收第一电压；存储电路与驱动电路的控制端连接；放电控制电路与存储电路以及驱动电路的控制端连接，且配置为控制存储电路两端的电压值，以及控制驱动电路的第二端放电；存储控制电路与驱动电路的控制端、驱动电路的第二端以及存储电路连接，且配置为控制存储电路存储驱动电路第二端的电压；数据写入电路与存储电路、数据信号输入端、第一控制信号端以及放电控制电路连接，且配置为在第一控制信号端输入的第一控制信号的控制下，将数据信号输入端提供的数据电压写入到存储电路以将数据电压存储在存储电路，控制驱动电路导通，以驱动发光元件发光。本公开至少一实施例还提供对应于上述像素电路的驱动方法、显示面板和电子设备。
本公开上述实施例提供的像素电路可以消除像素电路中驱动电路的阈值电压对驱动电流的影响，从而可以改善发光元件的显示效果，延长发光元件的使用寿命。
下面结合附图来描述本公开实施例的像素电路及其驱动方法、显示面板及电子设备。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开实施例提供一种的像素电路100，该像素电路100例如用于驱动显示面板的子像素中的发光元件发光。在本公开的至少一个实施例中，显示面板例如通过玻璃衬底制备，具体结构与制备工艺可以采用本领域中的常规方法，这里不再详述，且本公开的实施例对此不作限制。例如，发光元件可为OLED或QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)等，相应的显示面板为OLED显示面板或QLED显示面板。下面以发光元件为OLED为例进行说明，相应的描述也同样适用于QLED。
图2A为本公开一实施例提供的一种像素电路的结构示意图。如图2A所示，本公开实施例提供的像素电路100包括驱动电路10、存储电路20、放电控制电路30、存储控制电路40和数据写入电路50。
例如，驱动电路10包括控制端130(第一节点A)、第一端110和第二端120(第二节点B)，例如与发光元件(这里为OLED)、第一电压端VDD连接,且配置为控制驱动发光元件发光的驱动电流，驱动电路10的第一端110配置为从第一电压端VDD接收第一电压。例如，在发光阶段，驱动电路100可以向发光元件提供驱动电流以驱动发光元件进行发光，且可以根据需要的“灰度”发光。
存储电路20与驱动电路10的控制端130(第一节点A)连接，且配置为存储数据写入电路50写入的数据电压和/或阈值电压。例如，存储电路20可以存储该数据电压和/或阈值电压并利用存储的数据电压和/或阈值电压对驱动电路10进行控制。例如，在存储电路20包括存储电容的情形下，存储电路20可以将数据写入电路50写入的数据电压以及阈值电压存储在存储电容中，从而在例如发光阶段时可以利用存储的数据电压和/或阈值电压对驱动电路10进行控制。
放电控制电路30与存储电路20(第三节点C)以及驱动电路10的控制端130(第一节点A)连接，且配置为控制存储电路20两端的电压值，和控制驱动电路10的第二端放电。例如，在图2A所示的示例中，该放电控制电路30还与第一电压端VDD以及第三控制信号端(图中未示出)连接，且配置为响应于第三控制信号端提供的第三控制信号，将第一节点A和第三节点C与第一电压端VDD(例如，此时提供低电平(例如，0V(伏)或接地电压)的第一电压)连接，从而使得驱动电路的第二端120(例如，在上一个发光周期内为高电平)向第一电压端VDD放电。例如，在驱动电路10实现为驱动晶体管的情况下，当第二节点B的电压放电至驱动晶体管的阈值电压时截止。
存储控制电路40与驱动电路10的控制端130(第一节点A)、驱动电路10的第二端120(第二节点B)以及存储电路20连接，且配置为控制存储电路20存储驱动电路10放电后的电压。例如，存储控制电路40还与第二 控制信号端(图中未示出)连接，且配置为在第二控制信号端提供的第二控制信号的控制下导通，将驱动电路10放电后的电压(即第二节点B的电压)存储在存储电路20中。
数据写入电路50与存储电路20、数据信号输入端DATA、第一控制信号端Gn及放电控制电路30连接，且配置为在第一控制信号端Gn输入的第一控制信号的控制下，将数据电压Vdata(图中未示出)写入到存储电路20以将数据电压存储在存储电路20，控制驱动电路10导通，以驱动发光元件发光。例如，数据写入电路50可以响应于第一控制信号端Gn提供的第一控制信号而开启，从而可以将数据电压写入驱动电路10的控制端130(第一节点A)，并将数据电压Vdata存储在上述存储电路20中，以根据该数据电压Vdata生成驱动发光元件发光的驱动电流。例如，该数据电压Vdata的大小决定了该像素单元的发光亮度(即用于显示的灰度)。
例如，在图2B所示的示例中，还提供一种像素电路100’。该像素电路100’的结构与图2A中所示的像素电路100的结构类似，在此不再赘述，区别在于：该像素电路100’包括的放电控制电路30还可以与初始电压端Vinit以及第三控制信号端(图中未示出)连接，且配置为响应于第三控制信号端提供的第三控制信号，将第一节点A和第三节点C与初始电压端Vinit(例如，提供低电平(例如，0V或接地电压)的初始电压)连接，从而使得驱动电路的第二端120(例如，在上一个发光周期内为高电平)向初始电压端Vinit放电。
需要注意的是，在本公开实施例的说明中，第一节点A、第二节点B以及第三节点C并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点，以便于描述。
本公开上述实施例提供的像素电路可以消除像素电路中驱动电路的阈值电压漂移对发光元件的驱动电流的影响，从而可以改善发光元件的显示效果，延长发光元件的使用寿命。
图2A中所示的像素电路100的一个示例可以具体实现为图3A所示的像素电路结构。如图3A所示，该像素电路100包括驱动晶体管DRT和第一至第四晶体管T1、T2、T3、T4以及包括存储电容Cst和发光元件(即OLED)。 例如，第一至第四晶体管T1、T2、T3、T4被用作开关晶体管。例如，发光元件可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。例如，在本公开实施例中，各个开关晶体管可以采用N型晶体管，驱动晶体管DRT采用P型晶体管。例如，N型晶体管响应于高电平信号而开启，响应于低电平信号而截止，P型晶体管响应于低电平信号而开启，响应于高电平信号而截止，以下实施例与此相同，不再赘述。
在本公开的一个实施例中，如图3A所示，驱动电路10包括驱动晶体管DRT。驱动晶体管DRT的控制极(即栅极)作为驱动电路10的控制端130连接存储电路10，驱动晶体管DRT的第一极作为驱动电路10的第二端120连接发光元件的第一端，驱动晶体管DRT的第二极作为驱动电路10的第一端110连接第一电压端VDD，其中，发光元件的第二端连接第二电压端VEE以接收第二电压。
数据写入电路50包括第一晶体管T1。第一晶体管T1的控制极连接第一控制信号端Gn以接收第一控制信号，第一晶体管T1的第一极连接存储电路20(第三节点C)，第一晶体管T1的第二极连接数据信号输入端DATA以接收数据电压。
存储电路20包括存储电容Cst。存储电容Cst的第一端连接驱动晶体管T1的控制极(第一节点A)，存储电容Cst的第二端连接第一晶体管T1的第一极(第三节点C)。
存储控制电路40包括第二晶体管T2，第二晶体管T2的控制极连接第二控制信号端Gn-1以接收第二控制信号，第二晶体管T2的第一极连接驱动晶体管DRT的第一极(第二节点B)，第二晶体管T2的第二极连接存储电容Cst的第一端。
放电控制电路30包括第三晶体管T3和第四晶体管T4。第三晶体管T3的控制极连接第三控制信号端Gn-2以接收第三控制信号，第三晶体管T3的第一极连接第一电压端VDD，第三晶体管T3的第二极连接存储电容Cst的第二端。第四晶体管T4的控制极连接第三控制信号端Gn-2以接收第三控制信号，第四晶体管T4的第一极连接第一电压端VDD，第四晶体管T4的第 二极连接存储电容Cst的第一端。在本实施例中，T1、T2、T3、T4均为N型晶体管。
在本公开的实施例的像素电路中，发光元件的每个发光周期包括三个阶段。
在第一阶段，第一电压端VDD提供第一电压Vdd，所述第一电压Vdd为低电平(例如，该低电平为0V或接地电压)，第三控制信号端Gn-2输入第三控制信号以控制第三晶体管T3和第四晶体管T4导通，控制驱动晶体管DRT的第一极向第一电压端VDD放电，直至驱动晶体管DRT的第一极的电压达到阈值电压Vth为止。
在第二阶段，第二控制信号端Gn-1输入第二控制信号以控制第二晶体管T2导通，将阈值电压Vth存储至存储电容Cst。
在第三阶段，第一控制信号端Gn输入第一控制信号以控制第一晶体管T1导通，存储电容Cst的第一端耦合为数据电压与阈值电压之和Vdata+Vth，驱动晶体管DRT导通，发光元件开始发光。
例如，在第一电压端VDD提供的第一电压(即驱动晶体管DRT的栅极的电压)变为0时，驱动晶体管DRT的第一极的电压达到阈值电压Vth为止，数据信号输入端输入的数据电压为Vdata；例如，在第一电压端VDD提供的第一电压Vdd不为0(例如，为δ)时，驱动晶体管DRT的第一极的电压达到阈值电压Vth+δ为止(即满足驱动晶体管DRT的第一极和栅极的电压差达到阈值电压Vth)，此时数据信号输入端输入的数据电压的大小为Vdata-δ，从而可以保证驱动晶体管的栅极的电压为Vdata+Vth。需要注意的是，以下实施例与此相同，不再赘述。
例如，在第一阶段和第二阶段中改变第一电压端VDD提供的第一电压和第二电压端VEE提供的第二电压的大小以使得驱动电路的控制端可以向第一电压端VDD放电(例如，在驱动晶体管实现为N型晶体管时，为充电)。例如，第一阶段中，将第一电压由高电平变为低电平，将第二电压由低电平变为高电平，第二阶段中，保持第一电压为低电平，保持第二电平为高电平；在第三阶段中，将第一电压由第二阶段中的低电平变为高电平，将第二电压由第二阶段中的高电平变为低电平。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例的示例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
基于上述电路结构，可在发光元件的每个发光周期由第一电压端VDD、第二电压端VEE、第一控制信号端Gn、第二控制信号端Gn-1、第三控制信号端Gn-2和数据信号输入端DATA分别提供图4所示的信号时序，以控制发光元件发光。
例如，结合图3A和图4，在第一阶段，即t1时间段，第三控制信号端Gn-2输入高电平，第三晶体管T3和第四晶体管T4导通，第一电压端VDD输入的第一电压Vdd从高电平变为低电平(例如，该低电平为0V或接地)，第二电压端VEE输入的第二电压从低电平变为高电平，第一节点A和第三节点C与第一电压端VDD连接，为低电平，驱动晶体管DRT的第二极(例如漏极)与栅极短接，驱动晶体管DRT变成二极管结构，由于在上一发光周期驱动晶体管DRT的第一极(例如，源极)为高电平，因此驱动晶体管DRT的第一极向第一电压端VDD放电，直至驱动晶体管DRT的第一极与栅极的电压差达到阈值电压Vth为止，例如，在第一电压端VDD提供的第一电压为0V时，第二节点B的电压达到阈值电压Vth。
在第二阶段，即t2时间段，第二控制信号端Gn-1输入高电平，第二晶体管T2导通，第二节点B与第一节点A导通，第二节点B的电压，即阈值电压Vth，存储至存储电容Cst的第一端，即第一节点A。
在第三阶段，即t3时间段，第一控制信号端Gn输入高电平，第一晶体管T1导通，第一电压端VDD输入的第一电压从低电平变为高电平，第二电压端VEE输入的第二电压从高电平变为低电平，存储电容Cst的第二端写入数据电压Vdata，存储电容Cst的第一端耦合为数据电压与阈值电压之和Vdata+Vth，即第一节点A的电压为Vdata+Vth，驱动晶体管DRT导通，发光元件开始发光显示。在此阶段，第一电压经过驱动晶体管DRT对第二节 点B进行充电，第二节点B的电压被充电至第一电压Vdd。
具体地，流经发光元件的驱动电流I OLED的值可以根据下述公式得出：
I OLED＝1/2*K(Vgs-Vth)^2
其中，K为常数，Vgs为驱动晶体管DRT的栅极与源极之间的电压，即第一节点A与第二节点B之间的电压。当存储电容Cst的第一端的电压为Vdata+Vth时，即驱动晶体管DRT的栅极(第一节点A)电压为Vdata+Vth，驱动晶体管DRT导通，将其代入上述公式可以得到：
Vgs-Vth＝Vdata+Vth-Vdd-Vth
＝Vdata-Vdd。
由此可以看出，在发光元件发光时，其电流I与数据电压Vdata和第一电压Vdd相关，而不再与驱动晶体管DRT的阈值电压Vth相关，从而可以消除驱动晶体管的阈值电压对发光元件的驱动电流的影响，从而可以改善发光元件的显示效果，延长发光元件的使用寿命。
本公开实施例提供的像素电路，通过设置与驱动电路10相连的存储电路20，并通过与存储电路20相连的放电控制电路30控制驱动电路10的第二端放电，以及通过存储控制电路40控制存储电路20存储驱动电路10放电后的电压，最后在数据写入电路50写入数据电压时，可通过数据电压和存储电路20存储的电压导通驱动电路10。由此，当驱动电路10驱动发光元件发光时，驱动电路10的控制端电压可达到数据电压与存储的阈值电压之和，使得发光元件的电流与驱动电路10的阈值电压不相关，从而能够避免驱动电路10的阈值电压的变化对发光元件的驱动电流的影响，改善发光元件的发光效果，并延长发光元件的寿命。
本公开的实施例包括但不限于图3A中的配置方式，例如，如图3B所示，在本公开的又一个实施例中，像素电路100中的晶体管也可以都采用N型晶体管，此时第一极可以是源极，第二极可以是漏极。在本实施例中，该像素电路100中的发光元件的阳极和第一电压端VDD连接以接收第一电压。例如，在一个显示装置中，当图3B中所示的像素电路100呈阵列排布时，发光元件的阳极可以电连接到同一个电压端(例如公共电压端)，即采用共阳极连接方式。
需要说明的是，在本公开的实施例中，当驱动晶体管DRT采用N型晶体管时，其可以采用IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)制备工艺制作，相对于采用LTPS(Low Temperature Poly Silicon，低温多晶硅)制备工艺，可以有效减小驱动晶体管的尺寸以及防止出现漏电流的现象。
图2B中所示的像素电路100’可以具体实现为图3C所示的像素电路结构。如图3C所示，该像素电路的结构与图3A中所示的像素电路的结构类似，区别在于：放电控制电路30包括第三晶体管T3和第四晶体管T4的第一极均连接初始电压端Vinit。
例如，在第一阶段，初始电压端Vinit提供低电平(例如，该低电平为0V或接地电压)，第三控制信号端Gn-2输入第三控制信号以控制第三晶体管T3和第四晶体管T4导通，控制驱动晶体管DRT的第一极向初始电压端Vinit放电，直至驱动晶体管DRT的第一极与栅极的电压差达到阈值电压Vth为止。
需要注意的是，该像素电路的其他结构可以参考图3A中的介绍，在此不再赘述。
另需要注意的是，图3B所示的像素电路的工作原理与图3A所示的像素电路的工作原理类似，区别在于图3A所示的像素电路中的第一节点A至第三节点C在第一阶段是放电的过程，图3B所示的像素电路中的第一节点A至第三节点C在第一阶段是充电的过程。例如，例如，结合图3B和图4，在第一阶段将第一节点A和第三节点C充电至第二电压Vss，将第二节点B充电至Vss-Vth，从而在第二阶段，可以将第二节点B的带有阈值电压Vth的电压写入第一节点A，在第三阶段，通过电容的耦合作用，可以将数据电压Vdata写入第一节点A，从而在此阶段，第一节点A的电压为Vdata+Vss-Vth。
具体地，流经发光元件的驱动电流I OLED的值可以根据下述公式得出：
I OLED＝1/2*K(Vgs-Vth)^2
当存储电容Cst的第一端的电压为Vdata+Vss-Vth时，即驱动晶体管DRT的栅极(第一节点A)电压为Vdata+Vss-Vth，驱动晶体管DRT导通，此时驱动晶体管第一极(源极)的电压为Vdd，将其代入上述公式可以得到：
Vgs-Vth＝Vdata+Vss-Vth-Vdd-Vth
＝Vdata+Vss-Vdd。
由此可以看出，在发光元件发光时，其电流I与数据电压Vdata、第一电压Vdd和第二电压Vss相关，而不再与驱动晶体管DRT的阈值电压Vth相关，从而可以消除驱动晶体管的阈值电压对发光元件的驱动电流的影响，从而可以改善发光元件的显示效果，延长发光元件的使用寿命。
图3C所示的像素电路的工作原理与图3A所示的像素电路的工作原理类似，区别仅在于：在第一阶段，第一节点A和第三节点C通过初始电压端Vinit进行放电。在此不再赘述。
本公开一实施例还提供一种显示面板，包括阵列布置的多个像素单元。例如，该多个像素单元每个包括上述实施例提供的像素电路100或像素电路100’以及发光元件L。图5A为本公开一实施例提供的一种显示面板的示意框图。
如图5A所示，本公开实施例的显示面板1000，包括阵列布置的多个像素单元P。例如，该多个像素单元P每个包括本公开上述实施例提供的像素电路100/100’以及发光元件L，例如包括图3A、图3B或图3C中所示的像素电路。其具体的实施方式可参照上述像素电路100的实施例，为避免冗余，在此不再赘述。
例如，显示面板1000还包括多条扫描线。例如，该多条扫描线通过栅极驱动电路(图中未示出)驱动。
例如，多个像素单元排列为多行，第n(n为大于3的整数)行像素单元的像素电路100的数据写入电路50的第一控制信号端Gn连接到第n行扫描线，第n行像素单元的像素电路100的存储控制电路40连接到第n-1行扫描线，第n行像素单元的像素电路100的放电控制电路30连接到第n-2行扫描线。例如，第n-1行扫描线还与第n-1行的像素单元的像素电路100的数据写入电路50的第一控制信号端Gn连接。例如，第n-2行扫描线还与第n-2行的像素单元的像素电路100的数据写入电路50的第一控制信号端Gn连接。这样可以简化显示面板周围的布局空间，从而可以实现高分辨率显示面板的开发。
例如，发光元件L可为有机发光二极管或量子点发光二极管等，相应的显示面板为OLED显示面板或QLED显示面板。下面以发光元件为OLED为例进行说明，相应的描述也同样适用于QLED。
如图5A所示，显示面板1000还包括电压发生电路200。例如，该电压发生电路200与像素单元P中的像素电路100/100’连接，例如位于模组驱动电路系统中的电源管理集成电路之中。例如，电压发生电路200与像素电路100/100’的第一电压端VDD和/或第二电压端VEE连接，且配置为对应地改变第一电压端VDD提供的第一电压和/或第二电压端VEE提供的第二电压的大小。
例如，在第一阶段，该电压发生电路200改变第一电压和/或第二电压，例如，将第一电压控制在低电平，将第二电压控制在高电平，以控制驱动电路10的第二端120向第一电压端VDD放电；在第三阶段，电压发生电路200再次改变第一电压和第二电压，例如，将第一电压控制在高电平，将第二电压控制在低电平，以允许驱动电路10导通以驱动发光元件开始发光。以下是实施例与此相同，不再赘述。
图5B为本公开一实施例提供的另一种显示面板的示意框图。如图5B所示，显示面板11设置在显示装置1中，并与栅极驱动器12、定时控制器13和数据驱动器14电连接。该显示面板11包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12用于驱动多条扫描线GL；数据驱动器14用于驱动多条数据线DL；定时控制器13用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路100或像素电路100’。例如，包括图3A-3C任一所示像素电路。如图5B所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线对应连接到每行像素单元的像素电路100或像素电路100’中的数据写入电路50、存储控制电路30以及放电控制电路40以分别提供第一控制信号、第二控制信号和第三控制信号，该多条扫描线的连 接方式可以参考图5A所示的示例的相关描述，在此不再赘述。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图5B所示，每个像素单元P连接到三条扫描线GL(分别提供第一控制信号、第二控制信号和第三控制信号)、一条数据线DL、用于提供第一电压的第一电压线、用于提供第二电压的第二电压线或者还包括用于提供初始电压的初始电压线(图中未示出)。例如，第一电压线或第二电压线可以用相应的公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图5B中仅示出了部分的像素单元P、扫描线GL、数据线DL。需要注意的是，以下实施例与此相同，不再赘述。
例如，该多个像素单元P排列为多行，每一行像素单元P的数据写入电路50的第一控制信号端Gn连接到同一条扫描线GL，每一行像素单元P的像素电路的存储控制电路30和放电控制电路40分别连接到另两条扫描线GL以接收第一控制信号和第二控制信号。例如，每一列的数据线DL和本列像素电路10中的数据写入电路50连接以提供数据电压。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括第一控制信号、第二控制信号以及第三控制信号。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配显示面板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器12和数据驱动器14的控制。
例如，数据驱动电器14可以与多条数据线DL连接，以提供数据电压 Vdata；同时还可以与多条第一电压线、多条第二电压线和/或多条初始电压线连接以分别提供第一电压、第二电压和/或初始电压。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例提供的显示面板1000或显示面板11可以应用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、虚拟现实显示装置等任何具有显示功能的产品或部件中。
需要说明的是，为表示清楚、简洁，并没有给出该显示面板1000或显示面板11的全部组成单元。为实现显示面板的必要功能，本领域技术人员可以根据具体需要提供、设置其他未示出的组成单元，本公开的实施例对此不作限制。
本公开实施例提供的显示面板的显示效果好、寿命高，因而其显示性能较高。
本公开一实施例还提供一种电子设备。图6为本公开一实施例提供的一种电子设备的示意框图。
如图6所示，本公开实施例的电子设备10000包括本公开上述实施例提供的显示面板1000，例如包括图5A所示的显示面板1000或包括图5B中所示的显示面板11。该电子设备10000的具体的实施方式可参照上述显示面板的实施例，为避免冗余，在此不再赘述。
例如，本实施例提供的电子设备10000可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、虚拟现实设备等任何具有显示功能的产品或部件。
需要说明的是，为表示清楚、简洁，并没有给出该电子设备10000的全部组成单元。为实现电子设备的必要功能，本领域技术人员可以根据具体需要提供、设置其他未示出的组成单元，本公开的实施例对此不作限制。
本公开实施例提供的电子设备，其显示效果好、寿命高，因而其性能较高。
本公开的实施例还提供一种像素电路的驱动方法，可以用于驱动本公开 任一实施例提供的像素电路。图7为本公开一实施例提供的一种像素电路的驱动方法的流程图。下面，以图3A所示的像素电路的驱动方法为例进行介绍。例如，对于图3A所示的像素电路100的示例，该驱动方法包括步骤S1-S3。
步骤S1：通过放电控制电路控制驱动电路的第二端放电，使得所述驱动电路的第二端的电压基于所述驱动电路的阈值电压。
步骤S2：通过存储控制电路控制存储电路存储所述阈值电压。
步骤S3：通过数据写入电路将数据电压写入到存储电路，基于所述存储电路存储的数据电压和所述阈值电压，控制驱动电路导通，以驱动发光元件发光。
参照图2A和图3A，驱动电路10包括驱动晶体管DRT，驱动晶体管DRT的控制极(即栅极)连接存储电路20，驱动晶体管DRT的第一极连接发光元件的第一端，驱动晶体管DRT的第二极连接第一电压端VDD，其中，发光元件的第二端连接第二电压端VEE。
数据写入电路50包括第一晶体管T1，第一晶体管T1的控制极连接第一控制信号端Gn，第一晶体管T1的第一极连接存储电路20，第一晶体管T1的第二极连接数据信号输入端DATA。
存储电路20包括存储电容Cst，存储电容Cst的第一端连接驱动晶体管T1的控制极，存储电容Cst的第二端连接第一晶体管T1的第一极。
存储控制电路40包括第二晶体管T2，第二晶体管T2的控制极连接第二控制信号端Gn-1，第二晶体管T2的第一极连接驱动晶体管DRT的第一极，第二晶体管T2的第二极连接存储电容Cst的第一端。
放电控制电路30包括第三晶体管T3和第四晶体管T4。第三晶体管T3的控制极连接第三控制信号端Gn-2，第三晶体管T3的第一极连接第一电压端VDD，第三晶体管T3的第二极连接存储电容Cst的第二端。第四晶体管T4的控制极连接第三控制信号端Gn-2，第四晶体管T4的第一极连接第一电压端VDD，第四晶体管T4的第二极连接存储电容Cst的第一端。
在本公开的至少一个实施例的像素电路的驱动方法中，发光元件的每个发光周期包括三个阶段。
在第一阶段，控制放电控制电路40导通，控制驱动电路10的第二端120 向第一电压端VDD放电，直至驱动电路10的第二端的电压达到阈值电压为止。
在第二阶段，控制存储控制电路30导通，将阈值电压存储至存储电路20中。
在第三阶段，第一控制信号端输入第一控制信号以控制数据写入电路50导通，存储电路20的第一端耦合为数据电压与阈值电压之和，驱动电路10导通，发光元件发光。
例如，在一个示例中，该驱动方法还包括：在第一阶段，改变第一电压，以控制驱动电路10的第二端120向第一电压端VDD放电；在第三阶段，再次改变第一电压，以允许驱动电路导通以驱动发光元件发光。
例如，在另一个示例中，发光元件的第二端连接第二电压端以接收第二电压，该驱动方法还包括：在第一阶段，改变第一电压和第二电压，以控制驱动电路10的第二端120向第一电压端VDD放电(例如，在驱动晶体管实现为N型晶体管时，为充电)；在第三阶段，再次改变第一电压和第二电压，以允许驱动电路10导通以驱动发光元件L发光。
例如，在第一阶段和第二阶段中，将第一电压由高电平变为低电平，将第二电压由低电平变为高电平；在第三阶段中，将第一电压由第一阶段和第二阶段中的低电平变为高电平，将第二电压由第一阶段和第二阶段中的高电平变为低电平。
更具体地，在第一阶段，第三控制信号端Gn-2输入的第三控制信号控制第三晶体管T3和第四晶体管T4导通，控制驱动晶体管DRT的第一极向第一电压端VDD放电，直至驱动电路10的第二端的电压达到阈值电压为止或者直至驱动晶体管DRT的第一极和栅极的电压差达到阈值电压Vth为止。例如，在第一电压端VDD提供的第一电压为0时，驱动晶体管DRT的第一极的电压达到阈值电压Vth为止，数据信号输入端输入的数据电压为Vdata；例如，在第一电压端VDD提供的第一电压不为0(例如，为δ)时，驱动晶体管DRT的第一极的电压达到阈值电压Vth+δ为止，此时数据信号输入端输入的数据电压的大小为Vdata-δ，从而可以保证驱动晶体管的栅极的电压为Vdata+Vth。需要注意的是，以下实施例与此相同，不再赘述。
在第二阶段，第二控制信号端Gn-1输入的第二控制信号控制第二晶体管T2导通，将阈值电压Vth存储至存储电容Cst。
在第三阶段，第一控制信号端Gn输入的第一控制信号控制第一晶体管T1导通，存储电容Cst的第一端耦合为数据电压与阈值电压之和Vdata+Vth，驱动晶体管DRT导通，发光元件开始发光。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
例如，可在发光元件的每个发光周期由第一电压端VDD、第二电压端VEE、第一控制信号端Gn、第二控制信号端Gn-1、第三控制信号端Gn-2和数据信号输入端DATA分别提供图4所示的信号时序，以控制发光元件发光。
例如，结合图3A和图4，在第一阶段，即t1时间段，第三控制信号端Gn-2输入高电平，第三晶体管T3和第四晶体管T4导通，第一电压端VDD输入的第一电压从高变为低，第二电压端VEE输入的第二电压从低变为高。在此阶段，第一节点A和第三节点C与第一电压端VDD连接，为低电平，驱动晶体管DRT的第二极(例如漏极)与栅极短接，驱动晶体管DRT变成二极管结构，由于在上一发光周期驱动晶体管DRT的第一极(例如，源极)为高电平，因此驱动晶体管DRT的第一极向第一电压端VDD放电，直至驱动晶体管DRT的第一极和栅极的电压差达到驱动晶体管DRT的阈值电压为止，例如，在第一电压端VDD提供的第一电压Vdd为0V时，第二节点B的电压达到阈值电压Vth。
在第二阶段，即t2时间段，第二控制信号端Gn-1输入高电平，第二晶体管T2导通，第二节点B与第一节点A点导通，阈值电压Vth存储至存储电容Cst的第一端，即第一节点A。
在第三阶段，即t3时间段，第一控制信号端Gn输入高电平，第一晶体管T1导通，第一电压端VDD输入的第一电压Vdd从低变为高，第二电压 端VEE输入的第二电压从高变为低，存储电容Cst的第二端写入数据电压Vdata，存储电容Cst的第一端耦合为数据电压与阈值电压之和Vdata+Vth，即第一节点A的电压为Vdata+Vth，驱动晶体管DRT导通，发光元件开始发光显示。在此阶段，第一电压Vdd经过驱动晶体管DRT对第二节点B进行充电，第二节点B的电压被充电至第一电压Vdd。
具体地，流经发光元件的驱动电流I OLED的值可以根据下述公式得出：
I OLED＝1/2*K(Vgs-Vth)^2
其中，K为常数，Vgs为驱动晶体管DRT的栅极与源极之间的电压，即第一节点A与第二节点B之间的电压。当存储电容Cst的一端的电压为Vdata+Vth时，即驱动晶体管DRT栅极(第一节点A)的电压为Vdata+Vth时，驱动晶体管DRT导通，将其代入上述公式可以得到：
Vgs-Vth＝Vdata+Vth-Vdd-Vth
＝Vdata-Vdd。
由此可以看出，在发光元件发光时，其电流I与数据电压Vdata和第一电压Vdd相关，而不再与驱动晶体管DRT的阈值电压Vth相关。
根据本公开实施例的像素电路的控制方法，通过与存储电路相连的放电控制电路控制驱动电路放电，并通过与驱动电路相连的存储控制电路控制存储电路存储驱动电路放电后的电压，最后在数据写入电路写入数据电压时，可通过数据电压和存储电路存储的电压导通驱动电路，由此，当驱动电路驱动发光元件发光时，驱动电路的控制端电压可达到数据电压与存储的电压之和，使得发光元件的电流与驱动电路的阈值电压不相关，从而能够避免驱动电路阈值电压的变化对发光元件电流的影响，改善发光元件发光效果，并延长发光元件的寿命。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员 可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (15)

  1. 一种像素电路，包括驱动电路、存储电路、放电控制电路、存储控制电路和数据写入电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制驱动所述发光元件发光的驱动电流，所述驱动电路的第一端配置为从第一电压端接收第一电压；
    所述存储电路与所述驱动电路的控制端连接；
    所述放电控制电路与所述存储电路以及所述驱动电路的控制端连接，且配置为控制所述存储电路两端的电压值，以及控制所述驱动电路的第二端放电；
    所述存储控制电路与所述驱动电路的控制端、所述驱动电路的第二端以及所述存储电路连接，且配置为控制所述存储电路存储所述驱动电路的第二端的电压；以及
    所述数据写入电路与所述存储电路、数据信号输入端、第一控制信号端以及所述放电控制电路连接，且配置为响应于所述第一控制信号端输入的第一控制信号，将所述数据信号输入端提供的数据电压写入到所述存储电路以将所述数据电压存储在所述存储电路，控制所述驱动电路导通，以驱动所述发光元件发光。
  2. 根据权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管；
    所述驱动晶体管的控制极连接所述存储电路，所述驱动晶体管的第一极连接所述发光元件的第一端，所述驱动晶体管的第二极连接所述第一电压端，
    其中，所述发光元件的第二端连接第二电压端以接收第二电压。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入电路包括第一晶体管；
    所述第一晶体管的控制极连接所述第一控制信号端以接收所述第一控制信号，所述第一晶体管的第一极连接所述存储电路，所述第一晶体管的第二极连接所述数据信号输入端以接收所述数据电压。
  4. 根据权利要求3所述的像素电路，其中，所述存储电路包括存储电容；
    所述存储电容的第一端连接所述驱动晶体管的控制极，所述存储电容的第二端连接所述第一晶体管的第一极。
  5. 根据权利要求4所述的像素电路，其中，所述存储控制电路包括第二晶体管；
    所述第二晶体管的控制极连接第二控制信号端以接收第二控制信号，所述第二晶体管的第一极连接所述驱动晶体管的第一极，所述第二晶体管的第二极连接所述存储电容的第一端。
  6. 根据权利要求3所述的像素电路，其中，所述放电控制电路包括第三晶体管和第四晶体管；
    所述第三晶体管的控制极连接第三控制信号端以接收第三控制信号，所述第三晶体管的第一极连接所述第一电压端或初始电压端，所述第三晶体管的第二极连接所述存储电容的第二端；
    所述第四晶体管的控制极连接所述第三控制信号端以接收所述第三控制信号，所述第四晶体管的第一极连接所述第一电压端或初始电压端，所述第四晶体管的第二极连接所述存储电容的第一端。
  7. 一种显示面板，包括阵列布置的多个像素单元，其中，所述像素单元每个包括权利要求1-6任一所述的像素电路以及发光元件。
  8. 根据权利要求7所述的显示面板，还包括多条扫描线，其中，所述多个像素单元排列为多行，第n行像素单元的像素电路的数据写入电路的第一控制信号端连接到第n行扫描线，第n行像素单元的像素电路的存储控制电路连接到第n-1行扫描线，第n行像素单元的像素电路的放电控制电路连接到第n-2行扫描线；
    所述第n-1行扫描线还与第n-1行的像素单元的像素电路的数据写入电路的第一控制信号端连接；
    所述第n-2行扫描线还与第n-2行的像素单元的像素电路的数据写入电路的第一控制信号端连接；
    其中，n为大于3的整数。
  9. 根据权利要求8所述的显示面板，其中，所述发光元件为有机发光二 极管。
  10. 根据权利要求8所述的显示面板，还包括电压发生电路，
    其中，所述电压发生电路与所述第一电压端和/或第二电压端连接，且配置为对应地改变所述第一电压端提供的第一电压和/或所述第二电压端提供的第二电压的大小。
  11. 一种电子设备，包括如权利要求7-10任一所述的显示面板。
  12. 一种根据权利要求1所述的像素电路的驱动方法，包括：
    通过所述放电控制电路控制所述驱动电路的第二端放电，使得所述驱动电路的第二端的电压基于所述驱动电路的阈值电压；
    通过所述存储控制电路控制所述存储电路存储所述阈值电压；
    通过所述数据写入电路将所述数据电压写入到所述存储电路，基于所述存储电路存储的所述数据电压和所述阈值电压，控制所述驱动电路导通以驱动所述发光元件发光。
  13. 根据权利要求12所述的像素电路的驱动方法，其中，所述发光元件的每个发光周期包括三个阶段，所述驱动方法包括：
    在第一阶段，控制所述放电控制电路导通，控制所述驱动电路的第二端向所述第一电压端放电，直至所述驱动电路的第二端的电压达到所述阈值电压为止；
    在第二阶段，控制所述存储控制电路导通，将所述阈值电压存储至所述存储电路中；
    在第三阶段，所述第一控制信号端输入所述第一控制信号以控制所述数据写入电路导通，所述存储电容的第一端的电压耦合为所述数据电压与所述阈值电压之和，所述驱动电路导通，所述发光元件发光。
  14. 根据权利要求13所述所述的像素电路的驱动方法，还包括：
    在所述第一阶段，改变所述第一电压，以控制所述驱动电路的第二端向所述第一电压端放电；
    在所述第三阶段，再次改变所述第一电压，以允许所述驱动电路导通以驱动所述发光元件发光。
  15. 根据权利要求13所述所述的像素电路的驱动方法，其中，所述发光 元件的第二端连接第二电压端以接收第二电压，所述驱动方法还包括：
    在所述第一阶段，改变所述第一电压和所述第二电压，以控制所述驱动电路的第二端向所述第一电压端放电；
    在所述第三阶段，再次改变所述第一电压和所述第二电压，以允许所述驱动电路导通以驱动所述发光元件发光。
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