WO2019105332A1

WO2019105332A1 - Computational integrated circuit chip and corresponding circuit board

Info

Publication number: WO2019105332A1
Application number: PCT/CN2018/117589
Authority: WO
Inventors: Cunyong YANG; Guochen Sun; Micree ZHAN
Original assignee: Bitmain Technologies Inc.
Priority date: 2017-11-28
Filing date: 2018-11-27
Publication date: 2019-06-06

Abstract

A computational integrated circuit chip, comprising: a control unit(11) having a clock-signal output interface (14); a plurality of arithmetic units (12), each arithmetic unit (12) having a clock-signal input interface (15), the input interface (13) being connected to the clock-signal output interface(14); and an input/output interface (13). The control unit (11) exchanges data with external components through the input/output interface (13); and the control unit (11) sends an individual clock signal to the each arithmetic unit (12) according to a control command.

Description

COMPUTATIONAL INTEGRATED CIRCUIT CHIP AND CORRESPONDING CIRCUIT BOARD

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority to Chinese Patent Application No. 201721617833.8, entitled “COMPUTATIONAL INTEGRATED CIRCUIT CHIP AND CORRESPONDING CIRCUIT BOARD, ” filed on November 28, 2017, Chinese Patent Application No. 201721617831.9, entitled “COMPUTATIONAL SYSTEM AND CORRESPONDING ELECTRONIC APPARATUS, ” filed on November 28, 2017, and Chinese Patent Application No. 201711218135.5, entitled “COMPUTATIONAL SYSTEM AND CORRESPONDING ELECTRONIC APPARATUS, ” filed on November 28, 2017, the entire content of all three applications is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of electronic technology, in particular to a computational integrated circuit chip and corresponding circuit board.

BACKGROUND

In the field of electronic and integrated circuit design technology, a computational integrated circuit chip typically has a plurality of arithmetic units. Each arithmetic unit performs a computing task according to a control command. The computing task of an arithmetic unit is typically initiated by a clock signal sent by a control unit.

SUMMARY

In order to address the above technical problems in the prior art, the present disclosure provides a computational integrated circuit chip and a corresponding circuit board.

In one aspect of the present disclosure, a computational integrated circuit chip is provided. The computational integrated circuit chip comprises: a control unit having a clock-signal output interface; a plurality of arithmetic units, where each arithmetic unit has a clock-signal input interface and the input interface is connected to the clock-signal output interface; and an input/output interface. The control unit exchanges data with external components through the input/output interface; and the control unit sends an individual clock signal to the each arithmetic unit according to a control command.

In certain embodiments, the plurality of arithmetic units are organized into a plurality of arithmetic-unit groups, where each arithmetic-unit group comprisies two or more arithmetic units connected in series.

In certain embodiments, one arithmetic unit within the each arithmetic-unit group is connected to the control unit.

In certain embodiments, each arithmetic-unit group has a top arithmetic unit connected to the control unit, where the top arithmetic unit is an arithmetic unit placed closest to the control unit among all arithmetic units within the each arithmetic-unit group.

In certain embodiments, each arithmetic unit further comprises a computing component and a storage component, where the computing component and the storage component within each arithmetic unit are connected to each other, and the storage component stores computation data generated by the computing component.

In certain embodiments, the plurality of arithmetic units comprise a top arithmetic unit and one or more non-top arithmetic units, where each non-top arithmetic unit has a corresponding preceding arithmetic unit. And the computing component of each non-top arithmetic unit is connected to the storage component of the corresponding preceding arithmetic unit, where each non-top arithmetic unit reads data from the corresponding preceding arithmetic unit.

In certain embodiments, the computing component of the top arithmetic unit is connected to the control unit.

In certain embodiments, each arithmetic unit includes one or more microelectronic circuits.

In certain embodiments, the one or more microelectronic circuits include CMOS and/or NMOS transistors.

In certain embodiments, the plurality of arithmetic units compute a hash function using a SHA-2 type algorithm in a parallel computing scheme.

In another aspect of the present disclosure, a circuit board is provided. The circuit board comprises one or more computational integrated circuit chips in the forgoing description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly described below.

FIG. 1 is a structural diagram of a computational integrated circuit chip according to an exemplary embodiment of the present disclosure; and

FIG. 2 is structural diagram showing two arithmetic units connected in series in an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Technical solutions of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the described embodiments are some but not all of the embodiments of the present disclosure. Other embodiments derived by those with ordinary skills in the art on the basis of the described embodiments without inventive efforts should fall within the scope of the present disclosure.

The control unit in the computational integrated circuit chips is usually configured with a single clock signal line, and the control unit simultaneously sends the clock signal to all the arithmetic units through the clock signal line. However, when only a subset of the plurality of arithmetic units are required to operate, since the clock signal is transmitted to all the arithmetic units, the arithmetic units that are not required to perform work still operate, thereby causing waste of electric power.

One aspect of the present disclosure provides a computational integrated circuit chip. FIG. 1 is a structural diagram of a computational integrated circuit chip according to an embodiment of the present disclosure. As shown in FIG. 1, in certain embodiments, the computational integrated circuit chip includes: a control unit 11, two or more arithmetic units 12, and an input/output interface 13.

The control unit 11 is connected to the input/output interface 13 for data exchange with external components. Each arithmetic unit 12 has a clock signal input interface 15. The control unit 11 has a clock signal output interface 14 which is connected to the clock signal input interfaces 15 of each of the plurality of arithmetic units 12 through a plurality of lines. Each line connects the clock signal output interface 14 of the control unit 11 to the clock signal input interface 15 of a single arithmetic unit 12 to transmit a clock signal to the corresponding arithmetic unit 12 according to control commands.

As shown in the above design, certain embodiments of the present disclosure departure from a typical computational integrated circuit design where the control unit is configured with a single clock signal line, and the control unit simultaneously sends a clock signal to all the arithmetic units through the single clock signal line, causing all the arithmetic units to operate even when only a subset of the arithmetic units are required to operate, thus causing a significant waste of electric power.

In certain embodiments of the present disclosure, by incorporating a plurality of clock signal lines between the control unit 11 and the arithmetic units 12 of the computational integrated circuit chip, the clock signal output interface 14 of the control unit 11 and the clock signal input interface 15 of each of the arithmetic unit 12 are connected, that is, each arithmetic unit 12 may independently receive the clock signal that the control unit 11 transmits. Thus, each arithmetic unit 12 may perform arithmetic operation according to a specific task allocated to it by the control unit 11. And the control unit 11 may selectively activate a subset of the arithmetic units 12 to operate according to their respective computational tasks, which may significantly improve power efficiency for computational operations.

In certain embodiments of the present disclosure, the plurality of arithmetic units may be divided into two or more groups, and each group includes two or more arithmetic units connected in series.

For a computational integrated circuit chip configured with a plurality of arithmetic units, in order to save wiring space, reduce wiring complexity, and provide more convenient control of the arithmetic unit, the plurality of arithmetic units may be divided into two or more arithmetic-unit groups according to the available area on the computational integrated circuit chip, the operating characteristics, performance, and functions of the arithmetic units, as well as other factors. The arithmetic units within an arithmetic-unit group may be connected in series. The present disclosure does not specifically limit the specific grouping method. Those skilled in related art may group the arithmetic units according to a specific application.

Since the arithmetic units in each arithmetic-unit group are connected in series, only one arithmetic unit in each group needs to be connected to the control unit to read data. In certain embodiments, a top arithmetic unit in each arithmetic-unit group may be connected to the control unit, and the top arithmetic unit may be the arithmetic unit closest to the control unit, further saving the wiring space and reducing wiring complexity of the computational integrated circuit chip.

The foregoing description provides exemplary embodiments. A person skilled in the art may select a specific arithmetic unit within an arithmetic-unit group to be connected to the control unit according to a specific application. The present disclosure does not specifically limit the manner the arithmetic-unit group connects to the control unit.

In certain embodiments, each arithmetic unit comprises a computing component and a storage component that are connected to each other. The computing component is configured to perform a computing operation according to a computing task. The storage unit is configured to store computation result from the arithmetic unit.

FIG. 2 is a structural view of an embodiment of two arithmetic units 12 connected in series. As shown in FIG. 2, in certain embodiments, each arithmetic unit 12 comprises a computing component 21, a storage component 22, and a clock signal input interface 23.

The computing component 21 of an arithmetic unit may be connected to the storage component 22 of a preceding arithmetic unit 12 for reading data including a computation result stored in the storage component 22 of the preceding arithmetic unit 12. The computing component 21 may use the data from the preceding arithmetic unit to perform a computational operation.

The storage component 22 is also connected to the computing component 21 within the same arithmetic unit 12 for storing data including a computation result. The data stored in the storage component 22 may be available for a following arithmetic unit to read. The clock signal input interface 23 of each arithmetic unit is connected to the clock signal output interface of the control unit.

In certain embodiments, by using a sequential data connection configuration to connect a group of arithmetic units connected in series, each arithmetic unit may receive data that it requires. The forgoing sequential data connection configuration may save wiring space and reduce wiring complexity.

In certain embodiments, the computing component of a top arithmetic unit in an arithmetic-unit group may be connected to the control unit to receive data to be computed from the control unit.

Further, the arithmetic unit may be constructed with a microelectronic circuit, and the microelectronic circuit may be constructed with CMOS (complementary metal–oxide–semiconductor) and/or NMOS (negative channel metal-oxide-semiconductor) transistors.

Those skilled in the art may select a type of arithmetic units that match the operation purpose according to a specific application. The present disclosure does not specifically limit the selections of the arithmetic units and the storage units.

In certain embodiments, the computational integrated circuit chip may be used to perform Hash calculations in a cryptocurrency mining process. The backbone of a cryptocurrency is its blockchain, which is a global ledger formed by linking together individual blocks of transaction data. The blockchain only contains validated transactions, which prevents fraudulent transactions and double spending of the currency. The validation process relies on data being encrypted using algorithmic hashing. The resulting encrypted value is a series of numbers and letters that does not resemble the original data, and is called a hash. Cryptocurrency mining involves working with the hash. Hashing requires processing the data from a block through a mathematical function, which results in an output of a fixed length. Using a fixed length output increases security, since anyone trying to decrypt the hash won’ t be able to tell how long or short the input is simply by looking at the length of the output. For example, hashing the word “hello” will produce an output that is the same length as the hash for “I am going to the store” . The function used to generate the hash is deterministic, meaning that it will produce the same result each time the same input is used; can generate a hashed input efficiently; makes determining the input difficult (leading to mining) ; and makes small changes to the input result in a very different hash.

Solving the hash is essentially solving a complex mathematical problem, and starts with the data available in the block header. Each block header contains a version number, a timestamp, the hash used in the previous block, the hash of the Merkle Root, the nonce, and the target hash. The miner focuses on the nonce, a string of numbers. This number is appended to the hashed contents of the previous block, which is then itself hashed. If this new hash is less than or equal to the target hash, then it is accepted as the solution, the miner is given the reward, and the block is added to the blockchain.

In one example, BitCoin uses the SHA-256 hash algorithm to generate verifiably "random" numbers in a way that requires a predictable amount of CPU effort. Generating a SHA-256 hash with a value less than the current target solves a block and wins coins for mining machines. When a SHA-256 algorithm is used to solve a hash for block in a blockchain, the mining computer may calculate a hash functions of a set of random numbers to find a combination that match the current condition for a new block. As a result, an extremely large amount of computation may be required. The computational integrated circuit chip in the foregoing description may be used as Application Specific Integrated Chips (ASIC) to perform multiple hash calculations in parallel using the multiple arithmetic units. Further, since the multiple arithmetic units are connected in series and may communicate the calculation results to one another, these ASICs may be used to calculate a single hash or an iterated hash in parallel. The control unit may send clock signal to each arithmetic unit interdependently, and thus only activates the arithmetic units that are required to operate during one clock cycle. Embodiments of the present disclosure thus may improve both the calculation speed and energy efficiency of the computational integrated circuit chip in a mining machine.

According to another aspect of the present disclosure, a circuit board is provided. The circuit board includes one or more computational integrated circuit chips as described above.

The forgoing description and embodiments are exemplary descriptions of the technical solutions provided by the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art. The present disclosure is intended to cover any variations, modifications, equivalent substitutions, uses, or adaptations that are in accordance with the general principles of the present disclosure.

Claims

A computational integrated circuit chip, comprising:

a control unit having a clock-signal output interface;

a plurality of arithmetic units, each arithmetic unit having a clock-signal input interface, the input interface being connected to the clock-signal output interface; and

an input/output interface;

wherein:

the control unit exchanges data with external components through the input/output interface; and

the control unit sends an individual clock signal to the each arithmetic unit according to a control command.
The computational integrated circuit chip according to claim 1, wherein the plurality of arithmetic units are organized into a plurality of arithmetic-unit groups, each arithmetic-unit group comprising two or more arithmetic units connected in series.
The computational integrated circuit chip according to claim 2, wherein one arithmetic unit within the each arithmetic-unit group is connected to the control unit.
The computational integrated circuit chip according to claim 2, wherein the each arithmetic-unit group has a top arithmetic unit connected to the control unit, the top arithmetic unit being an arithmetic unit placed closest to the control unit among all arithmetic units within the each arithmetic-unit group.
The computational integrated circuit chip according to claim 1, wherein the each arithmetic unit further comprises a computing component and a storage component, the computing component and the storage component within the each arithmetic unit being connected to each other, the storage component storing computation data generated by the computing component.
The computational integrated circuit chip according to claim 5, wherein:

the plurality of arithmetic units comprise a top arithmetic unit and one or more non-top arithmetic units, each non-top arithmetic unit having a corresponding preceding arithmetic unit; and

the computing component of the each non-top arithmetic unit is connected to the storage component of the corresponding preceding arithmetic unit, each non-top arithmetic unit reading data from the corresponding preceding arithmetic unit.
The computational integrated circuit chip according to claim 6, wherein the computing component of the top arithmetic unit is connected to the control unit.
The computational integrated circuit chip according to claim 5, wherein the each arithmetic unit includes one or more microelectronic circuits.
The computational integrated circuit chip according to claim 8, wherein the one or more microelectronic circuits comprise CMOS and/or NMOS transistors.
The computational integrated circuit chip according to claim 1, wherein the plurality of arithmetic units compute a hash function in parallel.
A circuit board comprising a computational integrated circuit chip, wherein the computational integrated circuit chip comprises:

a control unit having a clock-signal output interface;

a plurality of arithmetic units, each arithmetic unit having a clock-signal input interface, the input interface being connected to the clock-signal output interface; and

an input/output interface;

wherein:

the control unit exchanges data with external components through the input/output interface; and

the control unit sends an individual clock signal to the each arithmetic unit according to a control command.
The circuit board according to claim 11, wherein the plurality of arithmetic units are organized into a plurality of arithmetic-unit groups, each arithmetic-unit group comprising two or more arithmetic units connected in series.
The circuit board according to claim 12, wherein one arithmetic unit within the each arithmetic-unit group is connected to the control unit.
The circuit board according to claim 12, wherein the each arithmetic-unit group has a top arithmetic unit connected to the control unit, the top arithmetic unit being an arithmetic unit placed closest to the control unit among all arithmetic units within the each arithmetic-unit group.
The circuit board according to claim 11, wherein the each arithmetic unit further comprises a computing component and a storage component, the computing component and the storage component within the each arithmetic unit being connected to each other, the storage component to storing computation data generated by the computing component.
The circuit board according to claim 15, wherein:

the plurality of arithmetic units comprise a top arithmetic unit and one or more non-top arithmetic units, each non-top arithmetic unit having a corresponding preceding arithmetic unit within the plurality of arithmetic units; and

the computing component of the each non-top arithmetic unit is connected to the storage component of the corresponding preceding arithmetic unit, the each non-top arithmetic unit reading data from the corresponding preceding arithmetic unit.
The circuit board according to claim 16, wherein the computing component of the top arithmetic unit is connected to the control unit.
The circuit board according to claim 17, wherein the each arithmetic unit includes one or more microelectronic circuits.
The circuit board according to claim 18, wherein the one or more microelectronic circuits comprise CMOS and/or NMOS transistors.
The circuit board according to claim 11, wherein the plurality of arithmetic units compute a hash function in parallel.