CN207503223U - A kind of operation chip and corresponding circuit board - Google Patents
A kind of operation chip and corresponding circuit board Download PDFInfo
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- CN207503223U CN207503223U CN201721617833.8U CN201721617833U CN207503223U CN 207503223 U CN207503223 U CN 207503223U CN 201721617833 U CN201721617833 U CN 201721617833U CN 207503223 U CN207503223 U CN 207503223U
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- arithmetic element
- arithmetic
- control unit
- operation chip
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Abstract
The utility model discloses a kind of operation chip and corresponding circuit board, the operation chip includes：Control unit, two or more arithmetic elements and input/output interface, wherein：Described control unit is connect with the input/output interface, for carrying out data exchange with outside；The clock output interface of described control unit is connect with the clock input interface of each arithmetic element, for giving each arithmetic element tranmitting data register signal respectively according to control command.The utility model can selectively start corresponding arithmetic element and work according to the processor active task of arithmetic element, so as to largely save power consumption, avoid the waste of power.
Description
Technical field
The utility model is related to electronic technology field, especially a kind of operation chip and corresponding circuit board.
Background technology
In electronic technology field, usually all there are multiple arithmetic elements, each arithmetic elements for existing operation chip interior
Respective processor active task is performed according to the control command of control unit, and the processor active task of each arithmetic element is usually single by control
The clock signal that member is sent starts, and the control unit of existing operation chip interior is only provided with a clock cable, control
Clock signal is sent to all arithmetic elements by unit simultaneously by this clock cable.But when multiple arithmetic elements
In only need partial arithmetic cell operation therein when, due to clock signal still be sent to all arithmetic elements, so as to cause
The arithmetic element for not needing to work also works, and has in turn resulted in the waste of power.
Utility model content
In order to solve above-mentioned problems of the prior art, the utility model proposes a kind of operation chip and corresponding electricity
Road plate.
One side according to the present utility model, proposes a kind of operation chip, and the operation chip includes：Control unit, two
A or multiple arithmetic elements and input/output interface, wherein：
Described control unit is connect with the input/output interface, for carrying out data exchange with outside；
The clock output interface of described control unit is connect with the clock input interface of each arithmetic element, for according to control
Each arithmetic element tranmitting data register signal is given in system order respectively.
Optionally, the arithmetic element is divided into two groups or multigroup, and every group of arithmetic element includes two or more series connection and connect
The arithmetic element connect.
Optionally, an arithmetic element in every group of arithmetic element is connect with described control unit.
Optionally, the chopped-off head arithmetic element in every group of arithmetic element is connect with described control unit.
Optionally, the arithmetic element includes：The arithmetic unit and storage unit of interconnection.
Optionally, the arithmetic element includes：Arithmetic unit, storage unit and clock input interface, wherein：
The arithmetic unit is connect with the storage unit of higher level's arithmetic element, for reading higher level's arithmetic element storage unit
The data of middle storage simultaneously carry out operation；
The arithmetic unit is connect with storage unit, for the data that operation obtains to be stored in storage unit, under
Grade arithmetic element is called；
The clock input interface and the clock output interface of described control unit connect.
Optionally, the arithmetic unit of chopped-off head arithmetic element is connect with described control unit.
Optionally, the arithmetic element is made of microelectronic circuit.
Optionally, the microelectronic circuit is managed by COMS, NMOS tube forms.
It is according to the present utility model in another aspect, propose a kind of circuit board, the circuit board include it is one or more as above
The operation chip.
Technical solution according to the present utility model is more by being added between the control unit and arithmetic element of operation chip
Clock cable so that the clock output interface of control unit is respectively formed company with the clock input interface of each arithmetic element
It connects, i.e., each arithmetic element can the independently received clock signal sent to control unit.The technical solution being capable of basis
The processor active task of arithmetic element selectively starts corresponding arithmetic element and works, so as to largely save
Power consumption avoids the waste of power.
Description of the drawings
Fig. 1 is the structure diagram according to the operation chip of one embodiment of the utility model；
Fig. 2 is the structure diagram according to the arithmetic element of one embodiment of the utility model.
Specific embodiment
For the purpose of this utility model, technical solution and advantage is more clearly understood, below in conjunction with specific embodiment, and
With reference to attached drawing, the utility model is further described.
One side according to the present utility model, proposes a kind of operation chip, and Fig. 1 is according to one embodiment of the utility model
The structure diagram of operation chip, as shown in Figure 1, in this embodiment, the operation chip includes：Control unit 11, two
Or multiple arithmetic elements 12 and input/output interface 13, wherein：
Described control unit 11 is connect with the input/output interface 13, for carrying out data exchange with outside；
The clock output interface 14 of described control unit 11 is connect with the clock input interface 15 of each arithmetic element, is used for
Each 12 tranmitting data register signal of arithmetic element is given respectively according to control command.
The control unit that the embodiment breaches conventional operation chip interior is only provided with a clock cable, and controls
Unit processed by this clock cable simultaneously clock signal is sent to all arithmetic elements, even if so as to cause it is multiple
Partial arithmetic cell operation therein is only needed in arithmetic element, clock signal is still sent to all arithmetic elements, and then
The problem of causing power serious waste.
The embodiment between the control unit 11 of operation chip and arithmetic element 12 by adding a plurality of clock signal
Line so that the clock output interface 14 of control unit 11 is respectively formed with the clock input interface 15 of each arithmetic element 12 and connect,
The clock signal that i.e. each arithmetic element 12 independently received can arrive control unit 11 and send, is distributed according to control unit 11
Task carry out data operation, such control unit just can selectively start corresponding according to the processor active task of arithmetic element
Arithmetic element work, so as to largely saving power consumption, avoid the waste of power.
In one embodiment of the utility model, the arithmetic element is divided into two groups or multigroup, every group of arithmetic element packet
Include two or more arithmetic elements being connected in series with.
It is usually required for setting multiple arithmetic elements on one operation chip, in order to save wiring space, it is multiple to reduce wiring
Miscellaneous degree is more convenient the control of control unit, can be according to the usable area of operation chip, the work characteristics of arithmetic element, operation
Multiple arithmetic elements are divided into two or more sets arithmetic element groups by the performance of unit, the function of arithmetic element or other factors, and
It is connected in series with each other the arithmetic element in each group of arithmetic element.
Illustrative explanation is above are only, in practical operation, those skilled in the art can be according to the needs of practical application
Arithmetic element is grouped, the utility model is not especially limited specific group technology.
Since the arithmetic element in every group of arithmetic element is connected in series with each other, as long as having one in every group of arithmetic element
A arithmetic element is connect with control unit can.In one embodiment of the utility model, it can make in every group of arithmetic element
Chopped-off head arithmetic element connect with described control unit, the chopped-off head arithmetic element is typically the nearest operation of distance controlling unit
Unit thus can further save wiring space, reduce wiring complexity.
Illustrative explanation is above are only, in practical operation, those skilled in the art can be according to the needs of practical application
The arithmetic element being connect with control unit is selected, the utility model is not especially limited it.
In one embodiment of the utility model, the arithmetic element includes：Arithmetic unit and storage unit, wherein：
The arithmetic unit and storage unit interconnect；
The arithmetic unit is used to perform arithmetic operation according to processor active task；
The storage unit is used to store the data obtained after arithmetic unit operation.
Fig. 2 is according to the structure diagram of the arithmetic element of one embodiment of the utility model, as shown in Fig. 2, in this practicality
In a novel embodiment, the arithmetic element 12 includes：Arithmetic unit 21, storage unit 22 and clock input interface 23,
In：
The arithmetic unit 21 is connect with the storage unit of higher level's arithmetic element, for reading higher level's arithmetic element storage part
The data that are stored in part simultaneously carry out operation；
The arithmetic unit 21 is connect with storage unit 22, for the data that operation obtains to be stored in storage unit 22
In, it is called for subordinate's arithmetic element；
The clock input interface 23 is connect with the clock output interface of described control unit.
In this embodiment, by the data connection step by step for the arithmetic element being mutually in series, each arithmetic element can
The data of oneself needs are enough obtained, and this cascaded structure can save wiring space, reduce wiring complexity.
In one embodiment of the utility model, arithmetic unit and the control of the chopped-off head arithmetic element of plural serial stage structure
Unit connection processed, for obtaining data to be calculated from control unit.
Further, the arithmetic element is made of microelectronic circuit, and the microelectronic circuit is managed by COMS, NMOS tube
Composition.
In practical applications, those skilled in the art can select what is matched with operation purpose according to the needs of practical application
Arithmetic element and storage unit, the utility model do not limit the selection of arithmetic element and storage unit, related model specifically
It is fixed.
Another aspect according to the present utility model, it is also proposed that a kind of circuit board, the circuit board include one or more such as
The upper operation chip.
Particular embodiments described above has carried out into one the purpose of this utility model, technical solution and advantageous effect
Step is described in detail, it should be understood that the foregoing is merely specific embodiment of the utility model, is not limited to this
Utility model, within the spirit and principle of the utility model, any modification, equivalent substitution, improvement and etc. done should all wrap
Containing being within the protection scope of the utility model.
Claims (10)
1. a kind of operation chip, which is characterized in that the operation chip includes：Control unit, two or more arithmetic elements and
Input/output interface, wherein：
Described control unit is connect with the input/output interface, for carrying out data exchange with outside；
The clock output interface of described control unit is connect with the clock input interface of each arithmetic element, for being ordered according to control
It enables respectively to each arithmetic element tranmitting data register signal.
2. operation chip according to claim 1, which is characterized in that the arithmetic element is divided into two groups or multigroup, often
Group arithmetic element includes two or more arithmetic elements being connected in series with.
3. operation chip according to claim 2 a, which is characterized in that arithmetic element and institute in every group of arithmetic element
State control unit connection.
4. operation chip according to claim 2, which is characterized in that chopped-off head arithmetic element and institute in every group of arithmetic element
State control unit connection.
5. operation chip according to claim 1, which is characterized in that the arithmetic element includes：The operation of interconnection
Component and storage unit.
6. operation chip according to claim 2, which is characterized in that the arithmetic element includes：Arithmetic unit, storage part
Part and clock input interface, wherein：
The arithmetic unit is connect with the storage unit of higher level's arithmetic element, is deposited for reading in higher level's arithmetic element storage unit
The data of storage simultaneously carry out operation；
The arithmetic unit is connect with storage unit, for the data that operation obtains to be stored in storage unit, is transported for subordinate
Calculate cell call；
The clock input interface and the clock output interface of described control unit connect.
7. operation chip according to claim 6, which is characterized in that the arithmetic unit of chopped-off head arithmetic element and the control
Unit connects.
8. the operation chip according to any one of claim 5-7, which is characterized in that the arithmetic element is by microelectronics electricity
Road forms.
9. operation chip according to claim 8, which is characterized in that the microelectronic circuit is managed by COMS, NMOS tube group
Into.
10. a kind of circuit board, which is characterized in that the circuit board includes one or more such as any one of claim 1-9 institutes
The operation chip stated.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721617833.8U CN207503223U (en) | 2017-11-28 | 2017-11-28 | A kind of operation chip and corresponding circuit board |
| PCT/CN2018/117589 WO2019105332A1 (en) | 2017-11-28 | 2018-11-27 | Computational integrated circuit chip and corresponding circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721617833.8U CN207503223U (en) | 2017-11-28 | 2017-11-28 | A kind of operation chip and corresponding circuit board |
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| Publication Number | Publication Date |
|---|---|
| CN207503223U true CN207503223U (en) | 2018-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201721617833.8U Active CN207503223U (en) | 2017-11-28 | 2017-11-28 | A kind of operation chip and corresponding circuit board |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019105332A1 (en) * | 2017-11-28 | 2019-06-06 | Bitmain Technologies Inc. | Computational integrated circuit chip and corresponding circuit board |
| CN110825664A (en) * | 2018-08-10 | 2020-02-21 | 北京百度网讯科技有限公司 | Information processing system and method |
-
2017
- 2017-11-28 CN CN201721617833.8U patent/CN207503223U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019105332A1 (en) * | 2017-11-28 | 2019-06-06 | Bitmain Technologies Inc. | Computational integrated circuit chip and corresponding circuit board |
| CN110825664A (en) * | 2018-08-10 | 2020-02-21 | 北京百度网讯科技有限公司 | Information processing system and method |
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