CN110113147A - A kind of digital encryption device and method - Google Patents
A kind of digital encryption device and method Download PDFInfo
- Publication number
- CN110113147A CN110113147A CN201910290575.4A CN201910290575A CN110113147A CN 110113147 A CN110113147 A CN 110113147A CN 201910290575 A CN201910290575 A CN 201910290575A CN 110113147 A CN110113147 A CN 110113147A
- Authority
- CN
- China
- Prior art keywords
- module
- information
- process control
- data information
- enable signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
The invention belongs to digital encryption fields, disclose a kind of digital encryption device and method, and data resolution module generates control information and primary data information (pdi) according to data packet；Process control module generates k enable signal according to the control information；The 1st enable signal is sent, so that the 1st hardware encryption module generates the 1st intermediate data information and the 1st feedback information according to primary data information (pdi)；And i-th of enable signal is successively sent according to (i-1)-th feedback signal and successively the value of i is updated according to the number of hardware encryption module, so that i-th of hardware encryption module generates i-th of intermediate data information according to (i-1)-th intermediate data information and i-th of enable signal and store, and i-th of feedback information is sent to process control module；Process control module sends END instruction so that data resolution module reads i-th of intermediate data information when i is more than or equal to k；It is adapting to different digital encryption algorithms and is reducing hardware cost.
Description
Technical field
The invention belongs to digital encryption field more particularly to a kind of digital encryption device and methods.
Background technique
Digital encryption algorithm is a kind of reliable method protected to information, it carries out information using cryptographic technique
Information screen is realized in encryption, to play the role of protecting information security.Two methods of software and hardware can technically be passed through
It realizes.And hardware approach has big advantage in speed.
With the large-scale application of the rapid development of semiconductor devices, especially ASIC, single digital encryption algorithm is very
The method for being easy infinitely to be collided cracks, to obtain corresponding hash value (useful information).In order to obtain more hash values,
People rely on CPU, GPU, FPGA, and the especially mode of asic chip forms high performance computing service device, for specific encryption
Algorithm, which is done, to be optimized quickly to crack Encryption Algorithm.Current many non-mainstream digital encryption algorithms are in order to maintain for ASIC's
Repellence, it strings together these algorithms by combining polyalgorithm, by certain rules.Once it was found that there is ASIC
When equipment is calculated, original algorithm team (can increase algorithm quantity, adjustment algorithm maps sequence by fine tune algorithm rapidly
Number, increase XOR operation etc.) so that the ASIC of rival fails, force its ASIC device to be scrapped.Because ASIC composition
Although high performance computing service device lower production costs, much faster, flexibility ratio is very low by calculating speed ratio x86CPU/GPU,
It can only be accelerated for specific algorithm, once algorithm is modified, existing investment will come to naught, and in general volume is huge
Greatly, special power supply and heat dissipation equipment are needed, it is not portable.Many non-mainstream digital encryption algorithms are all to use at present
X86CPU or GPU carries out high-performance calculation, although relatively flexibly, not influenced by algorithm modification, hardware cost compared with
It is high.
Therefore traditional digital encryption device haves the defects that hardware cost can not be reduced while adapting to different algorithms.
Summary of the invention
The present invention provides a kind of digital encryption device and methods, it is intended to solve nothing existing for traditional digital encryption device
Method reduces the problem of hardware cost while adapting to different algorithms.
On the one hand, the present invention provides a kind of digital encryption device, the digital encryption device includes:
For generating the data resolution module of control information and primary data information (pdi) according to the data packet received；
It is connect with the data resolution module, for generating k enable signal according to the control information；Send the 1st
Enable signal, so that the 1st hardware encryption module generates in the 1st according to the 1st enable signal and the primary data information (pdi)
Between data information and the 1st feedback information process control module；Wherein, k is the number of hardware encryption module, and k is greater than 2
Integer；
The process control module is also used to successively send i-th of enable signal to i-th according to (i-1)-th feedback signal
Hardware encryption module is simultaneously successively updated the value of i according to the number of hardware encryption module, so that i-th of hardware encryption module
I-th of intermediate data information is generated according to (i-1)-th intermediate data information and i-th of enable signal and is stored to storage mould
Block, and i-th of feedback information is sent to process control module；
The process control module be also used to when i be more than or equal to k when, send END instruction so that data resolution module according to
I-th of intermediate data information is read in the END instruction；
K hardware encryption module being connect with the process control module；
The memory module being connect with the data resolution module and the k hardware encryption modules.
On the other hand, the present invention provides a kind of digital encryption method, the digital encryption method includes:
Data resolution module generates control information and primary data information (pdi) according to the data packet received；
Process control module generates k enable signal according to the control information；Wherein, k is of hardware encryption module
Number, k are the integer greater than 2；
1st hardware encryption module generates the 1st intermediate data according to the 1st enable signal and the primary data information (pdi)
Information and the 1st feedback information；
I is set as 2 according to the 1st feedback information by the process control module；
I-th of enable signal is sent to corresponding i-th firmly according to (i-1)-th feedback information by the process control module
Part encrypting module；
I-th of hardware encryption module generates the according to (i-1)-th intermediate data information and i-th of enable signal
I intermediate data information is simultaneously stored to memory module, and sends i-th of feedback information to the process control module；
The process control module judges whether i is more than or equal to k；
If process control module, which judges that i is not more than, is equal to k, by i be updated to i's and 1 and, and execute the Row control
The step of i-th of enable signal is sent to corresponding i-th of hardware encryption module according to (i-1)-th feedback information by module；
If process control module judges that i is more than or equal to k, END instruction is sent；
The data resolution module reads i-th of intermediate data information according to the END instruction.
The embodiment of the present invention by process control module due to that can flexibly can call the execution sequence of algorithm and calculate
The quantity of method；Only need software modification mapping relations that can support new algorithm structure when algorithm changes；Polyalgorithm
Module can support different calculations and different digital confidentiality algorithm by the combination between algoritic module；And it is deposited by shared
The mode of storage realizes the minimum of hardware cost；Therefore it realizes and reduces hardware while adapting to different digital encryption algorithms
Cost.
Detailed description of the invention
Technological invention in order to illustrate the embodiments of the present invention more clearly will make below to required in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of function structure chart of digital encryption device provided in an embodiment of the present invention；
Fig. 2 is another function structure chart of digital encryption device provided in an embodiment of the present invention；
Fig. 3 is the implementation process schematic diagram of digital encryption method provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The modular structure that Fig. 1 shows digital encryption device provided in an embodiment of the present invention is only shown for ease of description
Part related to the embodiment of the present invention, details are as follows:
Above-mentioned digital encryption device include data resolution module 01, process control module 02, k hardware encryption module 03 with
And memory module 04.
Data resolution module 01 is used to generate control information and primary data information (pdi) according to the data packet received.
Process control module 02 is connect with data resolution module 01, for generating k enable signal according to the control information；Hair
The 1st enable signal is sent, so that the 1st hardware encryption module 03 generates the 1st according to the 1st enable signal and primary data information (pdi)
A intermediate data information and the 1st feedback information；Wherein, k is the number of hardware encryption module 03, and k is the integer greater than 2.
Process control module 02 be also used to successively according to (i-1)-th feedback signal send i-th of enable signal to i-th it is hard
Part encrypting module 03 is simultaneously successively updated the value of i according to the number of hardware encryption module 03, so that i-th of hardware encrypts mould
Block 03 generates i-th of intermediate data information according to (i-1)-th intermediate data information and i-th of enable signal and stores to storage mould
Block 04, and i-th of feedback information is sent to process control module 02.
Process control module 02 is also used to send END instruction so that 01 basis of data resolution module when i is more than or equal to k
I-th of intermediate data information is read in END instruction.
K hardware encryption module 03 is connect with process control module 02.
Memory module 04 is connect with data resolution module 01 and k hardware encryption module 03.
Process control module 02 receives the control information that data resolution module 01 is sent, and reorganizes calculate according to the control information
The sequence that method executes, there is a state machines inside process control module 02, will be sequentially generated respectively according to the sequence of algorithm
The enable signal of a hardware encryption module 03 can generate feedback signal, process after hardware encryption module 03 has executed calculating
It is seamless to be switched to next 03 module of hardware encryption module after control module 02 receives feedback signal, it sends corresponding hard
The enable signal of part encrypting module 03.The execution sequence of each algorithm is write in process control module 02 by software to reach
High efficient and flexible data calculate.State machine can be used in process control module 02, RISC, CPU or other control modes are realized.
Hardware encryption module 03 is the hardware realization of each independent Encryption Algorithm and common operative algorithm.It can root
Hardware realization, such as SHA256, DES, AES, RSA, ECC are carried out according to the demand of application, there are also some common wide digits
XOR operation, multiply-add operation, add operation, high-performance multiplying and shift operation etc..Its by an enable signal come
It is enabled, the data source of hardware encryption module 03 is in memory module 04, the results of intermediate calculations of hardware encryption module 03
It is stored in memory module 04, hardware encryption module 03 will be tied by calculating width as wide as possible and time as few as possible
Fruit is calculated, and the result of calculating also is stored in memory module 04 so that next hardware encryption module 03 carries out taking meter
It calculates.It is provided great flexibility to algorithm.
Memory module 04 can be shared storage array.Have two layers inside shared storage array, wherein one layer (first layer)
Data information is wanted for storing, in addition is used to store intermediate data information for one layer (second layer).Data information is by data solution
Analysis module 01 obtains, and is a relatively-stationary data, and the data of certain segment need to carry out according to demand from increasing, when each
When circulation starts, first hardware encryption module 03 calculated can be taken from the storage of this layer, and to increasing data certainly
Duan Jinhang is from increasing to take next time.The shared storage array of another layer of storage calculated result can be by calculated intermediate data
Information is stored, when entire circulation is completed, the beginning algorithm on the one hand newly recycled the data in first layer can be taken into
It is calculated, the data in the second layer can be packaged and issue data resolution module 01 by the same period, so as to next cycle
Vacating space come store algorithm calculating result.Hardware implementation cost can be substantially saved in this way, reach low cost
Target.The shared storage pool scheme of the innovation, can be greatly decreased the use of register, reduce the area of chip, reach it is low at
The design target.
As shown in Fig. 2, digital encryption device further includes PCIE interface module 05.
PCIE interface module 05 is connect with data resolution module 01, the data packet for forwarding host computer to send.
Data resolution module 01 is also used to judge whether i-th of intermediate data information meets default association according to configuration information
View.
If data resolution module 01 judges that i-th of intermediate data information meets preset protocol, PCIE according to configuration information
Interface module 05 is also used to forward i-th of intermediate data information to host computer.
Pass through PCIE (peripheral component interconnect express, the extension of high speed serialization computer
Bus standard) plug and play may be implemented in interface module, and without configuring power supply, electricity directly is taken from PCIE, cost is reduced, flexibly makes
With.PCIE was proposed by Intel in 2001, it is intended to substitute old PCI, PCI-X and AGP bus standard.PCIe belongs to high speed
Serial point-to-point binary channels high bandwidth transmission, the equipment distribution connected exclusively enjoys bandwidth chahnel, does not share bus bandwidth, main to prop up
Hold active power management, error reporting, end-to-end reliability transmission, the functions such as hot plug and service quality.PCI at present
Express 4.0 provides 16Gb/s bit rate.This interface can provide the quickly ability with host exchanging data.Work as high-performance
When calculation server chip is by PCIE interface access host on computer motherboard, software service program will be counted by driving
The data of calculation are sent to high performance computing service device chip by driving.High performance computing service device chip connects as a slave
The calculating data of host are received, and result is put back to host.Warm connection function is provided by PCIE interface, function of supplying power, and
The data communication link of high speed is provided, efficient data transport service, and ease for use and the available guarantee of high-performance are provided.
The present invention also provides a kind of digital encryption method, as shown in figure 3, digital encryption method includes step 301 to step
Rapid 308.
In step 301, data resolution module generates control information and primary data information (pdi) according to the data packet received.
In step 302, process control module generates k enable signal according to the control information；Wherein, k is hardware encryption
The number of module, k are the integer greater than 2.
In step 303, the 1st hardware encryption module generates the 1st according to the 1st enable signal and primary data information (pdi)
Intermediate data information and the 1st feedback information.
In step 304, i is set as 2 according to the 1st feedback information by process control module.
In step 305, i-th of enable signal is sent to correspondence according to (i-1)-th feedback information by process control module
I-th of hardware encryption module.
Within step 306, i-th of hardware encryption module is raw according to (i-1)-th intermediate data information and i-th of enable signal
It at i-th of intermediate data information and stores to memory module, and sends i-th of feedback information to process control module.
In step 307, process control module judges whether i is more than or equal to k.
In step 308, if process control module, which judges that i is not more than, is equal to k, by i be updated to i's and 1 and, and execute
Step 305.
In a step 309, if process control module judges that i is more than or equal to k, END instruction is sent.
In step 3010, data resolution module reads i-th of intermediate data information according to END instruction.
Step 301 further includes before step 300 in specific implementation.
In step 300, the data packet that PCIE interface module forwarding host computer is sent.
It can also include step 3011 and step 3012 after step 3010 in specific implementation.
In step 3011, it is pre- that data resolution module according to configuration information judges whether i-th of intermediate data information meets
If agreement.
In step 3012, if according to configuration information to judge that i-th of intermediate data information meets default for data resolution module
Agreement, then PCIE interface module forwards i-th of intermediate data information to host computer.
The embodiment of the present invention generates control information and initial data according to the data packet received by data resolution module
Information；Process control module generates k enable signal according to the control information；The 1st enable signal is sent, so that the 1st hardware
Encrypting module generates the 1st intermediate data information and the 1st feedback information according to the 1st enable signal and primary data information (pdi)；
Wherein, k is the number of hardware encryption module, and k is the integer greater than 2；And it is successively sent i-th according to (i-1)-th feedback signal
Enable signal is successively updated the value of i to i-th of hardware encryption module and according to the number of hardware encryption module, so that the
I hardware encryption module generates i-th of intermediate data information simultaneously according to (i-1)-th intermediate data information and i-th of enable signal
It stores to memory module, and sends i-th of feedback information to process control module；Process control module when i be more than or equal to k when,
END instruction is sent so that data resolution module reads i-th of intermediate data information according to END instruction；Therefore it realizes and is adapting to
Hardware cost is reduced while different digital encryption algorithm.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of digital encryption device, which is characterized in that the digital encryption device includes:
For generating the data resolution module of control information and primary data information (pdi) according to the data packet received；
It is connect with the data resolution module, for generating k enable signal according to the control information；The 1st is sent to enable
Signal, so that the 1st hardware encryption module generates the 1st mediant according to the 1st enable signal and the primary data information (pdi)
It is believed that the process control module of breath and the 1st feedback information；Wherein, k is the number of hardware encryption module, and k is whole greater than 2
Number；
The process control module is also used to successively send i-th of enable signal to i-th of hardware according to (i-1)-th feedback signal
Encrypting module is simultaneously successively updated the value of i according to the number of hardware encryption module so that i-th of hardware encryption module according to
(i-1)-th intermediate data information and i-th of enable signal generate i-th of intermediate data information and store to memory module,
And i-th of feedback information is sent to process control module；
The process control module is also used to when i is more than or equal to k, sends END instruction so that data resolution module is according to
I-th of intermediate data information is read in END instruction；
K hardware encryption module being connect with the process control module；
The memory module being connect with the data resolution module and the k hardware encryption modules.
2. digital encryption device as described in claim 1, which is characterized in that the digital encryption device further include:
It is connect with data resolution module, the PCIE interface module of the data packet for forwarding host computer to send.
3. digital encryption device as described in claim 1, which is characterized in that data resolution module is also used to according to configuration information
Judge whether i-th of intermediate data information meets preset protocol.
4. digital encryption device as described in claim 1, which is characterized in that if data resolution module judges according to configuration information
I-th of intermediate data information meets preset protocol, then PCIE interface module is also used to forward i-th of intermediate data information extremely
Host computer.
5. a kind of digital encryption method, which is characterized in that the digital encryption method includes:
Data resolution module generates control information and primary data information (pdi) according to the data packet received；
Process control module generates k enable signal according to the control information；Wherein, k is the number of hardware encryption module, k
For the integer greater than 2；
1st hardware encryption module generates the 1st intermediate data information according to the 1st enable signal and the primary data information (pdi)
With the 1st feedback information；
I is set as 2 according to the 1st feedback information by the process control module；
I-th of enable signal is sent to corresponding i-th of hardware according to (i-1)-th feedback information and added by the process control module
Close module；
I-th of hardware encryption module generates i-th according to (i-1)-th intermediate data information and i-th of enable signal
Intermediate data information is simultaneously stored to memory module, and sends i-th of feedback information to the process control module；
The process control module judges whether i is more than or equal to k；
If process control module, which judges that i is not more than, is equal to k, by i be updated to i's and 1 and, and execute the process control module
The step of i-th of enable signal is sent to corresponding i-th of hardware encryption module according to (i-1)-th feedback information；
If process control module judges that i is more than or equal to k, END instruction is sent；
The data resolution module reads i-th of intermediate data information according to the END instruction.
6. digital encryption device as claimed in claim 5, which is characterized in that the data resolution module is according to the number received
It is generated before controlling information and primary data information (pdi) according to packet further include:
The data packet that PCIE interface module forwards host computer to send.
7. digital encryption device as claimed in claim 5, which is characterized in that the data resolution module refers to according to the end
It enables after reading i-th of intermediate data information further include:
The data resolution module judges whether i-th of intermediate data information meets preset protocol according to configuration information.
8. digital encryption device as claimed in claim 5, which is characterized in that the data resolution module refers to according to the end
It enables after reading i-th of intermediate data information further include:
If the data resolution module judges that i-th of intermediate data information meets the preset protocol according to configuration information,
Then the PCIE interface module forwards i-th of intermediate data information to host computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910290575.4A CN110113147A (en) | 2019-04-11 | 2019-04-11 | A kind of digital encryption device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910290575.4A CN110113147A (en) | 2019-04-11 | 2019-04-11 | A kind of digital encryption device and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110113147A true CN110113147A (en) | 2019-08-09 |
Family
ID=67483829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910290575.4A Pending CN110113147A (en) | 2019-04-11 | 2019-04-11 | A kind of digital encryption device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110113147A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111143897A (en) * | 2019-12-24 | 2020-05-12 | 海光信息技术有限公司 | Data security processing device, system and processing method |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737415A (en) * | 1994-08-10 | 1998-04-07 | Fujitsu Limited | Data management module, data reproduction management device and data reproduction management system |
| US20070098155A1 (en) * | 2005-10-19 | 2007-05-03 | Yukiyoshi Nagasawa | Data processing device and data processing method |
| CN101281503A (en) * | 2008-05-29 | 2008-10-08 | 上海交通大学 | IDE hard disc physical enciphering system based on MEMS enciphered lock and double FPGA |
| US7634666B2 (en) * | 2003-08-15 | 2009-12-15 | Cityu Research Limited | Crypto-engine for cryptographic processing of data |
| CN102223228A (en) * | 2011-05-11 | 2011-10-19 | 北京航空航天大学 | Method for designing AES (Advanced Encryption Standard) encryption chip based on FPGA (Field Programmable Gate Array) and embedded encryption system |
| CN103731822A (en) * | 2012-10-15 | 2014-04-16 | 中国科学院微电子研究所 | System and method for achieving ZUC |
| CN105897407A (en) * | 2016-06-02 | 2016-08-24 | 北京赛思信安技术股份有限公司 | High-speed finite-length RC4 encryption and decryption device |
| CN106254286A (en) * | 2016-09-29 | 2016-12-21 | 上海航天测控通信研究所 | The adaptive blind equalization method of high-speed parallel process and device |
| CN106599735A (en) * | 2017-02-13 | 2017-04-26 | 珠海格力电器股份有限公司 | Data protection device and method, and storage controller |
| CN106850214A (en) * | 2017-03-13 | 2017-06-13 | 上海新储集成电路有限公司 | A kind of parallel encipher-decipher method |
| CN206348799U (en) * | 2016-09-19 | 2017-07-21 | 爱国者安全科技（北京）有限公司 | Encrypt storage device and safe storage system |
| CN108470129A (en) * | 2018-03-13 | 2018-08-31 | 杭州电子科技大学 | A kind of data protection special chip |
| CN109146258A (en) * | 2018-07-27 | 2019-01-04 | 深圳市致宸信息科技有限公司 | Driving data processing method and processing device based on block chain |
| CN109167662A (en) * | 2018-09-04 | 2019-01-08 | 上海易酷信息技术服务有限公司 | A kind of seed generation method and its equipment |
-
2019
- 2019-04-11 CN CN201910290575.4A patent/CN110113147A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737415A (en) * | 1994-08-10 | 1998-04-07 | Fujitsu Limited | Data management module, data reproduction management device and data reproduction management system |
| US7634666B2 (en) * | 2003-08-15 | 2009-12-15 | Cityu Research Limited | Crypto-engine for cryptographic processing of data |
| US20070098155A1 (en) * | 2005-10-19 | 2007-05-03 | Yukiyoshi Nagasawa | Data processing device and data processing method |
| CN101281503A (en) * | 2008-05-29 | 2008-10-08 | 上海交通大学 | IDE hard disc physical enciphering system based on MEMS enciphered lock and double FPGA |
| CN102223228A (en) * | 2011-05-11 | 2011-10-19 | 北京航空航天大学 | Method for designing AES (Advanced Encryption Standard) encryption chip based on FPGA (Field Programmable Gate Array) and embedded encryption system |
| CN103731822A (en) * | 2012-10-15 | 2014-04-16 | 中国科学院微电子研究所 | System and method for achieving ZUC |
| CN105897407A (en) * | 2016-06-02 | 2016-08-24 | 北京赛思信安技术股份有限公司 | High-speed finite-length RC4 encryption and decryption device |
| CN206348799U (en) * | 2016-09-19 | 2017-07-21 | 爱国者安全科技（北京）有限公司 | Encrypt storage device and safe storage system |
| CN106254286A (en) * | 2016-09-29 | 2016-12-21 | 上海航天测控通信研究所 | The adaptive blind equalization method of high-speed parallel process and device |
| CN106599735A (en) * | 2017-02-13 | 2017-04-26 | 珠海格力电器股份有限公司 | Data protection device and method, and storage controller |
| CN106850214A (en) * | 2017-03-13 | 2017-06-13 | 上海新储集成电路有限公司 | A kind of parallel encipher-decipher method |
| CN108470129A (en) * | 2018-03-13 | 2018-08-31 | 杭州电子科技大学 | A kind of data protection special chip |
| CN109146258A (en) * | 2018-07-27 | 2019-01-04 | 深圳市致宸信息科技有限公司 | Driving data processing method and processing device based on block chain |
| CN109167662A (en) * | 2018-09-04 | 2019-01-08 | 上海易酷信息技术服务有限公司 | A kind of seed generation method and its equipment |
Non-Patent Citations (5)
| Title |
|---|
| WANJUN YU ECT.: "High Performance PCIe Interface for the TPCM based on Linux platform", 《2015 8TH INTERNATIONAL SYMPOSIUM ON COMPUTATIONAL INTELLIGENCE AND DESIGN》 * |
| WANJUN YU ECT.: "High Performance PCIe Interface for the TPCM based on Linux platform", 《2015 8TH INTERNATIONAL SYMPOSIUM ON COMPUTATIONAL INTELLIGENCE AND DESIGN》, 12 May 2016 (2016-05-12) * |
| 许鹏: "基于 PCI 接口和 ATA 接口的物理认证和物理加密", 《中国优秀硕士毕业论文（信息科技辑）》 * |
| 许鹏: "基于 PCI 接口和 ATA 接口的物理认证和物理加密", 《中国优秀硕士毕业论文（信息科技辑）》, 15 December 2009 (2009-12-15) * |
| 郑光熙等: "基于COM口通信数据加密系统设计与实现", 《岭南师范学院学报》, no. 03, 15 June 2016 (2016-06-15) * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111143897A (en) * | 2019-12-24 | 2020-05-12 | 海光信息技术有限公司 | Data security processing device, system and processing method |
| CN111143897B (en) * | 2019-12-24 | 2023-11-17 | 海光信息技术股份有限公司 | Data security processing device, system and processing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3758282A1 (en) | Combined sha2 and sha3 based xmss hardware accelerator | |
| US20190132118A1 (en) | Technologies for low-latency cryptography for processor-accelerator communication | |
| CN108345806B (en) | Hardware encryption card and encryption method | |
| CN107103472B (en) | Algorithm processing module for block chain | |
| US20110123020A1 (en) | Endecryptor capable of performing parallel processing and encryption/decryption method thereof | |
| US20220337421A1 (en) | Low latency post-quantum signature verification for fast secure-boot | |
| US11423179B2 (en) | Integrated-chip-based data processing method, computing device, and storage media | |
| EP3758275B1 (en) | Post quantum public key signature operation for reconfigurable circuit devices | |
| EP3886360A1 (en) | Robust state synchronization for stateful hash-based signatures | |
| TW200830327A (en) | System and method for encrypting data | |
| CN112367155B (en) | FPGA-based ZUC encryption system IP core construction method | |
| WO2022132184A1 (en) | System, method and apparatus for total storage encryption | |
| CN109344664A (en) | A kind of cipher card and its encryption method that based on FPGA data are carried out with algorithm process | |
| CN110113147A (en) | A kind of digital encryption device and method | |
| US20210328779A1 (en) | Method and apparatus for fast symmetric authentication and session key establishment | |
| KR101923210B1 (en) | Apparatus for cryptographic computation on heterogeneous multicore processors and method thereof | |
| Nguyen et al. | A Lightweight AEAD encryption core to secure IoT applications | |
| CN114553411B (en) | Distributed memory encryption device and distributed memory decryption device | |
| US20230185905A1 (en) | Protection of authentication tag computation against power and electromagnetic side-channel attacks | |
| CN116073987A (en) | Reliability design method of block cipher mode, cipher card and server | |
| US10326587B2 (en) | Ultra-lightweight cryptography accelerator system | |
| US20210273790A1 (en) | Client device | |
| CN112865960B (en) | System, method and device for realizing high-speed key chain pre-calculation based on stream cipher | |
| CN210274109U (en) | Ethernet card device supporting encryption function | |
| JP5744673B2 (en) | Information processing system, information processing method, and program |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20230106 |