WO2019100553A1 - 一种Mura现象补偿方法及其装置 - Google Patents

一种Mura现象补偿方法及其装置 Download PDF

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WO2019100553A1
WO2019100553A1 PCT/CN2018/071672 CN2018071672W WO2019100553A1 WO 2019100553 A1 WO2019100553 A1 WO 2019100553A1 CN 2018071672 W CN2018071672 W CN 2018071672W WO 2019100553 A1 WO2019100553 A1 WO 2019100553A1
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compensation data
timing control
compensation
small
display panel
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PCT/CN2018/071672
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English (en)
French (fr)
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张华�
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/757,397 priority Critical patent/US11043173B1/en
Publication of WO2019100553A1 publication Critical patent/WO2019100553A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application relates to the field of display technologies, and in particular, to a Mura phenomenon compensation method and apparatus therefor.
  • the Timer Control Integrated Circuit has certain limitations on the data processing capability, such as a timing control chip that supports a maximum resolution of 3840*2160 and a refresh rate of 120 Hz.
  • the 7680*4320 resolution and 60Hz refresh rate display panel requires two timing control chips to be used in parallel.
  • the single timing control chip is responsible for the left, right, or upper and lower display areas.
  • the light and dark difference compensation technology of the display panel may encounter some problems in use, and the camera captures the display area of the entire display panel and calculates a corresponding grayscale compensation data matrix.
  • the timing control chips When the gray scale compensation data matrix is simultaneously transmitted to the plurality of timing control chips in parallel operation, since the single timing control chip is only responsible for data of a certain display area of the display panel, the timing control chips cannot distinguish between the corresponding areas of the control area. Effective compensation of the data matrix will result in errors in the compensation effect of each timing control chip.
  • the main purpose of the present application is to provide a Mura phenomenon compensation method and a device thereof, which are intended to achieve a correct compensation effect when the plurality of timing control chips are operated in parallel.
  • a Mura phenomenon compensation method for multiple timing control chips to process a display panel in parallel, which includes the following steps: Step 1: photographing the display area of the entire display panel; Step 2: calculating the entire display a compensation data matrix a of the display area of the panel; Step 3: The number of the plurality of timing control chips is set to N, and the display panel is divided into N small parts, and each of the timing control chips controls each of the small Part; Step 4: Set the resolution of the display panel to B1*B2, set the reference point of the compensation data matrix a equal interval to A1*A2, and the compensation data matrix a equals (B1/A1+1)*(B2/A2) +1), when the reference points corresponding to the N small parts are integers, the compensation data matrix a is split into N small matrices C, and each of the small matrices C is equal to (B1/A1+1)* ( (B2/A2)/N+1); when the reference points corresponding to the N small parts are not integers
  • each of the timing control chips is correspondingly connected to a flash memory, and each of the small matrices C is input to each of the flash memories.
  • the N timing control chips are commonly connected to a flash memory, and the flash memory is divided into N storage areas, and each of the small matrices C is input to each of the storage areas.
  • the setting N is equal to 2
  • the resolution of the display panel is set to 7680*4320
  • the reference point of the interval setting is 16*16
  • the compensation data matrix a is 481*271, at which time the two said small Partially corresponding reference points are integers
  • each of the small matrices C is 481*136.
  • the compensation data matrix a is 481*271 and is divided into two upper and lower small matrices, the compensation data of the 136th row of the compensation data matrix a is copied.
  • the setting N is equal to 2
  • the resolution of the display panel is set to 7680*4320
  • the reference point of the interval setting is 32*32
  • the compensation data matrix a is 241*136, at which time the two small parts are
  • the reference points corresponding to the display area are not integers
  • each of the small matrices C is 241*69.
  • the compensation data matrix a is 241*136 into two upper and lower small matrices
  • the compensation data of the 68th line and the 69th line of the compensation data matrix a is copied.
  • the present application further provides a Mura phenomenon compensation device, comprising: a display panel, the display panel is divided into a plurality of display areas; a plurality of timing control chips, each of the timing control chips and each of the display areas Corresponding connection; Mura phenomenon compensation processing chip for connecting with the timing control chip, the Mura phenomenon compensation processing chip is used for calculating the compensation data matrix a of the display area of the entire display panel, and splitting the compensation data matrix a into multiple A small matrix, each small matrix of data correspondingly compensating for each of the display areas.
  • each of the timing control chips is correspondingly connected to a flash memory, and data of each of the small matrices is input into each of the flash memories.
  • the plurality of timing control chips are connected in common to a flash memory, and the flash memory is divided into N storage areas, and data of each of the small matrices is input into each of the storage areas.
  • the Mura phenomenon compensation method and device provided by the application are respectively divided into the regions corresponding to the respective timing control chips by the compensation data of all regions of the display panel, and are respectively stored in different positions in the flash storage area, and the timings are respectively When the control chip is working, only the partial compensation data corresponding to itself is read, which avoids the fact that the plurality of timing control chips cannot distinguish the effective compensation data matrix corresponding to the area responsible for their own, thereby causing errors in the compensation effects of the respective timing control chips.
  • FIG. 1 is a schematic structural view of a Mura phenomenon compensation device according to the present application.
  • FIG. 2 is a flow chart of a first embodiment of a method for compensating for a Mura phenomenon according to the present application
  • FIG. 3 is a schematic flow chart of a second embodiment of a method for compensating a Mura phenomenon according to the present application
  • FIG. 4 is a schematic flow chart of a third embodiment of a method for compensating a Mura phenomenon according to the present application.
  • FIG. 5 is another schematic flowchart of the third embodiment of the Mura phenomenon compensation method of the present application.
  • the display panel such as a liquid crystal display panel (LCD panel) or an organic light emitting diode display panel (OLED panel)
  • LCD panel liquid crystal display panel
  • OLED panel organic light emitting diode display panel
  • the control factor causes the physical characteristics of the display panel to be different, resulting in uneven brightness when displaying a pure grayscale image in a range larger than one pixel point, that is, the Mura phenomenon in the industry.
  • the Mura phenomenon compensation method provided by the first embodiment of the present application is used for a display panel in which a plurality of timing control integrated circuits (TCON ICs) are processed in parallel.
  • the display panel is an LCD panel.
  • the Mura phenomenon compensation method includes the following steps:
  • Step 1 photographing the display area of the entire display panel, specifically, taking a picture of a display panel displaying a certain gray scale image with a camera directly above the center point of the display panel, and obtaining brightness data of the display panel by using the acquired image.
  • Step 2 Calculate the compensation data matrix a of the display area of the entire display panel according to the collected brightness data.
  • the Mura phenomenon compensation processing chip is connected to the timing control chip, and the Mura phenomenon compensation processing chip is used to calculate the compensation data matrix a of the display area of the entire display panel.
  • Step 3 The number of the plurality of timing control chips is set to N, and the display panel is divided into N small portions, and each of the timing control chips controls each of the small portions. Specifically, the compensation data of all areas of the display panel is split into the area portions corresponding to each of the timing control chips.
  • Step 4 Set the resolution of the display panel to B1*B2, and set the reference point of the compensation data matrix a to be equal to A1*A2.
  • the compensation data matrix a is equal to (B1/A1+1)*(B2/A2+1); when the reference points corresponding to the N small parts are integers, the compensation data matrix a is split into N a small matrix C, each of the small matrices C is equal to (B1/A1+1)*((B2/A2)/N+1); when the reference points corresponding to the N small parts are not integers, The compensation data matrix a is split into N small matrices C, each of which is equal to (B1/A1+1)*((B2/A2+1)/N+1).
  • Step 5 Input each of the small matrices into each of the corresponding timing control chips.
  • each of the timing control chips is correspondingly connected to a flash memory (also referred to as a flash memory), and each of the small matrices C is input into each of the flash memories.
  • the N timing control chips are commonly connected to a flash memory, and the flash memory is divided into N storage areas, and each of the small matrices C is input to each of the storage areas.
  • Step 6 Each of the timing control chips only reads the compensation data of the small matrix corresponding to the timing control chip, so that each of the timing control chips only reads the partial compensation data corresponding thereto, thereby making When the timing control chip is operated in parallel, the brightness compensation function of the display panel achieves the correct compensation effect, and the effective compensation data matrix corresponding to the region responsible for the region cannot be distinguished from the plurality of timing control chips, which may result in The compensation effect of each timing control chip is wrong.
  • the N setting of the plurality of timing control chips is equal to 2, that is, the timing control chip 1 (referred to as TCON1) and the timing control chip 2 ( Referred to as TCON2).
  • TCON1 the timing control chip 1
  • TCON2 the timing control chip 2
  • TCON2 the timing control chip 2
  • the compensation data reference point corresponding to the upper and lower portions of the display area is an integer, and the first row of pixels in the lower half is exactly the position of the compensation data reference point, but the compensation data of the last few pixels of the upper half needs to be used.
  • the compensation data matrix a of the entire display panel compensation reference point needs to be divided into upper and lower parts a1 and a2, which are respectively stored in different flash memories, corresponding to Two timing control chips are connected, and two timing control chips, TCON1 and TCON2, respectively read different flash memories when reading compensation data.
  • compensation data matrix a is 481*271 data
  • the position of compensation data of the 136th line of compensation data matrix a falls just on the first line of the lower half display area
  • the compensation data of the pixels in the last half of the display area of the upper half of the display area needs to be linearly interpolated by the compensation data of the 135th line and the 136th line in the compensation data matrix a, so it is necessary to split the compensation data matrix a.
  • the compensation data of the 136th line is copied, that is, the compensation data of the 136th line in the compensation data matrix a is used as the compensation data of the 136th line of the small matrix a1 (upper half), and also serves as the small matrix a2 (lower half).
  • the first line of the compensation data such that the small matrix a1 and the small matrix a2 are both 481*136 data matrices.
  • the N setting of the plurality of timing control chips is equal to 2, that is, the timing control chip 1 (referred to as TCON1) and the timing control. Chip 2 (TCON2 for short).
  • TCON1 the timing control chip 1
  • TCON2 the timing control. Chip 2
  • TCON1 the timing control chip 1
  • TCON2 the timing control. Chip 2
  • the resolution of the display panel is 7680*4320
  • the reference point of the interval setting is 32*32
  • the compensation data matrix a is 241*136.
  • the reference points corresponding to the display areas of the two small parts are not integers.
  • Each of the small matrices C is 241*69.
  • the compensation data reference point corresponding to the upper and lower partial display areas is not an integer, the 7680*4320 resolution, the compensation reference point interval setting is 32*32, and the compensation data matrix b is 241*136 data.
  • the boundary line of the display area of the upper and lower parts is just in the middle of the equal interval setting area where the compensation data of the 68th line and the 69th line of the compensation data matrix b is located, and the compensation data of the 69th line needs to be placed in the upper display area.
  • the compensation data of the 68th line and the 69th line of the compensation data matrix b are still used for 32*. 32 equally spaced linear interpolation calculations (pixel data from lines 17 to 32 in these intervals do not need to be calculated).
  • the 68th line of compensation data of the compensation data matrix b needs to be placed in the small matrix b2 of the lower half display area, and the pixel position of the 1st line of the lower half display area is the 68th line and the The 17th row of pixels in the equal interval corresponding to the 69-line compensation data.
  • the timing control chip When the timing control chip receives the grayscale data of the original pixel and calculates the compensation data of the corresponding pixel position, it is necessary to increase the row position of all the original pixels by 16, That is, the pixel of the first row of the display area becomes the pixel position of the 17th row in the small matrix b2, so that the compensation data calculated by the linear interpolation can correctly correspond to the position of the original pixel.
  • the present application includes a Mura phenomenon compensation device including a display panel that is divided into a plurality of display areas. A plurality of timing control chips, each of the timing control chips being respectively connected to each of the display areas. a Mura phenomenon compensation processing chip for connecting to the timing control chip, the Mura phenomenon compensation processing chip is configured to calculate a compensation data matrix a of the display area of the entire display panel, and split the compensation data matrix a into a plurality of small matrices. The data of each small matrix corresponds to each of the display areas.
  • each of the timing control chips is correspondingly connected to a flash memory, and data of each of the small matrices is input into each of the flash memories.
  • a plurality of the timing control chips are connected in common to a flash memory, and the flash memory is divided into N storage areas, and data of each of the small matrices is input into each of the storage areas. .
  • each of the timing control chips only reads the compensation data of the small matrix corresponding to the time, so that each of the timing control chips only reads the partial compensation data corresponding thereto, thereby making
  • the Mura compensation function can still work normally, which avoids the fact that multiple timing control chips cannot distinguish the effective compensation data matrix corresponding to their responsible regions, which will result in each timing control chip. The compensation effect is wrong.

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Abstract

一种Mura现象补偿方法及其装置，通过将显示面板所有区域的补偿数据拆分成各时序控制芯片对应负责的区域部分，分别存储在flash存储区中的不同位置，各时序控制芯片工作时只读取自身对应的部分补偿数据，避免了多个时序控制芯片之间无法区分自身负责区域所对应的有效补偿数据矩阵，从而导致各个时序控制芯片的补偿效果出现错误。

Description

一种Mura现象补偿方法及其装置
本申请要求于2017年11月23日提交中国专利局、申请号为2017112026400、申请名称为“一种Mura现象补偿方法及其装置”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请涉及显示技术领域，特别涉及一种Mura现象补偿方法及其装置。
背景技术
显示面板的驱动线路中，时序控制芯片(Timer Control Integrated Circuit，TCON IC)对数据的处理能力存在一定的局限性，例如最大支持3840*2160分辨率、120Hz刷新率的时序控制芯片，若要驱动7680*4320分辨率、60Hz刷新率的显示面板，则需要两颗时序控制芯片并联使用，单颗时序控制芯片负责左、右，或者上、下各一半的显示区域。当有多颗时序控制芯片并联使用来驱动显示面板时，显示面板的亮暗差异补偿技术使用上会遇到一些问题，相机拍摄整个显示面板的显示区域并计算出对应的灰阶补偿数据矩阵，将此灰阶补偿数据矩阵同时传输给并联工作的多颗时序控制芯片时，由于单颗时序控制芯片只负责显示面板的某一显示区域数据，时序控制芯片之间无法区分自身负责区域所对应的有效补偿数据矩阵，会导致各个时序控制芯片的补偿效果出现错误。
申请内容
本申请的主要目的是提供一种Mura现象补偿方法及其装置，旨在当使多颗时序控制芯片并联工作时，显示面板的亮暗补偿功能，还可以达到正确的补偿效果。
为实现上述目的，本申请提出的一种Mura现象补偿方法，用于多颗时序控制芯片并联处理显示面板，其包括以下步骤：步骤一：拍摄整个显示面板的显示区域；步骤二：计算整个显示面板的显示区域的补偿数据矩阵a；步骤三： 多颗所述时序控制芯片的数量设为N，将所述显示面板分成N个小部分，每一所述时序控制芯片控制每一所述小部分；步骤四：设定显示面板的分辨率为B1*B2，将补偿数据矩阵a等间隔设定参考点为A1*A2，补偿数据矩阵a等于(B1/A1+1)*(B2/A2+1)，当N个所述小部分对应的参考点为整数时，将补偿数据矩阵a拆分成N个小矩阵C，每一所述小矩阵C等于(B1/A1+1)*((B2/A2)/N+1)；当N个所述小部分对应的参考点不为整数时，将补偿数据矩阵a拆分成N个小矩阵C，每一所述小矩阵C等于(B1/A1+1)*((B2/A2+1)/N+1)；步骤五：将每一所述小矩阵分别输入到对应的每一所述时序控制芯片中；步骤六：每一所述时序控制芯片工作时只读取自身对应的所述小矩阵的补偿数据。
可选的，每一所述时序控制芯片对应连接一flash存储器，每一所述小矩阵C分别输入到每一所述flash存储器中。
可选的，N颗所述时序控制芯片共同连接一flash存储器，将所述flash存储器分成N个存储区，每一所述小矩阵C分别输入到每一所述存储区内。
可选的，设定N等于2，设定显示面板的分辨率为7680*4320，间隔设定的参考点为16*16，则补偿数据矩阵a为481*271，此时两个所述小部分对应的参考点为整数，每一所述小矩阵C均为481*136。
可选的，在将补偿数据矩阵a为481*271拆成两个上下的小矩阵时，复制一份所述补偿数据矩阵a的第136行的补偿数据。
可选的，设定N等于2，设定显示面板的分辨率为7680*4320，间隔设定的参考点为32*32，补偿数据矩阵a为241*136，此时两个所述小部分的显示区域对应的参考点不为整数，每一所述小矩阵C均为241*69。
可选的，在将补偿数据矩阵a为241*136拆成上下两个小矩阵时，复制一份所述补偿数据矩阵a的第68行和第69行补偿数据。
本申请还提供了一种Mura现象补偿装置，其中，包括：显示面板，所述显示面板分成多个显示区域；多颗时序控制芯片，每一所述时序控制芯片分别与每一所述显示区域对应连接；Mura现象补偿处理芯片，用于与所述时序控制芯片连接，Mura现象补偿处理芯片用于计算整个显示面板的显示区域的补偿数据矩阵a，且将补偿数据矩阵a拆分成多个小矩阵，每一小矩阵的数据对 应补偿每一所述显示区域。
可选的，每一所述时序控制芯片对应连接一flash存储器，每一所述小矩阵的数据分别输入到每一所述flash存储器中。
可选的，多颗所述时序控制芯片共同连接一flash存储器，将所述flash存储器分成N个存储区，每一所述小矩阵的数据分别输入到每一所述存储区内。
本申请所提供的一种Mura现象补偿方法及其装置，通过将显示面板所有区域的补偿数据拆分成各时序控制芯片对应负责的区域部分，分别存储在flash存储区中的不同位置，各时序控制芯片工作时只读取自身对应的部分补偿数据，避免了多个时序控制芯片之间无法区分自身负责区域所对应的有效补偿数据矩阵，从而导致各个时序控制芯片的补偿效果出现错误。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请Mura现象补偿装置的结构示意图；
图2为本申请Mura现象补偿方法第一实施例的流程框图；
图3为本申请Mura现象补偿方法第二实施例的流程示意图；
图4为本申请Mura现象补偿方法第三实施例的流程示意图；
图5为本申请Mura现象补偿方法第三实施例的另一流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
随着显示面板，例如液晶显示面板(Liquid Crystal Display Panel，LCD面板)、有机发光二极管显示面板(Organic Light Emitting Diode Display Panel, OLED面板)，向着轻薄大屏的方向发展，因实际制程上的不可控因素，使显示面板各处的物理特性存在差异，导致在大于一个像素点的范围内，显示纯灰度图像时亮度不均匀的现象，即业界所称的Mura现象。
请参看图1及图2所示，本申请的第一实施例所提供的Mura现象补偿方法，用于多颗时序控制芯片(Timer Control Integrated Circuit，TCON IC)并联处理的显示面板，本实施方式的显示面板为LCD面板。所述Mura现象补偿方法包括以下步骤：
步骤一：拍摄整个显示面板的显示区域，具体为在显示面板的中心点的正上方用一相机对显示一定灰度画面的显示面板拍照，通过采集到的图像得到所述显示面板的亮度数据。
步骤二：根据采集到的亮度数据，计算整个显示面板的显示区域的补偿数据矩阵a。具体的包括Mura现象补偿处理芯片，用于与所述时序控制芯片连接，Mura现象补偿处理芯片用于计算整个显示面板的显示区域的补偿数据矩阵a。
步骤三：多颗所述时序控制芯片的数量设为N，将所述显示面板分成N个小部分，每一所述时序控制芯片控制每一所述小部分。具体的将显示面板的所有区域的补偿数据拆分成每一所述时序控制芯片对应负责的区域部分。
步骤四：设定显示面板的分辨率为B1*B2，将补偿数据矩阵a等间隔设定参考点为A1*A2，多颗所述时序控制芯片并联驱动显示面板时，一定会存在相邻的边界区域，所以得到补偿数据矩阵a等于(B1/A1+1)*(B2/A2+1)；当N个所述小部分对应的参考点为整数时，将补偿数据矩阵a拆分成N个小矩阵C，每一所述小矩阵C等于(B1/A1+1)*((B2/A2)/N+1)；当N个所述小部分对应的参考点不为整数时，将补偿数据矩阵a拆分成N个小矩阵C，每一所述小矩阵C等于(B1/A1+1)*((B2/A2+1)/N+1)。
步骤五：将每一所述小矩阵分别输入到对应的每一所述时序控制芯片中。在本实施例中，每一所述时序控制芯片对应连接一flash存储器(又称闪存)，每一所述小矩阵C分别输入到每一所述flash存储器中。在其它实施例中，N颗所述时序控制芯片共同连接一flash存储器，将所述flash存储器分成N个存储区，每一所述小矩阵C分别输入到每一所述存储区内。
步骤六：每一所述时序控制芯片工作时只读取自身对应的所述小矩阵的补 偿数据，从而使得各所述时序控制芯片工作时只读取自身对应的部分补偿数据，以此使得多颗时序控制芯片并联工作时的，所述显示面板得亮暗补偿功能达到正确的补偿效果，避免了多颗所述时序控制芯片之间无法区分自身负责区域所对应的有效补偿数据矩阵，会导致各个时序控制芯片的补偿效果出现错误。
请参看图3，本申请的Mura现象补偿方法的第二实施例，将多颗所述时序控制芯片的N设定等于2，也就有时序控制芯片1(简称TCON1)和时序控制芯片2(简称TCON2)。设定显示面板的分辨率为7680*4320，间隔设定的参考点为16*16，则补偿数据矩阵a为481*271，此时两个所述小部分对应的参考点为整数，每一所述小矩阵C均为481*136。在将补偿数据矩阵a为481*271拆成两个上下的小矩阵C时，复制一份所述补偿数据矩阵a的第136行的补偿数据。
具体的，本实施例出现上、下部分显示区域对应的补偿数据参考点为整数，下半部分第一行像素正好是补偿数据参考点位置，但是上半部分最后几行像素的补偿数据需要使用到下半部分第一行的补偿参考点的补偿数据，此时需要将整个显示面板补偿参考点的补偿数据矩阵a分成上、下两部分a1和a2，分别存储在不同的flash存储器中，对应连接两颗时序控制芯片，两颗时序控制芯片，即TCON1和TCON2，在读取补偿数据时，分别读取不同的flash存储器。7680*4320分辨率、补偿参考点间隔设定16*16，补偿数据矩阵a为481*271个数据，补偿数据矩阵a的第136行补偿数据的位置刚好落在下半部分显示区域的第1行像素上，而上半部分显示区域最后几行像素的补偿数据，需要由补偿数据矩阵a中的第135行和第136行补偿数据进行线性插值计算得到，所以在拆分补偿数据矩阵a时需要将第136行的补偿数据复制一份，即补偿数据矩阵a中的第136行补偿数据作为小矩阵a1(上半部分)的第136行补偿数据，同时也作为小矩阵a2(下半部分)的第1行补偿数据，这样小矩阵a1和小矩阵a2均为481*136的数据矩阵。
请参看图4及图5，本申请的Mura现象补偿方法的第三实施例，将多颗所述时序控制芯片的N设定等于2，也就有时序控制芯片1(简称TCON1)和时序控制芯片2(简称TCON2)。设定显示面板的分辨率为7680*4320，间隔设定的参考点为32*32，补偿数据矩阵a为241*136，此时两个所述小部分的显示区域对应的参考点不为整数，每一所述小矩阵C均为241*69。在将补偿数据矩阵a 为241*136拆成上下两个小矩阵时，复制一份所述补偿数据矩阵a的第68行和第69行补偿数据。
具体的，本实施例出现上、下部分显示区域对应的补偿数据参考点不为整数，7680*4320分辨率、补偿参考点间隔设定32*32，补偿数据矩阵b为241*136个数据，上、下部分显示区域的分界线刚好处于补偿数据矩阵b的第68行和第69行补偿数据所在等间隔设定区域的中间位置，则需要将第69行补偿数据放在上半显示区域的小矩阵b1中，对于负责上半部分显示区域的时序控制芯片，当显示上半显示区域最后16行像素时，仍使用所述补偿数据矩阵b的第68行和第69行补偿数据进行32*32等间隔线性插值计算(此等间隔内的第17～32行像素数据不需要计算出来)。针对下半部分显示区域，则需要将所述补偿数据矩阵b的第68行补偿数据放在下半显示区域的小矩阵b2中，而下半部分显示区域第1行像素位置为第68行和第69行补偿数据对应的等间隔内的第17行像素，当此时序控制芯片接收到原始像素的灰阶数据后并计算相应像素位置的补偿数据时，需要将所有原始像素的行位置增加16，即显示区域的第1行像素变为小矩阵b2中的第17行像素位置，这样线性插值计算出来的补偿数据才能和原始像素的位置正确对应。
本申请包括一种Mura现象补偿装置，包括显示面板，所述显示面板分成多个显示区域。多颗时序控制芯片，每一所述时序控制芯片分别与每一所述显示区域对应连接。Mura现象补偿处理芯片，用于与所述时序控制芯片连接，Mura现象补偿处理芯片用于计算整个显示面板的显示区域的补偿数据矩阵a，且将补偿数据矩阵a拆分成多个小矩阵，每一小矩阵的数据对应补偿每一所述显示区域。
在其中一个实施例中，每一所述时序控制芯片对应连接一flash存储器，每一所述小矩阵的数据分别输入到每一所述flash存储器中。
在其中另一个实施例中，多颗所述时序控制芯片共同连接一flash存储器，将所述flash存储器分成N个存储区，每一所述小矩阵的数据分别输入到每一所述存储区内。
本申请，通过每一所述时序控制芯片工作时只读取自身对应的所述小矩阵的补偿数据，从而使得各所述时序控制芯片工作时只读取自身对应的部分补偿 数据，以此使得同一显示面板使用多颗时序控制芯片驱动时，Mura补偿功能仍能正常工作，避免了多颗所述时序控制芯片之间无法区分自身负责区域所对应的有效补偿数据矩阵，会导致各个时序控制芯片的补偿效果出现错误。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本申请的保护之内。

Claims (10)

  1. 一种Mura现象补偿方法，用于多颗时序控制芯片并联处理显示面板，其中，包括以下步骤：
    步骤一：拍摄整个显示面板的显示区域；
    步骤二：计算整个显示面板的显示区域的补偿数据矩阵a；
    步骤三：多颗所述时序控制芯片的数量设为N，将所述显示面板分成N个小部分，每一所述时序控制芯片控制每一所述小部分；
    步骤四：设定显示面板的分辨率为B1*B2，将补偿数据矩阵a等间隔设定参考点为A1*A2，补偿数据矩阵a等于(B1/A1+1)*(B2/A2+1)，当N个所述小部分对应的参考点为整数时，将补偿数据矩阵a拆分成N个小矩阵C，每一所述小矩阵C等于(B1/A1+1)*((B2/A2)/N+1)；当N个所述小部分对应的参考点不为整数时，将补偿数据矩阵a拆分成N个小矩阵C，每一所述小矩阵C等于(B1/A1+1)*((B2/A2+1)/N+1)；
    步骤五：将每一所述小矩阵分别输入到对应的每一所述时序控制芯片中；
    步骤六：每一所述时序控制芯片工作时只读取自身对应的所述小矩阵的补偿数据。
  2. 如权利要求1所述的Mura现象补偿方法，其中，每一所述时序控制芯片对应连接一flash存储器，每一所述小矩阵C分别输入到每一所述flash存储器中。
  3. 如权利要求1所述的Mura现象补偿方法，其中，N颗所述时序控制芯片共同连接一flash存储器，将所述flash存储器分成N个存储区，每一所述小矩阵C分别输入到每一所述存储区内。
  4. 如权利要求1所述的Mura现象补偿方法，其中，设定N等于2，设定显示面板的分辨率为7680*4320，间隔设定的参考点为16*16，则补偿数据矩阵a为481*271，此时两个所述小部分对应的参考点为整数，每一所述小矩阵C均为481*136。
  5. 如权利要求4所述的Mura现象补偿方法，其中，在将补偿数据矩阵a为481*271拆成两个上下的小矩阵时，复制一份所述补偿数据矩阵a的第136 行的补偿数据。
  6. 如权利要求1所述的Mura现象补偿方法，其中，设定N等于2，设定显示面板的分辨率为7680*4320，间隔设定的参考点为32*32，补偿数据矩阵a为241*136，此时两个所述小部分的显示区域对应的参考点不为整数，每一所述小矩阵C均为241*69。
  7. 如权利要求6所述的Mura现象补偿方法，其中，在将补偿数据矩阵a为241*136拆成上下两个小矩阵时，复制一份所述补偿数据矩阵a的第68行和第69行补偿数据。
  8. 一种Mura现象补偿装置，其中，包括：
    显示面板，所述显示面板分成多个显示区域；
    多颗时序控制芯片，每一所述时序控制芯片分别与每一所述显示区域对应连接；
    Mura现象补偿处理芯片，用于与所述时序控制芯片连接，Mura现象补偿处理芯片用于计算整个显示面板的显示区域的补偿数据矩阵a，且将补偿数据矩阵a拆分成多个小矩阵，每一小矩阵的数据对应补偿每一所述显示区域。
  9. 如权利要求8所述的Mura现象补偿装置，其中，每一所述时序控制芯片对应连接一flash存储器，每一所述小矩阵的数据分别输入到每一所述flash存储器中。
  10. 如权利要求8所述的Mura现象补偿装置，其中，多颗所述时序控制芯片共同连接一flash存储器，将所述flash存储器分成N个存储区，每一所述小矩阵的数据分别输入到每一所述存储区内。
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