WO2019095458A1 - 阵列基板、显示面板、显示设备及阵列基板的制作方法 - Google Patents

阵列基板、显示面板、显示设备及阵列基板的制作方法 Download PDF

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Publication number
WO2019095458A1
WO2019095458A1 PCT/CN2017/114701 CN2017114701W WO2019095458A1 WO 2019095458 A1 WO2019095458 A1 WO 2019095458A1 CN 2017114701 W CN2017114701 W CN 2017114701W WO 2019095458 A1 WO2019095458 A1 WO 2019095458A1
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Prior art keywords
substrate
data line
auxiliary electrode
electrode
insulating layer
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PCT/CN2017/114701
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English (en)
French (fr)
Inventor
邓竹明
柳铭岗
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/742,515 priority Critical patent/US10268094B1/en
Publication of WO2019095458A1 publication Critical patent/WO2019095458A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a display panel, a display device, and a method for fabricating an array substrate.
  • a liquid crystal display panel of a PSVA (Polymer Stabilized Vertivally Aligned) mode utilizes a vertical electric field in a vertical direction to drive liquid crystal molecules vertically disposed on a glass substrate to form a polymer-stabilized and vertically aligned liquid crystal. Display panel.
  • the liquid crystal display panel of this mode is in a black display state when no voltage is applied; after a certain voltage is applied, the liquid crystal molecules of the liquid crystal display panel are turned to the horizontal direction, and the liquid crystal display panel of the mode is in a white display state.
  • the existing curved liquid crystal display panel of the PSVA mode forms a light-shielding electrode on the data line, and the light-shielding electrode effectively reduces the side light leakage phenomenon of the curved liquid crystal display panel.
  • the light-shielding electrode completely covers the data line, the light-shielding electrode is easily affected by the high-low potential signal on the data line, so that a voltage difference is generated between the light-shielding electrode and the common electrode on the color filter substrate, thereby causing the liquid crystal display panel.
  • the side is leaking light.
  • a lateral electrode is disposed between two adjacent shading electrodes, and the lateral electrodes electrically connect adjacent two shading electrodes, thereby reducing a voltage difference between the shading electrodes, and maintaining the voltage of the shading electrodes to be stable, further
  • the lateral electrodes are located between adjacent pixel electrodes.
  • the lateral electrodes are bent toward one pixel electrode, thereby being between the pixel electrodes and the thin film transistors. The metal gap passes through.
  • ITO indium tin oxide
  • the ITO residue is easily formed between the pixel electrode and the lateral electrode, resulting in a short circuit between the pixel electrode and the lateral electrode, which affects the normal operation of the pixel electrode.
  • the technical problem to be solved by the present invention is to provide an array substrate, a liquid crystal display panel, a liquid crystal display device, and an array substrate manufacturing method, which are used to solve the problem that the shading electrode in the prior art is easily affected by high and low potential signals on the data line. A problem that affects the normal operation of the shading electrode.
  • an array substrate including:
  • An auxiliary electrode is disposed on the first substrate, the auxiliary electrode is configured to be electrically connected to the color filter substrate, and a vertical projection of the auxiliary electrode on the first substrate does not intersect the data line;
  • An insulating layer disposed on a surface of the auxiliary electrode facing away from the side of the first substrate, wherein the insulating layer is provided with an opening;
  • a light-shielding electrode comprising a body segment and a protruding segment interconnected, the body segment being located on a side of the data line facing away from the first substrate, and the vertical projection of the body segment on the first substrate
  • the data line, the protruding segment is located on the insulating layer, and the protruding segment contacts the auxiliary electrode through the opening.
  • the vertical projection of the protruding segment on the first substrate covers the opening.
  • the array substrate further includes a pixel electrode disposed on the first substrate, and a vertical projection of the auxiliary electrode on the first substrate is at least partially located at the data line and the pixel electrode The auxiliary electrode is used to reduce the influence of the data line on the pixel electrode.
  • the insulating layer includes a gate insulating layer and a passivation layer, wherein the gate insulating layer and the passivation layer are sequentially in a vertical projection range of the first substrate Stacked on the auxiliary electrode, the first substrate is further provided with a thin film transistor, the gate insulating layer is located between the gate and the source and the drain of the thin film transistor, and the passivation layer is located The source or the drain of the thin film transistor is between the pixel electrode.
  • the present invention also provides a display panel comprising a color filter substrate, a liquid crystal layer and an array substrate, the array substrate comprising: a first substrate and a data line, the data line is disposed on the first substrate; the auxiliary electrode is disposed The auxiliary electrode is configured to be electrically connected to the color filter substrate, the vertical projection of the auxiliary electrode on the first substrate does not intersect the data line, and the insulating layer is disposed on the auxiliary substrate a surface of the auxiliary electrode facing away from the side of the first substrate, the insulating layer is provided with an opening; the light shielding electrode comprises a body segment and a protruding segment which are integrally connected, wherein the body segment is located away from the data line a side of the first substrate, and a vertical projection of the body segment on the first substrate covers the data line, the protruding segment is on the insulating layer, and the protruding segment contacts through the opening The auxiliary electrode.
  • the color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located
  • the vertical projection of the protruding segment on the first substrate covers the opening.
  • the array substrate further includes a pixel electrode disposed on the first substrate, and a vertical projection of the auxiliary electrode on the first substrate is at least partially located at the data line and the pixel electrode The auxiliary electrode is used to reduce the influence of the data line on the pixel electrode.
  • the insulating layer includes a gate insulating layer and a passivation layer, wherein the gate insulating layer and the passivation layer are sequentially in a vertical projection range of the first substrate Stacked on the auxiliary electrode, the first substrate is further provided with a thin film transistor, the gate insulating layer is located between the gate and the source and the drain of the thin film transistor, and the passivation layer is located The source or the drain of the thin film transistor is between the pixel electrode.
  • the present invention further provides a display device including a backlight module and the display panel, the backlight module being disposed on a non-display surface side of the liquid crystal display panel to provide a backlight to display the liquid crystal display panel image.
  • the invention also provides a method for fabricating an array substrate, comprising:
  • a conductive layer on the first substrate Forming a conductive layer on the first substrate, patterning the conductive layer to form a light-shielding electrode, the light-shielding electrode comprising a body segment and a protruding segment interconnected, wherein the body segment is located away from the data line a side of a substrate, and a vertical projection of the body segment over the first substrate covers the data line, the protruding segment is on the insulating layer, and the protruding segment passes through the opening contact Shusuke Helper electrode.
  • the patterning before the forming the data line, patterning the first metal layer to form a gate, and forming a gate insulating layer on the gate to form the data line, the patterning The second metal layer forms a source and a drain, the data line is electrically connected to the source or the drain, and after forming the data line, forming a passivation layer on the source and the drain.
  • the gate insulating layer and the passivation layer are sequentially stacked on the auxiliary electrode to form the insulating layer.
  • the conductive layer is patterned to form a pixel electrode, and a vertical projection of the auxiliary electrode on the first substrate is at least partially located in the Between the data line and the pixel electrode, the auxiliary electrode is used to reduce the influence of the data line on the pixel electrode.
  • the vertical projection of the protruding segment on the first substrate covers the opening.
  • the main body segment of the light-shielding electrode covers the data line to avoid light leakage on the side of the liquid crystal display panel caused by the bending of the black matrix, and the protruding portion is contacted through the opening on the insulating layer and electrically connected to the auxiliary electrode, thereby passing the auxiliary electrode Electrically connected to the common electrode on the color filter substrate, since each of the light-shielding electrodes on the array substrate is electrically connected to the common electrode, the potentials of the respective light-shielding electrodes are uniform, and the high-low potential signal on the data line is reduced to the main body segment of the light-shielding electrode The effect of the shading electrode is normal, the product yield is high, and the production cost is saved.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the array substrate taken along line A-A of the embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a B-B of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of step S101 of the method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of step S102 of the method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of step S103 of the method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of step S104 of the method for fabricating an array substrate according to an embodiment of the present invention.
  • the array substrate 100 includes a first substrate 12 , a thin film transistor 20 , and a data line 64 . Scan line 62 and pixel electrode 50.
  • the array substrate 100 is applied to the liquid crystal display panel 200 of the PSVA mode.
  • the thin film transistor 20, the data line 64, the scan line 62, and the pixel electrode 50 are all formed on the first substrate 12.
  • the gate of the thin film transistor 20 is electrically connected to the scan line 62, and the source and drain of the thin film transistor 20.
  • One of the data line 64 and the pixel electrode 50 is electrically connected, respectively.
  • the data line 64 and the scan line 62 are staggered, and the thin film transistor 20 and the pixel electrode 50 are located in a pixel area enclosed between the scan line 62 and the data line 64. It should be noted that the data line 64 in FIG. Blocked by the light-shielding electrode 30.
  • the first substrate 12 is a flat substrate of a transparent material such as a glass substrate or a plastic substrate.
  • the array substrate 100 further includes an auxiliary electrode 60 and a pixel electrode 50 disposed on the first substrate 12.
  • the vertical projection of the auxiliary electrode 60 on the first substrate 12 is at least partially located between the data line 64 and the pixel electrode 50.
  • the auxiliary electrode 60 serves to reduce the influence of the data line 64 on the pixel electrode 50.
  • the array substrate 100 further includes a transition conductive layer connected between the pixel electrode 50 and the source or the drain of the thin film transistor 20, and the auxiliary electrode 60 is at least partially opposed to the source or the drain to form a memory. capacitance.
  • the surface of the auxiliary electrode 60 is further provided with an insulating layer 90 covering the auxiliary electrode 60 to separate the auxiliary electrode 60 from other structures such as spacers to prevent the auxiliary electrode 60 from being short-circuited to the outside.
  • the auxiliary electrode 60 is used for electrically connecting to the color filter substrate 140, and the vertical projection of the auxiliary electrode 60 at the first substrate 12 does not intersect with the data line 64.
  • the auxiliary electrode 60 is also electrically connected to the driving circuit, and the driving circuit sends a signal for controlling the voltage of the common electrode 16, And passed to the common electrode 16.
  • the array substrate 100 further includes an insulating layer 90 disposed on a surface of the auxiliary electrode 60 facing away from the first substrate 12, and the insulating layer 90 is provided with an opening 40 to expose the auxiliary electrode 60.
  • the insulating layer 90 is disposed on the surface of the auxiliary electrode 60 and covers the auxiliary electrode 60 to separate the auxiliary electrode 60 from the outside to prevent the auxiliary electrode 60 from being short-circuited to cause a defect.
  • the opening 40 is formed on the insulating layer 90 to expose the auxiliary electrode 60 covered by the insulating layer 90.
  • the array substrate 100 further includes a light-shielding electrode 30.
  • the light-shielding electrode 30 includes a body segment 34 and a protruding portion 32 which are integrally connected.
  • the body segment 34 is located away from the first substrate 12 of the data line 64.
  • One side, and the vertical projection of the body segment 34 on the first substrate 12 covers the data line 64.
  • the data line 64 is insulated from the body segment 34.
  • the body segment 34 is insulated by the insulating layer 90. .
  • the main body segments 34 are strip-shaped, and the main body segment 34 of each of the shading electrodes 30 covers a data line 64 to reduce the light leakage phenomenon on the side surface of the curved liquid crystal display panel 200.
  • the protruding section 32 is located on the insulating layer 90, and the protruding section 32 contacts the auxiliary electrode 60 through the opening 40.
  • the protruding section 32 extends from one side of the main body section 34 along the vertical section. The direction of 34 extends. Further, the protruding section 32 extends along the inner wall of the opening 40 toward the inside of the opening 40, and the protruding section 32 contacts the auxiliary electrode 60 exposed by the opening 40 when passing through the bottom of the opening 40.
  • the protruding segment 32 continues to extend along the inner wall of the opening 40 after contacting the auxiliary electrode 60 and extends out of the opening 40 to increase the contact area of the protruding segment 32 with the auxiliary electrode 60.
  • the vertical projection of the protruding section 32 on the first substrate 12 covers the opening 40.
  • the auxiliary electrode 60 exposed by the opening 40 is all in contact with the protruding section 32, thereby increasing the protruding section 32 and the auxiliary electrode 60. Contact area.
  • the main body segment 34 of the light-shielding electrode 30 covers the data line 64 to prevent light leakage from the side of the liquid crystal display panel 200 caused by the bending of the black matrix, and the protruding portion 32 contacts and is electrically connected to the auxiliary electrode 60 through the opening 40 in the insulating layer 90, thereby assisting
  • the electrode 60 is electrically connected to the common electrode 16 on the color filter substrate 140. Since each of the light-shielding electrodes 30 on the array substrate 100 is electrically connected to the common electrode 16, the potential of each of the light-shielding electrodes 30 is uniform, which is reduced on the data line 64. The influence of the high and low potential signals on the main body section 34 of the shading electrode 30, the normal operation of the shading electrode 30, the high product yield, and the production cost are saved.
  • the array substrate 100 further includes a thin film transistor 20 laminated on the surface of the first substrate 12 .
  • the thin film transistor 20 includes a gate electrode, a gate insulating layer 902, an active layer, and a layer, which are sequentially stacked, Source and drain, passivation layer 904.
  • a gate insulating layer 902 is disposed between the gate and the active layer for isolating the gate from the active layer to avoid interaction between the gate and the active layer, and the passivation layer 904 covers the source and the drain.
  • the pole is used to protect the source and drain and the entire thin film transistor 20.
  • the pixel electrode 50 is formed on the passivation layer 904, and at a position corresponding to the source or the drain of the passivation layer 904, the passivation layer 904 is provided with an opening to expose a part of the source or the drain.
  • the pixel electrode 50 contacts the source or the drain through the opening, thereby achieving electrical connection of the thin film transistor 20 and the pixel electrode 50.
  • the gate insulating layer 902 and the passivation layer 904 are sequentially stacked on the auxiliary electrode 60. Specifically, the auxiliary electrode 60 and the gate electrode are deposited on the auxiliary electrode 60.
  • the first metal layer on the first substrate 12 is simultaneously formed after being patterned, and the source and the drain are formed by patterning the second metal layer deposited on the first substrate 12, and within the coverage of the protruding segment 32.
  • the second metal layer is etched and removed, so that within the coverage of the protruding segment 32, the passivation layer 904 is located on the surface of the gate insulating layer 902 and is stacked with the gate insulating layer 902 to form an insulating layer 90.
  • the passivation layer 904 and the gate insulating layer 902 are formed of the same insulating material, or may be formed of different insulating materials. Further, the opening 40 penetrates the passivation layer 904 and the gate insulating layer 902 at the same time, thereby exposing the auxiliary electrode 60.
  • the main body segment 34 of the light-shielding electrode 30 covers the data line 64 to prevent light leakage from the side of the liquid crystal display panel 200 caused by the bending of the black matrix, and the protruding portion 32 contacts and is electrically connected to the auxiliary electrode 60 through the opening 40 in the insulating layer 90, thereby assisting
  • the electrode 60 is electrically connected to the common electrode 16 on the color filter substrate 140. Since each of the light-shielding electrodes 30 on the array substrate 100 is electrically connected to the common electrode 16, the potential of each of the light-shielding electrodes 30 is uniform, which is reduced on the data line 64. The influence of the high and low potential signals on the main body section 34 of the shading electrode 30, the normal operation of the shading electrode 30, the high product yield, and the production cost are saved.
  • an embodiment of the present invention further provides a display panel 200 including a color filter substrate 140, a liquid crystal layer 80, and an array substrate 100 according to an embodiment of the present invention.
  • the color filter substrate 140 is disposed opposite to the array substrate 100, and the liquid crystal layer is disposed.
  • the 80 is located between the array substrate 100 and the color filter substrate 140, and changes the liquid crystal molecular deflection of the liquid crystal layer 80 according to the pressure difference between the array substrate 100 and the color filter substrate 140.
  • the display panel 200 may be a curved display panel 200.
  • the color filter substrate 140 includes a second substrate 14 and a common electrode 16, the second substrate 14 is disposed opposite to the first substrate 12, and the common electrode 16 is located on a side of the second substrate 14 facing the array substrate 100, and the liquid crystal The layer 80 is located between the pixel electrode 50 and the common electrode 16, and is changed according to the voltage difference between the pixel electrode 50 and the common electrode 16.
  • the liquid crystal molecules of the liquid crystal layer 80 are deflected.
  • the common electrode 16 is a conductive layer formed on the surface of the first substrate 12 by etching or the like. In fact, a plurality of contact points are provided in the sealant connecting the color filter substrate 140 and the array substrate 100 for electrically connecting the shading electrode 30, the auxiliary electrode 60 on the array substrate 100 and the common electrode 16 on the color filter substrate 140. connection.
  • an embodiment of the present invention further provides a display device 300 including a backlight module 82 and a liquid crystal display panel 200 according to an embodiment of the present invention.
  • the backlight module 82 is disposed on a non-display side of the liquid crystal display panel 200 .
  • the liquid crystal display device 300 can be a curved display device 300.
  • the liquid crystal display device 300 is a television, a display, a mobile phone, a tablet computer, a notebook computer, or the like.
  • the main body segment 34 of the light-shielding electrode 30 covers the data line 64 to prevent light leakage from the side of the liquid crystal display panel 200 caused by the bending of the black matrix, and the protruding portion 32 contacts and is electrically connected to the auxiliary electrode 60 through the opening 40 in the insulating layer 90, thereby assisting
  • the electrode 60 is electrically connected to the common electrode 16 on the color filter substrate 140. Since each of the light-shielding electrodes 30 on the array substrate 100 is electrically connected to the common electrode 16, the potential of each of the light-shielding electrodes 30 is uniform, which is reduced on the data line 64. The influence of the high and low potential signals on the main body section 34 of the shading electrode 30, the normal operation of the shading electrode 30, the high product yield, and the production cost are saved.
  • an embodiment of the present invention further provides a method for fabricating an array substrate 100. Specifically, the method includes the following steps.
  • the manner of forming the first metal layer may be vapor deposition, and the manner of patterning the first metal layer may be etching or the like.
  • the patterned first metal layer forms the auxiliary electrode 60
  • a gate is also formed, and the gate does not intersect the auxiliary electrode 60.
  • the manner of forming the second metal layer may be vapor deposition, and the manner of patterning the second metal layer may be etching or the like.
  • the patterned second metal layer forms the data line 64, a source and a drain are also formed, and the source or drain is electrically coupled to the data line 64.
  • an insulating layer 90 is formed on a surface of the auxiliary electrode 60 facing away from the first substrate 12, and an opening 40 is provided in the insulating layer 90 to expose the auxiliary electrode 60.
  • the insulating layer 90 includes a gate insulating layer 902 and a passivation layer 904 .
  • the patterned first metal layer forms a gate
  • the gate insulating layer 902 is formed on the gate.
  • the patterned second metal layer forms a source and a drain.
  • the data line 64 is electrically connected to the source or the drain.
  • the passivation layer 904 is formed on the source and the drain, and the gate insulating layer 902 and the passivation layer 904 are sequentially stacked on the auxiliary electrode 60.
  • An insulating layer 90 is formed.
  • the thin film transistor 20 includes a gate electrode, a gate insulating layer 902, an active layer, a source and a drain, and a passivation layer 904 which are sequentially stacked.
  • a gate insulating layer 902 is disposed between the gate and the active layer for isolating the gate from the active layer to avoid interaction between the gate and the active layer, and the passivation layer 904 covers the source and the drain.
  • the pole is used to protect the source and drain and the entire thin film transistor 20.
  • the pixel electrode 50 is formed on the passivation layer 904, and at a position corresponding to the source or the drain of the passivation layer 904, the passivation layer 904 is provided with an opening to expose a part of the source or the drain.
  • the pixel electrode 50 contacts the source or the drain through the opening, thereby achieving electrical connection of the thin film transistor 20 and the pixel electrode 50.
  • the gate insulating layer 902 and the passivation layer 904 are sequentially stacked on the auxiliary electrode 60. Specifically, the auxiliary electrode 60 and the gate electrode are deposited on the auxiliary electrode 60.
  • the first metal layer on the first substrate 12 is simultaneously formed after being patterned, and the source and the drain are formed by patterning the second metal layer deposited on the first substrate 12, and within the coverage of the protruding segment 32.
  • the second metal layer is etched and removed, so that within the coverage of the protruding segment 32, the passivation layer 904 is located on the surface of the gate insulating layer 902 and is stacked with the gate insulating layer 902 to form an insulating layer 90.
  • the passivation layer 904 and the gate insulating layer 902 are formed of the same insulating material, or may be formed of different insulating materials. Further, the opening 40 penetrates the passivation layer 904 and the gate insulating layer 902 at the same time, thereby exposing the auxiliary electrode 60.
  • the light-shielding electrode 30 includes a body segment 34 and a protruding portion 32 which are integrally connected, and the body segment 34 is located away from the first substrate 12 of the data line 64.
  • One side, and the vertical projection of the body segment 34 on the first substrate 12 covers the data line 64, the protruding segment 32 is on the insulating layer 90, and the protruding segment 32 contacts the auxiliary electrode 60 through the opening 40.
  • the light-shielding electrode 30 includes a body segment 34 and a protruding segment 32 which are integrally connected, and the body segment 34 is located on a side of the data line 64 facing away from the first substrate 12, and the body segment 34
  • the vertical projection of the first substrate 12 covers the data lines 64.
  • the data lines 64 are insulated from the body segments 34.
  • the body segments 34 are isolated by an insulating layer 90.
  • the main body segments 34 are strip-shaped, and the main body segment 34 of each of the shading electrodes 30 covers a data line 64 to reduce the light leakage phenomenon on the side surface of the curved liquid crystal display panel 200.
  • the protruding section 32 is located on the insulating layer 90, and the protruding section 32 contacts the auxiliary electrode 60 through the opening 40.
  • the protruding section 32 extends from one side of the main body section 34 along the vertical section. The direction of 34 extends. Further, the protruding section 32 extends along the inner wall of the opening 40 toward the inside of the opening 40, and the protruding section 32 contacts the auxiliary electrode 60 exposed by the opening 40 when passing through the bottom of the opening 40.
  • the protruding segment 32 continues to extend along the inner wall of the opening 40 after contacting the auxiliary electrode 60 and extends out of the opening 40 to increase the contact area of the protruding segment 32 with the auxiliary electrode 60.
  • the vertical projection of the protruding section 32 on the first substrate 12 covers the opening 40.
  • the auxiliary electrode 60 exposed by the opening 40 is all in contact with the protruding section 32, thereby increasing the protruding section 32 and the auxiliary electrode 60. Contact area.
  • the main body segment 34 of the light-shielding electrode 30 covers the data line 64 to prevent light leakage from the side of the liquid crystal display panel 200 caused by the bending of the black matrix, and the protruding portion 32 contacts and is electrically connected to the auxiliary electrode 60 through the opening 40 in the insulating layer 90, thereby assisting
  • the electrode 60 is electrically connected to the common electrode 16 on the color filter substrate 140. Since each of the light-shielding electrodes 30 on the array substrate 100 is electrically connected to the common electrode 16, the potential of each of the light-shielding electrodes 30 is uniform, which is reduced on the data line 64. The influence of the high and low potential signals on the main body section 34 of the shading electrode 30, the normal operation of the shading electrode 30, the high product yield, and the production cost are saved.

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Abstract

一种阵列基板（100）、显示面板（200）、显示设备（300）及阵列基板（100）的制作方法，阵列基板（100）包括：第一基板（12）和数据线（64），数据线（64）设置于第一基板（12）上；辅助电极（60），设置于第一基板（12）上，辅助电极（60）用于电连接至彩膜基板（140），辅助电极（60）在第一基板（12）的垂直投影与数据线（64）不相交；绝缘层（90），设置于辅助电极（60）背离第一基板（12）一侧的表面上，绝缘层（90）设有开孔（40）；遮光电极（30），包括互连为一体的主体段（34）与突出段（32），主体段（34）位于数据线（64）背离第一基板（12）的一侧，并且主体段（34）在第一基板（12）的垂直投影覆盖数据线（64），突出段（32）位于绝缘层（90）上，并且突出段（32）穿过开孔（40）接触辅助电极（60）。具有产品良率高，节省生产成本的优点。

Description

阵列基板、显示面板、显示设备及阵列基板的制作方法
本申请要求于2017年11月17日提交中国专利局、申请号为201711143426.2、发明名称为“阵列基板、显示面板、显示设备及阵列基板的制作方法”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其是涉及一种阵列基板、显示面板、显示设备及阵列基板的制作方法。
背景技术
PSVA(Polmer Stabilized Vertivally Aligned，聚合物稳定的垂直排列液晶)模式的液晶显示面板是利用垂直方向的纵向电场，来驱动垂直配置于玻璃基板上的液晶分子，从而形成聚合物稳定并垂直排列的液晶显示面板。该模式的液晶显示面板在不施加电压时为黑色显示状态；在施加一定电压后，液晶显示面板的液晶分子倒向水平方向，该模式的液晶显示面板为白色显示状态。目前，为了避免黑矩阵弯曲造成的液晶显示面板侧面漏光，现有的PSVA模式的曲面液晶显示面板在数据线上形成了一层遮光电极，该遮光电极有效的减少曲面液晶显示面板的侧面漏光现象。但是，由于遮光电极完全覆盖于数据线上，因此遮光电极很容易受到数据线上的高低电位信号的影响，使得遮光电极与彩膜基板上的公共电极之间产生电压差，从而导致液晶显示面板的侧面漏光。
现有技术中，在相邻的两条遮光电极之间设置横向电极，横向电极电连接相邻的两个遮光电极，从而降低各遮光电极之间的电压差，保持遮光电极的电压稳定，进一步的，横向电极位于相邻的像素电极之间，横向电极为了避开同样位于相邻的像素电极之间的薄膜晶体管，横向电极会偏向一个像素电极弯折，从而从像素电极与薄膜晶体管之间的金属缝隙处穿过。实际上，由于横向电极与像素电极距离太近，在物理气相沉积及蚀刻氧化铟锡(Indium tin oxide，ITO) 导电层形成像素电极和横向电极的过程中，像素电极和横向电极之间极易形成ITO残留，导致像素电极和横向电极之间形成短路，影响像素电极正常工作。
发明内容
本发明要解决的技术问题是提供一种阵列基板、液晶显示面板、液晶显示设备及阵列基板的制作方法，用以解决现有技术中遮光电极很容易受到数据线上的高低电位信号的影响，影响遮光电极正常工作的问题。
为解决上述技术问题，本发明提供一种阵列基板，包括：
第一基板和数据线，所述数据线设置于所述第一基板上；
辅助电极，设置于所述第一基板上，所述辅助电极用于电连接至彩膜基板，所述辅助电极在所述第一基板的垂直投影与所述数据线不相交；
绝缘层，设置于所述辅助电极背离所述第一基板一侧的表面上，所述绝缘层设有开孔；
遮光电极，包括互连为一体的主体段与突出段，所述主体段位于所述数据线背离所述第一基板的一侧，并且所述主体段在所述第一基板的垂直投影覆盖所述数据线，所述突出段位于所述绝缘层上，并且所述突出段穿过所述开孔接触所述辅助电极。
一种实施方式中，所述突出段在所述第一基板的垂直投影覆盖所述开孔。
一种实施方式中，所述阵列基板还包括设置于所述第一基板上的像素电极，所述辅助电极在所述第一基板上的垂直投影至少部分位于所述数据线与所述像素电极之间，所述辅助电极用于降低所述数据线对所述像素电极的影响。
一种实施方式中，所述绝缘层包括栅极绝缘层和钝化层，在所述突出段在所述第一基板的垂直投影范围内，所述栅极绝缘层与所述钝化层依次层叠设置于所述辅助电极上，所述第一基板上还设有薄膜晶体管，所述栅极绝缘层位于所述薄膜晶体管的栅极与源极、漏极之间，所述钝化层位于所述薄膜晶体管的源极或漏极与所述像素电极之间。
本发明还提供一种显示面板，包括彩膜基板、液晶层及阵列基板，所述阵列基板包括，第一基板和数据线，所述数据线设置于所述第一基板上；辅助电极，设置于所述第一基板上，所述辅助电极用于电连接至彩膜基板，所述辅助电极在所述第一基板的垂直投影与所述数据线不相交；绝缘层，设置于所述辅 助电极背离所述第一基板一侧的表面上，所述绝缘层设有开孔；遮光电极，包括互连为一体的主体段与突出段，所述主体段位于所述数据线背离所述第一基板的一侧，并且所述主体段在所述第一基板的垂直投影覆盖所述数据线，所述突出段位于所述绝缘层上，并且所述突出段穿过所述开孔接触所述辅助电极。所述彩膜基板与所述阵列基板相对设置，所述液晶层位于阵列基板与彩膜基板之间，并根据阵列基板与彩膜基板之间的压差改变所述液晶层的液晶分子偏转。
一种实施方式中，所述突出段在所述第一基板的垂直投影覆盖所述开孔。
一种实施方式中，所述阵列基板还包括设置于所述第一基板上的像素电极，所述辅助电极在所述第一基板上的垂直投影至少部分位于所述数据线与所述像素电极之间，所述辅助电极用于降低所述数据线对所述像素电极的影响。
一种实施方式中，所述绝缘层包括栅极绝缘层和钝化层，在所述突出段在所述第一基板的垂直投影范围内，所述栅极绝缘层与所述钝化层依次层叠设置于所述辅助电极上，所述第一基板上还设有薄膜晶体管，所述栅极绝缘层位于所述薄膜晶体管的栅极与源极、漏极之间，所述钝化层位于所述薄膜晶体管的源极或漏极与所述像素电极之间。
本发明还提供一种显示设备，包括背光模组及所述的显示面板，所述背光模组设置于所述液晶显示面板的非显示面一侧，以提供背光源使所述液晶显示面板显示图像。
本发明还提供一种阵列基板的制作方法，包括：
提供第一基板，在所述第一基板上形成第一金属层，图案化所述第一金属层形成辅助电极，所述辅助电极用于电连接至彩膜基板；
在所述第一基板上形成第二金属层，图案化所述第二金属层形成数据线，所述数据线在所述第一基板的垂直投影与所述辅助电极不相交；
在所述辅助电极背离所述第一基板一侧的表面上形成绝缘层，并在所述绝缘层设置开孔；
形成导电层于所述第一基板上，图案化所述导电层形成遮光电极，所述遮光电极包括互连为一体的主体段与突出段，所述主体段位于所述数据线背离所述第一基板的一侧，并且所述主体段在所述第一基板的垂直投影覆盖所述数据线，所述突出段位于所述绝缘层上，并且所述突出段穿过所述开孔接触所述辅 助电极。
一种实施方式中，形成所述数据线之前，图案化所述第一金属层形成栅极，并形成栅极绝缘层于所述栅极上，形成所述数据线的过程中，图案化所述第二金属层形成源极和漏极，所述数据线电连接至所述源极或所述漏极，形成所述数据线之后，形成钝化层于所述源极和所述漏极上，所述栅极绝缘层与所述钝化层依次层叠于所述辅助电极上形成所述绝缘层。
一种实施方式中，图案化所述导电层形成所述遮光电极的过程中，图案化所述导电层形成像素电极，所述辅助电极在所述第一基板上的垂直投影至少部分位于所述数据线与所述像素电极之间，所述辅助电极用于降低所述数据线对所述像素电极的影响。
一种实施方式中，所述突出段在所述第一基板的垂直投影覆盖所述开孔。
本发明的有益效果如下：遮光电极的主体段覆盖数据线，避免黑矩阵弯曲造成的液晶显示面板侧面漏光，突出段穿过绝缘层上的开孔接触并电连接至辅助电极，从而通过辅助电极电连接至彩膜基板上的公共电极，由于阵列基板上的每一个遮光电极都电连接至公共电极，各遮光电极的电位一致，减小了数据线上的高低电位信号对遮光电极的主体段的影响，遮光电极的正常工作，产品良率高，节省生产成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的阵列基板的结构示意图。
图2为本发明实施例提供的阵列基板的A-A截面示意图。
图3为本发明实施例提供的阵列基板的B-B截面示意图。
图4为本发明实施例提供的显示面板的示意图。
图5为本发明实施例提供的显示设备的示意图。
图6为本发明实施例提供的阵列基板的制作方法的步骤S101的示意图。
图7为本发明实施例提供的阵列基板的制作方法的步骤S102的示意图。
图8为本发明实施例提供的阵列基板的制作方法的步骤S103的示意图。
图9为本发明实施例提供的阵列基板的制作方法的步骤S104的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请一并参阅图1、图2及图3，请一并参阅图1、图2及图3，本发明实施例一提供的阵列基板100包括第一基板12、薄膜晶体管20、数据线64、扫描线62及像素电极50。一种实施方式中，阵列基板100应用于PSVA模式的液晶显示面板200。具体到图1，薄膜晶体管20、数据线64、扫描线62及像素电极50均形成于第一基板12上，薄膜晶体管20的栅极电连接扫描线62，薄膜晶体管20的源极和漏极分别电连接数据线64和像素电极50之一。本实施例中，数据线64与扫描线62交错排列，薄膜晶体管20与像素电极50位于扫描线62与数据线64之间围成的像素区域内，需要注意的是，图1中数据线64被遮光电极30遮挡。一种实施方式中，第一基板12为玻璃基板或塑料基板等透明材料的平整的基板。
本实施例中，阵列基板100还包括设置于第一基板12上的辅助电极60和像素电极50，辅助电极60在第一基板12上的垂直投影至少部分位于数据线64与像素电极50之间，辅助电极60用于降低数据线64对像素电极50的影响。一种实施方式中，阵列基板100还包括连接于像素电极50与薄膜晶体管20的源极或漏极之间的过渡导电层，辅助电极60至少部分与源极或漏极正对，从而形成存储电容。一种实施方式中，辅助电极60的表面还设有绝缘层90，绝缘层90覆盖辅助电极60，以将辅助电极60与间隔柱等其他结构隔开，避免辅助电极60与外界短路。本实施例中，辅助电极60用于电连接至彩膜基板140，辅助电极60在第一基板12的垂直投影与数据线64不相交。具体的，辅助电极60还电连接至驱动电路，驱动电路发出控制公共电极16电压的信号， 并传递至公共电极16。
本实施例中，阵列基板100还包括绝缘层90，绝缘层90设置于辅助电极60背离第一基板12一侧的表面上，绝缘层90设有开孔40以露出辅助电极60。一种实施方式中，绝缘层90设置于辅助电极60的表面，并覆盖辅助电极60，以将辅助电极60与外界隔开，避免辅助电极60被短路而引起不良。本实施例中，开孔40形成于绝缘层90上，将被绝缘层90覆盖的辅助电极60暴露。
结合图1和图3，本实施例中，阵列基板100还包括遮光电极30，遮光电极30包括互连为一体的主体段34与突出段32，主体段34位于数据线64背离第一基板12的一侧，并且主体段34在第一基板12的垂直投影覆盖数据线64，进一步的，数据线64与主体段34之间相互绝缘，一种实施方式中，主体段34通过绝缘层90隔绝。本实施例中，主体段34为条状，每一个遮光电极30的主体段34覆盖一个数据线64，以减少曲面液晶显示面板200的侧面漏光现象。本实施例中，突出段32位于绝缘层90上，并且突出段32穿过开孔40接触辅助电极60，具体的，突出段32从主体段34的一侧延伸出来，沿着垂直于主体段34的方向延伸。进一步的，突出段32沿着开孔40的内壁向开孔40内部延伸，突出段32经过开孔40的底部时接触被开孔40暴露的辅助电极60。一种实施方式中，突出段32接触辅助电极60后继续沿着开孔40的内壁延伸，并延伸出开孔40，以增大突出段32与辅助电极60的接触面积。一种实施方式中，突出段32在第一基板12的垂直投影覆盖开孔40，换言之，开孔40露出的辅助电极60全部与突出段32接触，从而增大突出段32与辅助电极60的接触面积。
遮光电极30的主体段34覆盖数据线64，避免黑矩阵弯曲造成的液晶显示面板200侧面漏光，突出段32穿过绝缘层90上的开孔40接触并电连接至辅助电极60，从而通过辅助电极60电连接至彩膜基板140上的公共电极16，由于阵列基板100上的每一个遮光电极30都电连接至公共电极16，各遮光电极30的电位一致，减小了数据线64上的高低电位信号对遮光电极30的主体段34的影响，遮光电极30的正常工作，产品良率高，节省生产成本。
本实施例中，阵列基板100还包括薄膜晶体管20层叠设置于第一基板12的表面。薄膜晶体管20包括依次层叠设置的栅极、栅极绝缘层902、有源层、 源极和漏极、钝化层904。具体的，栅极绝缘层902位于栅极与有源层之间，用于隔绝栅极与有源层，避免栅极与有源层之间的相互影响，钝化层904覆盖源极和漏极，用于保护源极和漏极及整个薄膜晶体管20。一种实施方式中，像素电极50形成于钝化层904上，并且在钝化层904对应源极或漏极的位置，钝化层904设有开口，以暴露出部分源极或漏极，像素电极50穿过开口接触源极或漏极，从而实现薄膜晶体管20与像素电极50的电连接。本实施例中，在突出段32在第一基板12的垂直投影范围内，栅极绝缘层902与钝化层904依次层叠设置于辅助电极60上，具体的，辅助电极60与栅极为沉积于第一基板12上的第一金属层经过图案化后同时形成的，源极和漏极为沉积于第一基板12上的第二金属层经过图案化后形成，并且在突出段32的覆盖范围内，第二金属层被刻蚀、移除，因此在突出段32的覆盖范围内，钝化层904位于栅极绝缘层902的表面，并与栅极绝缘层902堆叠形成绝缘层90。一种实施方式中，钝化层904和栅极绝缘层902为相同的绝缘材料形成，也可以为不同的绝缘材料形成。进一步的，开孔40同时穿透钝化层904与栅极绝缘层902，从而暴露出辅助电极60。
遮光电极30的主体段34覆盖数据线64，避免黑矩阵弯曲造成的液晶显示面板200侧面漏光，突出段32穿过绝缘层90上的开孔40接触并电连接至辅助电极60，从而通过辅助电极60电连接至彩膜基板140上的公共电极16，由于阵列基板100上的每一个遮光电极30都电连接至公共电极16，各遮光电极30的电位一致，减小了数据线64上的高低电位信号对遮光电极30的主体段34的影响，遮光电极30的正常工作，产品良率高，节省生产成本。
请参阅图4，本发明实施例还提供一种显示面板200，包括彩膜基板140、液晶层80及本发明实施例提供的阵列基板100，彩膜基板140与阵列基板100相对设置，液晶层80位于阵列基板100与彩膜基板140之间，并根据阵列基板100与彩膜基板140之间的压差改变液晶层80的液晶分子偏转。一种实施方式中，显示面板200可以为曲面显示面板200。一种实施方式中，彩膜基板140包括第二基板14和公共电极16，第二基板14与第一基板12相对设置，公共电极16位于第二基板14面对阵列基板100的一侧，液晶层80位于像素电极50与公共电极16之间，并根据像素电极50与公共电极16之间的压差改 变液晶层80的液晶分子偏转。一种实施方式中，公共电极16为经过蚀刻等方式形成于第一基板12表面的导电层。实际上，在连接彩膜基板140与阵列基板100的框胶中设有多个接触点，用于将阵列基板100上的遮光电极30、辅助电极60与彩膜基板140上的公共电极16电连接。
请参阅图5，本发明实施例还提供一种显示设备300，包括背光模组82及本发明实施例提供的液晶显示面板200，背光模组82设置于液晶显示面板200的非显示面一侧，以提供背光源使液晶显示面板200显示图像。一种实施方式中，液晶显示设备300可以为曲面显示设备300。本实施例中，液晶显示设备300为电视、显示器、手机、平板电脑、笔记本电脑等。
遮光电极30的主体段34覆盖数据线64，避免黑矩阵弯曲造成的液晶显示面板200侧面漏光，突出段32穿过绝缘层90上的开孔40接触并电连接至辅助电极60，从而通过辅助电极60电连接至彩膜基板140上的公共电极16，由于阵列基板100上的每一个遮光电极30都电连接至公共电极16，各遮光电极30的电位一致，减小了数据线64上的高低电位信号对遮光电极30的主体段34的影响，遮光电极30的正常工作，产品良率高，节省生产成本。
请参阅图6至图9，本发明实施例还提供一种阵列基板100的制作方法，具体的，该方法包括以下步骤。
S101、提供第一基板12，在第一基板12上形成第一金属层，图案化第一金属层形成辅助电极60，辅助电极60用于电连接至彩膜基板140。
请参阅图6，形成第一金属层的方式可以为气相沉积，图案化第一金属层的方式可以为刻蚀等方式。一种实施方式中，图案化第一金属层形成辅助电极60的同时，还形成栅极，并且栅极与辅助电极60不相交。
S102、在第一基板12上形成第二金属层，图案化第二金属层形成数据线64，数据线64在第一基板12的垂直投影与辅助电极60不相交。
请参阅图7，形成第二金属层的方式可以为气相沉积，图案化第二金属层的方式可以为刻蚀等方式。一种实施方式中，图案化第二金属层形成数据线64的同时，还形成源极和漏极，并且源极或漏极与数据线64电连接。
S103、在辅助电极60背离第一基板12一侧的表面上形成绝缘层90，并在绝缘层90设置开孔40以露出辅助电极60。
请参阅图8，本实施例中，绝缘层90包括栅极绝缘层902与钝化层904。具体的，形成数据线64之前，图案化第一金属层形成栅极，并形成栅极绝缘层902于栅极上，形成数据线64的过程中，图案化第二金属层形成源极和漏极，数据线64电连接至源极或漏极，形成数据线64之后，形成钝化层904于源极和漏极上，栅极绝缘层902与钝化层904依次层叠于辅助电极60上形成绝缘层90。
本实施例中，薄膜晶体管20包括依次层叠设置的栅极、栅极绝缘层902、有源层、源极和漏极、钝化层904。具体的，栅极绝缘层902位于栅极与有源层之间，用于隔绝栅极与有源层，避免栅极与有源层之间的相互影响，钝化层904覆盖源极和漏极，用于保护源极和漏极及整个薄膜晶体管20。一种实施方式中，像素电极50形成于钝化层904上，并且在钝化层904对应源极或漏极的位置，钝化层904设有开口，以暴露出部分源极或漏极，像素电极50穿过开口接触源极或漏极，从而实现薄膜晶体管20与像素电极50的电连接。本实施例中，在突出段32在第一基板12的垂直投影范围内，栅极绝缘层902与钝化层904依次层叠设置于辅助电极60上，具体的，辅助电极60与栅极为沉积于第一基板12上的第一金属层经过图案化后同时形成的，源极和漏极为沉积于第一基板12上的第二金属层经过图案化后形成，并且在突出段32的覆盖范围内，第二金属层被刻蚀、移除，因此在突出段32的覆盖范围内，钝化层904位于栅极绝缘层902的表面，并与栅极绝缘层902堆叠形成绝缘层90。一种实施方式中，钝化层904和栅极绝缘层902为相同的绝缘材料形成，也可以为不同的绝缘材料形成。进一步的，开孔40同时穿透钝化层904与栅极绝缘层902，从而暴露出辅助电极60。
S104、形成导电层于第一基板12上，图案化导电层形成遮光电极30，遮光电极30包括互连为一体的主体段34与突出段32，主体段34位于数据线64背离第一基板12的一侧，并且主体段34在第一基板12的垂直投影覆盖数据线64，突出段32位于绝缘层90上，并且突出段32穿过开孔40接触辅助电极60。
请参阅图9，本实施例中，遮光电极30包括互连为一体的主体段34与突出段32，主体段34位于数据线64背离第一基板12的一侧，并且主体段34 在第一基板12的垂直投影覆盖数据线64，进一步的，数据线64与主体段34之间相互绝缘，一种实施方式中，主体段34通过绝缘层90隔绝。本实施例中，主体段34为条状，每一个遮光电极30的主体段34覆盖一个数据线64，以减少曲面液晶显示面板200的侧面漏光现象。本实施例中，突出段32位于绝缘层90上，并且突出段32穿过开孔40接触辅助电极60，具体的，突出段32从主体段34的一侧延伸出来，沿着垂直于主体段34的方向延伸。进一步的，突出段32沿着开孔40的内壁向开孔40内部延伸，突出段32经过开孔40的底部时接触被开孔40暴露的辅助电极60。一种实施方式中，突出段32接触辅助电极60后继续沿着开孔40的内壁延伸，并延伸出开孔40，以增大突出段32与辅助电极60的接触面积。一种实施方式中，突出段32在第一基板12的垂直投影覆盖开孔40，换言之，开孔40露出的辅助电极60全部与突出段32接触，从而增大突出段32与辅助电极60的接触面积。
遮光电极30的主体段34覆盖数据线64，避免黑矩阵弯曲造成的液晶显示面板200侧面漏光，突出段32穿过绝缘层90上的开孔40接触并电连接至辅助电极60，从而通过辅助电极60电连接至彩膜基板140上的公共电极16，由于阵列基板100上的每一个遮光电极30都电连接至公共电极16，各遮光电极30的电位一致，减小了数据线64上的高低电位信号对遮光电极30的主体段34的影响，遮光电极30的正常工作，产品良率高，节省生产成本。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易的想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (13)

  1. 一种阵列基板，其中，包括：
    第一基板和数据线，所述数据线设置于所述第一基板上；
    辅助电极，设置于所述第一基板上，所述辅助电极用于电连接至彩膜基板，所述辅助电极在所述第一基板的垂直投影与所述数据线不相交；
    绝缘层，设置于所述辅助电极背离所述第一基板一侧的表面上，所述绝缘层设有开孔；
    遮光电极，包括互连为一体的主体段与突出段，所述主体段位于所述数据线背离所述第一基板的一侧，并且所述主体段在所述第一基板的垂直投影覆盖所述数据线，所述突出段位于所述绝缘层上，并且所述突出段穿过所述开孔接触所述辅助电极。
  2. 根据权利要求1所述的阵列基板，其中，所述突出段在所述第一基板的垂直投影覆盖所述开孔。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括设置于所述第一基板上的像素电极，所述辅助电极在所述第一基板上的垂直投影至少部分位于所述数据线与所述像素电极之间，所述辅助电极用于降低所述数据线对所述像素电极的影响。
  4. 根据权利要求3所述的阵列基板，其中，所述绝缘层包括栅极绝缘层和钝化层，在所述突出段在所述第一基板的垂直投影范围内，所述栅极绝缘层与所述钝化层依次层叠设置于所述辅助电极上，所述第一基板上还设有薄膜晶体管，所述栅极绝缘层位于所述薄膜晶体管的栅极与源极、漏极之间，所述钝化层位于所述薄膜晶体管的源极或漏极与所述像素电极之间。
  5. 一种显示面板，其中，包括彩膜基板、液晶层及阵列基板，所述阵列基板包括，第一基板和数据线，所述数据线设置于所述第一基板上；辅助电极，设置于所述第一基板上，所述辅助电极用于电连接至彩膜基板，所述辅助电极在所述第一基板的垂直投影与所述数据线不相交；绝缘层，设置于所述辅助电极背离所述第一基板一侧的表面上，所述绝缘层设有开孔；遮光电极，包括互连为一体的主体段与突出段，所述主体段位于所述数据线背离所述第一基板的 一侧，并且所述主体段在所述第一基板的垂直投影覆盖所述数据线，所述突出段位于所述绝缘层上，并且所述突出段穿过所述开孔接触所述辅助电极。所述彩膜基板与所述阵列基板相对设置，所述液晶层位于阵列基板与彩膜基板之间，并根据阵列基板与彩膜基板之间的压差改变所述液晶层的液晶分子偏转。
  6. 根据权利要求5所述的显示面板，其中，所述突出段在所述第一基板的垂直投影覆盖所述开孔。
  7. 根据权利要求6所述的显示面板，其中，所述阵列基板还包括设置于所述第一基板上的像素电极，所述辅助电极在所述第一基板上的垂直投影至少部分位于所述数据线与所述像素电极之间，所述辅助电极用于降低所述数据线对所述像素电极的影响。
  8. 根据权利要求7所述的显示面板，其中，所述绝缘层包括栅极绝缘层和钝化层，在所述突出段在所述第一基板的垂直投影范围内，所述栅极绝缘层与所述钝化层依次层叠设置于所述辅助电极上，所述第一基板上还设有薄膜晶体管，所述栅极绝缘层位于所述薄膜晶体管的栅极与源极、漏极之间，所述钝化层位于所述薄膜晶体管的源极或漏极与所述像素电极之间。
  9. 一种显示设备，其中，包括背光模组及权利要求5所述的显示面板，所述背光模组设置于所述液晶显示面板的非显示面一侧，以提供背光源使所述液晶显示面板显示图像。
  10. 一种阵列基板的制作方法，其中，包括：
    提供第一基板，在所述第一基板上形成第一金属层，图案化所述第一金属层形成辅助电极，所述辅助电极用于电连接至彩膜基板；
    在所述第一基板上形成第二金属层，图案化所述第二金属层形成数据线，所述数据线在所述第一基板的垂直投影与所述辅助电极不相交；
    在所述辅助电极背离所述第一基板一侧的表面上形成绝缘层，并在所述绝缘层设置开孔；
    形成导电层于所述第一基板上，图案化所述导电层形成遮光电极，所述遮光电极包括互连为一体的主体段与突出段，所述主体段位于所述数据线背离所述第一基板的一侧，并且所述主体段在所述第一基板的垂直投影覆盖所述数据线，所述突出段位于所述绝缘层上，并且所述突出段穿过所述开孔接触所述辅 助电极。
  11. 根据权利要求10所述的阵列基板的制作方法，其中，形成所述数据线之前，图案化所述第一金属层形成栅极，并形成栅极绝缘层于所述栅极上，形成所述数据线的过程中，图案化所述第二金属层形成源极和漏极，所述数据线电连接至所述源极或所述漏极，形成所述数据线之后，形成钝化层于所述源极和所述漏极上，所述栅极绝缘层与所述钝化层依次层叠于所述辅助电极上形成所述绝缘层。
  12. 根据权利要求10所述的阵列基板的制作方法，其中，图案化所述导电层形成所述遮光电极的过程中，图案化所述导电层形成像素电极，所述辅助电极在所述第一基板上的垂直投影至少部分位于所述数据线与所述像素电极之间，所述辅助电极用于降低所述数据线对所述像素电极的影响。
  13. 根据权利要求1所述的阵列基板的制作方法，其中，所述突出段在所述第一基板的垂直投影覆盖所述开孔。
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