WO2019091197A1 - 一种针对高速信号连接器优化分析方法与系统 - Google Patents

一种针对高速信号连接器优化分析方法与系统 Download PDF

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WO2019091197A1
WO2019091197A1 PCT/CN2018/103439 CN2018103439W WO2019091197A1 WO 2019091197 A1 WO2019091197 A1 WO 2019091197A1 CN 2018103439 W CN2018103439 W CN 2018103439W WO 2019091197 A1 WO2019091197 A1 WO 2019091197A1
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pin
pad
length
excess
speed signal
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PCT/CN2018/103439
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English (en)
French (fr)
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刘法志
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郑州云海信息技术有限公司
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Priority to US16/493,256 priority Critical patent/US11189980B2/en
Publication of WO2019091197A1 publication Critical patent/WO2019091197A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70—Testing of connections between components and printed circuit boards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
    • H01R43/16—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for manufacturing contact members, e.g. by punching and by bending
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/08—Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures

Definitions

  • the present invention relates to the field of signal transmission, and in particular to a method and system for optimizing analysis of a high speed signal connector.
  • Backplane connectors are a type of connector commonly used in large communication devices, ultra-high-performance servers, and supercomputers, industrial computers, and high-end storage devices.
  • the main function is to connect the single board and the back board.
  • the single board and the back board have a vertical structure of 90 degrees, which transmits high-speed differential signals or single-ended signals and transmits large current.
  • a connector is an indispensable component in an electronic device. It refers to connecting two active devices to transmit current or signals. Between the blocked or isolated circuits in the circuit, a bridge of communication is established to allow current to flow, enabling the circuit to perform its intended function.
  • connection PIN pin in the high-speed connector is too long, which not only causes additional material costs, but also has more connector PIN stubs and PIN stubs in the board that result in loss of signal quality.
  • the object of the present invention is to provide an optimized analysis method and system for a high-speed signal connector, to solve the problem that the existing connector pins and pads are too long, affecting signal quality, and reduce loss in signal transmission and improve signal. quality.
  • the present invention provides an optimized analysis method for a high speed signal connector, comprising the following steps:
  • the excess portion of the pin is equivalent to an inductor and a capacitor; the excess portion of the pad is equivalent to an inductor and a capacitor;
  • the length of the pin and the excess portion of the pad when the performance parameter is optimal is obtained, and the pin and the pad are respectively cut according to the length of the pin and the excess portion of the pad.
  • the calculation formula that the excess portion of the pin is equivalent to the inductance and the capacitance and the excess portion of the pad is equivalent to the inductance and the capacitance is as follows:
  • L1 4(0.01*D)/(d1/D+0.44), D is the diameter of the pin, and d1 is the length of the extra part of the pin;
  • L2 4(0.01*D)/(d2/D+0.44), D is the diameter of the pin, and d2 is the length of the excess pad;
  • the performance parameters include the magnitude of insertion loss and return loss and whether there is a resonance phenomenon.
  • the selection criteria of the performance parameters are as follows: insertion loss and return loss are smaller and there is no resonance.
  • the invention also discloses an optimization analysis system for a high speed signal connector, comprising:
  • a length setting module for setting a pin of the high speed signal connector and an excess portion of the pad to different lengths
  • a performance analysis module configured to separately perform performance analysis on the connector with different lengths of the pin and the pad, and compare the performance parameters
  • the truncation length determining module is configured to obtain the length of the pin and the excess portion of the pad when the performance parameter is optimal, and to cut off the pin and the pad according to the length of the pin and the excess portion of the pad.
  • the equivalent module calculation formula is as follows:
  • L1 4(0.01*D)/(d1/D+0.44), D is the diameter of the pin, and d1 is the length of the extra part of the pin;
  • L2 4(0.01*D)/(d2/D+0.44), D is the diameter of the pin, and d2 is the length of the excess pad;
  • the performance parameters include the magnitude of insertion loss and return loss and whether there is a resonance phenomenon.
  • the criterion for determining the performance parameter is as follows: insertion loss and return loss are smaller and there is no resonance.
  • the present invention compares the pins of the redundant portion of the connector with the pads into inductance and capacitance, and performs performance analysis in the Hspice software to obtain the pin and the optimal performance parameter.
  • the length of the excess portion of the pad, and the pin and the pad are cut off according to the length, which solves the problem that the existing connector pins and pads are too long, affecting signal quality, reducing loss in signal transmission, and improving signal Quality, pin cutoff helps reduce the cost of materials, and the cutting of the pads helps create more space for routing and ease of design.
  • FIG. 1 is a flowchart of a method for optimizing analysis of a high-speed signal connector according to an embodiment of the present application
  • FIG. 2 is a schematic external view of a connector according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a connector pin according to an embodiment of the present application.
  • FIG. 5 is a comparison diagram of return loss of different pin and pad lengths according to an embodiment of the present application.
  • FIG. 6 is a structural block diagram of an optimization analysis system for a high speed signal connector according to an embodiment of the present invention.
  • an embodiment of the present invention discloses a method for optimizing analysis of a high-speed signal connector, including the following steps:
  • equivalent part of the pin is equivalent to an inductor and a capacitor; and the excess part of the pad is equivalent to an inductor and a capacitor;
  • S103 Perform performance analysis on the connector with different lengths of the excess part of the pin and the pad respectively, and compare the performance parameters;
  • S104 Obtain the length of the excess portion of the pin and the pad when the performance parameter is optimal, and cut off the pin and the pad according to the length of the pin and the excess portion of the pad.
  • the connector design usually consists of a plastic connection socket and a small circuit board or flexible circuit board composed of high-speed wires, as shown in Figure 2, the socket on the left side of this connector can be inserted into the backplane or other The board, the connection board connector on the right side can be connected to an external device such as a signal cable.
  • the pin of the traditional high-speed connector is shown in Figure 3.
  • the excess part of the connector A and the excess part of the pad B are too long, and the extra part will generate extra capacitance and inductance during signal transmission, thus affecting the high speed. Signal transmission.
  • the pin of the connector and the pad portion of the connector pin correspond to a high-speed line
  • the model of the high-speed line is equivalent to a combination of a capacitor and an inductor.
  • the pin of the connector is equivalent to the inductor and the capacitor, and the excess segment of the pin is equivalent to the inductor L1 and the capacitor C1, and the excess segment of the pad is equivalent to the inductor L2 and the capacitor C2:
  • L1 4(0.01*D)/(d1/D+0.44), D is the diameter of the pin, and d1 is the length of the extra part of the pin;
  • L2 4(0.01*D)/(d2/D+0.44), D is the diameter of the pin, and d2 is the length of the excess pad;
  • the relevant parameters in the Hspice software are set to the above inductance and capacitance, and the insertion loss and return loss are obtained.
  • Insertion loss and return loss parameters for different lengths of pins and pads are extracted and compared.
  • the performance analysis of the original length and the partially truncated connector is performed, and the performance analysis before and after the truncation is compared as shown in FIGS. 4 and 5.
  • the insertion loss will resonate.
  • the resonance will greatly affect the transmission quality of the signal in the high-speed line, and will form a back-and-forth reflection between the signal pins. This reflection not only causes electromagnetic
  • the loss of the signal on the other hand, the continuous reflection will oscillate the signal waveform. After the length is shortened, the resonance phenomenon disappears, indicating that the cut-off connector has a large improvement in signal transmission quality in terms of the insertion loss parameter.
  • the return loss at the original length is basically the same as the return loss after the length is shortened. However, when the frequency exceeds 60 GHz, the signal loss after the length is shortened is smaller than the signal loss at the original length. .
  • the pin and the pad of the redundant part of the connector are equivalent to the inductance and the capacitance, and the performance analysis is performed in the Hspice software to obtain the pin and the excess portion of the pad under the optimal performance parameter.
  • Length, and cut off the pins and pads according to the length solve the problem that the existing connector pins and pads are too long, affecting signal quality, reduce loss in signal transmission, improve signal quality, and pin Truncation helps to reduce the cost of materials, and the truncation of the pads helps create more space for routing and ease of design.
  • an embodiment of the present invention further discloses an optimization analysis system for a high-speed signal connector, including:
  • a length setting module for setting the pins and pads of the excess portion of the high speed signal connector to different lengths
  • L1 4(0.01*D)/(d1/D+0.44), D is the diameter of the pin, and d1 is the length of the extra part of the pin;
  • L2 4(0.01*D)/(d2/D+0.44), D is the diameter of the pin, and d2 is the length of the excess pad;
  • a performance analysis module configured to separately perform performance analysis on the connector with different lengths of the pin and the pad, and compare the performance parameters
  • the performance parameters include the magnitude of insertion loss and return loss and whether there is resonance.
  • the truncation length determining module is configured to obtain the length of the pin and the excess portion of the pad when the performance parameter is optimal, and to cut off the pin and the pad according to the length of the pin and the excess portion of the pad.
  • the optimal criteria for the performance parameters are as follows: insertion loss and return loss are smaller and there is no resonance.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented directly in hardware, a software module executed by a processor, or a combination of both.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

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  • Theoretical Computer Science (AREA)
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Abstract

一种针对高速信号连接器优化分析方法与系统，所述方法包括：将连接器中管脚与焊盘的多余部分设置为不同长度（101）；将管脚与焊盘的多余部分等效为电感和电容（102）；分别对管脚与焊盘的多余部分为不同长度的连接器进行性能分析，比对性能参数（103）；选择性能参数最优的管脚和焊盘多余部分的长度，对管脚和焊盘进行截断（104）。上述方法解决了现有连接器管脚和焊盘过长，影响信号质量的问题，减小了信号传输中的损耗，提高信号质量，管脚的截断有助于减少材料的成本费用，焊盘的截断有助于产生更大的空间进行走线，方便设计。

Description

一种针对高速信号连接器优化分析方法与系统
本申请要求于2017年11月9日提交中国专利局、申请号为201711100088.4、发明名称为“一种针对高速信号连接器优化分析方法与系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及信号传输领域，特别是涉及一种针对高速信号连接器优化分析方法与系统。
背景技术
背板连接器是大型通讯设备、超高性能服务器和巨型计算机、工业计算机、高端存储设备常用的一类连接器。主要作用是连接单板和背板，单板和背板间呈90度垂直结构，传递高速差分信号或单端信号以及传递大电流。
连接器是电子设备中必不可少的部件，是指连接两个有源器件进行传输电流或信号。在电路内被阻断处或孤立不通的电路之间，架起沟通的桥梁，从而使电流流通，使电路实现预定的功能。
现有连接器中，还是延续传统的PIN脚设计。高速连接器中的连接PIN脚太长，这样不仅会造成额外的材料成本，还会存在更多的连接器PIN Stub和电路板中的PIN Stub造成信号质量的损失。
发明内容
本发明的目的是提供一种针对高速信号连接器优化分析方法与系统，以解决现有连接器管脚和焊盘过长，影响信号质量的问题，实现减小信号传输中的损耗，提高信号质量。
为达到上述技术目的，本发明提供了一种针对高速信号连接器优化分析方法，包括以下步骤：
将高速信号连接器中管脚与焊盘的多余部分分别设置为不同长度；
将所述管脚的多余部分等效为电感和电容；将所述焊盘的多余部分等效为电感和电容；
分别对所述管脚与焊盘的多余部分为不同长度的连接器进行性能分析，比对性能参数；
获取性能参数最优时的管脚和焊盘多余部分的长度，并根据所述管脚和焊盘多余部分的长度分别对管脚和焊盘进行截断。
优选地，所述将所述管脚的多余部分等效为电感和电容以及将所述焊盘的多余部分等效为电感和电容的计算公式如下：
L1＝4(0.01*D)/(d1/D+0.44)，D为管脚直径，d1为为管脚多余部分长度；
L2＝4(0.01*D)/(d2/D+0.44)，D为管脚直径，d2为为焊盘多余部分长度；
C1＝4ε/d1，ε为介质介电常数，d1为管脚多余部分长度；
C2＝4ε/d2，ε为介质介电常数，d2为焊盘多余部分长度。
优选地，所述性能参数包括插入损耗和回波损耗的大小以及是否有谐振现象。
优选地，所述性能参数的选择标准如下：插入损耗和回波损耗更小且无谐振现象。
本发明还公开了一种针对高速信号连接器优化分析系统，包括：
长度设置模块，用于将高速信号连接器中管脚与焊盘的多余部分分别设置为不同长度；
等效模块，用于将所述管脚的多余部分等效为电感和电容；将所述焊盘的多余部分等效为电感和电容；
性能分析模块，用于分别对所述管脚与焊盘的多余部分为不同长度的连接器进行性能分析，比对性能参数；
截断长度确定模块，用于获取性能参数最优时的管脚和焊盘多余部分的长度，并根据所述管脚和焊盘多余部分的长度分别对管脚和焊盘进行截断。
优选地，所述等效模块计算公式如下：
L1＝4(0.01*D)/(d1/D+0.44)，D为管脚直径，d1为为管脚多余部分长度；
L2＝4(0.01*D)/(d2/D+0.44)，D为管脚直径，d2为为焊盘多余部分长度；
C1＝4ε/d1，ε为介质介电常数，d1为管脚多余部分长度；
C2＝4ε/d2，ε为介质介电常数，d2为焊盘多余部分长度。
优选地，所述性能参数包括插入损耗和回波损耗的大小以及是否有谐振现象。
优选地，所述性能参数最优的判断标准如下：插入损耗和回波损耗更小且 无谐振现象。
发明内容中提供的效果仅仅是实施例的效果，而不是发明所有的全部效果，上述技术方案中的一个技术方案具有如下优点或有益效果：
与现有技术相比，本发明通过将连接器中多余部分的管脚与焊盘进行等效为电感和电容，并在Hspice软件中进行性能分析，获得性能参数最优情况下的管脚与焊盘多余部分的长度，并按照此长度对管脚和焊盘进行截断，解决了现有连接器管脚和焊盘过长，影响信号质量的问题，减小信号传输中的损耗，提高信号质量，管脚的截断有助于减少材料的成本费用，焊盘的截断有助于产生更大的空间进行走线，方便设计。
附图说明
为了更清楚的说明本发明实施例或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例所提供的一种针对高速信号连接器优化分析方法流程图；
图2为本申请实施例所提供的一种连接器外形示意图；
图3为本申请实施例所提供的一种连接器管脚示意图；
图4为本申请实施例所提供的一种不同管脚和焊盘长度下插入损耗对比图；
图5为本申请实施例所提供的一种不同管脚和焊盘长度下回波损耗对比图；
图6为本发明实施例提供的一种针对高速信号连接器优化分析系统结构框图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保 护的范围。
下面结合附图对本发明实施例所提供的一种针对高速信号连接器优化分析方法与系统进行详细说明。
如图1所示，本发明实施例公开了一种针对高速信号连接器优化分析方法，包括以下步骤：
S101：将高速信号连接器中管脚和焊盘的多余部分分别设置为不同长度；
S102：将管脚的多余部分等效为电感和电容；将焊盘的多余部分等效为电感和电容；
S103：分别对管脚与焊盘的的多余部分为不同长度的连接器进行性能分析，比对性能参数；
S104：获取性能参数最优时的管脚和焊盘多余部分的长度，并根据管脚和焊盘多余部分的长度分别对管脚和焊盘进行截断。
在连接器设计中，通常由塑料材质的连接插座和由高速线组成的小段电路板或者柔性电路板组成，如图2所示，在此连接器中左侧的插座可以插到背板或者其他板卡，右侧的连接电路板接头可以连接像信号线缆之类的外接器件。
传统高速连接器的管脚如图3所示，连接器多余部分管脚A和多余部分焊盘B由于长度过长，其多余部分在信号传输过程中会产生额外的电容和电感，从而影响高速信号的传输。
由于连接器传输的是高速信号，而高速信号的传输需要高速线，因此连接器的管脚以及连接器管脚的焊盘部分相当于高速线，而高速线的模型相当于电容和电感的组合。在高速线传输信号时就是以电磁波的形式进行传播。
将连接器中多余部分的管脚与焊盘设置为不同长度。
在Hspice软件中，将连接器的管脚等效为电感和电容，将管脚的多余节段等效为电感L1和电容C1，将焊盘的多余节段等效为电感L2和电容C2：
L1＝4(0.01*D)/(d1/D+0.44)，D为管脚直径，d1为为管脚多余部分长度；
L2＝4(0.01*D)/(d2/D+0.44)，D为管脚直径，d2为为焊盘多余部分长度；
C1＝4ε/d1，ε为介质介电常数，d1为管脚多余部分长度；
C2＝4ε/d2，ε为介质介电常数，d2为焊盘多余部分长度。
在Hspice软件中的相关参数设置为上述电感和电容大小，获得插入损耗 以及回波损耗。
分别提取不同长度多余部分管脚与焊盘情况下的插入损耗和回波损耗参数，并进行比对。在本实施例中，对原始长度以及部分截断后的连接器进行性能分析，截断前和截断后的性能分析对比如图4和图5。
在管脚与焊盘的原始长度下，插入损耗会出现谐振现象，谐振会极大影响高速线中信号的传输质量，会在信号管脚之间形成来回反射，这种反射一方面不仅造成电磁信号的损耗，另一方面连续的反射会对信号波形形成震荡。而在将长度缩短后，谐振现象消失，表明就插入损耗参数而言，截断的连接器在信号传输质量方面有较大的提升。
而回波损耗在频率小于60GHz时，原始长度下的回波损耗与长度缩短后的回波损耗基本一致，但在频率超过60GHz时，长度缩短后的信号损失比原始长度下的信号损失要小。
由于管脚或者焊盘末端相当于开路，因此存在信号反射问题，验证发现，当多余部分在四分之一信号波长时会发生谐振现象，所述信号波长为信号周期与速率的乘积：L＝T*V，式中T表示信号周期，V表示速率。剩余管脚和焊盘越小，对于高速信号的影响越小，且材料成本越低。
通过对管脚和焊盘不同长度下的连接器进行性能分析，选择性能参数最优的管脚和焊盘多余部分的长度，对管脚和焊盘进行截断。
本发明实施例通过将连接器中多余部分的管脚与焊盘进行等效为电感和电容，并在Hspice软件中进行性能分析，获得性能参数最优情况下的管脚与焊盘多余部分的长度，并按照此长度对管脚和焊盘进行截断，解决了现有连接器管脚和焊盘过长，影响信号质量的问题，减小信号传输中的损耗，提高信号质量，管脚的截断有助于减少材料的成本费用，焊盘的截断有助于产生更大的空间进行走线，方便设计。
如图6所示，本发明实施例还公开了一种针对高速信号连接器优化分析系统，包括：
长度设置模块，用于将高速信号连接器中多余部分的管脚与焊盘分别设置为不同长度；
等效模块，用于将所述管脚的多余部分等效为电感和电容；将所述焊盘的多余部分等效为电感和电容；所述等效模块计算公式如下：
L1＝4(0.01*D)/(d1/D+0.44)，D为管脚直径，d1为为管脚多余部分长度；
L2＝4(0.01*D)/(d2/D+0.44)，D为管脚直径，d2为为焊盘多余部分长度；
C1＝4ε/d1，ε为介质介电常数，d1为管脚多余部分长度；
C2＝4ε/d2，ε为介质介电常数，d2为焊盘多余部分长度。
性能分析模块，用于分别对所述管脚与焊盘的多余部分为不同长度的连接器进行性能分析，比对性能参数；
所述性能参数包括插入损耗和回波损耗的大小以及是否有谐振现象。
截断长度确定模块，用于获取性能参数最优时的管脚和焊盘多余部分的长度，并根据所述管脚和焊盘多余部分的长度分别对管脚和焊盘进行截断。
所述性能参数最优的判断标准如下：插入损耗和回波损耗更小且无谐振现象。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上对本发明所提供的针对高速信号连接器优化分析方法与系统进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。

Claims (8)

  1. 一种针对高速信号连接器优化分析方法，其特征在于，包括：
    将高速信号连接器中管脚与焊盘的多余部分分别设置为不同长度；
    将所述管脚的多余部分等效为电感和电容；将所述焊盘的多余部分等效为电感和电容；
    分别对所述管脚与焊盘的多余部分为不同长度的连接器进行性能分析，比对性能参数；
    获取性能参数最优时的管脚和焊盘多余部分的长度，并根据所述管脚和焊盘多余部分的长度分别对管脚和焊盘进行截断。
  2. 根据权利要求1所述的针对高速信号连接器优化分析方法，其特征在于，所述将所述管脚的多余部分等效为电感和电容以及将所述焊盘的多余部分等效为电感和电容的计算公式如下：
    L1＝4(0.01*D)/(d1/D+0.44)，D为管脚直径，d1为为管脚多余部分长度；
    L2＝4(0.01*D)/(d2/D+0.44)，D为管脚直径，d2为为焊盘多余部分长度；
    C1＝4ε/d1，ε为介质介电常数，d1为管脚多余部分长度；
    C2＝4ε/d2，ε为介质介电常数，d2为焊盘多余部分长度。
  3. 根据权利要求1所述的针对高速信号连接器优化分析方法，其特征在于，所述性能参数包括插入损耗和回波损耗的大小以及是否有谐振现象。
  4. 根据权利要求3所述的针对高速信号连接器优化分析方法，其特征在于，所述性能参数最优的判断标准如下：插入损耗和回波损耗更小且无谐振现象。
  5. 一种针对高速信号连接器优化分析系统，其特征在于，包括：
    长度设置模块，用于将高速信号连接器中管脚与焊盘的多余部分分别设置为不同长度；
    等效模块，用于将所述管脚的多余部分等效为电感和电容；将所述焊盘的多余部分等效为电感和电容；
    性能分析模块，用于分别对所述管脚与焊盘的多余部分为不同长度的连接器进行性能分析，比对性能参数；
    截断长度确定模块，用于获取性能参数最优时的管脚和焊盘多余部分的长 度，并根据所述管脚和焊盘多余部分的长度分别对管脚和焊盘进行截断。
  6. 根据权利要求5所述的针对高速信号连接器优化分析系统，其特征在于，所述等效模块计算公式如下：
    L1＝4(0.01*D)/(d1/D+0.44)，D为管脚直径，d1为为管脚多余部分长度；
    L2＝4(0.01*D)/(d2/D+0.44)，D为管脚直径，d2为为焊盘多余部分长度；
    C1＝4ε/d1，ε为介质介电常数，d1为管脚多余部分长度；
    C2＝4ε/d2，ε为介质介电常数，d2为焊盘多余部分长度。
  7. 根据权利要求5所述的针对高速信号连接器优化分析系统，其特征在于，所述性能参数包括插入损耗和回波损耗的大小以及是否有谐振现象。
  8. 根据权利要求7所述的针对高速信号连接器优化分析系统，其特征在于，所述性能参数最优的判断标准如下：插入损耗和回波损耗更小且无谐振现象。
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