WO2019090762A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2019090762A1
WO2019090762A1 PCT/CN2017/110695 CN2017110695W WO2019090762A1 WO 2019090762 A1 WO2019090762 A1 WO 2019090762A1 CN 2017110695 W CN2017110695 W CN 2017110695W WO 2019090762 A1 WO2019090762 A1 WO 2019090762A1
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Prior art keywords
gate
substrate
layer
forming
drain
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PCT/CN2017/110695
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English (en)
French (fr)
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吴展兴
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吴展兴
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Priority to PCT/CN2017/110695 priority Critical patent/WO2019090762A1/zh
Priority to TW107139697A priority patent/TW201919131A/zh
Publication of WO2019090762A1 publication Critical patent/WO2019090762A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Definitions

  • the present invention relates to a method of forming a semiconductor structure, and more particularly to a method of forming a semiconductor structure including a gate.
  • T-type gates also known as Y-type gates or mushroom gates, are commonly used gate structures in three-five transistor power amplifiers.
  • 1 is a partial cross-sectional view showing a structure of a high electron mobility transistor (HEMT) used as a power amplifier, which includes a T-type gate 101 having a narrow root 101a in contact with the channel region and a head 101b which is wider above.
  • the wider head 101b can increase the cross-sectional area and reduce the gate series resistance; the narrower root 101a can reduce the gate length and reduce the gate capacitance.
  • the prior art uses an expensive electron beam lithography process or a deep UV stepper to fabricate a T-type gate, which results in high cost and is difficult to popularize. Therefore, there is still a need for novel and innovative technologies to solve the above problems.
  • a method of fabricating a gate using a spacer to define a gate length is provided.
  • the method of the present invention produces a variety of semiconductor gates including T-type gates.
  • the implementation of the present invention allows the use of general lithography process equipment that is not limited by expensive electron beam lithography processes or deep UV steppers.
  • the present invention also provides an easy method of protecting the substrate from the active region during gate fabrication.
  • the present invention utilizes a photoresist that defines a gate structure to protect other active regions of the substrate, thereby eliminating many additional protection processes.
  • the present invention can simultaneously remove all the photoresists defining the gate structure, which makes the process easier.
  • the present invention utilizes a lift-off process to fabricate a gate which is advantageous for the fabrication of III-V compound semiconductor components.
  • a T-type gate by metal etching because the material properties of the III-V compound itself are dry etching (such as inductively coupled plasma ion etching ICP or reactive ion etching RIE). ) sensitive, the surface is easily damaged and the carrier concentration is lost. Since the active layer of the module is very thin, ion etching close to the surface easily removes the active layer or causes serious carrier loss and cannot maintain the integrity of the active layer, an etching process is used to fabricate a general III-V compound semiconductor device. It is more difficult.
  • the present invention is advantageous The use of a lift-off process to fabricate a gate, particularly a T-type gate of a III-V compound semiconductor, avoids the dilemma of metal etching.
  • the method of the present invention produces a variety of semiconductor gates including T-type gates.
  • the implementation of the present invention allows the use of general lithography process equipment that is not limited by expensive electron beam lithography processes or deep UV steppers.
  • the present invention also includes other embodiments to solve other problems and the embodiments described above are disclosed in detail in the following embodiments.
  • FIG. 1 is a schematic cross-sectional view showing a part of a structure of a high electron mobility transistor (HEMT) used as a power amplifier;
  • HEMT high electron mobility transistor
  • FIG. 2a, 2b, 3, 4, 5, 5a, 6a, 7a, 8a, 6b, 6b', 7b, 8b, 9, 10, 11 are schematic views showing a manufacturing process of a gate structure according to a first embodiment of the present invention, wherein 6a, 7a and 8a relate to the first method; Figures 6b, 6b', 7b and 8b relate to the second method;
  • FIG. 12 and FIG. 13 are schematic diagrams showing a manufacturing process of a gate structure according to a second embodiment of the present invention.
  • FIG. 14a, 14b and 14c are schematic views showing a manufacturing process of a gate structure according to a third embodiment of the present invention.
  • 15a, 15b and 15c are schematic views showing a manufacturing process of a gate structure according to a fourth embodiment of the present invention.
  • Figure 16 is a view showing a gate structure of a fifth embodiment of the present invention.
  • 17a, 17b, 17c and 17d are schematic views showing a manufacturing process of a gate structure according to a sixth embodiment of the present invention.
  • the substrate is usually a gallium arsenide substrate, but may be any other semiconductor material suitable for forming a gate structure thereon, such as InP, GaN, Si, SiC, SiGe, GaSb, Group IV, Group IV-IV, III-V. Family, II-VI.
  • the substrate can include various active components such as various epitaxial layers used to fabricate pHEMT, HEMT, MESFET, MOSFET, and the like. This embodiment is an example of making a gate of a HEMT, and the steps start at one.
  • the substrate 200 of each epitaxial layer, source S and drain D is already included.
  • Fig. 2a is a plan view of the substrate 200, and Fig.
  • FIG. 2b is a schematic cross-sectional view taken along the dashed line from point A to point A of Fig. 2a.
  • the surface of the substrate 200 includes a plurality of drains D and a plurality of sources S protruding from the surface of the substrate 200.
  • a first patterned photoresist layer 310 is formed on the substrate 200.
  • the first patterned photoresist layer 310 covers a portion of the substrate 200.
  • the pattern of the first patterned photoresist layer 310 determines the location at which the gate is to be subsequently formed. In this embodiment, the position of the gate is preferably defaulted between the source S and the source S and closer to the sidewall Sw of the source S with respect to the drain D.
  • the first patterned photoresist layer 310 is designed to cover all of the drain D and the source S and has an opening 320 in one of the drains D and one of the sources S thereof. Used to make gates.
  • the first patterned photoresist layer 310 specifically includes a sidewall Sw of the photoresist sidewall 310s covering the source S, and also includes a sidewall Dw of the photoresist D covering the drain sidewall D.
  • the first patterned photoresist layer 310 can be formed by a conventional spin coating method and lithography.
  • the photoresist thickness can be, for example, a thickness of 100 to 10,000 angstroms. In some examples, if the thickness of the first patterned photoresist layer 310 is too large, an excessive aspect ratio may be formed to affect the filling of the subsequent gate metal.
  • a dielectric layer 410 is conformally deposited along the surface of the structure 200 of FIG. Specifically, the dielectric layer 410 covers a portion of the substrate 200 that is not covered by the first patterned photoresist layer 310; the dielectric layer 410 also covers the top and sidewalls of the first patterned photoresist layer 310, which includes the covered light. The sidewalls 310s and 310d are blocked. Dielectric layer 410 may be formed using plasma assisted chemical vapor deposition (PECVD) or atomic layer deposition (ALD) or other CVD, and the material may be silicon oxide (SiOx) or nitrogen oxide (SiNx) or other suitable material. The thickness of the dielectric layer 410 depends on the gate length of the gate to be subsequently formed. The thickness of the dielectric layer 410 is preferably in the range of 50 angstroms to 8000 angstroms in accordance with the process of the present invention.
  • PECVD plasma assisted chemical vapor deposition
  • ALD atomic layer deposition
  • SiNx
  • spacers 510d and 510s are formed on the sidewalls of the first patterned photoresist layer 310.
  • the dielectric layer 410 on the surface of the substrate 200 and the top of the first patterned photoresist layer 310 is removed by anisotropic etching (dry etching), but the sidewalls 310d and 310s covering the first patterned photoresist layer 310 are left.
  • the electrical layer 410 forms spacers 510d and 510s, wherein the spacers 510d are adjacent to the drain D, and the spacers 510s are adjacent to the source S.
  • the spacer 510s is the position at which the gate is to be subsequently formed.
  • Figure 5a is an enlarged schematic view of the spacer 510s/510d.
  • the spacer 510s/510d includes a curved portion 511 (which may be referred to as a bending spacer) and an equal portion 522 (which may be referred to as an equal gap, uniform) Spacer) below.
  • the height ratio of the curved portion 511 to the height of the equal portion 522 is about 1:2.
  • Figures 6a, 7a and 8a are first methods; Figures 6b, 6b', 7b and 8b are second methods. After the gate opening is formed, the gate insulating layer and the gate metal can be filled to complete the gate structure.
  • a second photoresist layer 610 is formed on the substrate 200, and the second photoresist layer 610 is covered.
  • the first patterned photoresist layer 310 and the spacers 510d and 510s are covered.
  • the second photoresist layer 610 can be formed flat by the existing spin coating and lithography methods.
  • the second photoresist layer 610 and the first patterned photoresist layer 310 may use the same or different materials, preferably using the same material with subsequent one-time removal.
  • the height of the second photoresist layer 610 may need to be larger.
  • a portion of the second photoresist layer 610 and a portion of the first patterned photoresist layer 310 are removed to expose the curved portion 511 of the spacer 510d/510s.
  • This step can be carried out using reactive ion etching or any other suitable technique such as plasma asher.
  • the spacers 510d/510s include the curved portion 511 and the equal portion 522, and the photoresist removal amount in this step is controlled to expose the curved portion 511 of the spacer 510d/510s, leaving the equal portion 522 remaining in the residue.
  • the second photoresist layer 610' is in the remaining first patterned photoresist layer 310'.
  • the portion of the spacers 510d/510s buried in the residual photoresist layers 610' and 310' determines the subsequent formation of the gate root profile. If the bent portion 511 is not entirely exposed and buried in the residual photoresist layers 610' and 310', the subsequently formed gate may have a narrow and fragile neck.
  • the spacers 510d and 510s are removed to form openings 811s and 811d in the remaining second photoresist layer 610' and the remaining first patterned photoresist layer 310', and the opening 811s defines the gate.
  • the present invention provides various embodiments having openings of from 50 Angstroms to 6000 Angstroms. This step can be carried out using liquid phase chemical etching, such as BOE/HF + H2O.
  • FIG. 8a is another optional step of forming the notch portion 811r in the substrate 200 after removing the spacers 510d and 510s. In some instances, this step can be used to remove the cladding layer on the surface of the substrate 200.
  • the remaining second photoresist layer 610' and the remaining first patterned photoresist layer 310' are shielded, and the openings 811s and 811d the bottom substrate 200 are etched to form the notch portion 811r to expose the epitaxial layer inside the substrate 200.
  • the cladding layer on the surface of the substrate 200 is removed, for example, to expose the Schottky barrier layer.
  • a second method of forming a gate opening using a spacer is illustrated below as shown in Figures 6b, 7b and 8b.
  • the first patterned photoresist layer 310 is completely removed and this step can be accomplished by a suitable etching and development process.
  • an alternative photoresist layer 730 is formed on the surface of the substrate 200 with reference to FIG. 7b of the second method, and the thickness of the replacement photoresist layer 730 is controlled to cover the source S, the drain D, or other active regions on the substrate 200.
  • the equidistant portions 522 of the spacers 510d and 510s are buried in the replacement photoresist layer 733 and the curved portions 511 of the spacers 510d and 510s are exposed.
  • the alternative photoresist layer 730 can be formed using any suitable means to avoid damaging the spacers 510d and 510s and to accurately control the thickness of the replacement photoresist layer 730. For example, referring to FIG.
  • a flat photoresist layer 730' may be formed to cover the source S, the drain D, other active regions on the substrate 200, and the spacers 510d and All portions of 510s, and then etch back a portion of the material of the planar photoresist layer 730' to expose the curved portions 511 of the spacers 510d and 510s, and the equidistant portions 522 of the spacers 510d and 510s are still buried in the flat photoresist layer.
  • the etched flat photoresist layer 730' is an alternative photoresist layer 733 (Fig. 7b).
  • a suitable photoresist material can be placed in a nozzle to form a flat photoresist layer 730' by a vapor spray method. Note that the portion of the spacer 510d/510s buried in the replacement photoresist layer 730 determines the subsequent formation of the gate root profile. If the curved portion 511 is not entirely exposed and buried in the replacement photoresist layer 730, the subsequently formed gate has a narrow and fragile neck.
  • the spacers 510d and 510s are removed to form an opening 811s and 811d in the alternative photoresist layer 730.
  • the opening 811s defines the bottom dimension of the gate, wherein the opening 811s is adjacent to the source S.
  • the present invention provides various embodiments having openings of from 50 Angstroms to 6000 Angstroms. This step can be carried out using liquid phase chemical etching, such as BOE/HF + H2O.
  • a gate insulating layer (not necessary) may be formed along the surfaces of the openings 811s and 811d by various suitable methods and a gate conductive layer may be formed on the gate insulating layer to constitute a gate structure.
  • FIG. 8b is another optional step of forming the notch portion 811r in the substrate 200 after removing the spacers 510d and 510s. This step can be referred to the foregoing without further description.
  • the fabrication of the gate insulating layer can be performed by either FIG. 8a of the first method or FIG. 8b of the second method.
  • the fabrication step of the gate insulating layer of Figure 9 is Figure 8b which continues the second method.
  • the gate insulating layer is not necessary and may be selected as such.
  • a conformal insulating layer 920 is formed to cover the openings 811d/811s and the replacement photoresist layer 730 (if the first method covers the remaining second photoresist layer 610' and the remaining first photoresist layer 310'). In the example in which the notch 811r is formed, the conformal insulating layer 920 also covers the notch 811r.
  • the insulating layer 920 is a relatively thin layer compared to each of the photoresist layers described above.
  • the insulating layer 920 has a thickness in the range of 50 to 2000 angstroms.
  • the preferred material may be a high dielectric (high K) insulating material such as HfOx, or AlOx or TiOx.
  • the fabrication of the gate conductive layer is performed.
  • the conductive layer 930 is formed to cover the conformal insulating layer 920, and the openings 811d/811s and the notches 811r are filled. This step can be accomplished by sputtering or other isotropic deposition methods.
  • the material of the conductive layer 930 can be any suitable metal or conductive material.
  • a third patterned photoresist 940 is formed on the conductive layer 930, and the third patterned photoresist 940 defines the top shape of the gate.
  • the gate is located near the opening 811s of the source, so the third patterned photoresist 940 does not cover the opening 811d near the drain.
  • the third patterned photoresist 940 can be used to design the wide head of the gate, but this case is not limited to the T-type gate.
  • Forming the third patterned photoresist 940 can be performed by existing spin coating methods and lithography.
  • the third patterned photoresist 940 may use the same or different material as the foregoing alternative photoresist layer 730, the second photoresist layer 610, or the first patterned photoresist layer 310, and preferably the same material has a subsequent use. Remove.
  • a third patterned photoresist 940 is used as a shield, and a portion of the conductive layer 930 is removed to form a gate conductive layer 1010; the photoresist 940 may be patterned in a third step in the same step or in different steps.
  • a portion of the conformal insulating layer 920 is removed to form a gate insulating layer 1020. This step can be accomplished using wet etching or with dry plasma etching. Note that this step also removes the conformal insulating layer 920 and the conductive layer 930 in the opening 811d and the notch 811r.
  • the third patterned photoresist 940 and the replacement photoresist layer 730 are removed to expose the gate 1100 on the substrate 200.
  • Figure 11 is an embodiment of forming a T-type gate having a wider top and a narrower root. This step can be performed by any suitable method, such as liquid phase etching, using any suitable photoresist removal technique.
  • the remaining second photoresist layer 610' (as shown in FIGS. 7a and 8a)
  • the remaining first patterned photoresist layer 310' as shown in FIGS. 7a and 8a
  • the third patterned photoresist 940 can be removed simultaneously.
  • this example proposes a structure in which the gate 1100 and the drain D have a notch 811r, and the notch 811r exposes an epitaxial layer inside the substrate 200, such as a Schottky barrier layer.
  • the gap 811r can be placed at the depletion edge by appropriate design, which can alleviate the current crowding effect to increase the breakdown voltage without reducing or sacrificing the transistor's cut off frequency and gain. This can increase the performance of the power amplifier.
  • the present invention includes another embodiment in which a metal layer is deposited on the notch 811r but not as a gate, and the metal layer is floated and not electrically connected to the outside, and the metal layer can be adapted to the surface depletion region.
  • the electric field is distributed to achieve the required breakdown voltage and high cutoff frequency and high gain.
  • a semiconductor structure including a substrate 200 having a drain D, a source S and a gate 1100 between the drain D and the source S, wherein the substrate 200 further includes a substrate surface 200a, the substrate surface 200a has a substrate 200 A notch 811r is between the drain D and the gate S.
  • the substrate 200 further includes an epitaxial structure including a cladding layer 210 formed in the cladding layer 210 and exposing the Schottky barrier layer 220 under the cladding layer 210.
  • the substrate surface 200a further includes a gate opening (i.e., the aforementioned opening 811s), and the gate 1100 extends upward from the gate opening 811s. Since the gate opening 811s and the notch 811r are formed in the same layer and in the same process, the gate opening 811s and the notch 811r have substantially the same depth.
  • FIG. 12 and 13 show the second embodiment in which there is no gap between the gate and the drain.
  • Figure 12 is a Figure 6b following the second method.
  • the spacer 510d is further removed to form with reference to Fig. 6b, as shown in Fig. 12, leaving only the structure of the spacer 510s.
  • Performing this step can cover the gate S and the drain D and the spacer 510s with a suitable shield to remove the spacer 510d by liquid etching.
  • FIGS. 6b', 7b, 8b, FIG. 9 to FIG. 11, and the like the gate 1300 shown in FIG. 13 can be obtained, and there is no gap 811r between the gate 1300 and the drain D.
  • the substrate 200 of the embodiment (as shown in FIG. 2b) has a substrate surface between the drain D and the source S that is flat, so the spacers 510d/510s are formed on the flat surface;
  • the substrate 200' of the third embodiment (eg Figure 14a) has a wide recess 1400 between its drain D and source S, and spacers 1412d/1412s are formed on the surface of the wide recess 1400. Note that this wide depression is mainly used to relieve surface depletion and surface current clustering effects to increase the breakdown voltage, mainly to improve the performance of high power amplifiers.
  • a substrate 200' having respective epitaxial layers, a source S and a drain D is provided, wherein the substrate 200' has a wide recess 1400 between its drain D and source S; the first on the substrate 200' A patterned photoresist layer 1410; and spacers 1412d/1412s are formed on the surface of the wide recess 1400.
  • the surface of the substrate 200' may be a cladding layer 210', and under the cladding layer 210' is a Schottky barrier layer 220'. Therefore, the surface of the wide recess 1400 is the cladding layer 210'.
  • the method of forming the structure of Fig. 14a includes first providing a substrate 200' having a wide recess 1400, and then forming a first patterned photoresist layer 1410 such that its sidewalls land on the surface of the wide recess 1400. A spacer 1412d/1412s is then formed on the surface of the wide recess 1400. For details, refer to FIG. 2a, FIG. 2b, FIG. 3 to FIG. 5, and FIG. 5a of the foregoing first embodiment.
  • the openings can be defined by spacers 1412d/1412s, referring to the method of Figs. 6b, 7b, and 8b of the first embodiment described above, to form a structure as shown in Fig. 14b.
  • openings 1416s and 1416d are in the alternative photoresist layer 1415, and the opening 1416s is adjacent to the source S and defines the bottom dimension of the gate.
  • the opening 1416d is adjacent to the drain D. Note that the openings 1416s and 1416d may have a certain depth to expose the Schottky barrier layer 220'.
  • FIG. 14c A semiconductor structure is provided as shown in FIG. 14c, comprising a substrate 200' having a drain D, a source S and a gate 1420 between the drain D and the source S, wherein the substrate 200' further comprises a substrate surface 200'a, the substrate surface 200'a has a wide recess 1400 between the drain D and the source S and a gap (ie, the aforementioned opening 1416d is formed on the bottom surface of the wide recess 1400, wherein the notch 1416d is located at the gate 1420 and the drain
  • the substrate 200' further includes an epitaxial structure including a cladding layer 210', and the wide recess 1400 and the notch 1416d are formed in the cladding layer 210', wherein the notch 1416d is exposed under the cladding layer 210' Scho
  • the bottom surface of the wide recess 1400 further includes a gate opening (ie, opening 1416s), the gate 1420 extends upward from the gate opening 1416s, and the gate opening 1416s is substantially identical to the gap 1416d. Depth, because they are formed on the same layer and in the same process step. Meanwhile, as shown in Fig. 12, the third embodiment can also remove the notch 1416d.
  • the substrate 200' of the third embodiment has a wide recess 1400 between the drain D and the source S, and the spacers 1412d/1412s are formed in the wide recess.
  • the substrate 200" of the fourth embodiment has its drain D and source S
  • a substrate 200" having respective epitaxial layers, a source S and a drain D wherein the substrate 200" has a wide recess 1500 between the drain D and the source S and a platform 1501 adjacent to the wide recess 1500 a first patterned photoresist layer 1510 on the substrate 200"; and a spacer 1512d adjacent to the drain D as described above is formed on the surface of the stage 1501, and a spacer 1512s adjacent to the source S is formed on the surface of the wide recess 1500
  • the surface of the substrate 200" may be a cladding layer 210", and the underlying layer 210" is a Schottky barrier layer 220".
  • the surface of the platform 1501 is a cladding layer 210", a wide depression 1500
  • the surface is also a cladding layer 201".
  • the method of forming the structure of Figure 15a includes first providing a substrate 200" having a wide recess 1500 and a land 1501, followed by forming a first patterned photoresist layer 1510, and then forming a spacer 1512d/1512s .
  • the gate opening 1516s and the opening 1516d adjacent to the drain may be defined by the spacer 1512d/1512s, referring to the method of FIG. 6b, FIG. 7b, and FIG. 8b of the foregoing first embodiment.
  • openings 1516s and 1416d are formed in the alternative photoresist layer 1515, which defines the bottom dimension of the gate. Note that the opening 1516s has a certain depth to expose the Schottky barrier layer 220". The opening 1516d does not expose the Schottky barrier layer 220" only to expose the overlying cladding layer 210".
  • a semiconductor structure includes a substrate 200" having a drain D, a source S and a gate 1520 between the drain D and the source S, and the substrate 200" further including a substrate surface 200"a
  • the substrate surface 200"a has a wide recess 1500 between the drain D and the source S and is closer to the source S, and at least one notch (ie, the aforementioned opening 1516d) is formed between the wide recess 1500 and the drain D.
  • the substrate 200" further includes an epitaxial structure including a cladding layer 210", and a wide recess 1500 and a notch 1516d are formed in the cladding layer 210". Note that the notch 1516d does not expose the Schottky barrier layer 220" under the cladding layer 210".
  • the surface of the wide recess 1500 also includes a gate opening (i.e., the aforementioned opening 1516s), and the gate 1520 extends upward from the gate opening 1516s.
  • This gap 1516d can be used to adapt the breakdown voltage of the transistor in the high power amplifier without sacrificing the cutoff frequency and gain of the transistor to achieve optimum power amplification performance.
  • Figure 16 is a fifth embodiment of the multi-notch of the present invention, and this embodiment of the present invention can be implemented by referring to the above description.
  • the step begins with a substrate 1700 that already includes each epitaxial layer.
  • the substrate 1700 includes a plurality of protrusions on the surface of the substrate 1700 Bungee D and multiple source S.
  • the surface of the substrate 1700 further includes a spacer 1701 and a spacer 1702 in a region of the wide recess 1700a and closer to the source S.
  • An opening 1705 is formed between the spacer 1701 and the spacer 1702 to expose the surface of the substrate 1700 on the wide recess 1700a.
  • the bottom of the opening 1705 defines the gate length Lg of the T-type gate.
  • the surface of the substrate 1700 further includes a patterned photoresist layer 1703 adjacent to the spacers 1701 and the spacers 1702.
  • the patterned photoresist layer 1703 covers most of the region of the substrate 1700, the drain D and the source S, but does not cover the spacer 1701, the spacer 1702, and the opening 1705.
  • the structure illustrated in Figure 17a can be fabricated with reference to the method of forming the foregoing structure of Figure 5.
  • the preferred width w of the spacer 1701 or the spacer 1702 is between 0.05 and 0.2 ⁇ m, and the distance between the outer side of the spacer 1701 and the outer side of the spacer 1702 is L.
  • the preferred range is between 0.25 and 0.7 ⁇ m or less, such as between 0.1 and 0.2 ⁇ m.
  • a flat photoresist layer 1706 is formed to cover the structure shown in FIG. 17a, and the flat photoresist layer 1706 fills the opening 1705 at the same time.
  • the thickness of the flat photoresist layer 1706 is preferably 0.3 to 2 ⁇ m. Note that the patterned photoresist layer 1703 is different from the flat photoresist layer 1706, and the patterned photoresist layer 1703 can be made of a material different in sensitivity to the flat photoresist layer 1706.
  • the flat photoresist layer 1706 is exposed and developed by optical lithography to expose the opening 1705 and form a larger opening 1707 over the opening 1705.
  • the opening 1707 is formed by the inclined photoresist walls A1 and A2.
  • a metallic conductive material is deposited in opening 1705 and opening 1707.
  • This step can be accomplished using existing directional deposition metal evaporation methods. Note that as shown, the oblique orientation of the photoresist walls A1 and A2 will prevent the deposited metal from being tightly bonded to the photoresist walls A1 and A2, facilitating subsequent photoresist stripping. In contrast, as shown, the oblique direction of the spacer 1701 or the spacer 1702 will cause the deposited metal to be easily bonded to the spacer 1701 or the spacer 1702, facilitating the formation of a structurally stable T-gate.
  • the planar photoresist layer 1706 and the patterned photoresist layer 1703 are removed in a suitable manner, such as a liquid phase etching or development process, to form a structure as shown in Figure 17d.
  • a semiconductor structure comprising a substrate 1700 having a drain D, a source S, and a gate G between the drain D and the source S.
  • the substrate 1700 further includes a pair of spacers 1701/1702 adjacent to the gate G, the pair of spacers 1701/1702 defining a gate length Lg of the gate G.
  • the gate G further includes a narrow root portion 1710r and a wide head portion 1710h.
  • the pair of spacer walls 1701/1702 are located on the same plane as the narrow root portion 1710r, and the pair of spacer walls 1701/1702 are adjacent to the narrow root.
  • the substrate 1700 further includes a substrate surface 1700 s, a wide recess 1700a on the surface of the substrate between the drain D and the source S, and the pair of spacers 1701/1702 and the narrow root 1710r are located in the wide recess 1700a.

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  • Junction Field-Effect Transistors (AREA)

Abstract

一种闸极（1100, 1300）的形成方法，包含形成第一图案化光阻层（310）于基板（200）上；形成间隙壁（510d, 510s）于该第一图案化光阻层（310）的侧壁上，其中该间隙壁（510d, 510s）包含弯曲部分；去除第一图案化光阻层（310）；形成替代光阻层（730）于该基板（200）上，使该间隙壁（510d, 510s）插在该替代光阻层（730）中而露出该弯曲部分；以及去除该间隙壁（510d, 510s）以形成开口（811d, 811s）于该替代光阻层（730）中，其中该开口（811d, 811s）定义闸极（1100, 1300）的底部尺寸。还包含根据上述方法形成的所述的闸极（1100, 1300）结构。

Description

半导体结构及其形成方法 技术领域
本发明涉及是一种半导体结构的形成方法，特别是涉及含有闸极的半导体结构的形成方法。
背景技术
T型闸极，也称为Y型闸极或蘑菇闸极，是三五族晶体管功率放大器中常用的闸极结构。图1为现有用作功率放大器的高电子迁移率晶体管(HEMT)的部分结构剖面示意图，其包含T型闸极101，具有与通道区接触的狭窄根部101a以及上方较宽大的头部101b。较宽大的头部101b可增加截面积而降低闸极串联电阻；较狭窄的根部101a可缩小闸极长度减少闸极电容。为了达到极短的闸极长度，现有技术采用昂贵的电子束微影制程或深UV步进机等设备来制作T型闸极，导致高成本故产品难以普及。因此，仍需要新颖创新的技术来解决上述的问题。
发明内容
本发明一方面提供一种利用间隙壁来定义闸极长度的闸极制造方法。本发明的方法可制作各种半导体闸极，包含T型闸极。实施本发明可使用一般的微影制程设备，不被昂贵的电子束微影制程或深UV步进机等设备所限制。本发明还提供闸极制造过程中保护基板已完成主动区域的简易方法。本发明利用定义闸极结构的光阻保护基板的其他主动区域，因此省去许多额外的保护制程。此外，本发明可将定义闸极结构的所有光阻同时去除，使制程更加简便。
本发明是利用剥离(Lift-Off)制程制造闸极，对III-V族化合物半导体组件的制造是有利的。一般III-V族化合物半导体组件，要以金属蚀刻的方式制造T型闸极相对困难，因为III-V族化合物本身材料性质对干蚀刻(如感应耦合电浆离子蚀刻ICP或反应式离子蚀刻RIE)较敏感，表面容易受损而流失载体浓度。因为组件活化层(active layer)非常薄，靠近表面的离子蚀刻很容易去掉活化层或产生严重的载体流失，无法保持活化层的整体性，所以使用蚀刻制程来制造一般III-V族化合物半导体组件难度较高。本发明是利 用剥离(Lift-Off)制程制造闸极，特别是III-V族化合物半导体的T型闸极可避免金属蚀刻的困境。
本发明的方法可制作各种半导体闸极，包含T型闸极。实施本发明可使用一般的微影制程设备，不被昂贵的电子束微影制程或深UV步进机等设备所限制。
本发明还包含其他实施例以解决其他问题并合并上述的实施例详细揭露于以下实施方式中。
附图说明
图1为现有用作功率放大器的高电子迁移率晶体管(HEMT)的部分结构剖面示意图；
图2a,2b,3,4,5,5a,6a,7a,8a,6b,6b’,7b,8b,9,10,11为本发明第一实施例的闸极结构制造过程示意图，其中图6a、7a及8a涉及第一方法；图6b、图6b’、图7b及8b涉及第二方法；
图12及图13为本发明第二实施例的闸极结构制造过程示意图；
图14a、14b及14c为本发明第三实施例的闸极结构制造过程示意图；
图15a、15b及15c为本发明第四实施例的闸极结构制造过程示意图；
图16为本发明第五实施例的闸极结构；
图17a,17b,17c及17d为本发明的第六实施例的闸极结构制造过程示意图。
元件标号说明
101、1420、1520              T型闸极
101a、1710r                  根部
101b、1710h                  头部
200、200’、1700             基板
S                            源极
G、1100、1300                闸极
D                            汲极
310、310’、610’、730’     光阻层
310d、310s                   光阻侧壁
320、811d、811s、1416d、1416s、1516d、1516s、1705、1707    开口
Sw、Dw                       侧壁
410                        介电层
510d、510s、1412d、1412s、1512d、1512s、1701、1702   间隙壁
511                        弯曲部分
522                        等齐部分
610                        第二光阻层
811r                       缺口部
730、1415、1515            替代光阻层
920、1020                  绝缘层
930、1010                  导电层
940                        第三图案化光阻
220、220’                 肖特基阻障层
210’                      披覆层
1400、1500、1700a          凹陷
1410、1510                 第一图案化光阻层
200’a、200”a、1700s      基板表面
1501                       平台
1703                       图案光阻层
1706                       平坦光阻层
A1、A2                     阻壁
具体实施方式
以下将参考所附图式示范本发明的较佳实施例。所附图式中相似组件是采用相同的组件符号。应注意为清楚呈现本发明，所附图式中的各组件并非按照实物的比例绘制，而且为避免模糊本发明的内容，以下说明亦省略现有的原理、零组件、相关材料、及其相关处理技术。
以下结合所附图式说明本发明闸极结构的较佳制作实施例。
首先说明第一实施例，提供一基板。基板通常为砷化镓基板，但也可以是其他合适在上面制作闸极结构的任何其他半导体材料，譬如InP,GaN,Si,SiC,SiGe,GaSb,IV族,IV-IV族,III-V族,II-VI族。基板可以包含各种主动组件，譬如用来制作pHEMT、HEMT、MESFET、MOSFET的各种磊晶层等等。本实施例以制作一HEMT的闸极为例，步骤开始于一 已包含各磊晶层、源极S与汲极D的基板200。图2a为基板200的俯视图，图2b为图2a中沿A点至A’点的虚线的剖面示意图。基板200的表面包含突出于基板200表面的多个汲极D与多个源极S。
参考图3，形成一第一图案化光阻层310于基板200上。第一图案化光阻层310覆盖基板200的一部分。第一图案化光阻层310的图案决定后续所要形成闸极的位置。在此实施例中，闸极的位置较佳地默认在源极S与源极S之间且相对于汲极D较靠近源极S的侧壁Sw。如图3所示，在本实施例中，第一图案化光阻层310设计成覆盖所有的汲极D及源极S且留有开口320在其中一个汲极D及其中一个源极S之间用来制作闸极。第一图案化光阻层310特别包含光阻侧壁310s覆盖源极S的侧壁Sw，也同时包含光阻侧壁310d覆盖汲极D的侧壁Dw。可用现有的旋涂法与微影来形成第一图案化光阻层310。光阻厚度举例而言可为100至10,000埃的厚度。在某些实例中，第一图案化光阻层310的厚度若过大，可能形成过大的高宽比影响后续闸极金属的填入。
同时参考图3及图4，沿图3的结构200的表面共形地沉积一介电层410。具体地，介电层410覆盖基板200上方的未被第一图案化光阻层310覆盖的部分；介电层410也覆盖第一图案化光阻层310的顶部及侧壁，其包含覆盖光阻侧壁310s及310d。可使用电浆辅助化学气相沉积(PECVD)或原子层沉积(ALD)或其他CVD来形成介电层410，材料可为氧化硅(SiOx)或氧化氮(SiNx)或其他合适材料。介电层410的厚度取决于后续所要形成的闸极的闸极长度，根据本发明的制法，介电层410的厚度范围较佳在50埃～8000埃之间。
参考图5，形成间隙壁510d及510s在第一图案化光阻层310的侧壁上。利用非等向性蚀刻(干蚀刻)去除基板200表面上及第一图案化光阻层310顶部的介电层410，但保留覆盖第一图案化光阻层310的侧壁310d及310s的介电层410以形成间隙壁510d及510s，其中间隙壁510d邻近汲极D，间隙壁510s邻近源极S。如图所示，在此实施例中，间隙壁510s即为后续所要制作闸极的位置。图5a为间隙壁510s/510d的放大示意图，间隙壁510s/510d包含一弯曲部分511(可称为弯曲间隙壁bending spacer)于上方，及等齐部分522(可称为等齐间隙壁，uniform spacer)于下方。较佳地，弯曲部分511的高度与等齐部分522的高度比约为1：2。
以下说明利用间隙壁510s形成闸极开口的两个方法。图6a、7a及8a为第一方法；图6b、图6b’、图7b及8b为第二方法。闸极开口形成后可填入闸极绝缘层与闸极金属即完成闸极结构。
首先参考第一方法的图6a，形成一第二光阻层610于基板200上，第二光阻层610覆 盖第一图案化光阻层310与间隙壁510d及510s。可用现有的旋涂与微影方法平坦式地来形成第二光阻层610。第二光阻层610与第一图案化光阻层310可使用相同或不同的材料，较佳使用相同的材料有利用后续的一次移除。在优选实例中，为尽量使第二光阻层610形成平坦的上表面，第二光阻层610的高度可能需大些。
参考第一方法的图7a，去除一部分的第二光阻层610与一部分的该第一图案化光阻层310以露出间隙壁510d/510s的弯曲部分511。可用反应性离子蚀刻或任何其他合适的技术(如电浆灰化plasma asher)来进行此步骤。如前述所述，间隙壁510d/510s包含弯曲部分511及等齐部分522，控制此步骤的光阻去除量使其露出间隙壁510d/510s的弯曲部分511，而使等齐部分522保留在残留的第二光阻层610’与残留的第一图案化光阻层310’中。间隙壁510d/510s埋藏在残留光阻层610’与310’中的部分决定后续形成闸极根部外型。如果弯曲部分511没有全部露出而埋藏在残留光阻层610’与310’中，可能会使后续形成的闸极有狭窄脆弱的颈部。
参考第一方法的图8a，去除间隙壁510d及510s以形成开口811s及811d在残留的第二光阻层610’及残留的第一图案化光阻层310’中，开口811s定义闸极的底部尺寸，其中开口811s是邻近源极S。本发明提供开口在50埃～6000埃的各种实施例。可使用液相化学蚀刻来进行此步骤，譬如使用BOE/HF+H2O。开口811s及811d形成后，可用各种合适的方法沿开口811s及811d表面形成闸极绝缘层(非必要)并于闸极绝缘层上形成闸极导电层，以构成闸极结构。此外，图8a为去除间隙壁510d及510s后形成缺口部811r于基板200中的另一选择性步骤。在某些实例中，此步骤可用来去除基板200表面的披覆层。实施方法为以残留的第二光阻层610’及残留的第一图案化光阻层310’为屏蔽，蚀刻开口811s及811d底部基板200以形成缺口部811r露出基板200内部的磊晶层。举例而言，譬如将基板200表面的披覆层去除而露出肖特基阻障层。
以下说明利用间隙壁形成闸极开口的第二方法如图6b、7b及8b所示。延续图5及图5a，接着参考第二方法的图6b，完全去除第一图案化光阻层310，可用合适的蚀刻与显影制程完成此步骤。接着，参考第二方法的图7b形成一替代光阻层730于基板200表面上，控制替代光阻层730的厚度使其足以覆盖源极S、汲极D、或基板200上的其它主动区域，将间隙壁510d及510s的等齐部分522埋藏在替代光阻层733中且使间隙壁510d及510s的弯曲部分511露出。可使用任何合适的方式来形成替代光阻层730，以避免破坏间隙壁510d及510s并且可精准地控制替代光阻层730的厚度。举例而言，参考图6b’，可先形成平坦光阻层730’覆盖源极S、汲极D、基板200上的其它主动区域，及间隙壁510d及 510s所有部分，然后再回蚀平坦光阻层730’的一部分材料以使间隙壁510d及510s的弯曲部分511露出，间隙壁510d及510s的等齐部分522仍埋藏在平坦光阻层中，此经回蚀过的平坦光阻层730’即为替代光阻层733(如图7b)。可将合适光阻材料置于喷嘴(nozzle)，用蒸汽喷发(vapor spray)法形成平坦光阻层730’。注意间隙壁510d/510s埋藏在替代光阻层730中的部分决定后续形成闸极根部外型。如果弯曲部分511没有全部露出而埋藏在替代光阻层730中，会使后续形成的闸极有狭窄脆弱的颈部。
参考第二方法的图8b，去除间隙壁510d及510s以形成一开口811s及811d于替代光阻层730中，开口811s定义闸极的底部尺寸，其中开口811s是邻近源极S。本发明提供开口在50埃～6000埃的各种实施例。可使用液相化学蚀刻来进行此步骤，譬如使用BOE/HF+H2O。开口811s及811d形成后，可用各种合适的方法沿开口811s及811d表面形成闸极绝缘层(非必要)并于闸极绝缘层上形成闸极导电层，以构成闸极结构。此外，图8b为去除间隙壁510d及510s后形成缺口部811r于基板200中的另一选择性步骤。此步骤可参考前述在此不赘述。
可延续第一方法的图8a或第二方法的图8b进行闸极绝缘层的制作。图9的闸极绝缘层的制作步骤是延续第二方法的图8b。闸极绝缘层并非必要，可选择性为之。形成一共形绝缘层920覆盖开口811d/811s及替代光阻层730(若于第一方法则覆盖残留的第二光阻层610’及残留的第一光阻层310’)。在有形成缺口811r的实例中，共形绝缘层920也覆盖缺口811r。可使用电浆辅助化学气相沉积(PECVD)、其它CVD或原子层沉积(ALD)来完成此步骤。相较于上述各光阻层，绝缘层920为一较薄层。较佳而言，绝缘层920的厚度范围为50～2000埃，较佳材料可为高介电是数(high K)的绝缘材譬如HfOx,或AlOx或TiOx。
接着，同样参考图9，进行闸极导电层的制作。在共形绝缘层920形成之后，形成导电层930覆盖共形绝缘层920，并将开口811d/811s及缺口811r填满。可用溅镀或其他各向同性(isotropic)的沉积的方法来完成此步骤。导电层930的材料可为任何合适的金属或导电材。接着，同样参考图9，形成一第三图案化光阻940于导电层930上，第三图案化光阻940定义闸极的顶部形状。在此实施例中，闸极位于靠近源极的开口811s，因此第三图案化光阻940没有覆盖靠近汲极的开口811d。在形成T型闸极的实例中，可利用第三图案化光阻940来设计闸极的宽大头部，但本案不以T型闸极为限。形成第三图案化光阻940可用现有的旋涂法与微影。第三图案化光阻940可使用与前述替代光阻层730、第二光阻层610、或第一图案化光阻层310相同或不同的材料，较佳使用相同的材料有利用后续的一次移除。
接着，参考图9及图10，以第三图案化光阻940为屏蔽，去除一部分的导电层930以形成闸极导电层1010；可在相同步骤或不同步骤中以第三图案化光阻940为屏蔽，去除一部分的共形绝缘层920以形成闸极绝缘层1020。可使用湿式蚀刻或与干式电浆蚀刻来完成此步骤。注意此步骤也同时去除开口811d及缺口811r中的共形绝缘层920及导电层930。
参考图11，将第三图案化光阻940及替代光阻层730移除以显露出闸极1100于基板200上。图11为形成T型闸极的实施例，其具有较宽的顶部与较窄的根部。可用任何合适的方法，譬如液相蚀刻可用任何合适的光阻移除技术执行此步骤。在较佳的实例中，替代光阻层730(残留的第二光阻层610’(如图7a及图8a)、残留的第一图案光阻层310’(如图7a及图8a))及第三图案化光阻940可同时移除。
注意图11所示的闸极1100位于汲极D与源极S之间，相较于汲极D，闸极1100邻近源极S。此外，此实例提出一种闸极1100与汲极D之间有缺口811r的结构，缺口811r露出基板200内部的磊晶层，譬如肖特基阻障层。可经由适当设计使缺口811r位在空乏区边缘(depletion edge)，如此可缓和电流丛聚效应，以增加崩溃电压而不会降低或牺牲晶体管的截止频率(cut off frequency)及增益(gain)，如此可以增加功率放大器的效能。本发明包含另一实施例可在缺口811r沉积金属层但不以此作为闸极，而让此金属层呈现漂浮状态(floating)不与外面电性接通，此金属层可以调适表面空乏区的电场分布，以达到需要的崩溃电压及高截止频率及高增益。
参考图11提出一半导体结构，包含基板200，基板200具有汲极D、源极S与门极1100位于汲极D及源极S之间，其中基板200还包含基板表面200a，基板表面200a具有一缺口811r于汲极D与闸极S之间。基板200还包含磊晶结构，磊晶结构包含披覆层210，缺口811r形成在披覆层210中且露出披覆层210底下的肖特基阻障层220。注意基板表面200a还包含闸极开口(即前述开口811s)，闸极1100自闸极开口811s往上延伸。因为闸极开口811s与缺口811r在同一层且同一道制程形成，所以闸极开口811s与缺口811r具有实质上相同的深度。
图12及图13为闸极与汲极之间没有缺口的第二实施例的作法。图12为接续第二方法的图6b。参考图6b进一步地去除间隙壁510d以形成，如图12所示，只剩下间隙壁510s的结构。执行此步骤可利用合适的屏蔽盖住闸极S与汲极D及间隙壁510s，以液相蚀刻将间隙壁510d去除。然后再参考前述的图6b’、7b、8b、图9至图11等说明即可获得图13所示的闸极1300，其闸极1300与汲极D之间不存在缺口811r。
图14a、14b及14c为本发明第三实施例。第三实施例与第一实施例的差别在于第一 实施例的基板200(如图2b)其汲极D与源极S之间的基板表面是平坦的，所以间隙壁510d/510s是形成在平坦表面上；第三实施例的基板200’(如图14a)其汲极D与源极S之间有宽凹陷1400，间隙壁1412d/1412s是形成在宽凹陷1400的表面上。注意此宽凹陷主要是用来舒缓表面空乏区及表面电流丛聚效应，以增加崩溃电压，主要是提升高功率放大器的效能。
参考图14a，其包含具有各磊晶层、源极S与汲极D的基板200’，其中基板200’其汲极D与源极S之间有宽凹陷1400；基板200’上的第一图案化光阻层1410；及间隙壁1412d/1412s形成在宽凹陷1400的表面上。在此实施例中，基板200’表面可为披覆层210’，披覆层210’底下为肖特基阻障层220’。因此，宽凹陷1400的表面为披覆层210’。
形成图14a的结构的方法，包含先提供具有宽凹陷1400的基板200’，接着形成第一图案化光阻层1410使其侧壁落在宽凹陷1400的表面上。然后形成间隙壁1412d/1412s在宽凹陷1400的表面上。具体实施内容可参考前述第一实施例的图2a、图2b、图3至图5、及图5a。
形成图14a的结构后，可接着参考前述第一实施例的图6b、图7b、及图8b的方法，利用间隙壁1412d/1412s定义开口，形成如图14b所示的结构。如图所示，开口1416s及1416d于替代光阻层1415中，开口1416s邻近源极S并定义闸极的底部尺寸。开口1416d邻近汲极D。注意开口1416s及1416d可有一定的深度而露出肖特基阻障层220’。
形成图14b的结构后，可接着参考前述第一实施例的图9、图10、及图11的方法，形成如图14c所示的具有T型闸极1420的结构。如图14c所示提出一种半导体结构，包含基板200’，基板200’具有汲极D、源极S与门极1420位于汲极D及源极S之间，其中基板200’还包含基板表面200’a，基板表面200’a具有宽凹陷1400于汲极D与源极S之间及缺口(即前述的开口1416d形成于宽凹陷1400的底表面，其中缺口1416d位于闸极1420与汲极D之间。基板200’还包含磊晶结构，此磊晶结构包含披覆层210’，宽凹陷1400与缺口1416d形成在披覆层210’中，其中缺口1416d露出披覆层210’底下的肖特基阻障层220’。宽凹陷1400的底表面还包含闸极开口(即开口1416s)，闸极1420自闸极开口1416s往上延伸，闸极开口1416s与缺口1416d具有实质上相同的深度，因为他们在同一层且为同一道制程步骤形成。同时，如图12，第三实施例也可把缺口1416d拿掉。
图15a、15b及15c为本发明第四实施例。第四实施例与第三实施例的差别在于第三实施例的基板200’(如图14a)其汲极D与源极S之间有宽凹陷1400，间隙壁1412d/1412s是形成在宽凹陷1400的表面上；第四实施例的基板200”(如图15a)其汲极D与源极S之 间有宽凹陷1500及宽凹陷1500旁边的平台1501，邻近汲极D的间隙壁1512d形成在平台1501的表面上，邻近源极S的间隙壁1512s形成在宽凹陷1500的表面上。因此间隙壁1512d是站在比间隙壁1512s更高的位置。
参考图15a，其包含具有各磊晶层、源极S与汲极D的基板200”，其中基板200”其汲极D与源极S之间有宽凹陷1500及宽凹陷1500旁边的平台1501；基板200”上的第一图案化光阻层1510；及如前述邻近汲极D的间隙壁1512d形成在平台1501的表面上，邻近源极S的间隙壁1512s形成在宽凹陷1500的表面上。基板200”表面可为披覆层210”，披覆层210”底下为肖特基阻障层220”。注意在此实施例中，平台1501的表面为披覆层210”，宽凹陷1500的表面也是披覆层201”。形成图15a的结构的方法，包含首先提供具有宽凹陷1500及平台1501的基板200”，接着形成第一图案化光阻层1510，然后形成间隙壁1512d/1512s。具体实施方法可参考前述第一实施例的图2a、图2b、图3至图5、及图5a。
形成图15a的结构后，可接着参考前述第一实施例的图6b、图7b、及图8b的方法，利用间隙壁1512d/1512s定义闸极开口1516s及邻近汲极的开口1516d，形成如图15b所示的结构。如图所示，开口1516s及1416d形成于替代光阻层1515中，开口1516s定义闸极的底部尺寸。注意开口1516s有一定的深度而露出肖特基阻障层220”。开口1516d未露出肖特基阻障层220”只露出上方的披覆层210”。
形成图15b的结构后，可接着参考前述第一实施例的图9、图10、及图11的方法，形成如图15c所示的具由T型闸极1520的结构。如图15c所示提供一种半导体结构包含基板200”，基板”具有汲极D、源极S与门极1520位于汲极D及源极S之间，基板200”还包含基板表面200”a，基板表面200”a具有宽凹陷1500于汲极D与源极S之间且比较靠近源极S，及至少一个缺口(即前述的开口1516d)形成于宽凹陷1500与汲极D之间。基板200”还包含磊晶结构，磊晶结构包含披覆层210”，宽凹陷1500与缺口1516d形成在披覆层210”中。注意缺口1516d未露出披覆层210”底下的肖特基阻障层220”。宽凹陷1500的表面还包含闸极开口(即前述的开口1516s)，闸极1520自闸极开口1516s往上延伸。此缺口1516d可用以调适高功率放大器里晶体管的崩溃电压，同时又不会牺牲晶体管的截止频率及增益，而达到最佳的功率放大效能。图16为本发明多缺口的第五实施例，可参见以上介绍的内容实现本发明的此实施例。
图17a至图17d为本发明的第六实施例，为一种T型闸极的制造方法。如图17a所示，步骤开始于一已包含各磊晶层的基板1700。基板1700上包含突出于基板1700表面的多个 汲极D和多个源极S。汲极D与源极S之间有宽凹陷1700a。基板1700的表面还包含间隙壁1701及间隙壁1702于宽凹陷1700a的区域并较靠近源极S。间隙壁1701及间隙壁1702之间具有一开口1705露出基板1700于宽凹陷1700a的表面。开口1705的底部定义了T型闸极的闸极长度Lg。基板1700的表面还包含图案光阻层1703、紧邻该间隙壁1701、及间隙壁1702。图案光阻层1703覆盖基板1700大部分区域、汲极D与源极S，但未覆盖间隙壁1701、间隙壁1702及开口1705。可参考形成前述的图5结构的方法来制造图17a所述的结构。
注意在此实施例中，如图所示，间隙壁1701或间隙壁1702的较佳宽度w在0.05～0.2μm之间，间隙壁1701的外侧与间隙壁1702的外侧两者之间的距离L其较佳范围在0.25～0.7μm之间或更小如0.1～0.2μm之间。闸极长度Lg、间隙壁1701的外侧与间隙壁1702的外侧两者之间的距离L、及间隙壁1701或间隙壁1702的宽度w基本上符合以下算式：Lg＝L-2w。由此可知，适当地调整间隙壁的宽度w可以制作出符合所需的闸极长度Lg。
接着如图17b所示，形成一平坦光阻层1706覆盖图17a所示的结构，平坦光阻层1706同时填满开口1705。平坦光阻层1706的厚度较佳为0.3～2μm。注意图案光阻层1703不同于平坦光阻层1706，譬如图案光阻层1703可使用对光敏感程度与平坦光阻层1706不同的材料制成。
接着，参考图17c，利用光微影(optical lithography)来曝光显影该平坦光阻层1706使露出开口1705并于开口1705上方形成一更大的开口1707。如图所示，开口1707是由倾斜的光阻壁A1与A2所形成。
参考图17d，沉积金属导电材料于开口1705及开口1707中。可使用现有的方向性沉积(directional deposition)金属蒸镀法来完成此步骤。注意，如图所示，光阻壁A1及A2的倾斜方向将使所沉积的金属不会与光阻壁A1及A2紧密结合，有利于后续的光阻剥离。相对地，如图所示，间隙壁1701或间隙壁1702的倾斜方向将使所沉积的金属易与间隙壁1701或间隙壁1702紧密结合，有利于形成结构稳固的T型闸极。接着，以合适的方式，譬如液相蚀刻或显影方法，去除平坦光阻层1706及图案光阻层1703以形成如图17d所示的结构。
参考图17d，显示一半导体结构，包含基板1700，具有汲极D、源极S、与门极G位于汲极D及源极S之间。基板1700还包含一对间隙壁1701/1702紧邻闸极G，该对间隙壁1701/1702定义闸极G的闸极长度Lg。闸极G还包含一窄根部1710r以及宽头部1710h，该对间隙壁1701/1702与窄根部1710r位于同一平面上，该对间隙壁1701/1702紧邻窄根 部1710r，该对间隙壁1701/1701与窄根部1710r共同支撑宽头部1710h。基板1700还包含基板表面1700s，基板表面上的宽凹陷1700a于汲极D与源极S之间，该对间隙壁1701/1702与窄根部1710r是位于宽凹陷1700a中。
综上所述，本发明提供的上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (37)

  1. 一种闸极结构的形成方法，其特征在于，包含：
    形成第一图案化光阻层于基板上；
    形成间隙壁于所述第一图案化光阻层的侧壁上，其中所述间隙壁包含弯曲部分；
    去除所述第一图案化光阻层；
    形成替代光阻层于所述基板上，使所述间隙壁插在所述替代光阻层中而露出所述弯曲部分；以及
    去除所述间隙壁以形成开口于所述替代光阻层中，其中所述开口是定义闸极的底部尺寸。
  2. 如权利要求1所述的形成方法，其特征在于，还包含沿所述开口表面形成闸极绝缘层及于所述闸极绝源层上形成闸极导电层。
  3. 如权利要求1所述的形成方法，其特征在于，还包含：
    形成共形绝缘层覆盖所述开口及所述替代光阻层；
    形成导电层覆盖所述共形绝缘层；以及
    形成第三图案化光阻于所述导电层上，所述第三图案化光阻是定义所述闸极的顶部形状。
  4. 如权利要求3所述的形成方法，其特征在于，还包含：
    以所述第三图案化光阻为屏蔽，去除一部分的所述导电层以形成闸极导电层；及以所述第三图案化光阻为屏蔽，去除一部分的所述共形绝缘层以形成闸极绝缘层。
  5. 如权利要求4所述的形成方法，其特征在于，还包含：
    同时移除残留的第二光阻层及残留的所述第一图案化光阻层及所述第三图案化光阻以露出所述闸极于基板上。
  6. 如权利要求1所述的形成方法，其特征在于，其中所述基板包含至少一个汲极及至少一个源极突出于所述基板的表面，所述第一图案化光阻层覆盖所述汲极及所述源极，并且所述第一图案化光阻层具有侧壁是接近所述源极而远离所述汲极，所述侧壁介于所述 源极与所述汲极之间。
  7. 如权利要求2所述的形成方法，其特征在于，还包含于形成所述闸极绝缘层前，在所述开口的底部形成缺口以露出所述基板内部的磊晶层。
  8. 如权利要求2所述的形成方法，其特征在于，其中所述闸极为T型闸极。
  9. 如权利要求2所述的形成方法，其特征在于，其中所述开口的大小范围在50埃～6000埃。
  10. 一种闸极结构的形成方法，其特征在于，包含：
    形成第一图案化光阻层于基板上；
    形成间隙壁于所述第一图案化光阻层的侧壁上，其中所述间隙壁包含弯曲部分；
    形成第二光阻层于所述基板上，所述第二光阻层覆盖所述第一图案化光阻层与所述间隙壁；
    去除一部分的所述第二光阻层与一部分的第一光阻层以露出所述间隙壁的所述弯曲部分；以及
    去除所述间隙壁以形成开口于残留的所述第二光阻层及所述第一图案化光阻层中，其中所述开口是定义闸极的底部尺寸。
  11. 如权利要求10所述的形成方法，其特征在于，还包含沿所述开口表面形成闸极绝缘层及于所述闸极绝源层上形成闸极导电层。
  12. 如权利要求10所述的形成方法，其特征在于，还包含：
    形成共形绝缘层覆盖所述开口及所述残留的所述第二光阻层及所述残留的所述第一光阻层；
    形成导电层覆盖所述共形绝缘层；以及
    形成第三图案化光阻于所述导电层上，所述第三图案化光阻是定义所述闸极的顶部形状。
  13. 如权利要求12所述的形成方法，其特征在于，还包含：
    以所述第三图案化光阻为屏蔽，去除一部分的所述导电层以形成闸极导电层；及以所述第三图案化光阻为屏蔽，去除一部分的所述共形绝缘层以形成闸极绝缘层。
  14. 如权利要求13所述的形成方法，其特征在于，还包含：
    同时移除残留的所述第二光阻层及残留的所述第一图案化光阻层及所述第三图案化光阻以露出所述闸极于基板上。
  15. 如权利要求10所述的形成方法，其特征在于，其中所述基板包含至少一个汲极及至少一个源极突出于所述基板的表面，所述第一图案化光阻层覆盖所述汲极及所述源极，并且所述间隙壁介于所述源极与所述汲极之间。
  16. 如权利要求15所述的形成方法，其特征在于，还包含于形成所述闸极绝缘层前，在所述开口的底部形成缺口以露出所述基板内部的磊晶层，所述缺口是介于所述闸极与所述汲极之间。
  17. 如权利要求11所述的形成方法，其特征在于，其中所述闸极为T型闸极。
  18. 如权利要求11所述的形成方法，其特征在于，其中所述开口的大小范围在50埃～6000埃。
  19. 一种半导体结构，其特征在于，包含：
    基板，所述基板具有汲极、源极及闸极位于所述汲极及所述源极之间，其中所述基板还包含基板表面，所述基板表面具有缺口于所述汲极与所述闸极之间。
  20. 如权利要求19所述的半导体结构，其特征在于，其中所述基板还包含磊晶结构，所述磊晶结构包含披覆层，所述缺口是形成在所述披覆层中且露出所述披覆层底下的肖特基阻障层。
  21. 如权利要求19所述的半导体结构，其特征在于，其中所述基板表面还包含闸极 开口，所述闸极自所述闸极开口往上延伸，所述闸极开口与所述缺口具有实质上相同的深度。
  22. 如权利要求19所述的半导体结构，其特征在于，其中所述闸极为T型闸极。
  23. 一种半导体结构，其特征在于，包含：
    基板，所述基板具有汲极、源极及闸极位于所述汲极及所述源极之间，其中所述基板还包含基板表面，所述基板表面具有宽凹陷于所述汲极与所述源极之间及缺口形成于所述宽凹陷的底表面，其中所述缺口位于所述闸极与所述汲极之间。
  24. 如权利要求23所述的半导体结构，其特征在于，其中所述基板还包含磊晶结构，所述磊晶结构包含披覆层，所述宽凹陷与所述缺口是形成在所述披覆层中，其中所述缺口露出所述披覆层底下的肖特基阻障层。
  25. 如权利要求23所述的半导体结构，其特征在于，其中所述宽凹陷的底表面还包含闸极开口，所述闸极自所述闸极开口往上延伸，所述闸极开口与所述缺口具有实质上相同的深度。
  26. 如权利要求23所述的半导体结构，其中所述闸极为T型闸极。
  27. 一种半导体结构，其特征在于，包含：
    基板，所述基板具有汲极、源极及闸极位于所述汲极及所述源极之间，其中所述基板还包含基板表面，所述基板表面具有宽凹陷于所述汲极与所述源极之间及至少一个缺口形成于所述宽凹陷与所述汲极之间。
  28. 如权利要求27所述的半导体结构，其特征在于，其中所述基板还包含磊晶结构，所述磊晶结构包含披覆层，所述宽凹陷与所述缺口是形成在所述披覆层中。
  29. 如权利要求27所述的半导体结构，其特征在于，其中所述缺口未露出所述披覆层底下的肖特基阻障层。
  30. 如权利要求27所述的半导体结构，其特征在于，其中所述宽凹陷的表面还包含闸极开口，所述闸极自所述闸极开口往上延伸。
  31. 如权利要求27所述的半导体结构，其特征在于，其中所述闸极为T型闸极。
  32. 如权利要求27所述的半导体结构，其特征在于，其中所述缺口有多个。
  33. 一种半导体结构，其特征在于，包含：
    基板，所述基板具有汲极、源极及闸极位于所述汲极及所述源极之间，其中所述基板还包含对间隙壁紧邻所述闸极，所述对间隙壁是定义所述闸极的闸极长度。
  34. 如权利要求33所述的半导体结构，其特征在于，其中所述闸极还包含窄根部以及宽头部，对间隙壁与所述窄根部位于同一平面上，所述对间隙壁紧邻所述窄根部，所述对间隙壁与所述窄根部共同支撑所述宽头部。
  35. 如权利要求33所述的半导体结构，其特征在于，所述基板还包含基板表面，所述基板表面具有宽凹陷于所述汲极与所述源极的之间，所述对间隙壁与所述窄根部是位于所述宽凹陷中。
  36. 如权利要求33所述的半导体结构，其特征在于，其中所述对间隙壁的各自宽度在0.05～0.2μm之间。
  37. 如权利要求33所述的半导体结构，其特征在于，其中所述对的一个间隙壁的外侧与另一个间隙壁的外侧两者之间的距离在0.25～0.7μm之间或0.1～0.2μm之间。
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CN101022129A (zh) * 2007-03-26 2007-08-22 电子科技大学 源漏双凹结构的金属半导体场效应晶体管
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US20110180850A1 (en) * 2010-01-25 2011-07-28 Ishiang Shih Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits
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US20060220065A1 (en) * 2005-03-31 2006-10-05 Eudyna Devices Inc. Semiconductor device and fabrication method therefor
CN101542685A (zh) * 2006-11-29 2009-09-23 美光科技公司 减小半导体装置的临界尺寸的方法和具有减小的临界尺寸的部分制造的半导体装置
CN101022129A (zh) * 2007-03-26 2007-08-22 电子科技大学 源漏双凹结构的金属半导体场效应晶体管
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CN104851788A (zh) * 2015-04-28 2015-08-19 厦门市三安集成电路有限公司 一种砷化镓基晶体管的t型栅的制作方法

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