WO2019080211A1 - Drive compensation circuit and data drive apparatus - Google Patents

Drive compensation circuit and data drive apparatus

Info

Publication number
WO2019080211A1
WO2019080211A1 PCT/CN2017/111259 CN2017111259W WO2019080211A1 WO 2019080211 A1 WO2019080211 A1 WO 2019080211A1 CN 2017111259 W CN2017111259 W CN 2017111259W WO 2019080211 A1 WO2019080211 A1 WO 2019080211A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
signal
compensation
temporary storage
storage unit
Prior art date
Application number
PCT/CN2017/111259
Other languages
French (fr)
Chinese (zh)
Inventor
王振岭
黄泰钧
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/576,863 priority Critical patent/US10242631B1/en
Priority to EP17929435.0A priority patent/EP3703043A4/en
Priority to JP2020511500A priority patent/JP2020531915A/en
Priority to KR1020207014543A priority patent/KR102365389B1/en
Publication of WO2019080211A1 publication Critical patent/WO2019080211A1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a driving compensation circuit and a data driving device.
  • FIG. 1 shows a data driving circuit in the prior art.
  • the data driving voltage is supplied to the data line, in order to realize the compensation of the Vth of the transistor T1, it is necessary to provide the transistor T1 with two different data voltages.
  • Some data drive chip MINI The frequency of the LVDS is balanced.
  • the present invention provides a driving compensation circuit, including: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
  • the first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
  • the first temporary storage unit is configured to acquire and store a first compensation signal
  • the second temporary storage unit is configured to acquire and store a second compensation signal
  • the gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or
  • the second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit
  • the analog signal is amplified by a preset multiple and sent to the data driving circuit for compensation; the amplifying unit is an analog buffer amplifier, and the gating unit is a strobe switch chip.
  • the first temporary storage unit includes a first receiver, a first shift register, and a first data register, the first receiver, the first shift register, and the first The data registers are connected in sequence.
  • the second temporary storage unit includes a second receiver, a second shift register, and a second data register, the second receiver, the second shift register, and the second The data registers are connected in sequence.
  • the first receiver and the second receiver are both Mini-LVDS receivers.
  • a frame memory is further included, and the frame memory stores the first compensation signal or the second compensation signal.
  • the first data register has a first control port for accessing the first control signal STB1; and the second data register has a second control port for receiving Into the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
  • the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion
  • the unit and the amplifying unit process and transmit to the data line;
  • the second control signal STB2 When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
  • the present invention also provides a driving compensation circuit, comprising: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
  • the first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
  • the first temporary storage unit is configured to acquire and store a first compensation signal
  • the second temporary storage unit is configured to acquire and store a second compensation signal
  • the gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or
  • the second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit
  • the analog signal is amplified by a preset multiple and sent to the data drive circuit for compensation.
  • the first temporary storage unit includes a first receiver, a first shift register, and a first data register, the first receiver, the first shift register, and the first The data registers are connected in sequence.
  • the second temporary storage unit includes a second receiver, a second shift register, and a second data register, the second receiver, the second shift register, and the second The data registers are connected in sequence.
  • the first receiver and the second receiver are both Mini-LVDS receivers.
  • a frame memory is further included, and the frame memory stores the first compensation signal or the second compensation signal.
  • the first data register has a first control port for accessing the first control signal STB1; and the second data register has a second control port for receiving Into the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
  • the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion
  • the unit and the amplifying unit process and transmit to the data line;
  • the second control signal STB2 When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
  • An embodiment of the present invention further provides a data driving apparatus, including a data driving unit and a driving compensation circuit, wherein the data driving unit and the driving compensation circuit are both connected to a data line;
  • the driving compensation circuit includes: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
  • the first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
  • the first temporary storage unit is configured to acquire and store a first compensation signal
  • the second temporary storage unit is configured to acquire and store a second compensation signal
  • the gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or
  • the second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit
  • the analog signal is amplified by a preset multiple and sent to the data drive circuit for compensation.
  • the first temporary storage unit includes a first receiver, a first shift register, and a first data register, the first receiver, the first shift register, and the first The data registers are connected in sequence.
  • the second temporary storage unit includes a second receiver, a second shift register, and a second data register, the second receiver, the second shift register, and the second The data registers are connected in sequence.
  • the first receiver and the second receiver are both Mini-LVDS receivers.
  • a frame memory is further included, and the frame memory stores the first compensation signal or the second compensation signal.
  • the first data register has a first control port for accessing the first control signal STB1; and the second data register has a second control port for receiving Into the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
  • the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion
  • the unit and the amplifying unit process and transmit to the data line;
  • the second control signal STB2 When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
  • Embodiments of the present invention have the beneficial effect of effectively compensating the driving voltage of the data driving unit.
  • FIG. 1 is a schematic structural view of a data line driving circuit in the prior art.
  • FIG. 2 is a circuit schematic diagram of a drive compensation circuit in a preferred embodiment of the present invention.
  • FIG. 3 is a detailed circuit schematic diagram of a drive compensation circuit in a preferred embodiment of the present invention.
  • Figure 4 is a timing diagram of signals in an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a driving compensation circuit according to a preferred embodiment of the present invention.
  • the driving compensation circuit includes a first temporary storage unit 10, a second temporary storage unit 20, a gate unit 30, an electric displacement converter 40, a digital-to-analog conversion unit 50, and an amplification unit 60.
  • the first temporary storage unit 20 and the second temporary storage unit 30 are respectively connected to the gate unit 30, and the gate unit 30, the electric displacement converter 40, the digital-to-analog conversion unit 50, and the amplification unit 60 are sequentially connected.
  • the first temporary storage unit 10 is configured to acquire and store the first compensation signal.
  • the second temporary storage unit 20 is configured to acquire and store a second compensation signal.
  • the strobe unit 30 is configured to selectively connect the first temporary storage unit 10 or the second temporary storage unit 20 with the electric displacement converter 40, and the potential transfer unit 40 sets the first compensation signal or the second compensation.
  • the signal processing is sent to the digital-to-analog conversion unit 50, and the digital-to-analog conversion unit 50 converts the corresponding analog signal into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplification unit 60 amplifies the analog signal by a preset multiple and sends it to the data driving circuit. Compensation, the data driving circuit outputs the compensated driving voltage signal to the data line.
  • the potential shifter 40 is configured to process the first compensation signal or the second compensation signal and send it to the digital-to-analog conversion unit 50. For example, if the voltage of the first compensation signal or the second compensation signal is 3.3V, the potential shifter further boosts 3.3V to a voltage of 5V required by the digital-to-analog conversion unit 50.
  • the amplifying unit 60 is an analog buffer amplifier to enhance the driving capability of the output.
  • the digital to analog conversion unit 50 is a conventional miniature digital to analog converter.
  • the gating unit 30 is a gating switch chip.
  • the first temporary storage unit 10 includes a first receiver 11, a first shift register 12, and a first data register 13, a first receiver 11, and a first shift register 12. And the first data register 13 is sequentially connected.
  • the second temporary storage unit 20 includes a second receiver 21, a second shift register 22, and a second data register 23, and the second receiver 21, the second shift register 22, and the second data register 23 are sequentially connected. .
  • the first receiver 11 and the second receiver 12 are both Mini-LVDS receivers.
  • the drive compensation circuit further includes a frame memory that stores the first compensation signal or the second compensation signal.
  • first data register 13 has a first control port for accessing the first control signal STB1;
  • second data register 23 has a second control port for accessing the second control signal STB2;
  • the pass unit 30 has a third control port for accessing the third control signal DS;
  • the first compensation signal in the frame memory is started to be read into the first shift register 12, and when the first control signal STB1 is at a rising edge, the first compensation is performed.
  • the signal is output to the first data register 13.
  • the first compensation signal in the first data register 13 is passed through the electric displacement converter 40, the digital-to-analog conversion unit 50, and the amplification.
  • Unit 60 processes and transmits to the data line.
  • the second compensation signal is stored in the second data register 23, when the third control signal DS is low level and the second control signal STB2 is falling edge, The second compensation signal is transmitted to the data line.
  • the first control signal STB1, the second control signal STB2, and the third control signal DS are square wave signals, and the timing relationship thereof is as shown in FIG.
  • the embodiment of the invention further provides a data driving device, comprising a data driving unit and a driving compensation circuit, wherein the data driving unit is electrically connected to the driving compensation circuit, and the data driving unit is connected to the data line.
  • the drive compensation circuit is the drive compensation circuit in the above embodiment.

Abstract

Disclosed in the present invention is a drive compensation circuit, comprising: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit and an amplification unit; the first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, while the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplification unit are connected in sequence.

Description

一种驱动补偿电路及数据驱动装置 Driving compensation circuit and data driving device 技术领域Technical field
本发明涉及液晶显示领域，特别是涉及一种驱动补偿电路及数据驱动装置。The present invention relates to the field of liquid crystal display, and in particular to a driving compensation circuit and a data driving device.
背景技术Background technique
请参照图1，图1现有技术中的数据驱动电路，其在给数据线提供数据驱动电压时，为了实现对于晶体管T1的Vth的补偿，需要给晶体管T1提供两次不同的数据电压，现有的数据驱动芯片的MINI LVDS的频率交底，若要满足对晶体管T1的Vth的补偿，需要通过先降低帧率后，再提供MINI CLK的方法进行补偿。这样的方法不能满足量产的需求。Please refer to FIG. 1. FIG. 1 shows a data driving circuit in the prior art. When the data driving voltage is supplied to the data line, in order to realize the compensation of the Vth of the transistor T1, it is necessary to provide the transistor T1 with two different data voltages. Some data drive chip MINI The frequency of the LVDS is balanced. To compensate for the Vth of the transistor T1, it is necessary to compensate by providing the MINI CLK by first reducing the frame rate. Such an approach cannot meet the needs of mass production.
因此，现有技术存在缺陷，急需改进。Therefore, the prior art has drawbacks and is in urgent need of improvement.
技术问题technical problem
本发明的目的在于提供一种驱动补偿电路及数据驱动装置，具有对数据驱动单元的驱动电压进行有效补偿的有益效果。It is an object of the present invention to provide a drive compensation circuit and a data drive device that have the beneficial effect of effectively compensating the drive voltage of the data drive unit.
技术解决方案Technical solution
为解决上述问题，本发明提供的技术方案如下：In order to solve the above problems, the technical solution provided by the present invention is as follows:
本发明提供一种驱动补偿电路，包括：第一暂存单元、第二暂存单元、选通单元、电位移转器、数模转换单元以及放大单元；The present invention provides a driving compensation circuit, including: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
所述第一暂存单元以及所述第二暂存单元分别与所述选通单元连接，所述选通单元、所述电位移转器、所述数模转换单元以及所述放大单元依次连接；The first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
所述第一暂存单元用于获取并存储第一补偿信号；The first temporary storage unit is configured to acquire and store a first compensation signal;
所述第二暂存单元用于获取并存储第二补偿信号；The second temporary storage unit is configured to acquire and store a second compensation signal;
所述选通单元用于选择性地将所述第一暂存单元或所述第二暂存单元与所述电位移转器接通，所述电位转移器将所述第一补偿信号或所述第二补偿信号处理后发送给所述数模转换单元，所述数模转换单元根据所述第一补偿信号或所述第二补偿信号转换成对应的模拟信号，所述放大单元将所述模拟信号放大预设倍数后发送给数据驱动电路进行补偿；所述放大单元为模拟缓冲放大器，所述选通单元为选通开关芯片。The gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or The second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit The analog signal is amplified by a preset multiple and sent to the data driving circuit for compensation; the amplifying unit is an analog buffer amplifier, and the gating unit is a strobe switch chip.
在本发明的驱动补偿电路中，所述第一暂存单元包括第一接收器、第一移位寄存器以及第一数据暂存器，所述第一接收器、第一移位寄存器以及第一数据暂存器依次连接。In the driving compensation circuit of the present invention, the first temporary storage unit includes a first receiver, a first shift register, and a first data register, the first receiver, the first shift register, and the first The data registers are connected in sequence.
在本发明的驱动补偿电路中，所述第二暂存单元包括第二接收器、第二移位寄存器以及第二数据暂存器，所述第二接收器、第二移位寄存器以及第二数据暂存器依次连接。In the driving compensation circuit of the present invention, the second temporary storage unit includes a second receiver, a second shift register, and a second data register, the second receiver, the second shift register, and the second The data registers are connected in sequence.
在本发明的驱动补偿电路中，所述第一接收器以及所述第二接收器均为Mini-LVDS接收器。In the drive compensation circuit of the present invention, the first receiver and the second receiver are both Mini-LVDS receivers.
在本发明的驱动补偿电路中，还包括一帧存储器，所述帧存储器存储有所述第一补偿信号或所述第二补偿信号。In the driving compensation circuit of the present invention, a frame memory is further included, and the frame memory stores the first compensation signal or the second compensation signal.
在本发明的驱动补偿电路中，所述第一数据暂存器具有第一控制端口，用于接入第一控制信号STB1；所述第二数据暂存器具有第二控制端口，用于接入第二控制信号STB2；所述选通单元具有第三控制端口，用于接入第三控制信号DS；In the driving compensation circuit of the present invention, the first data register has a first control port for accessing the first control signal STB1; and the second data register has a second control port for receiving Into the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
当所述第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器中，当所述第一控制信号STB1处于上升沿时，将所述第一补偿信号输出到所述第一数据暂存器中；When the third control signal DS is at a low level, starting to read the first compensation signal in the frame memory into the first shift register, when the first control signal STB1 is at a rising edge, The first compensation signal is output to the first data register;
当所述第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将所述第一数据暂存器中的第一补偿信号经过所述电位移转器、数模转换单元以及放大单元处理后传输给数据线；When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion The unit and the amplifying unit process and transmit to the data line;
当所述第二控制信号STB2处于上升沿时，将所述第二补偿信号存入所述第二数据暂存器中，当所述第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把所述第二补偿信号传输给数据线。When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
本发明还提供一种驱动补偿电路，包括：第一暂存单元、第二暂存单元、选通单元、电位移转器、数模转换单元以及放大单元；The present invention also provides a driving compensation circuit, comprising: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
所述第一暂存单元以及所述第二暂存单元分别与所述选通单元连接，所述选通单元、所述电位移转器、所述数模转换单元以及所述放大单元依次连接；The first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
所述第一暂存单元用于获取并存储第一补偿信号；The first temporary storage unit is configured to acquire and store a first compensation signal;
所述第二暂存单元用于获取并存储第二补偿信号；The second temporary storage unit is configured to acquire and store a second compensation signal;
所述选通单元用于选择性地将所述第一暂存单元或所述第二暂存单元与所述电位移转器接通，所述电位转移器将所述第一补偿信号或所述第二补偿信号处理后发送给所述数模转换单元，所述数模转换单元根据所述第一补偿信号或所述第二补偿信号转换成对应的模拟信号，所述放大单元将所述模拟信号放大预设倍数后发送给数据驱动电路进行补偿。The gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or The second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit The analog signal is amplified by a preset multiple and sent to the data drive circuit for compensation.
在本发明的驱动补偿电路中，所述第一暂存单元包括第一接收器、第一移位寄存器以及第一数据暂存器，所述第一接收器、第一移位寄存器以及第一数据暂存器依次连接。In the driving compensation circuit of the present invention, the first temporary storage unit includes a first receiver, a first shift register, and a first data register, the first receiver, the first shift register, and the first The data registers are connected in sequence.
在本发明的驱动补偿电路中，所述第二暂存单元包括第二接收器、第二移位寄存器以及第二数据暂存器，所述第二接收器、第二移位寄存器以及第二数据暂存器依次连接。In the driving compensation circuit of the present invention, the second temporary storage unit includes a second receiver, a second shift register, and a second data register, the second receiver, the second shift register, and the second The data registers are connected in sequence.
在本发明的驱动补偿电路中，所述第一接收器以及所述第二接收器均为Mini-LVDS接收器。In the drive compensation circuit of the present invention, the first receiver and the second receiver are both Mini-LVDS receivers.
在本发明的驱动补偿电路中，还包括一帧存储器，所述帧存储器存储有所述第一补偿信号或所述第二补偿信号。In the driving compensation circuit of the present invention, a frame memory is further included, and the frame memory stores the first compensation signal or the second compensation signal.
在本发明的驱动补偿电路中，所述第一数据暂存器具有第一控制端口，用于接入第一控制信号STB1；所述第二数据暂存器具有第二控制端口，用于接入第二控制信号STB2；所述选通单元具有第三控制端口，用于接入第三控制信号DS；In the driving compensation circuit of the present invention, the first data register has a first control port for accessing the first control signal STB1; and the second data register has a second control port for receiving Into the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
当所述第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器中，当所述第一控制信号STB1处于上升沿时，将所述第一补偿信号输出到所述第一数据暂存器中；When the third control signal DS is at a low level, starting to read the first compensation signal in the frame memory into the first shift register, when the first control signal STB1 is at a rising edge, The first compensation signal is output to the first data register;
当所述第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将所述第一数据暂存器中的第一补偿信号经过所述电位移转器、数模转换单元以及放大单元处理后传输给数据线；When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion The unit and the amplifying unit process and transmit to the data line;
当所述第二控制信号STB2处于上升沿时，将所述第二补偿信号存入所述第二数据暂存器中，当所述第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把所述第二补偿信号传输给数据线。When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
本发明实施例还提供了一种数据驱动装置，包括数据驱动单元以及驱动补偿电路，所述数据驱动单元以及所述驱动补偿电路均与数据线连接；An embodiment of the present invention further provides a data driving apparatus, including a data driving unit and a driving compensation circuit, wherein the data driving unit and the driving compensation circuit are both connected to a data line;
所述驱动补偿电路包括：第一暂存单元、第二暂存单元、选通单元、电位移转器、数模转换单元以及放大单元；The driving compensation circuit includes: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
所述第一暂存单元以及所述第二暂存单元分别与所述选通单元连接，所述选通单元、所述电位移转器、所述数模转换单元以及所述放大单元依次连接；The first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
所述第一暂存单元用于获取并存储第一补偿信号；The first temporary storage unit is configured to acquire and store a first compensation signal;
所述第二暂存单元用于获取并存储第二补偿信号；The second temporary storage unit is configured to acquire and store a second compensation signal;
所述选通单元用于选择性地将所述第一暂存单元或所述第二暂存单元与所述电位移转器接通，所述电位转移器将所述第一补偿信号或所述第二补偿信号处理后发送给所述数模转换单元，所述数模转换单元根据所述第一补偿信号或所述第二补偿信号转换成对应的模拟信号，所述放大单元将所述模拟信号放大预设倍数后发送给数据驱动电路进行补偿。The gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or The second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit The analog signal is amplified by a preset multiple and sent to the data drive circuit for compensation.
在本发明的数据驱动装置中，所述第一暂存单元包括第一接收器、第一移位寄存器以及第一数据暂存器，所述第一接收器、第一移位寄存器以及第一数据暂存器依次连接。In the data driving apparatus of the present invention, the first temporary storage unit includes a first receiver, a first shift register, and a first data register, the first receiver, the first shift register, and the first The data registers are connected in sequence.
在本发明的数据驱动装置中，所述第二暂存单元包括第二接收器、第二移位寄存器以及第二数据暂存器，所述第二接收器、第二移位寄存器以及第二数据暂存器依次连接。In the data driving apparatus of the present invention, the second temporary storage unit includes a second receiver, a second shift register, and a second data register, the second receiver, the second shift register, and the second The data registers are connected in sequence.
在本发明的数据驱动装置中，所述第一接收器以及所述第二接收器均为Mini-LVDS接收器。In the data driving device of the present invention, the first receiver and the second receiver are both Mini-LVDS receivers.
在本发明的数据驱动装置中，还包括一帧存储器，所述帧存储器存储有所述第一补偿信号或所述第二补偿信号。In the data driving device of the present invention, a frame memory is further included, and the frame memory stores the first compensation signal or the second compensation signal.
在本发明的数据驱动装置中，所述第一数据暂存器具有第一控制端口，用于接入第一控制信号STB1；所述第二数据暂存器具有第二控制端口，用于接入第二控制信号STB2；所述选通单元具有第三控制端口，用于接入第三控制信号DS；In the data driving apparatus of the present invention, the first data register has a first control port for accessing the first control signal STB1; and the second data register has a second control port for receiving Into the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
当所述第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器中，当所述第一控制信号STB1处于上升沿时，将所述第一补偿信号输出到所述第一数据暂存器中；When the third control signal DS is at a low level, starting to read the first compensation signal in the frame memory into the first shift register, when the first control signal STB1 is at a rising edge, The first compensation signal is output to the first data register;
当所述第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将所述第一数据暂存器中的第一补偿信号经过所述电位移转器、数模转换单元以及放大单元处理后传输给数据线；When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion The unit and the amplifying unit process and transmit to the data line;
当所述第二控制信号STB2处于上升沿时，将所述第二补偿信号存入所述第二数据暂存器中，当所述第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把所述第二补偿信号传输给数据线。When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
有益效果 Beneficial effect
本发明实施例具有对数据驱动单元的驱动电压进行有效补偿的有益效果。Embodiments of the present invention have the beneficial effect of effectively compensating the driving voltage of the data driving unit.
附图说明DRAWINGS
图1是现有技术中的数据线驱动电路的结构示意图。1 is a schematic structural view of a data line driving circuit in the prior art.
图2是本发明一优选实施例中的驱动补偿电路的电路原理图。2 is a circuit schematic diagram of a drive compensation circuit in a preferred embodiment of the present invention.
图3是本发明一优选实施例中的驱动补偿电路的详细电路原理图。3 is a detailed circuit schematic diagram of a drive compensation circuit in a preferred embodiment of the present invention.
图4是本发明实施例中的信号时序图。Figure 4 is a timing diagram of signals in an embodiment of the present invention.
本发明的最佳实施方式BEST MODE FOR CARRYING OUT THE INVENTION
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. The directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc., are merely references. Attach the direction of the drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.
在图中，结构相似的模块是以相同标号表示。In the figures, structurally similar modules are denoted by the same reference numerals.
请参照图2，图2是本发明一优选实施例中驱动补偿电路的结构示意图。该驱动补偿电路包括：第一暂存单元10、第二暂存单元20、选通单元30、电位移转器40、数模转换单元50以及放大单元60。其中，第一暂存单元20以及第二暂存单元30分别与选通单元30连接，选通单元30、电位移转器40、数模转换单元50以及放大单元60依次连接。Please refer to FIG. 2. FIG. 2 is a schematic structural diagram of a driving compensation circuit according to a preferred embodiment of the present invention. The driving compensation circuit includes a first temporary storage unit 10, a second temporary storage unit 20, a gate unit 30, an electric displacement converter 40, a digital-to-analog conversion unit 50, and an amplification unit 60. The first temporary storage unit 20 and the second temporary storage unit 30 are respectively connected to the gate unit 30, and the gate unit 30, the electric displacement converter 40, the digital-to-analog conversion unit 50, and the amplification unit 60 are sequentially connected.
其中，该第一暂存单元10用于获取并存储第一补偿信号。The first temporary storage unit 10 is configured to acquire and store the first compensation signal.
其中，该第二暂存单元20用于获取并存储第二补偿信号。The second temporary storage unit 20 is configured to acquire and store a second compensation signal.
其中，该选通单元30用于选择性地将第一暂存单元10或第二暂存单元20与电位移转器40接通，电位转移器40将第一补偿信号或所述第二补偿信号处理后发送给数模转换单元50，数模转换单元50根据第一补偿信号或第二补偿信号转换成对应的模拟信号，放大单元60将模拟信号放大预设倍数后发送给数据驱动电路进行补偿，数据驱动电路将补偿后的驱动电压信号输出给数据线。The strobe unit 30 is configured to selectively connect the first temporary storage unit 10 or the second temporary storage unit 20 with the electric displacement converter 40, and the potential transfer unit 40 sets the first compensation signal or the second compensation. The signal processing is sent to the digital-to-analog conversion unit 50, and the digital-to-analog conversion unit 50 converts the corresponding analog signal into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplification unit 60 amplifies the analog signal by a preset multiple and sends it to the data driving circuit. Compensation, the data driving circuit outputs the compensated driving voltage signal to the data line.
该电位转移器40用于将第一补偿信号或所述第二补偿信号处理后发送给数模转换单元50。例如，所述第一补偿信号或所述第二补偿信号的电压为3.3V，则该电位转移器将3.3V进一步提升至数模转换单元50需要的电压5V。The potential shifter 40 is configured to process the first compensation signal or the second compensation signal and send it to the digital-to-analog conversion unit 50. For example, if the voltage of the first compensation signal or the second compensation signal is 3.3V, the potential shifter further boosts 3.3V to a voltage of 5V required by the digital-to-analog conversion unit 50.
该放大单元60为模拟缓冲放大器，以增强输出的驱动能力。The amplifying unit 60 is an analog buffer amplifier to enhance the driving capability of the output.
该数模转换单元50为常规的微型的数模转换器。The digital to analog conversion unit 50 is a conventional miniature digital to analog converter.
该选通单元30为选通开关芯片。The gating unit 30 is a gating switch chip.
具体地，请同时参照图3，该第一暂存单元10包括第一接收器11、第一移位寄存器12以及第一数据暂存器13，第一接收器11、第一移位寄存器12以及第一数据暂存器13依次连接。Specifically, referring to FIG. 3, the first temporary storage unit 10 includes a first receiver 11, a first shift register 12, and a first data register 13, a first receiver 11, and a first shift register 12. And the first data register 13 is sequentially connected.
第二暂存单元20包括第二接收器21、第二移位寄存器22以及第二数据暂存器23，第二接收器21、第二移位寄存器22以及第二数据暂存器23依次连接。The second temporary storage unit 20 includes a second receiver 21, a second shift register 22, and a second data register 23, and the second receiver 21, the second shift register 22, and the second data register 23 are sequentially connected. .
第一接收器11以及第二接收器12均为Mini-LVDS接收器。The first receiver 11 and the second receiver 12 are both Mini-LVDS receivers.
在一些实施例中，驱动补偿电路还包括一帧存储器，帧存储器存储有所述第一补偿信号或所述第二补偿信号。In some embodiments, the drive compensation circuit further includes a frame memory that stores the first compensation signal or the second compensation signal.
进一步地，第一数据暂存器13具有第一控制端口，用于接入第一控制信号STB1；第二数据暂存器23具有第二控制端口，用于接入第二控制信号STB2；选通单元30具有第三控制端口，用于接入第三控制信号DS；Further, the first data register 13 has a first control port for accessing the first control signal STB1; the second data register 23 has a second control port for accessing the second control signal STB2; The pass unit 30 has a third control port for accessing the third control signal DS;
当第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器12中，当第一控制信号STB1处于上升沿时，将第一补偿信号输出到所述第一数据暂存器13中。When the third control signal DS is at a low level, the first compensation signal in the frame memory is started to be read into the first shift register 12, and when the first control signal STB1 is at a rising edge, the first compensation is performed. The signal is output to the first data register 13.
当第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将第一数据暂存器13中的第一补偿信号经过电位移转器40、数模转换单元50以及放大单元60处理后传输给数据线。When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register 13 is passed through the electric displacement converter 40, the digital-to-analog conversion unit 50, and the amplification. Unit 60 processes and transmits to the data line.
当第二控制信号STB2处于上升沿时，将第二补偿信号存入第二数据暂存器23中，当第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把第二补偿信号传输给数据线。When the second control signal STB2 is at the rising edge, the second compensation signal is stored in the second data register 23, when the third control signal DS is low level and the second control signal STB2 is falling edge, The second compensation signal is transmitted to the data line.
在该实施例中，该第一控制信号STB1、第二控制信号STB2、第三控制信号DS均为方波信号，其时序关系如图3所示。In this embodiment, the first control signal STB1, the second control signal STB2, and the third control signal DS are square wave signals, and the timing relationship thereof is as shown in FIG.
本发明实施例还提供了一种数据驱动装置，包括数据驱动单元以及驱动补偿电路，所述数据驱动单元与所述驱动补偿电路均电连接，数据驱动单元与数据线连接。该驱动补偿电路为上述实施例中的驱动补偿电路。The embodiment of the invention further provides a data driving device, comprising a data driving unit and a driving compensation circuit, wherein the data driving unit is electrically connected to the driving compensation circuit, and the data driving unit is connected to the data line. The drive compensation circuit is the drive compensation circuit in the above embodiment.
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In the above, the present invention has been disclosed in the above preferred embodiments, but the preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the invention. The invention is modified and retouched, and the scope of the invention is defined by the scope defined by the claims.

Claims (18)

  1. 一种驱动补偿电路，其包括：第一暂存单元、第二暂存单元、选通单元、电位移转器、数模转换单元以及放大单元；A driving compensation circuit includes: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
    所述第一暂存单元以及所述第二暂存单元分别与所述选通单元连接，所述选通单元、所述电位移转器、所述数模转换单元以及所述放大单元依次连接；The first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
    所述第一暂存单元用于获取并存储第一补偿信号；The first temporary storage unit is configured to acquire and store a first compensation signal;
    所述第二暂存单元用于获取并存储第二补偿信号；The second temporary storage unit is configured to acquire and store a second compensation signal;
    所述选通单元用于选择性地将所述第一暂存单元或所述第二暂存单元与所述电位移转器接通，所述电位转移器将所述第一补偿信号或所述第二补偿信号处理后发送给所述数模转换单元，所述数模转换单元根据所述第一补偿信号或所述第二补偿信号转换成对应的模拟信号，所述放大单元将所述模拟信号放大预设倍数后发送给数据驱动电路进行补偿；所述放大单元为模拟缓冲放大器，所述选通单元为选通开关芯片。The gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or The second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit The analog signal is amplified by a preset multiple and sent to the data driving circuit for compensation; the amplifying unit is an analog buffer amplifier, and the gating unit is a strobe switch chip.
  2. 根据权利要求1所述驱动补偿电路，其中，所述第一暂存单元包括第一接收器、第一移位寄存器以及第一数据暂存器，所述第一接收器、第一移位寄存器以及第一数据暂存器依次连接。The driving compensation circuit according to claim 1, wherein said first temporary storage unit comprises a first receiver, a first shift register and a first data register, said first receiver, said first shift register And the first data register is sequentially connected.
  3. 根据权利要求2所述驱动补偿电路，其中，所述第二暂存单元包括第二接收器、第二移位寄存器以及第二数据暂存器，所述第二接收器、第二移位寄存器以及第二数据暂存器依次连接。The driving compensation circuit according to claim 2, wherein said second temporary storage unit comprises a second receiver, a second shift register and a second data register, said second receiver, said second shift register And the second data register is sequentially connected.
  4. 根据权利要求3所述驱动补偿电路，其中，所述第一接收器以及所述第二接收器均为Mini-LVDS接收器。The drive compensation circuit according to claim 3, wherein said first receiver and said second receiver are both Mini-LVDS receivers.
  5. 根据权利要求3所述驱动补偿电路，其中，还包括一帧存储器，所述帧存储器存储有所述第一补偿信号或所述第二补偿信号。A drive compensation circuit according to claim 3, further comprising a frame memory, said frame memory storing said first compensation signal or said second compensation signal.
  6. 根据权利要求5所述驱动补偿电路，其中，所述第一数据暂存器具有第一控制端口，用于接入第一控制信号STB1；所述第二数据暂存器具有第二控制端口，用于接入第二控制信号STB2；所述选通单元具有第三控制端口，用于接入第三控制信号DS；The driving compensation circuit according to claim 5, wherein said first data register has a first control port for accessing a first control signal STB1; and said second data register has a second control port, For accessing the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
    当所述第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器中，当所述第一控制信号STB1处于上升沿时，将所述第一补偿信号输出到所述第一数据暂存器中；When the third control signal DS is at a low level, starting to read the first compensation signal in the frame memory into the first shift register, when the first control signal STB1 is at a rising edge, The first compensation signal is output to the first data register;
    当所述第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将所述第一数据暂存器中的第一补偿信号经过所述电位移转器、数模转换单元以及放大单元处理后传输给数据线；When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion The unit and the amplifying unit process and transmit to the data line;
    当所述第二控制信号STB2处于上升沿时，将所述第二补偿信号存入所述第二数据暂存器中，当所述第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把所述第二补偿信号传输给数据线。When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
  7. 一种驱动补偿电路，其包括：第一暂存单元、第二暂存单元、选通单元、电位移转器、数模转换单元以及放大单元；A driving compensation circuit includes: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
    所述第一暂存单元以及所述第二暂存单元分别与所述选通单元连接，所述选通单元、所述电位移转器、所述数模转换单元以及所述放大单元依次连接；The first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
    所述第一暂存单元用于获取并存储第一补偿信号；The first temporary storage unit is configured to acquire and store a first compensation signal;
    所述第二暂存单元用于获取并存储第二补偿信号；The second temporary storage unit is configured to acquire and store a second compensation signal;
    所述选通单元用于选择性地将所述第一暂存单元或所述第二暂存单元与所述电位移转器接通，所述电位转移器将所述第一补偿信号或所述第二补偿信号处理后发送给所述数模转换单元，所述数模转换单元根据所述第一补偿信号或所述第二补偿信号转换成对应的模拟信号，所述放大单元将所述模拟信号放大预设倍数后发送给数据驱动电路进行补偿。The gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or The second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit The analog signal is amplified by a preset multiple and sent to the data drive circuit for compensation.
  8. 根据权利要求7所述驱动补偿电路，其中，所述第一暂存单元包括第一接收器、第一移位寄存器以及第一数据暂存器，所述第一接收器、第一移位寄存器以及第一数据暂存器依次连接。The driving compensation circuit according to claim 7, wherein said first temporary storage unit comprises a first receiver, a first shift register and a first data register, said first receiver, said first shift register And the first data register is sequentially connected.
  9. 根据权利要求8所述驱动补偿电路，其中，所述第二暂存单元包括第二接收器、第二移位寄存器以及第二数据暂存器，所述第二接收器、第二移位寄存器以及第二数据暂存器依次连接。The driving compensation circuit according to claim 8, wherein said second temporary storage unit comprises a second receiver, a second shift register, and a second data register, said second receiver, said second shift register And the second data register is sequentially connected.
  10. 根据权利要求9所述驱动补偿电路，其中，所述第一接收器以及所述第二接收器均为Mini-LVDS接收器。The drive compensation circuit according to claim 9, wherein said first receiver and said second receiver are both Mini-LVDS receivers.
  11. 根据权利要求9所述驱动补偿电路，其中，还包括一帧存储器，所述帧存储器存储有所述第一补偿信号或所述第二补偿信号。A drive compensation circuit according to claim 9, further comprising a frame memory, said frame memory storing said first compensation signal or said second compensation signal.
  12. 根据权利要求11所述驱动补偿电路，其中，所述第一数据暂存器具有第一控制端口，用于接入第一控制信号STB1；所述第二数据暂存器具有第二控制端口，用于接入第二控制信号STB2；所述选通单元具有第三控制端口，用于接入第三控制信号DS；The driving compensation circuit according to claim 11, wherein said first data register has a first control port for accessing a first control signal STB1; and said second data register has a second control port, For accessing the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
    当所述第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器中，当所述第一控制信号STB1处于上升沿时，将所述第一补偿信号输出到所述第一数据暂存器中；When the third control signal DS is at a low level, starting to read the first compensation signal in the frame memory into the first shift register, when the first control signal STB1 is at a rising edge, The first compensation signal is output to the first data register;
    当所述第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将所述第一数据暂存器中的第一补偿信号经过所述电位移转器、数模转换单元以及放大单元处理后传输给数据线；When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion The unit and the amplifying unit process and transmit to the data line;
    当所述第二控制信号STB2处于上升沿时，将所述第二补偿信号存入所述第二数据暂存器中，当所述第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把所述第二补偿信号传输给数据线。When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
  13. 一种数据驱动装置，其特征在于，包括数据驱动单元以及驱动补偿电路，所述数据驱动单元以及所述驱动补偿电路均与数据线连接；A data driving device, comprising: a data driving unit and a driving compensation circuit, wherein the data driving unit and the driving compensation circuit are connected to a data line;
    所述驱动补偿电路包括：第一暂存单元、第二暂存单元、选通单元、电位移转器、数模转换单元以及放大单元；The driving compensation circuit includes: a first temporary storage unit, a second temporary storage unit, a gating unit, an electric displacement converter, a digital-to-analog conversion unit, and an amplifying unit;
    所述第一暂存单元以及所述第二暂存单元分别与所述选通单元连接，所述选通单元、所述电位移转器、所述数模转换单元以及所述放大单元依次连接；The first temporary storage unit and the second temporary storage unit are respectively connected to the gating unit, and the gating unit, the electric displacement converter, the digital-to-analog conversion unit and the amplifying unit are sequentially connected ;
    所述第一暂存单元用于获取并存储第一补偿信号；The first temporary storage unit is configured to acquire and store a first compensation signal;
    所述第二暂存单元用于获取并存储第二补偿信号；The second temporary storage unit is configured to acquire and store a second compensation signal;
    所述选通单元用于选择性地将所述第一暂存单元或所述第二暂存单元与所述电位移转器接通，所述电位转移器将所述第一补偿信号或所述第二补偿信号处理后发送给所述数模转换单元，所述数模转换单元根据所述第一补偿信号或所述第二补偿信号转换成对应的模拟信号，所述放大单元将所述模拟信号放大预设倍数后发送给数据驱动电路进行补偿。The gating unit is configured to selectively connect the first temporary storage unit or the second temporary storage unit to the electric displacement converter, and the potential transfer device will use the first compensation signal or The second compensation signal is processed and sent to the digital-to-analog conversion unit, and the digital-to-analog conversion unit converts into a corresponding analog signal according to the first compensation signal or the second compensation signal, and the amplifying unit The analog signal is amplified by a preset multiple and sent to the data drive circuit for compensation.
  14. 根据权利要求13所述数据驱动装置，其特征在于，所述第一暂存单元包括第一接收器、第一移位寄存器以及第一数据暂存器，所述第一接收器、第一移位寄存器以及第一数据暂存器依次连接。The data driving device according to claim 13, wherein the first temporary storage unit comprises a first receiver, a first shift register and a first data register, the first receiver, the first shift The bit register and the first data register are sequentially connected.
  15. 根据权利要求14所述数据驱动装置，其特征在于，所述第二暂存单元包括第二接收器、第二移位寄存器以及第二数据暂存器，所述第二接收器、第二移位寄存器以及第二数据暂存器依次连接。The data driving device according to claim 14, wherein said second temporary storage unit comprises a second receiver, a second shift register and a second data register, said second receiver, said second shift The bit register and the second data register are sequentially connected.
  16. 根据权利要求15所述数据驱动装置，其特征在于，所述第一接收器以及所述第二接收器均为Mini-LVDS接收器。The data driving device according to claim 15, wherein said first receiver and said second receiver are both Mini-LVDS receivers.
  17. 根据权利要求15所述驱动补偿电路，其中，还包括一帧存储器，所述帧存储器存储有所述第一补偿信号或所述第二补偿信号。A drive compensation circuit according to claim 15, further comprising a frame memory, said frame memory storing said first compensation signal or said second compensation signal.
  18. 根据权利要求17所述驱动补偿电路，其中，所述第一数据暂存器具有第一控制端口，用于接入第一控制信号STB1；所述第二数据暂存器具有第二控制端口，用于接入第二控制信号STB2；所述选通单元具有第三控制端口，用于接入第三控制信号DS；The driving compensation circuit according to claim 17, wherein said first data register has a first control port for accessing a first control signal STB1; said second data register has a second control port, For accessing the second control signal STB2; the gating unit has a third control port for accessing the third control signal DS;
    当所述第三控制信号DS为低电平时，开始读取所述帧存储器中的第一补偿信号到所述第一移位寄存器中，当所述第一控制信号STB1处于上升沿时，将所述第一补偿信号输出到所述第一数据暂存器中；When the third control signal DS is at a low level, starting to read the first compensation signal in the frame memory into the first shift register, when the first control signal STB1 is at a rising edge, The first compensation signal is output to the first data register;
    当所述第三控制信号DS为高电平，且第一控制信号STB1为下降沿时，将所述第一数据暂存器中的第一补偿信号经过所述电位移转器、数模转换单元以及放大单元处理后传输给数据线；When the third control signal DS is at a high level, and the first control signal STB1 is a falling edge, the first compensation signal in the first data register is passed through the electric displacement converter and digital-to-analog conversion The unit and the amplifying unit process and transmit to the data line;
    当所述第二控制信号STB2处于上升沿时，将所述第二补偿信号存入所述第二数据暂存器中，当所述第三控制信号DS为低电平且所述第二控制信号STB2为下降沿时，把所述第二补偿信号传输给数据线。When the second control signal STB2 is at a rising edge, storing the second compensation signal in the second data register, when the third control signal DS is at a low level and the second control When the signal STB2 is a falling edge, the second compensation signal is transmitted to the data line.
PCT/CN2017/111259 2017-10-25 2017-11-16 Drive compensation circuit and data drive apparatus WO2019080211A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104809993A (en) * 2015-04-15 2015-07-29 深圳市华星光电技术有限公司 Source electrode driver and liquid crystal display
CN106531084A (en) * 2017-01-05 2017-03-22 上海天马有机发光显示技术有限公司 Organic light emitting display panel and driving method thereof, and organic light emitting display apparatus
CN106847175A (en) * 2017-03-01 2017-06-13 京东方科技集团股份有限公司 Electroluminescent display panel and its uniformity of luminance compensation process, system
CN107086023A (en) * 2017-05-04 2017-08-22 合肥鑫晟光电科技有限公司 Pixel driver compensation circuit and its driving compensation method, display device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004165749A (en) * 2002-11-11 2004-06-10 Rohm Co Ltd Gamma correction voltage generating apparatus, gamma correction apparatus, and display device
US8289258B2 (en) * 2007-03-16 2012-10-16 Lg Display Co., Ltd. Liquid crystal display
JP2008298997A (en) * 2007-05-30 2008-12-11 Toshiba Matsushita Display Technology Co Ltd Display, and driving method for display
KR101289652B1 (en) * 2010-12-10 2013-07-25 엘지디스플레이 주식회사 Liquid crystal display
WO2014174905A1 (en) * 2013-04-23 2014-10-30 シャープ株式会社 Display device and drive current detection method for same
CN104867455B (en) * 2015-06-16 2017-05-03 深圳市华星光电技术有限公司 System and method for compensating AMOLED voltage drop
CN107039003B (en) * 2017-06-14 2019-07-02 深圳市华星光电半导体显示技术有限公司 It is suitble to the data driving chip framework and sequence controller framework of AMOLED compensation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104809993A (en) * 2015-04-15 2015-07-29 深圳市华星光电技术有限公司 Source electrode driver and liquid crystal display
CN106531084A (en) * 2017-01-05 2017-03-22 上海天马有机发光显示技术有限公司 Organic light emitting display panel and driving method thereof, and organic light emitting display apparatus
CN106847175A (en) * 2017-03-01 2017-06-13 京东方科技集团股份有限公司 Electroluminescent display panel and its uniformity of luminance compensation process, system
CN107086023A (en) * 2017-05-04 2017-08-22 合肥鑫晟光电科技有限公司 Pixel driver compensation circuit and its driving compensation method, display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3703043A4 *

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