EP3703043A1 - Drive compensation circuit and data drive apparatus - Google Patents
Drive compensation circuit and data drive apparatus Download PDFInfo
- Publication number
- EP3703043A1 EP3703043A1 EP17929435.0A EP17929435A EP3703043A1 EP 3703043 A1 EP3703043 A1 EP 3703043A1 EP 17929435 A EP17929435 A EP 17929435A EP 3703043 A1 EP3703043 A1 EP 3703043A1
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- Prior art keywords
- register
- unit
- signal
- compensation
- data
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
Definitions
- the present disclosure relates to a technological field of liquid crystal displays, and more particularly to a drive compensation circuit and a data drive device.
- FIG. 1 illustrates a drive compensation circuit in the prior art.
- two different data voltages are required for a transistor T1 to compensate a threshold voltage Vth of the transistor T1.
- a frequency of a MINI LVDS of a conventional data drive chip is lower.
- a compensation method is to decrease a frame rate and then to provide a MINI CLK, thereby compensating the Vth of the transistor T1.
- the method cannot meet the demand for mass production.
- An objective of the present disclosure is to provide a drive compensation circuit and a data drive device having a beneficial effect of effectively compensating a drive voltage of a data drive unit.
- the present disclosure provides a drive compensation circuit including a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit.
- the first register unit and the second register unit are respectively connected to the selection unit.
- the selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence.
- the first register unit is configured to acquire and store a first compensation signal.
- the second register unit is configured to acquire and store a second compensation signal.
- the selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter.
- the voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit.
- the digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal.
- the amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation.
- the amplification unit is an analog buffer amplifier.
- the selection unit is a switch chip.
- the first register unit includes a first receiver, a first shift register, and a first data register.
- the first receiver, the first shift register, and the first data register are connected in sequence.
- the second register unit includes a second receiver, a second shift register, and a second data register.
- the second receiver, the second shift register, and the second data register are connected in sequence.
- the first receiver and the second receiver are Mini-LVDS receivers.
- the drive compensation circuit of the present disclosure further includes a frame memory.
- the frame memory stores the first compensation signal and the second compensation signal.
- the first data register has a first control port configured to access a first control signal STB1
- the second data register has a second control port configured to access a second control signal STB2
- the selection unit has a third control port configured to access a third control signal DS.
- the third control signal DS When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register.
- the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit.
- the second compensation signal is stored in the second data register.
- the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- the present disclosure further provides a drive compensation circuit including a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit.
- the first register unit and the second register unit are respectively connected to the selection unit.
- the selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence.
- the first register unit is configured to acquire and store a first compensation signal.
- the second register unit is configured to acquire and store a second compensation signal.
- the selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter.
- the voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit.
- the digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal.
- the amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation.
- the first register unit includes a first receiver, a first shift register, and a first data register.
- the first receiver, the first shift register, and the first data register are connected in sequence.
- the second register unit includes a second receiver, a second shift register, and a second data register.
- the second receiver, the second shift register, and the second data register are connected in sequence.
- the first receiver and the second receiver are Mini-LVDS receivers.
- the drive compensation circuit of the present disclosure further includes a frame memory.
- the frame memory stores the first compensation signal and the second compensation signal.
- the first data register has a first control port configured to access a first control signal STB1
- the second data register has a second control port configured to access a second control signal STB2
- the selection unit has a third control port configured to access a third control signal DS.
- the third control signal DS When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register.
- the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit.
- the second compensation signal is stored in the second data register.
- the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- An embodiment of the present disclosure further provides a data drive device including a data drive unit and a drive compensation circuit.
- the data drive unit and the drive compensation circuit are connected to data lines.
- the drive compensation circuit includes a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit.
- the first register unit and the second register unit are respectively connected to the selection unit.
- the selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence.
- the first register unit is configured to acquire and store a first compensation signal.
- the second register unit is configured to acquire and store a second compensation signal.
- the selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter.
- the voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit.
- the digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal.
- the amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation.
- the first register unit includes a first receiver, a first shift register, and a first data register.
- the first receiver, the first shift register, and the first data register are connected in sequence.
- the second register unit includes a second receiver, a second shift register, and a second data register.
- the second receiver, the second shift register, and the second data register are connected in sequence.
- the first receiver and the second receiver are Mini-LVDS receivers.
- the data drive device of the present disclosure further includes a frame memory.
- the frame memory stores the first compensation signal and the second compensation signal.
- the first data register has a first control port configured to access a first control signal STB1
- the second data register has a second control port configured to access a second control signal STB2
- the selection unit has a third control port configured to access a third control signal DS.
- the third control signal DS When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register.
- the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit.
- the second compensation signal is stored in the second data register.
- the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- the embodiments of the present disclosure have a beneficial effect of effectively compensating a drive voltage of a data drive unit.
- FIG. 2 illustrates a structural diagram of a drive compensation circuit in accordance with a preferred embodiment of the present disclosure.
- the drive compensation circuit includes a first register unit 10, a second register unit 20, a selection unit 30, a voltage level shifter 40, a digital-to-analog conversion unit 50, and an amplification unit 60.
- the first register unit 20 and the second register unit 30 are respectively connected to the selection unit 30.
- the selection unit 30, the voltage level shifter 40, the digital-to-analog conversion unit 50, and the amplification unit 60 are connected in sequence.
- the first register unit 10 is configured to acquire and store a first compensation signal.
- the second register unit 20 is configured to acquire and store a second compensation signal.
- the selection unit 30 is configured to selectively connect the first register unit 10 or the second register unit 20 to the voltage level shifter 40.
- the voltage level shifter 40 processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit 50.
- the digital-to-analog conversion unit 50 converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal.
- the amplification unit 60 amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation.
- the data drive circuit outputs compensated drive voltage signals to data lines.
- the voltage level shifter 40 is configured to process and transmit the first compensation signal or the second compensation signal to the digital-to-analog conversion unit 50.
- a voltage of the first compensation signal or the second compensation signal is 3.3V.
- the voltage level shifter 40 increases 3.3V to 5V required by the digital-to-analog conversion unit 50.
- the amplification unit 60 is an analog buffer amplifier to enhance output drive ability.
- the digital-to-analog conversion unit 50 is a normal miniature digital-to-analog converter.
- the selection unit 30 is a switch chip.
- the first register unit 10 includes a first receiver 11, a first shift register 12, and a first data register 13.
- the first receiver 11, the first shift register 12, and the first data register 13 are connected in sequence.
- the second register unit 20 includes a second receiver 21, a second shift register 22, and a second data register 23.
- the second receiver 21, the second shift register 22, and the second data register 13 are connected in sequence.
- the first receiver 11 and the second receiver 21 are Mini-LVDS receivers.
- the drive compensation circuit further includes a frame memory.
- the frame memory stores the first compensation signal and the second compensation signal.
- first data register 13 has a first control port configured to access a first control signal STB1.
- the second data register 23 has a second control port configured to access a second control signal STB2.
- the selection unit 30 has a third control port configured to access a third control signal DS.
- the first compensation signal in the frame memory is read and stored in the first shift register 12.
- the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register 13.
- the first compensation signal in the first data register 13 is transmitted to the data lines after being processed by the voltage level shifter 40, the digital-to-analog conversion unit 50, and the amplification unit 60.
- the second compensation signal is stored in the second data register 23.
- the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- the first control signal STB1, the second control signal STB2, and the third control signal DS are square wave signals, and a timing diagram is shown in FIG. 4 .
- An embodiment of the present disclosure further provides a data drive device including a data drive unit and a drive compensation circuit.
- the data drive unit is electrically coupled to the drive compensation circuit.
- the data drive unit is electrically coupled to data lines.
- the drive compensation circuit is described as above.
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Abstract
Description
- The present disclosure relates to a technological field of liquid crystal displays, and more particularly to a drive compensation circuit and a data drive device.
- Please refer to
FIG. 1. FIG. 1 illustrates a drive compensation circuit in the prior art. When one data drive voltage is provided for one data line, two different data voltages are required for a transistor T1 to compensate a threshold voltage Vth of the transistor T1. A frequency of a MINI LVDS of a conventional data drive chip is lower. A compensation method is to decrease a frame rate and then to provide a MINI CLK, thereby compensating the Vth of the transistor T1. However, the method cannot meet the demand for mass production. - Consequently, defects exists in the prior art and urgently need to be improved.
- An objective of the present disclosure is to provide a drive compensation circuit and a data drive device having a beneficial effect of effectively compensating a drive voltage of a data drive unit.
- To solve the above-mentioned problem, technical schemes provided by the present disclosure are as follows.
- The present disclosure provides a drive compensation circuit including a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit.
- The first register unit and the second register unit are respectively connected to the selection unit. The selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence.
- The first register unit is configured to acquire and store a first compensation signal.
- The second register unit is configured to acquire and store a second compensation signal.
- The selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter. The voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit. The digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal. The amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation. The amplification unit is an analog buffer amplifier. The selection unit is a switch chip.
- In the drive compensation circuit of the present disclosure, the first register unit includes a first receiver, a first shift register, and a first data register. The first receiver, the first shift register, and the first data register are connected in sequence.
- In the drive compensation circuit of the present disclosure, the second register unit includes a second receiver, a second shift register, and a second data register. The second receiver, the second shift register, and the second data register are connected in sequence.
- In the drive compensation circuit of the present disclosure, the first receiver and the second receiver are Mini-LVDS receivers.
- The drive compensation circuit of the present disclosure further includes a frame memory. The frame memory stores the first compensation signal and the second compensation signal.
- In the drive compensation circuit of the present disclosure, the first data register has a first control port configured to access a first control signal STB1, the second data register has a second control port configured to access a second control signal STB2, and the selection unit has a third control port configured to access a third control signal DS.
- When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register.
- When the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit.
- When the second control signal STB2 is at a rising edge, the second compensation signal is stored in the second data register. When the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- The present disclosure further provides a drive compensation circuit including a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit.
- The first register unit and the second register unit are respectively connected to the selection unit. The selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence.
- The first register unit is configured to acquire and store a first compensation signal.
- The second register unit is configured to acquire and store a second compensation signal.
- The selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter. The voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit. The digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal. The amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation.
- In the drive compensation circuit of the present disclosure, the first register unit includes a first receiver, a first shift register, and a first data register. The first receiver, the first shift register, and the first data register are connected in sequence.
- In the drive compensation circuit of the present disclosure, the second register unit includes a second receiver, a second shift register, and a second data register. The second receiver, the second shift register, and the second data register are connected in sequence.
- In the drive compensation circuit of the present disclosure, the first receiver and the second receiver are Mini-LVDS receivers.
- The drive compensation circuit of the present disclosure further includes a frame memory. The frame memory stores the first compensation signal and the second compensation signal.
- In the drive compensation circuit of the present disclosure, the first data register has a first control port configured to access a first control signal STB1, the second data register has a second control port configured to access a second control signal STB2, and the selection unit has a third control port configured to access a third control signal DS.
- When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register.
- When the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit.
- When the second control signal STB2 is at a rising edge, the second compensation signal is stored in the second data register. When the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- An embodiment of the present disclosure further provides a data drive device including a data drive unit and a drive compensation circuit. The data drive unit and the drive compensation circuit are connected to data lines.
- The drive compensation circuit includes a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit.
- The first register unit and the second register unit are respectively connected to the selection unit. The selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence.
- The first register unit is configured to acquire and store a first compensation signal.
- The second register unit is configured to acquire and store a second compensation signal.
- The selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter. The voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit. The digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal. The amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation.
- In the data drive device of the present disclosure, the first register unit includes a first receiver, a first shift register, and a first data register. The first receiver, the first shift register, and the first data register are connected in sequence.
- In the data drive device of the present disclosure, the second register unit includes a second receiver, a second shift register, and a second data register. The second receiver, the second shift register, and the second data register are connected in sequence.
- In the data drive device of the present disclosure, the first receiver and the second receiver are Mini-LVDS receivers.
- The data drive device of the present disclosure further includes a frame memory. The frame memory stores the first compensation signal and the second compensation signal.
- In the data drive device of the present disclosure, the first data register has a first control port configured to access a first control signal STB1, the second data register has a second control port configured to access a second control signal STB2, and the selection unit has a third control port configured to access a third control signal DS.
- When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register.
- When the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit.
- When the second control signal STB2 is at a rising edge, the second compensation signal is stored in the second data register. When the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
- The embodiments of the present disclosure have a beneficial effect of effectively compensating a drive voltage of a data drive unit.
-
-
FIG. 1 illustrates a drive compensation circuit in the prior art. -
FIG. 2 illustrates a structural diagram of a drive compensation circuit in accordance with a preferred embodiment of the present disclosure. -
FIG. 3 illustrates a detailed circuit diagram of a drive compensation circuit in accordance with a preferred embodiment of the present disclosure. -
FIG. 4 illustrates a signal timing diagram in accordance with an embodiment of the present disclosure. - The following embodiments are referring to the accompanying drawings for exemplifying specific implementable embodiments of the present disclosure. Furthermore, directional terms described by the present disclosure, such as upper, lower, front, back, left, right, inner, outer, side, etc., are only directions by referring to the accompanying drawings, and thus the used directional terms are used to describe and understand the present disclosure, but the present disclosure is not limited thereto.
- In the drawings, elements with similar structures are labeled with like reference numerals.
- Please refer to
FIG. 2. FIG. 2 illustrates a structural diagram of a drive compensation circuit in accordance with a preferred embodiment of the present disclosure. The drive compensation circuit includes afirst register unit 10, asecond register unit 20, aselection unit 30, avoltage level shifter 40, a digital-to-analog conversion unit 50, and anamplification unit 60. Thefirst register unit 20 and thesecond register unit 30 are respectively connected to theselection unit 30. Theselection unit 30, thevoltage level shifter 40, the digital-to-analog conversion unit 50, and theamplification unit 60 are connected in sequence. - The
first register unit 10 is configured to acquire and store a first compensation signal. - The
second register unit 20 is configured to acquire and store a second compensation signal. - The
selection unit 30 is configured to selectively connect thefirst register unit 10 or thesecond register unit 20 to thevoltage level shifter 40. Thevoltage level shifter 40 processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit 50. The digital-to-analog conversion unit 50 converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal. Theamplification unit 60 amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation. The data drive circuit outputs compensated drive voltage signals to data lines. - The
voltage level shifter 40 is configured to process and transmit the first compensation signal or the second compensation signal to the digital-to-analog conversion unit 50. For example, a voltage of the first compensation signal or the second compensation signal is 3.3V. Thevoltage level shifter 40 increases 3.3V to 5V required by the digital-to-analog conversion unit 50. - The
amplification unit 60 is an analog buffer amplifier to enhance output drive ability. - The digital-to-
analog conversion unit 50 is a normal miniature digital-to-analog converter. - The
selection unit 30 is a switch chip. - Please refer to
FIG. 3 . Thefirst register unit 10 includes afirst receiver 11, afirst shift register 12, and afirst data register 13. Thefirst receiver 11, thefirst shift register 12, and the first data register 13 are connected in sequence. - The
second register unit 20 includes asecond receiver 21, asecond shift register 22, and asecond data register 23. Thesecond receiver 21, thesecond shift register 22, and the second data register 13 are connected in sequence. - The
first receiver 11 and thesecond receiver 21 are Mini-LVDS receivers. - In some embodiments, the drive compensation circuit further includes a frame memory. The frame memory stores the first compensation signal and the second compensation signal.
- Further, the first data register 13 has a first control port configured to access a first control signal STB1. The second data register 23 has a second control port configured to access a second control signal STB2. The
selection unit 30 has a third control port configured to access a third control signal DS. - When the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the
first shift register 12. When the first control signal STB1 is at a rising edge, the first compensation signal is outputted to thefirst data register 13. - When the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register 13 is transmitted to the data lines after being processed by the
voltage level shifter 40, the digital-to-analog conversion unit 50, and theamplification unit 60. - When the second control signal STB2 is at a rising edge, the second compensation signal is stored in the
second data register 23. When the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines. - In the present embodiment, the first control signal STB1, the second control signal STB2, and the third control signal DS are square wave signals, and a timing diagram is shown in
FIG. 4 . - An embodiment of the present disclosure further provides a data drive device including a data drive unit and a drive compensation circuit. The data drive unit is electrically coupled to the drive compensation circuit. The data drive unit is electrically coupled to data lines. The drive compensation circuit is described as above.
- In summary, although the present disclosure has been provided in the preferred embodiments described above, the foregoing preferred embodiments are not intended to limit the present invention. Those skilled in the art, without departing from the spirit and scope of the present invention, may make modifications and variations, so the scope of the protection of the present disclosure is defined by the claims.
Claims (18)
- A drive compensation circuit, comprising a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit;
wherein the first register unit and the second register unit are respectively connected to the selection unit, and the selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence;
the first register unit is configured to acquire and store a first compensation signal;
the second register unit is configured to acquire and store a second compensation signal;
the selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter, the voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit, the digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal, and the amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation;
the amplification unit is an analog buffer amplifier, and the selection unit is a switch chip. - The drive compensation circuit of claim 1, wherein the first register unit comprises a first receiver, a first shift register, and a first data register, and the first receiver, the first shift register, and the first data register are connected in sequence.
- The drive compensation circuit of claim 2, wherein the second register unit comprises a second receiver, a second shift register, and a second data register, and the second receiver, the second shift register, and the second data register are connected in sequence.
- The drive compensation circuit of claim 3, wherein the first receiver and the second receiver are Mini-LVDS receivers.
- The drive compensation circuit of claim 3, further comprising a frame memory, and the frame memory storing the first compensation signal and the second compensation signal.
- The drive compensation circuit of claim 5, wherein the first data register has a first control port configured to access a first control signal STB1, the second data register has a second control port configured to access a second control signal STB2, and the selection unit has a third control port configured to access a third control signal DS;
when the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register; when the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register;
when the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit;
when the second control signal STB2 is at a rising edge, the second compensation signal is stored in the second data register; when the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines. - A drive compensation circuit, comprising a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit;
wherein the first register unit and the second register unit are respectively connected to the selection unit, and the selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence;
the first register unit is configured to acquire and store a first compensation signal;
the second register unit is configured to acquire and store a second compensation signal;
the selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter, the voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit, the digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal, and the amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation. - The drive compensation circuit of claim 7, wherein the first register unit comprises a first receiver, a first shift register, and a first data register, and the first receiver, the first shift register, and the first data register are connected in sequence.
- The drive compensation circuit of claim 8, wherein the second register unit comprises a second receiver, a second shift register, and a second data register, and the second receiver, the second shift register, and the second data register are connected in sequence.
- The drive compensation circuit of claim 9, wherein the first receiver and the second receiver are Mini-LVDS receivers.
- The drive compensation circuit of claim 9, further comprising a frame memory, and the frame memory storing the first compensation signal and the second compensation signal.
- The drive compensation circuit of claim 11, wherein the first data register has a first control port configured to access a first control signal STB1, the second data register has a second control port configured to access a second control signal STB2, and the selection unit has a third control port configured to access a third control signal DS;
when the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register; when the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register;
when the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit;
when the second control signal STB2 is at a rising edge, the second compensation signal is stored in the second data register; when the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines. - A data drive device, comprising a data drive unit and a drive compensation circuit, and the data drive unit and the drive compensation circuit are connected to data lines,
wherein the drive compensation circuit comprises a first register unit, a second register unit, a selection unit, a voltage level shifter, a digital-to-analog conversion unit, and an amplification unit;
the first register unit and the second register unit are respectively connected to the selection unit, and the selection unit, the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit are connected in sequence;
the first register unit is configured to acquire and store a first compensation signal;
the second register unit is configured to acquire and store a second compensation signal;
the selection unit is configured to selectively connect the first register unit or the second register unit to the voltage level shifter, the voltage level shifter processes and transmits the first compensation signal or the second compensation signal to the digital-to-analog conversion unit, the digital-to-analog conversion unit converts the processed first compensation signal or the processed second compensation signal to a corresponding analog signal, and the amplification unit amplifies the analog signal with a predetermined multiple and then transmits the amplified analog signal to a data drive circuit for compensation. - The data drive device of claim 13, wherein the first register unit comprises a first receiver, a first shift register, and a first data register, and the first receiver, the first shift register, and the first data register are connected in sequence.
- The data drive device of claim 14, wherein the second register unit comprises a second receiver, a second shift register, and a second data register, and the second receiver, the second shift register, and the second data register are connected in sequence.
- The data drive device of claim 15, wherein the first receiver and the second receiver are Mini-LVDS receivers.
- The data drive device of claim 15, further comprising a frame memory, and the frame memory storing the first compensation signal and the second compensation signal.
- The data drive device of claim 17, wherein the first data register has a first control port configured to access a first control signal STB1, the second data register has a second control port configured to access a second control signal STB2, and the selection unit has a third control port configured to access a third control signal DS;
when the third control signal DS is at a low level, the first compensation signal in the frame memory is read and stored in the first shift register; when the first control signal STB1 is at a rising edge, the first compensation signal is outputted to the first data register;
when the third control signal DS is at a high level and the first control signal STB1 is at a falling edge, the first compensation signal in the first data register is transmitted to data lines after being processed by the voltage level shifter, the digital-to-analog conversion unit, and the amplification unit;
when the second control signal STB2 is at a rising edge, the second compensation signal is stored in the second data register; when the third control signal DS is at a low level and the second control signal STB2 is at a falling edge, the second compensation signal is transmitted to the data lines.
Applications Claiming Priority (2)
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CN201711009010.1A CN107845359A (en) | 2017-10-25 | 2017-10-25 | Drive compensation circuit and data driven unit |
PCT/CN2017/111259 WO2019080211A1 (en) | 2017-10-25 | 2017-11-16 | Drive compensation circuit and data drive apparatus |
Publications (2)
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EP3703043A1 true EP3703043A1 (en) | 2020-09-02 |
EP3703043A4 EP3703043A4 (en) | 2021-07-28 |
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EP17929435.0A Withdrawn EP3703043A4 (en) | 2017-10-25 | 2017-11-16 | Drive compensation circuit and data drive apparatus |
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EP (1) | EP3703043A4 (en) |
JP (1) | JP2020531915A (en) |
KR (1) | KR102365389B1 (en) |
CN (1) | CN107845359A (en) |
WO (1) | WO2019080211A1 (en) |
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JP2004165749A (en) * | 2002-11-11 | 2004-06-10 | Rohm Co Ltd | Gamma correction voltage generating apparatus, gamma correction apparatus, and display device |
US8289258B2 (en) * | 2007-03-16 | 2012-10-16 | Lg Display Co., Ltd. | Liquid crystal display |
JP2008298997A (en) * | 2007-05-30 | 2008-12-11 | Toshiba Matsushita Display Technology Co Ltd | Display, and driving method for display |
KR101289652B1 (en) * | 2010-12-10 | 2013-07-25 | 엘지디스플레이 주식회사 | Liquid crystal display |
CN105144274B (en) * | 2013-04-23 | 2017-07-11 | 夏普株式会社 | Display device and its driving current detection method |
CN104809993A (en) * | 2015-04-15 | 2015-07-29 | 深圳市华星光电技术有限公司 | Source electrode driver and liquid crystal display |
CN104867455B (en) * | 2015-06-16 | 2017-05-03 | 深圳市华星光电技术有限公司 | System and method for compensating AMOLED voltage drop |
CN106531084B (en) * | 2017-01-05 | 2019-02-05 | 上海天马有机发光显示技术有限公司 | Organic light emitting display panel and its driving method, organic light-emitting display device |
CN106847175B (en) * | 2017-03-01 | 2018-12-28 | 京东方科技集团股份有限公司 | Electroluminescent display panel and its uniformity of luminance compensation process, system |
CN107086023A (en) * | 2017-05-04 | 2017-08-22 | 合肥鑫晟光电科技有限公司 | Pixel driver compensation circuit and its driving compensation method, display device |
CN107039003B (en) * | 2017-06-14 | 2019-07-02 | 深圳市华星光电半导体显示技术有限公司 | It is suitble to the data driving chip framework and sequence controller framework of AMOLED compensation |
-
2017
- 2017-10-25 CN CN201711009010.1A patent/CN107845359A/en active Pending
- 2017-11-16 EP EP17929435.0A patent/EP3703043A4/en not_active Withdrawn
- 2017-11-16 KR KR1020207014543A patent/KR102365389B1/en active IP Right Grant
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KR102365389B1 (en) | 2022-02-18 |
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EP3703043A4 (en) | 2021-07-28 |
KR20200063245A (en) | 2020-06-04 |
CN107845359A (en) | 2018-03-27 |
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