WO2019072218A1 - 信号转换方法和装置、家庭总线系统hbs电路和用户设备 - Google Patents

信号转换方法和装置、家庭总线系统hbs电路和用户设备 Download PDF

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Publication number
WO2019072218A1
WO2019072218A1 PCT/CN2018/109919 CN2018109919W WO2019072218A1 WO 2019072218 A1 WO2019072218 A1 WO 2019072218A1 CN 2018109919 W CN2018109919 W CN 2018109919W WO 2019072218 A1 WO2019072218 A1 WO 2019072218A1
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Prior art keywords
signal
bit
spi
hbs
uart
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PCT/CN2018/109919
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English (en)
French (fr)
Inventor
石靖峰
杜明龙
侯磊
葛磊磊
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青岛海信日立空调系统有限公司
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Priority to US16/755,493 priority Critical patent/US11226917B2/en
Priority to EP18865821.5A priority patent/EP3697028B1/en
Publication of WO2019072218A1 publication Critical patent/WO2019072218A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40078—Bus configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard

Definitions

  • the present disclosure relates to the field of communications, and in particular, to a signal conversion method and apparatus, a Home Bus System (HBS) HBS circuit, and a user equipment.
  • HBS Home Bus System
  • Multi-line products have long used HomeBus (HB) communication, which is stable and reliable, and wiring does not need to consider polarity.
  • HB HomeBus
  • MCU Micro Control Unit
  • an embodiment of the present disclosure provides a home bus system HBS circuit for implementing home bus HB communication through a Microchip chip, the circuit comprising: a Microchip chip, an HBS communication chip, a resistor, a capacitor, and a triode,
  • the Microchip chip includes a universal asynchronous transceiver transmitter UART input pin and a serial peripheral interface SPI output pin
  • the HBS communication chip includes an input pin; the SPI output pin is coupled to a base of the transistor, a first end of the capacitor, a collector of the transistor is connected to the first end of the resistor and an input pin of the HBS communication chip, an emitter of the transistor is grounded, and a second end of the resistor is connected to the power source The second end of the capacitor is grounded.
  • an embodiment of the present disclosure provides a signal conversion apparatus, including: a control chip configured to convert a communication signal to be transmitted into a synchronous analog signal, the synchronous analog signal conforming to a home bus system HBS protocol; HBS communication And configured to convert the synchronous analog signal into a differential analog signal for HBS communication.
  • an embodiment of the present disclosure further provides a home bus system HBS circuit, including the above-described signal conversion device.
  • an embodiment of the present disclosure further provides a user equipment, including the signal conversion apparatus of the second aspect, or the home bus system HBS circuit of the first aspect.
  • an embodiment of the present disclosure provides a signal conversion method, including: acquiring a communication signal to be sent; converting the communication signal into a synchronous analog signal conforming to a home bus system HBS protocol; converting the synchronous analog signal into Differential analog signal.
  • an embodiment of the present disclosure provides a controller, including: a memory, configured to store a computer program, and a processor, to execute the computer program, to implement the method as described in the fifth aspect above.
  • an embodiment of the present disclosure provides a computer storage medium, comprising: the computer storage medium for storing a computer program, where the computer program is executed to implement the method as described in the fifth aspect.
  • an embodiment of the present disclosure provides a computer program product, the computer program product comprising instructions, when executed on a computer, for implementing the method as described in the fifth aspect above.
  • FIG. 1 is a schematic flowchart diagram of a signal conversion method according to some embodiments of the present disclosure.
  • FIG. 2 is a schematic flow chart of a method for converting a communication signal into a synchronous analog signal according to some embodiments of the present disclosure.
  • Figure 3 is a schematic diagram of a frame of a UART signal.
  • FIG. 4 is a schematic diagram of a UART signal modulated by a PWM clock signal in the related art.
  • FIG. 5 is a schematic diagram of a grouping manner used in data conversion according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of still another grouping manner used in data conversion according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of waveform correspondence between a UART signal, an SPI signal, and an HB signal in some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a signal conversion apparatus according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a control chip according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a processor according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an HBS circuit according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another HBS circuit according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic structural diagram of still another HBS circuit according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic flowchart diagram of another signal conversion method according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic structural diagram of another signal conversion apparatus according to some embodiments of the present disclosure.
  • the present disclosure provides a signal conversion method and apparatus, a home bus system HBS circuit, and a user equipment, such that a chip without a synchronous clock signal, such as a Microchip chip, implements Home Bus HomeBus communication.
  • some embodiments of the present disclosure provide a signal conversion method, including:
  • the communication signal to be transmitted in step 101 can be, for example, a chip without a synchronous clock signal, such as a signal of a Microchip chip to be output and requiring communication.
  • the communication signal to be sent in step 101 may be a UART signal conforming to a UART (Universal Asynchronous Receiver/Transmitter, UART) communication protocol.
  • the communication signal can be generated internally by the chip or externally.
  • the communication signal is converted into a synchronous analog signal by a control chip.
  • Step 102 can simulate a synchronous analog signal conforming to the HBS protocol of the home bus system by calculating the built-in program of the chip and calculating by the built-in program.
  • Step 103 continues with converting the synchronous analog signal to a differential analog signal.
  • the signal conversion method of the present disclosure implements HomeBus communication by using a software simulation method, and saves I/O resources of the control chip compared with the scheme of receiving an external clock synchronization signal and implementing HomeBus communication according to the received clock synchronization signal. A part of the external circuit is omitted.
  • the signal conversion method of the present disclosure can realize HomeBus communication without a clock synchronization signal.
  • the communication signal is converted to the synchronous analog signal by looking up a preset modulation translation table, wherein the modulation translation table includes the communication signal and a home bus system compliant HBS protocol.
  • the modulation translation table includes the communication signal and a home bus system compliant HBS protocol.
  • the corresponding relationship of the synchronous analog signals by searching for the modulation translation table, the communication signal to be transmitted can be converted into a synchronous analog signal.
  • the signal format of the synchronous analog signal conforms to the HBS protocol of the home bus system, so the HBS communicator such as the MM1192 communication chip can be identified.
  • the above method for converting data using a translation table can be used to implement asynchronous communication analog synchronous communication, and the response speed is fast.
  • the step of converting the communication signal into a synchronous analog signal may include:
  • the communication signal is a UART signal conforming to the UART communication protocol
  • the synchronous analog signal is an SPI signal conforming to the SPI communication protocol as an example.
  • the related art is modulated according to the UART signal and the input clock signal.
  • the modulated signal can be a modulated UART signal.
  • the communication signal and the synchronous analog signal can also be other signal formats, and those skilled in the art can easily obtain the corresponding conversion of the communication signal to the synchronous analog signal on the basis of the present disclosure. method.
  • the UART signal is a UART signal that is not synchronized with the clock, and a total of 11 bits can be transmitted in one frame of the signal.
  • the 11 bits include a 1-bit start bit, an 8-bit (1 byte) data body bit (D0-D7), a 1-bit parity bit, and a 1-bit stop bit.
  • the modulated one frame signal includes 22 bits.
  • the SPI signal is generated according to the UART signal by an algorithm without reference to the synchronous clock signal, and the signal format of the generated SPI signal and the modulated UART signal generated by the UART signal reference synchronous clock signal in the related art are modulated.
  • the signal format is the same, that is, the SPI signal is in accordance with the HBS protocol of the home bus system.
  • Each 4 bytes of the SPI signal can correspond to one frame of the UART signal.
  • the baud rate of the SPI signal is equal to twice the baud rate of the UART signal.
  • the SPI signal simulates the modulated UART signal.
  • the converted SPI signal is used to simulate the modulated UART signal.
  • the baud rate of the SPI signal needs to be equal to twice the baud rate of the UART signal. For example, if the baud rate of the UART signal is 9600 bps, the baud rate of the output SPI signal needs to be 19200 bps.
  • Each SPI packet of the SPI signal can be 8, 16, or 32 bits. Assuming that 8 bits are selected as an SPI packet, at least 3 SPI packets are required to simulate the modulated 22 bits of a UART signal.
  • the corresponding conversion of the byte of the SPI signal and the bit of a frame of the UART signal can be realized by looking up the table, and the conversion efficiency is higher by looking up the table.
  • the corresponding conversion of the bytes of the SPI signal to the bits of a frame of the UART signal can also be accomplished by any other method known to those skilled in the art, such as software programming.
  • valid data for one frame of the UART signal can be simulated by transmitting a four byte SPI packet.
  • the first byte of the SPI signal corresponds to the start bit of one frame of the UART signal
  • the second byte and the third byte of the SPI signal correspond to the data of the UART signal.
  • Bit for example, the second byte of the SPI signal corresponds to the 0th bit (D0) to the 3rd bit (D3) of the data body bit of the UART signal
  • the third byte of the SPI signal corresponds to the 4th of the UART signal.
  • Bit (D4) to 7th bit (D7); the fourth byte of the SPI signal corresponds to the parity bit and the stop bit of the UART signal. That is, the start bit of the UART signal is the first set of bits and corresponds to the first byte of the SPI signal; the 0th bit to the 3rd bit of the data body bit (D0-D7) of the UART signal Bits (D0-D3) are the second group of bits and correspond to the second byte of the SPI signal; the fourth bit to the seventh bit (D4-D7) of the data body bit of the UART signal are Three sets of bits corresponding to the third byte of the SPI signal; the parity bit and the stop bit of the UART signal being a fourth set of bits and corresponding to the fourth byte of the SPI signal. According to the above grouping manner, each group of bit values of one message frame of the UART signal is read, and a corresponding SPI signal is obtained by looking up a modulation translation table.
  • the following five arrays are translated sub-tables of the modulation translation table for quickly finding the converted four-byte SPI packet by each set of bit values of the UART signal. For example, assuming the UART signal is "0x00" and the baud rate is 9600 bps, the four-byte SPI packet of the converted SPI signal includes: “0x01” + "0x55” + "0x55” + “0x40", And its baud rate is 19200bps.
  • the first set of bits, the start of the original data, corresponds to the first byte of the SPI packet. Since the start bits of all data are the same, all data in the array table0[256] corresponding to the first byte is 0x01.
  • the translation subtable corresponding to the first set of bits ie the array table0[256] is expressed as follows:
  • the start bit of the input UART signal is 0, so it is possible to directly define the value corresponding to the first bit in all arrays to be 0x01.
  • the second set of bits i.e., the 0th bit of the original data to the 3rd bit D0, D1, D2, D3 corresponds to the second byte of the SPI data.
  • the data sent by the UART data and the SPI data are reversed in order, so the original binary data needs to be reversed when the data is converted.
  • the SOP MM1192 communication chip an HBS communication chip
  • MITSUMI is used to generate a differential analog signal from the synchronous analog signal, considering that the SPI output of the PIC32MX series chip is low when idle.
  • the idle signal input requirement of the MM1192 is high, and a transistor is required to level invert before inputting the MM1192.
  • the data needs to be reversed when the data is converted, that is, the "0" data is inverted to "1", and the "1" data is inverted to "0".
  • the chip that outputs the SPI signal and the chip that receives the SPI signal at the back end are at the same level when idle, so level inversion may not be performed.
  • the implementation of this part of the data transformation can be programmed using Turbo C software, or pre-programmed sub-tables and obtained by look-up table.
  • the translation sub-table corresponding to the second set of bits, that is, the array Table1 [256] is expressed as follows:
  • the third set of bits corresponds to the third byte of the SPI data.
  • the array Table2[256] is used to store the conversion data of the third set of bits. This part of the conversion is similar to Table1[256].
  • the translation sub-table corresponding to the third set of bits, that is, the array Table 2 [256] is expressed as follows:
  • the fourth set of bits is the odd check bit and the stop bit in the original data, corresponding to the fourth byte in the SPI data. If the parity check uses odd parity, the translation sub-table corresponding to the fourth group of bits, ie, the array Table3_1[256], is expressed as follows:
  • the 8-bit data body bit actually takes two complete bytes.
  • the UART signal is converted to generate an SPI signal according to a preset modulation translation table, wherein the SPI signal includes 4 bytes, and the first 6 data bits in the first byte of the SPI signal are empty. The last four bytes in the fourth byte are empty, and the null byte can be assigned a value of 0.
  • the preset modulation translation table stores a preset relationship, and the preset relationship is used to convert the start bit of the UART signal into The last two data bits in the first byte of the SPI signal convert the D0-D3 data bits of the UART signal to the left and right inversion and perform data inversion to generate the second byte of the SPI signal, and the D4 of the UART signal.
  • the -D7 data bit is converted to the third byte of the SPI signal after the left and right inversion and data inversion, and the parity and stop bits of the UART signal are converted into the first four bytes of the fourth byte.
  • the start bit of the UART signal is converted to the last two data bits in the first byte of the SPI signal, ie the first byte data is 0x01.
  • the first byte of the SPI signal corresponds to the start bit of the UART signal and the D0 bit of the data body bit to the D2 bit, and the second byte of the SPI signal.
  • the third byte of the SPI signal corresponds to the D7 bit, the parity bit and the stop bit of the data body bit.
  • the start bit and the D0 bit to the D2 bit of the data body bit are the first group of bits and correspond to the first byte of the SPI signal;
  • the D3 bit to the D6 bit of the data body bit Bits are a second set of bits and correspond to a second byte of the SPI signal;
  • a D7 bit of the data body bit, the parity bit, and the stop bit are a third set of bits, and corresponding to The third byte of the SPI signal.
  • a delay of one byte may be added, that is, the fourth byte of the SPI signal is used for delay.
  • each group of bit values of one message frame of the UART signal is read, and a corresponding SPI signal is obtained by, for example, searching for a modulation translation table.
  • the data conversion of mode 2 is similar to that of mode 1, except that the modulation translation table is different.
  • step 102 the data format is converted by the software method, and the signal conforming to the HBS protocol of the home bus system is simulated, that is, the synchronous analog signal obtained through step 102 has a signal format consistent with the modulated UART signal in the related art, thereby supporting HBS communication.
  • the synchronous analog signal can be converted into a differential analog signal by an HBS communication chip.
  • the HBS communication chip supports HBS communication.
  • the HBS communication chip can be the SOP MM1192 communication chip produced by MITSUMI.
  • the chip that performs the data conversion can be a Microchip chip; the Microchip chip sends an SPI signal through the SPI output pin, which is used as an input to the MM1192 communication chip to obtain a differential analog signal.
  • the UART signal is converted to obtain an SPI signal, and finally a differential analog HB signal is generated by the HBS communication chip 12.
  • the signal conversion device 10 includes a control chip 11 and an HBS communicator 12, and the control chip 11 is configured to convert a communication signal into a synchronous analog signal, the synchronous analog signal conforming to a home bus system HBS protocol; HBS The communicator 12 is configured to convert the synchronized analog signal to a differential analog signal.
  • the control chip 11 can be, for example, a Microchip chip and a chip or circuit that implements a similar function.
  • the HBS communicator 12 can be, for example, an HBS communication chip and a chip or circuit that implements a similar function.
  • the HBS communication chip can be, for example, the MM1192 communication. chip.
  • the control chip 11 includes a processor 1101 and a memory 1102; the processor 1101 is configured to convert the communication signal into a location by searching a preset modulation translation table. A synchronous analog signal is described; a memory 1102 is configured to store the modulation translation table.
  • the modulation translation table includes a correspondence between the communication signal and a synchronous analog signal conforming to a home bus system HBS protocol.
  • the processor 1101 includes an acquisition module 1101a and an analog module 1101b.
  • the obtaining module 1101a is configured to read each group of bit values of a message frame of the communication signal according to a preset grouping manner, wherein a group of bit values of the message frame includes one or more bits of the message frame The value of the bit.
  • a frame of the UART signal that is not synchronously clock-modulated includes 11 bits, and a predetermined grouping manner may be: the start bit is the first group of bits, and the 0th bit to the 3rd bit of the data body bit The bit is a second set of bits, the fourth bit to the seventh bit of the data body bit being a third set of bits, the parity bit and the terminating bit being a fourth set of bits.
  • the simulation module 1101b is configured to convert each of the read bit values into one byte of the synchronous analog signal by looking up the modulation translation table; wherein the modulation translation table includes a plurality of translation sub-tables, each The translation subtable includes a mapping of all possible values of a set of bits to corresponding bytes of the synchronous analog signal. For a set of bit values, by looking up the corresponding translation sub-table, the corresponding data after conversion to the synchronous analog signal can be obtained, which is usually one byte of the synchronous analog signal.
  • the control chip 11 includes a Serial Peripheral Interface (SPI), and the output pin TX of the serial peripheral interface is configured as an output pass.
  • SPI Serial Peripheral Interface
  • the HBS communicator 12 is an HBS communication chip, the HBS communication chip 12 includes an input pin IN, and the input pin IN is configured to receive the synchronous analog signal.
  • the HBS communication chip 12 generates a differential analog signal for HBS communication based on the synchronous analog signal.
  • the level shifter 13 needs to be set to perform level inversion to match the input of the HBS communication chip.
  • Pin IN requirements As shown in FIG. 11, in some embodiments of the present disclosure, an output pin TX of the serial peripheral interface is connected to an input pin IN of the HBS communication chip through the level shifter 13; The level shifter 13 is configured to level invert the synchronous analog signal outputted by the output pin TX of the serial peripheral interface to match the requirements of the input pin IN of the HBS communication chip.
  • the idle level of the control chip 11 is the same as the idle level of the HBS communication chip 12, for example, both low level or high level, and the control chip 11 and the communication chip 12 are There is no level shifter 13 between them.
  • the control chip 11 is, for example, a Microchip chip
  • the HBS communicator 12 is an HBS communication chip
  • the level shifter 13 includes a transistor Q1, a resistor R1, and a capacitor C1.
  • the Microchip chip 11 includes a Universal Asynchronous Receiver/Transmitter (UART) input pin RX, a Serial Peripheral Interface (SPI) output pin TX, and an interrupt pin INT.
  • the HBS communication chip 12 includes Input pin IN.
  • the UART input pin RX of the Microchip chip 11 is connected to the interrupt pin INT, and the UART input pin RX is configured to receive signals.
  • the output pin TX of the SPI is configured as an output signal, that is, the communication signal to be transmitted is first converted into an SPI signal output in the Microchip chip 11, and the signal format of the SPI signal conforms to the HBS protocol of the home bus system.
  • the SPI signal is input to the HBS communication chip 12 via the level shifter 13.
  • the HBS communication chip 12 finally outputs an analog differential signal by collecting a signal on the bus where the input pin IN is located.
  • the SPI output pin TX of Microchip chip 11 is connected to the base B of transistor Q1 and the first terminal of capacitor C1.
  • the collector C of the transistor Q1 is connected to the first end of the resistor R1 and the input pin IN of the HBS communication chip 12.
  • the emitter E of the transistor Q1 is grounded, the second end of the resistor R1 is connected to the positive voltage power signal VCC (for example, 5V), and the second end of the capacitor C1 is grounded.
  • the Microchip chip 11 can be a PIC32MX chip
  • the HBS communication chip 12 can use a MM1192 communication chip. Since the SPI output pin TX of the PIC32MX series chip is low when idle, and the idle signal input of the input pin IN of the MM1192 is required to be high level, the transistor Q1 is used for level inversion before the SPI signal is input to the MM1192. turn.
  • R1 is the pull-up resistor of transistor Q1
  • C1 is the filter capacitor.
  • the control chip 11 communicates in a synchronous transmission asynchronous reception manner.
  • the input pin RX of the first logical communication port 113 of the control chip 11 is configured as a UAPT signal receiving port
  • the output pin TX of the first logical communication port 113 of the control chip is configured as an SPI signal transmitting port.
  • the serial clock (SCK) port that matches the SPI bus may take effect automatically. In this case, the SCK port can no longer be used for other input and output (I/O). ).
  • the input pin RX of the second logical communication port 111 of the control chip 11 is configured as a UART signal receiving port, and the output pin TX0 of the second logical communication port 111 is configured.
  • the output pin TX of the third logical communication port 112 is configured as an SPI signal transmitting port, and the input pin RX0 of the third logical communication port 112 is configured to be grounded.
  • a receive port of a UART of a control chip can be used to receive signals and the receive port can be configured to be independently received, the transmit port of the UART can still be used as other functions; one using a control chip
  • the SPI's transmit port sends a signal and configures the transmit port to transmit independently.
  • the SPI receive port can still be used as another function.
  • the embodiment of the present disclosure further provides a home bus system HBS circuit, which is applied to realize home bus HB communication through a Microchip chip.
  • the circuit includes: Microchip chip 11 , HBS communication chip 12 , resistor R , and capacitor C1 and transistor Q1. The connection relationship of these components can be referred to the above description, and will not be described again.
  • the Microchip chip 11 receives a UART signal through the UART input pin.
  • the Microchip chip 11 is configured to convert a UART signal into an SPI signal, wherein every 4 bytes of the SPI signal corresponds to a frame of the UART signal, and a baud rate of the SPI signal is equal to the UART signal. At twice the baud rate, the SPI signal conforms to the HBS protocol of the Home Bus System.
  • the Microchip chip 11 transmits the SPI signal through the SPI output pin.
  • the HBS communication chip 12 is configured to receive the SPI signal and output a differential analog signal.
  • the Microchip chip 11 is configured to convert the UART signal into an SPI signal by converting a bit value "0" of a data bit in the UART signal to the SPI signal.
  • the two-bit value of the middle data bit is "0, 1"; the bit value "1” of the data bit in the UART signal is correspondingly converted into the two-bit bit value "1, 1" of the data bit in the SPI signal.
  • conforming to the HBS protocol means that there is a transition between "0” and “1", and the HBS communication chip can trigger a pulse of the differential signal by a transition between "0" and "1".
  • the Microchip chip does not have a synchronous clock I/O port, and there is no circuit that simulates an external synchronous clock, that is, the Microchip chip 11 does not refer to the synchronous clock signal during data conversion.
  • the embodiment of the present disclosure further provides a signal conversion method applied to the circuit shown in FIG. 11, as shown in FIG. 14, the method includes:
  • the Microchip chip receives the UART signal through the UART input pin, wherein the UART signal is not modulated by the synchronous clock.
  • the Microchip chip converts the UART signal into an SPI signal, wherein each 4 bytes of the SPI signal corresponds to one frame of the UART signal, and the baud rate of the SPI signal is equal to twice the baud rate of the UART signal, and the SPI signal conforms to the family.
  • Bus system HBS protocol
  • the Microchip chip transmits an SPI signal through the SPI output pin, and the SPI signal is used as an input of the HBS communication chip to obtain a differential analog HB signal.
  • the input UART signal is converted into an SPI signal according to a byte by the Microchip chip, so that the SPI signal conforms to the HBS protocol of the home bus system.
  • the SPI signal is used as the input of the HBS communication chip, and finally the HBS communication chip outputs the differential analog HB signal to realize the HomeBus communication of the home bus.
  • the embodiment of the present application provides a signal conversion apparatus, which is applied to the foregoing method, for implementing home bus HB communication through a Microchip chip.
  • the apparatus includes:
  • the receiving unit 1103 is configured to receive the UART signal through the UART input pin, where the UART signal is not synchronized with the clock.
  • the converting unit 1104 is configured to convert the UART signal received by the receiving unit 1103 into an SPI signal, wherein each 4 bytes of the SPI signal corresponds to one frame of the UART signal, and the baud rate of the SPI signal is equal to the baud rate of the UART signal. Twice, the SPI signal conforms to the HBS protocol of the Home Bus System.
  • the transmitting unit 1105 is configured to send the SPI signal converted by the converting unit 1104 through the SPI output pin, and the SPI signal is used as an input of the HBS communication chip to obtain a differential analog HB signal.
  • Some embodiments of the present disclosure also provide a home bus system HBS circuit, including any of the signal conversion devices described above.
  • the home bus system HBS circuit provided by the embodiment of the present disclosure may use a control chip that does not have a synchronous clock signal output, such as a Microchip chip.
  • Some embodiments of the present disclosure also provide a user equipment, including a home bus system HBS circuit or any of the signal conversion devices described.
  • the user equipment may also be a smart home product such as an air conditioner, a refrigerator, a washing machine, a television, a kitchen appliance, or the like.
  • the user device can be a multi-connected air conditioning product.
  • the user equipment may also be an electronic device such as a mobile phone or a gaming device or any device that may access an HBS communication network or a similar communication network.
  • a similar communication network here refers to a communication network in which communication requires a synchronized clock signal.
  • An embodiment of the present disclosure provides a controller, the controller including: a memory for storing a computer program, and a processor for executing the computer program to implement the method as follows:
  • An embodiment of the present disclosure provides a computer storage medium, including: the computer storage medium is used to store a computer program, and when the computer program is executed, the method is as follows:
  • Embodiments of the present disclosure provide a computer program product, the computer program product comprising instructions for implementing a method as described below when run on a computer:
  • the obtaining module and the analog module may be separately set, or may be integrated into one processor of the controller, or may be stored in the memory of the controller in the form of program code, and processed by one of the controllers.
  • the device calls and executes the functions of the above modules.
  • the processor described herein may be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated systems configured to implement embodiments of the present disclosure. Circuit.
  • the size of the sequence numbers of the above steps does not mean the order of execution order, and the order of execution of each step should be determined by its function and internal logic, and should not be implemented in the implementation of the embodiments of the present disclosure. Form any limit.
  • the disclosed systems, devices, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the functional modules is only a logical functional division.
  • there may be another division manner for example, multiple functional modules or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or functional module, and may be electrical, mechanical or otherwise.
  • the functional modules, units or components described as separate components may or may not be physically separated, and the components displayed as components may or may not be physical units, that is, may be located in one place, or may be distributed in many places. On a network unit. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module or component in various embodiments of the present disclosure may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the steps of the method or algorithm described in the embodiments of the present disclosure may be implemented by means of a processor executing software instructions.
  • the software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory ( Erasable programmable ROM (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM) or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the processor may be a central processing unit (CPU), a field programmable logic array (FPGA), a microcontroller (MCU), a specific function application circuit (ASIC), etc., having logic computing capabilities and/or program execution capabilities.
  • the computer program product includes one or more computer instructions.
  • the processes or functions described in accordance with embodiments of the present application are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device that includes one or more servers, data centers, etc. that can be integrated with the media.
  • the usable medium may be a magnetic medium or a semiconductor medium or the like.
  • the network can include wireless networks, wired networks, and/or any combination of wireless networks and wired networks.
  • the network may include a local area network, the Internet, a telecommunications network, an internet of things based on the Internet and/or telecommunications network, and/or any combination of the above networks, and the like.
  • the wired network can be communicated by using, for example, a twisted pair cable, a coaxial cable, or an optical fiber.
  • the wireless network can use, for example, a 3G/4G/5G mobile communication network, Bluetooth, Zigbee, or WiFi.

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Abstract

一种家庭总线系统HBS电路，应用于通过Microchip芯片实现家庭总线HB通信，所述电路包括：Microchip芯片、HBS通讯芯片、电阻、电容和三极管，所述Microchip芯片包括通用异步收发传输器UART输入管脚和串行外设接口SPI输出管脚，所述HBS通讯芯片包括输入管脚；所述SPI输出管脚连接至所述三极管的基极、所述电容的第一端，所述三极管的集电极连接至所述电阻的第一端以及所述HBS通讯芯片的输入管脚，所述三极管的发射极接地，所述电阻的第二端连接至电源，所述电容的第二端接地。

Description

信号转换方法和装置、家庭总线系统HBS电路和用户设备
本申请要求于2017年10月11日提交中国专利局、申请号为201710942121.1、发明名称为“家庭总线系统HBS电路、信号转换方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及通信领域，尤其涉及一种信号转换方法和装置、家庭总线系统(Home Bus System，HBS)HBS电路和用户设备。
背景技术
多联机产品长期以来都使用家庭总线(HomeBus，HB)通讯，该通讯方式稳定可靠、接线也无需考虑极性。但是支持此通讯方式的微控制单元(Micro Control Unit，MCU)多年以来只局限于日本的芯片厂家，经常出现供货不足的情况。
其他类型芯片例如Microchip芯片，虽然技术支援及供货保障能力均较强，芯片价格也较上述厂家有优势。但是此类芯片由于没有HomeBus通讯所需要的同步时钟因此并不支持HomeBus通讯。
发明内容
第一方面，本公开的实施例提供了一种家庭总线系统HBS电路，应用于通过Microchip芯片实现家庭总线HB通信，所述电路包括：Microchip芯片、HBS通讯芯片、电阻、电容和三极管，所述Microchip芯片包括通用异步收发传输器UART输入管脚和串行外设接口SPI输出管脚，所述HBS通讯芯片包括输入管脚；所述SPI输出管脚连接至所述三极管的基极、所述电容的第一端，所述三极管的集电极连接至所述电阻的第一端以及所述HBS通讯芯片的输入管脚，所述三极管的发射极接地，所述电阻的第二端连接至电源，所述电容的第二端接地。
第二方面，本公开的实施例提供了一种信号转换装置，包括：控制芯片，配置为将欲发送的通讯信号转换为同步模拟信号，所述同 步模拟信号符合家庭总线系统HBS协议；HBS通讯器，配置为将所述同步模拟信号转化为用于HBS通讯的差分模拟信号。
第三方面，本公开实施例还提供了一种家庭总线系统HBS电路，包括上述的信号转换装置。
第四方面，本公开实施例还提供了一种用户设备，包括第二方面所述的信号转换装置，或者包括第一方面所述的家庭总线系统HBS电路。
第五方面，本公开实施例提供一种信号转换方法，包括：获取欲发送的通讯信号；将所述通讯信号转换为符合家庭总线系统HBS协议的同步模拟信号；将所述同步模拟信号转化为差分模拟信号。
第六方面，本公开实施例提供一种控制器，包括：存储器，用于存储计算机程序；处理器，用于执行所述计算机程序，以实现如上述第五方面所述的方法。
第六方面，本公开实施例提供一种计算机存储介质，包括：所述计算机存储介质用于存储计算机程序，所述计算机程序执行时用于实现如第五方面所述的方法。
第七方面，本公开实施例提供一种计算机程序产品，所述计算机程序产品包含指令，所述指令在计算机上运行时，用于实现如上述第五方面所述的方法。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一些实施例提供的信号转换方法的流程示意图。
图2为本公开的一些实施例提供的通讯信号转换为同步模拟信号的方法流程示意图。
图3为一帧UART信号的示意图。
图4为相关技术中经过PWM时钟信号调制后的UART信号的示意图。
图5为本公开的一些实施例提供的数据变换时用到的一种分组方式的示意图。
图6为本公开的一些实施例提供的数据变换时用到的又一种分组方式的示意图。
图7为本公开一些实施例中UART信号、SPI信号和HB信号的波形对应关系示意图。
图8为本公开的一些实施例提供的信号转换装置的结构示意图。
图9为本公开的一些实施例提供的一种控制芯片的结构示意图。
图10为本公开的一些实施例提供的一种处理器的结构示意图。
图11为本公开的一些实施例提供的一种HBS电路的结构示意图。
图12为本公开的一些实施例提供的另一种HBS电路的结构示意图。
图13为本公开的一些实施例提供的又一种HBS电路的结构示意图。
图14为本公开的一些实施例提供的另一种信号转换方法的流程示意图。
图15为本公开的一些实施例提供的另一种信号转换装置的结构示意图。
具体实施方式
本公开提供一种信号转换方法和装置、家庭总线系统HBS电路和用户设备，可使无同步时钟信号的芯片例如Microchip芯片实现家庭总线HomeBus通讯。
下面结合附图，对本公开的实施例进行描述。
如图1所示，本公开的一些实施例提供一种信号转换方法，包括：
101、获取欲发送的通讯信号，所述欲发送的通讯信号未经同步时钟调制；
102、将所述通讯信号转换为符合家庭总线系统HBS协议的同步模拟信号；
103、将所述同步模拟信号转化为差分模拟信号。
步骤101中欲发送的通讯信号例如可以是无同步时钟信号的芯片如Microchip芯片的待输出并要求通信的信号。例如，步骤101中欲发送的通讯信号可以是符合UART(Universal Asynchronous Receiver/Transmitter，UART)通信协议的UART信号。该通讯信号可以是芯片内部生成的，也可以是从外部接收到的。步骤102中通过控制芯片将所述通讯信号转换为同步模拟信号。步骤102可通过在控制芯片内置程序，并通过内置程序的计算从而模拟出符合家庭总线系统HBS协议的同步模拟信号。步骤103再继续将同步模拟信号转化为差分模拟信号。
本公开的信号转换方法使用软件模拟的方法实现HomeBus通讯，与接收外部时钟同步信号并根据接收到的时钟同步信号实现HomeBus通讯的方案相比，不但节省了控制芯片的I/O资源，也可省去一部分外部电路。本公开的信号转换方法不需要时钟同步信号即可实现HomeBus通讯。
在本公开的一些实施例中，通过查找预先设置的调制翻译表，将所述通讯信号转换为所述同步模拟信号，其中，所述调制翻译表包括所述通讯信号与符合家庭总线系统HBS协议的同步模拟信号的对应关系。本实施例中，通过查找调制翻译表，可以将欲发送的通讯信号转换为同步模拟信号。同步模拟信号的信号格式符合家庭总线系统HBS协议，因此HBS通讯器例如MM1192通讯芯片可识别。上述使用翻译表进行数据转化的方法可以用于实现异步通讯模拟同步通讯，反应速度快。
如图2所示，在本公开的一些实施例中，通讯信号转换为同步模拟信号的步骤可包括：
1021、按预设的分组方式，读取所述通讯信号的一个消息帧的各组比特值，其中，所述消息帧的一组比特值包括所述消息帧的一位或多位比特位的取值；
1022、通过查找所述调制翻译表，将读取到的每组比特值转换为所述同步模拟信号的一个字节；其中，所述调制翻译表包括多个翻译子表，每个翻译子表包括一组比特位的所有可能取值到所述同步模拟信号的对应字节的映射。
下面以所述通讯信号为符合UART通信协议的UART信号，所述同步模拟信号为符合SPI通信协议的SPI信号为例进行说明，对应的，相关技术中根据UART信号和输入的时钟信号调制生成的调制后信号可以是调制后的UART信号。当然，本领域技术人员可以理解的是，通讯信号、同步模拟信号还可以是其他的信号格式，而且在本公开的基础上，本领域技术人员可以容易地获得通讯信号到同步模拟信号的相应转换方法。
UART信号是未经同步时钟调制的UART信号，该信号的一帧一共可以传输11个比特位。参照图3中所示，这11个比特位包括1比特的起始位、8比特(1字节)的数据主体位(D0-D7)、1比特的奇偶检验位、1比特的终止位。
参照图4中所示，如果上述UART信号被二倍频的脉冲宽度调制(Pulse Width Modulation，PWM)时钟信号调制，调制后的一帧信号包括22比特位。
在一些实施例中，不参考同步时钟信号，通过算法根据UART信号生成SPI信号，并使得生成的SPI信号的信号格式和相关技术中UART信号参考同步时钟信号调制后所生成的调制后的UART信号的信号格式相同，即该SPI信号是符合家庭总线系统HBS协议的。
SPI信号中每4个字节可以对应UART信号的一帧，SPI信号的波特率等于UART信号的波特率的两倍，SPI信号模拟调制后的UART 信号。
转换后的SPI信号用来模拟调制后的UART信号，SPI信号的波特率需要等于UART信号的波特率的两倍。例如假设UART信号的波特率为9600bps，输出的SPI信号的波特率需要为19200bps。
SPI信号的每个SPI数据包可以是8、16、32比特位。假设选择8比特位作为一个SPI数据包，为了模拟一帧UART信号经调制后的22比特位就需要至少3个SPI数据包。SPI信号的字节与一帧UART信号的比特的对应转换可以通过查表来实现，通过查表其转换效率更高。或者，SPI信号的字节与一帧UART信号的比特的对应转换还可以通过本领域技术人员所知的任何其他方法例如软件编程来实现。
方式一、
在一些实施例，可以通过发送四个字节的SPI数据包，模拟UART信号一帧的有效数据。例如，如图5所示，在一个SPI数据包中，SPI信号的第一字节对应UART信号一帧数据的起始位，SPI信号的第二字节和第三字节对应UART信号的数据位，例如：SPI信号的第二字节对应UART信号一帧数据的数据主体位的第0比特(D0)至第3比特位(D3)，SPI信号的第三字节对应UART信号的第4比特位(D4)至第7比特位(D7)；SPI信号的第四字节对应UART信号的奇偶检验位和终止位。即，所述UART信号的起始位为第一组比特位，并对应所述SPI信号的第一字节；所述UART信号的数据主体位(D0-D7)的第0比特至第3比特位(D0-D3)为第二组比特位，并对应所述SPI信号的第二字节；所述UART信号的数据主体位的第4比特位至第7比特位(D4-D7)为第三组比特位，并对应所述SPI信号的第三字节；所述UART信号的奇偶检验位和所述终止位为第四组比特位，并对应所述SPI信号的第四字节。按上述分组方式，读取所述UART信号的一个消息帧的各组比特值，并通过查找调制翻译表得到对应的SPI信号。
以下五个数组为调制翻译表的翻译子表，用于通过UART信号的各组比特值来快速查找转换后的四个字节的SPI数据包。例如，假设UART信号为“0x00”，波特率为9600bps，则经转换后的SPI信号的 四个字节的SPI数据包包括：“0x01”+“0x55”+“0x55”+“0x40”，并且其波特率为19200bps。
第一组比特位即原始数据的起始位对应SPI数据包的第一个字节。因为所有数据的起始位均相同，所以第一个字节对应的数组table0[256]中的所有数据均为0x01。
在软件编程中，第一组比特位对应的翻译子表，即数组table0[256]表述如下：
const unsigned char TXnum_table0[256]＝{//第1字节
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//0～9
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//10～19
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//20～29
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//30～39
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//40～49
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//50～59
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//60～69
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//70～79
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//80～89
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//90～99
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//100～109
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//110～119
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//120～129
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//130～139
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//140～149
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//150～149
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//160～169
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//170～179
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//180～189
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//190～199
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//200～209
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//210～219
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//220～229
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//230～239
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//240～249
0x01,0x01,0x01,0x01,0x01,0x01//250～255
}；
即输入的UART信号的起始位为0，因此可以直接定义所有数组中与第一比特位对应数值为0x01。
第二组比特位即原始数据中的第0比特位至第3比特位D0、D1、D2、D3对应SPI数据的第二个字节。UART数据和SPI数据发送的数据顺序相反，因此数据转化时需要将原二进制数据左右颠倒。另外，如果使用PIC32MX350F256L芯片实现数据转化，使用MITSUMI生产的SOP MM1192通讯芯片(一种HBS通讯芯片)从同步模拟信号生成差分模拟信号，考虑到PIC32MX系列芯片SPI输出在空闲时是低电平,而MM1192的空闲信号输入要求是高电平,还需要一个三极管在输入MM1192之前进行电平反转。同时，数据转化时需要将原二进制数据进行数据反转，即“0”数据反转成“1”，“1”数据反转成“0”。在一些实施例中，输出SPI信号的芯片和后端的接收SPI信号的芯片空闲时的电平相同，因此可以不进行电平反转。此部分数据转化的实现可以使用Turbo C软件编程，或者预先编制翻译子表并通过查表获得。第二组比特位对应的翻译子表，即数组Table1[256]表述如下：
const unsigned char TXnum_table1[256]＝{//第二字节
0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,//0～9
0x44,0x4,0x50,0x10,0x40,0x0,0x55,0x15,0x45,0x5,//10～19
0x51,0x11,0x41,0x1,0x54,0x14,0x44,0x4,0x50,0x10,//20～29
0x40,0x0,0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,//30～39
0x54,0x14,0x44,0x4,0x50,0x10,0x40,0x0,0x55,0x15,//40～49
0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,0x44,0x4,//50～59
0x50,0x10,0x40,0x0,0x55,0x15,0x45,0x5,0x51,0x11,//60～69
0x41,0x1,0x54,0x14,0x44,0x4,0x50,0x10,0x40,0x0,//70～79
0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,//80～89
0x44,0x4,0x50,0x10,0x40,0x0,0x55,0x15,0x45,0x5,//90～99
0x51,0x11,0x41,0x1,0x54,0x14,0x44,0x4,0x50,0x10,//100～109
0x40,0x0,0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,//110～119
0x54,0x14,0x44,0x4,0x50,0x10,0x40,0x0,0x55,0x15,//120～129
0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,0x44,0x4,//130～139
0x50,0x10,0x40,0x0,0x55,0x15,0x45,0x5,0x51,0x11,//140～149
0x41,0x1,0x54,0x14,0x44,0x4,0x50,0x10,0x40,0x0,//150～159
0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,//160～169
0x44,0x4,0x50,0x10,0x40,0x0,0x55,0x15,0x45,0x5,//170～179
0x51,0x11,0x41,0x1,0x54,0x14,0x44,0x4,0x50,0x10,//180～189
0x40,0x0,0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,//190～199
0x54,0x14,0x44,0x4,0x50,0x10,0x40,0x0,0x55,0x15,//200～209
0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,0x44,0x4,//210～219
0x50,0x10,0x40,0x0,0x55,0x15,0x45,0x5,0x51,0x11,//220～229
0x41,0x1,0x54,0x14,0x44,0x4,0x50,0x10,0x40,0x0,//230～239
0x55,0x15,0x45,0x5,0x51,0x11,0x41,0x1,0x54,0x14,//240～249
0x44,0x4,0x50,0x10,0x40,0x00//250～255
}；
第三组比特位即原始数据中的数据主体位的第4比特位至第7比特位D4、D5、D6、D7，对应SPI数据的第三个字节。数组Table2[256]用于存储第三组比特位的转化数据。此部分的转化和Table1[256]相似。第三组比特位对应的翻译子表，即数组Table2[256]表述如下：
const unsigned char TXnum_table2[256]＝{//第三字节
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,//0～9
0x55,0x55,0x55,0x55,0x55,0x55,0x15,0x15,0x15,0x15,//10～19
0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,//20～29
0x15,0x15,0x45,0x45,0x45,0x45,0x45,0x45,0x45,0x45,//30～39
0x45,0x45,0x45,0x45,0x45,0x45,0x45,0x45,0x5,0x5,//40～49
0x5,0x5,0x5,0x5,0x5,0x5,0x5,0x5,0x5,0x5,//50～59
0x5,0x5,0x5,0x5,0x51,0x51,0x51,0x51,0x51,0x51,//60～69
0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,//70～79
0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x11,//80～89
0x11,0x11,0x11,0x11,0x11,0x11,0x41,0x41,0x41,0x41,//90～99
0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,//100～109
0x41,0x41,0x1,0x1,0x1,0x1,0x1,0x1,0x1,0x1,//110～119
0x1,0x1,0x1,0x1,0x1,0x1,0x1,0x1,0x54,0x54,//120～129
0x54,0x54,0x54,0x54,0x54,0x54,0x54,0x54,0x54,0x54,//130～139
0x54,0x54,0x54,0x54,0x14,0x14,0x14,0x14,0x14,0x14,//140～149
0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,//150～159
0x44,0x44,0x44,0x44,0x44,0x44,0x44,0x44,0x44,0x44,//160～169
0x44,0x44,0x44,0x44,0x44,0x44,0x4,0x4,0x4,0x4,//170～179
0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,//180～189
0x4,0x4,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,//190～199
0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x50,0x10,0x10,//200～209
0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,//210～219
0x10,0x10,0x10,0x10,0x40,0x40,0x40,0x40,0x40,0x40,//220～229
0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,//230～239
0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,//240～249
0x0,0x0,0x0,0x0,0x0,0x0//250～255
}；
第四组比特位即原始数据中的奇检验位和终止位，对应SPI数据中的第四个字节。如果奇偶检验采用奇校验，则第四组比特位对应的翻译子表，即数组Table3_1[256]表述如下：
const unsigned char TXnum_table3_1[256]＝{//第四字节奇校验 列表
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,//0～9
0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//10～19
0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,//20～29
0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//30～39
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,//40～49
0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,//50～59
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,//60～69
0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//70～79
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,//80～89
0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,//90～99
0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,//100～109
0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//110～119
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,//120～129
0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,//130～139
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,//140～149
0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//150～159
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,//160～169
0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//170～179
0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,//180～189
0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//190～199
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,//200～209
0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,//210～219
0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,//220～229
0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//230～239
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,//240～249
0x0,0x40,0x0,0x40,0x40,0x00//250～255
}；
如果奇偶检验采用偶校验，则第四组比特位对应的翻译子表， 即数组Table3_2[256]表述如下：
const unsigned char TXnum_table3_2[256]＝{//第四字节
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,//0～9
0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//10～19
0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,//20～29
0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//30～39
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,//40～49
0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,//50～59
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,//60～69
0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//70～79
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,//80～89
0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,//90～99
0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,//100～109
0x0,0x40,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//110～119
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,//120～129
0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,//130～139
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,//140～149
0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,//150～159
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,//160～169
0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//170～179
0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,//180～189
0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//190～199
0x0,0x40,0x40,0x0,0x40,0x0,0x0,0x40,0x0,0x40,//200～209
0x40,0x0,0x40,0x0,0x0,0x40,0x40,0x0,0x0,0x40,//210～219
0x0,0x40,0x40,0x0,0x0,0x40,0x40,0x0,0x40,0x0,//220～229
0x0,0x40,0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,//230～239
0x40,0x0,0x0,0x40,0x0,0x40,0x40,0x0,0x0,0x40,//240～249
0x40,0x0,0x40,0x0,0x0,0x40//250～255
}。
上述原始数据中，实际上是8bit的数据主体位独占了两个完整的字节。在一些实施例中，根据预设的调制翻译表将UART信号进行转化生成SPI信号，其中，SPI信号包括4个字节，SPI信号的第一个字节中的前6个数据位为空，第四个字节中的后四个字节为空，空字节可以赋值为0，预设的调制翻译表中存储有预设关系，预设关系用于将UART信号的起始位转换为SPI信号的第一个字节中的后两个数据位，将UART信号的D0-D3数据位转换为左右颠倒并进行数据反转后生成SPI信号的第二个字节，将UART信号的D4-D7数据位转换为左右颠倒并进行数据反转后生成SPI信号的第三个字节，将UART信号的奇偶校验位和停止位转换成第四个字节中的前四个字节。
在一些实施例中，将UART信号的起始位转换为SPI信号的第一个字节中的后两个数据位，即第一字节数据为0x01。
方式二、
如图6所示，在另一些实施例，SPI信号的第一字节对应UART信号一帧数据的起始位和数据主体位的D0比特位至D2比特位)，SPI信号的第二字节对应数据主体位的D3比特位至D6比特位)，SPI信号的第三字节对应数据主体位的D7比特位、奇偶检验位和终止位。即，所述起始位和所述数据主体位的D0比特至D2比特位为第一组比特位，并对应所述SPI信号的第一字节；所述数据主体位的D3比特至D6比特位为第二组比特位，并对应所述SPI信号的第二字节；所述数据主体位的D7比特位、所述奇偶检验位和所述终止位为第三组比特位，并对应所述SPI信号的第三字节。
另外，可选的，为了保证数据的准确性，可以再加上一个字节的延时，即SPI信号的第四字节用于延时。
按上述分组方式，读取所述UART信号的一个消息帧的各组比特值，并通过例如查找调制翻译表的方法得到对应的SPI信号。方式二的数据转化与方式一大致类似，只是调制翻译表存在不同。
步骤102中通过软件的方法实现数据格式的转换，模拟符合家 庭总线系统HBS协议的信号，即通过步骤102得到的同步模拟信号具有与相关技术中调制后的UART信号一致的信号格式，从而可支持HBS通讯。
步骤103中可以通过HBS通讯芯片，将所述同步模拟信号转化为差分模拟信号。HBS通讯芯片支持HBS通讯，例如HBS通讯芯片可以是MITSUMI生产的SOP MM1192通讯芯片。例如，在一些实施例中，执行数据转换的芯片可以是Microchip芯片；Microchip芯片通过SPI输出管脚发送SPI信号，该SPI信号用作MM1192通讯芯片的输入以获取差分模拟信号。
参照图7中所示，显示了UART信号经过转换后得到SPI信号，并且最后通过HBS通讯芯片12生成差分模拟HB信号。
本公开的一些实施例还提供一种信号转换装置。如图8所示，所述信号转换装置10包括：控制芯片11和HBS通讯器12，控制芯片11配置为将通讯信号转换为同步模拟信号，所述同步模拟信号符合家庭总线系统HBS协议；HBS通讯器12配置为将所述同步模拟信号转化为差分模拟信号。参考图8所示，控制芯片11例如可以是Microchip芯片以及实现类似功能的芯片或电路，HBS通讯器12例如可以是HBS通讯芯片以及实现类似功能的芯片或电路，HBS通讯芯片例如可以是MM1192通讯芯片。
如图9所示，在本公开的一些实施例中，所述控制芯片11包括处理器1101和存储器1102；处理器1101配置为通过查找预先设置的调制翻译表，将所述通讯信号转换为所述同步模拟信号；存储器1102配置为存储所述调制翻译表。其中，所述调制翻译表包括所述通讯信号与符合家庭总线系统HBS协议的同步模拟信号的对应关系。
如图10所示，在本公开的一些实施例中，所述处理器1101包括获取模块1101a和模拟模块1101b。获取模块1101a配置为按预设的分组方式，读取所述通讯信号的一个消息帧的各组比特值，其中，所述消息帧的一组比特值包括所述消息帧的一位或多位比特位的取值。例如，未经同步时钟调制的UART信号的一帧包括11个比特位， 一种预设的分组方式可以为：起始位为第一组比特位，数据主体位的第0比特至第3比特位为第二组比特位，所述数据主体位的第4比特位至第7比特位为第三组比特位，所述奇偶检验位和所述终止位为第四组比特位。模拟模块1101b配置为通过查找所述调制翻译表，将读取到的每组比特值转换为所述同步模拟信号的一个字节；其中，所述调制翻译表包括多个翻译子表，每个翻译子表包括一组比特位的所有可能取值到所述同步模拟信号的对应字节的映射。对一组比特值，通过查找对应的翻译子表，可以获得转化为同步模拟信号后的对应数据，通常是同步模拟信号的一个字节。
在本公开的一些实施例中，参考图11所示，所述控制芯片11包括串行外设接口(Serial Peripheral Interface，SPI)，所述串行外设接口的输出管脚TX配置为输出经过数据转化的同步模拟信号；所述HBS通讯器12为HBS通讯芯片，HBS通讯芯片12包括输入管脚IN，所述输入管脚IN配置为接收所述同步模拟信号。HBS通讯芯片12根据同步模拟信号生成用于HBS通讯的差分模拟信号。
如果控制芯片11在空闲时是低电平,而HBS通讯芯片12的空闲信号输入要求是高电平，则需要设置电平转换器13进行电平反转，以匹配所述HBS通讯芯片的输入管脚IN的要求。如图11所示，在本公开的一些实施例中，所述串行外设接口的输出管脚TX通过所述电平转换器13连接到所述HBS通讯芯片的输入管脚IN；所述电平转换器13配置为所述串行外设接口的输出管脚TX输出的所述同步模拟信号进行电平反转，以匹配所述HBS通讯芯片的输入管脚IN的要求。在本公开的另一些实施例中，控制芯片11的空闲电平与HBS通讯芯片12的空闲电平相同，例如都是低电平或都是高电平，则控制芯片11与通讯芯片12之间不存在电平转换器13。
在本公开的一些实施例中，参照图11中所示，控制芯片11例如为Microchip芯片，HBS通信器12为HBS通信芯片，电平转换器13包括三极管Q1、电阻R1和电容C1。Microchip芯片11包括通用异步收发传输器(Universal Asynchronous Receiver/Transmitter， UART)输入管脚RX、串行外设接口(Serial Peripheral Interface，SPI)输出管脚TX和中断管脚INT，HBS通信芯片12包括输入管脚IN。
Microchip芯片11的UART输入管脚RX和中断管脚INT相连，UART输入管脚RX配置为接收信号。SPI的输出管脚TX配置为输出信号，即欲发送的通讯信号在Microchip芯片11中先转换成SPI信号输出，SPI信号的信号格式符合家庭总线系统HBS协议。SPI信号经过电平转换器13输入HBS通信芯片12。HBS通信芯片12通过采集输入管脚IN所在总线上的信号，最终输出模拟差分信号。
Microchip芯片11的SPI输出管脚TX连接至三极管Q1的基极B以及电容C1的第一端。三极管Q1的集电极C连接至电阻R1的第一端以及HBS通信芯片12的输入管脚IN。三极管Q1的发射极E接地，电阻R1的第二端连接至正电压电源信号VCC(例如5V)，电容C1的第二端接地。
例如，Microchip芯片11可以是PIC32MX芯片，HBS通信芯片12可以采用MM1192通讯芯片。由于PIC32MX系列芯片的SPI输出管脚TX在空闲时是低电平，而MM1192的输入管脚IN的空闲信号输入要求是高电平，所以三极管Q1用于在SPI信号输入MM1192之前进行电平反转。R1作为三极管Q1的上拉电阻，C1为滤波电容。
参照图12中所示，在本公开的一些实施例中，所述控制芯片11采用同步发送异步接收的方式通讯。所述控制芯片11的第一逻辑通讯端口113的输入管脚RX配置为UAPT信号接收端口，所述控制芯片的第一逻辑通讯端口113的输出管脚TX配置为SPI信号发送端口。在硬件设计时需要注意，对一些芯片而言，与SPI总线匹配的串行时钟线(Serial Clock，SCK)端口可能自动生效，这种情况下SCK端口不可再用做其它输入输出(I/O)。
在本公开的一些实施例中，如图13所示，所述控制芯片11的第二逻辑通讯端口111的输入管脚RX配置为UART信号接收端口，第二逻辑通讯端口111的输出管脚TX0配置为接地；所述第三逻辑通讯端口112的输出管脚TX配置为SPI信号发送端口，所述第三逻辑通 讯端口112的输入管脚RX0配置为接地。该设计实现了HBS同时发送同时接收；避免了定时器模拟叠加频繁进入中断的问题；无需考虑送信数据和送信时钟边沿难以对齐的问题；另外，送信采用数据模拟，解决了SPI信号以及起始位、停止位和校验位与普通UART信号不同的问题。
例如，在本公开的一些实施例中，可使用控制芯片的一个UART的接收端口接收信号并将该接收端口配置成独立接收，该UART的发送端口仍然可以作为其它功能使用；使用控制芯片的一个SPI的发送端口发送信号并将该发送端口配置成独立发送，SPI的接收端口仍然可以作为其它功能使用。
本公开实施例还提供了一种家庭总线系统HBS电路，应用于通过Microchip芯片实现家庭总线HB通信，参照图11所示，所述电路包括：Microchip芯片11、HBS通讯芯片12、电阻R、电容C1和三极管Q1。这些元件的连接关系可参照上面的描述，不再赘述。
所述Microchip芯片11通过所述UART输入管脚接收UART信号。所述Microchip芯片11配置为将UART信号转换为SPI信号，其中，所述SPI信号中每4个字节对应所述UART信号的一帧，所述SPI信号的波特率等于所述UART信号的波特率的两倍，所述SPI信号符合家庭总线系统HBS协议。所述Microchip芯片11通过所述SPI输出管脚发送所述SPI信号。所述HBS通讯芯片12配置为接收所述SPI信号并输出差分模拟信号。
在本公开的一些实施例中，所述Microchip芯片11配置为通过以下方式将所述UART信号转换为SPI信号：将所述UART信号中数据位的比特值“0”对应转换为所述SPI信号中数据位的两位比特值“0,1”；将所述UART信号中数据位的比特值“1”对应转换为所述SPI信号中数据位的两位比特值“1,1”。
在一些实施例中，符合HBS协议是指存在“0”“1”之间的跳变，HBS通讯芯片可以通过“0”“1”之间的跳变来触发差分信号的 脉冲。
在本公开的一些实施例中，所述Microchip芯片不具有同步时钟I/O端口，也无模拟外部同步时钟的电路，即所述Microchip芯片11数据转化时不参考同步时钟信号。
本公开实施例还提供了一种信号转换方法，应用于图11所示电路，参照图14中所示，该方法包括：
201、Microchip芯片通过UART输入管脚接收UART信号，其中，UART信号未经同步时钟调制。
202、Microchip芯片将UART信号转换为SPI信号，其中，SPI信号中每4个字节对应UART信号的一帧，SPI信号的波特率等于UART信号的波特率的两倍，SPI信号符合家庭总线系统HBS协议。
203、Microchip芯片通过SPI输出管脚发送SPI信号，该SPI信号用作HBS通信芯片的输入以获取差分模拟HB信号。
本申请实施例提供的信号转换方法，通过Microchip芯片将输入的UART信号按照字节转换为SPI信号，使SPI信号符合家庭总线系统HBS协议。SPI信号用作HBS通讯芯片的输入，最终HBS通讯芯片输出差分模拟HB信号，实现了家庭总线HomeBus通讯。
本申请实施例提供了一种信号转换装置，应用于上述方法，用于实现通过Microchip芯片实现家庭总线HB通信，参照图15中所示，该装置包括：
接收单元1103，用于通过UART输入管脚接收UART信号，其中，UART信号未经同步时钟调制。
转换单元1104，用于将接收单元1103接收的UART信号转换为SPI信号，其中，SPI信号中每4个字节对应UART信号的一帧，SPI信号的波特率等于UART信号的波特率的两倍，SPI信号符合家庭总线系统HBS协议。
发送单元1105，用于通过SPI输出管脚发送转换单元1104所转换的SPI信号，SPI信号用作HBS通信芯片的输入以获取差分模拟HB信号。
本公开的一些实施例还提供一种家庭总线系统HBS电路，包括上面所述的任一信号转换装置。本公开实施例提供的家庭总线系统HBS电路可使用不具有同步时钟信号输出的控制芯片，例如Microchip芯片。
本公开的一些实施例还提供一种用户设备，包括家庭总线系统HBS电路或者所述的任一信号转换装置。所述用户设备还可以是空调、冰箱、洗衣机、电视机、厨房电器等智能家居产品。例如，所述用户设备可以是多联机空调产品。所述用户设备还可以是手机、游戏设备等电子设备或者任何有可能接入HBS通讯网络或类似通讯网络的设备。此处的类似通讯网络指的是通讯需要同步时钟信号才能进行的通讯网络。
本公开实施例提供一种控制器，该控制器包括：存储器，用于存储计算机程序；处理器，用于执行所述计算机程序，以实现如下所述的方法：
101、获取欲发送的通讯信号；
102、通过控制芯片，将所述通讯信号转换为同步模拟信号，该同步模拟信号符合家庭总线系统HBS协议；
103、将所述同步模拟信号转化为差分模拟信号。
本公开实施例提供一种计算机存储介质，包括：所述计算机存储介质用于存储计算机程序，所述计算机程序执行时用于实现如下所述的方法：
101、获取欲发送的通讯信号；
102、通过控制芯片，将所述通讯信号转换为同步模拟信号，该同步模拟信号符合家庭总线系统HBS协议；
103、将所述同步模拟信号转化为差分模拟信号。
本公开实施例提供一种计算机程序产品，所述计算机程序产品包含指令，所述指令在计算机上运行时，用于实现如下所述的方法：
101、获取欲发送的通讯信号；
102、通过控制芯片，将所述通讯信号转换为同步模拟信号，该同步模拟信号符合家庭总线系统HBS协议；
103、将所述同步模拟信号转化为差分模拟信号。
由于本公开实施例中的装置可以应用于上述方法，因此，其所能获得的技术效果也可参考上述方法实施例，本公开实施例在此不再赘述。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、设备、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
上述获取模块和模拟模块可以为单独设置，也可以一起集成在控制器的某一个处理器中实现，此外，也可以以程序代码的形式存储于控制器的存储器中，由控制器的某一个处理器调用并执行以上各模块的功能。这里所述的处理器可以是一个中央处理器(Central Processing Unit，CPU)，或者是特定集成电路(Application Specific Integrated Circuit，ASIC)，或者是被配置成实施本公开实施例的一个或多个集成电路。
在本公开的各种实施例中，上述各步骤的序号的大小并不意味着执行顺序的先后，各步骤的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的功能模块及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本公开的范围。
在本公开所提供的几个实施例中，应该理解到，所揭露的系统、设备、装置和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述功能模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个功能 模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或功能模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的功能模块、单元或组件可以是或者也可以不是物理上分开的，作为组件显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能模块或元件可以集成在一个单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
本公开实施例所描述的方法或者算法的步骤可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read only memory，ROM)、可擦除可编程只读存储器(erasable programmable ROM，EPROM)、电可擦可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。处理器可以是中央处理单元(CPU)、现场可编程逻辑阵列(FPGA)、单片机(MCU)、特定功能应用电路(ASIC)等具有逻辑运算能力和/或程序执行能力的器件。
当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计 算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(Digital Subscriber Line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质或者半导体介质等。
在本公开实施例中，在发生数据、信息等的通讯时，可通过网络连接进行直接或间接地通信。例如，网络可以包括无线网络、有线网络、和/或无线网络和有线网络的任意组合。网络可以包括局域网、互联网、电信网、基于互联网和/或电信网的物联网、和/或以上网络的任意组合等。有线网络例如可以采用双绞线、同轴电缆或光纤等传输方式进行通信，无线网络例如可以采用3G/4G/5G移动通信网络、蓝牙、Zigbee或者WiFi等通信方式。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种家庭总线系统HBS电路，应用于通过Microchip芯片实现家庭总线HB通信，所述电路包括：Microchip芯片、HBS通讯芯片、电阻、电容和三极管，所述Microchip芯片包括通用异步收发传输器UART输入管脚和串行外设接口SPI输出管脚，所述HBS通讯芯片包括输入管脚；
    所述SPI输出管脚连接至所述三极管的基极、所述电容的第一端，所述三极管的集电极连接至所述电阻的第一端以及所述HBS通讯芯片的输入管脚，所述三极管的发射极接地，所述电阻的第二端连接至电源，所述电容的第二端接地。
  2. 根据权利要求1所述的家庭总线系统HBS电路，其中，
    所述Microchip芯片通过所述UART输入管脚接收UART信号；
    所述Microchip芯片配置为将所述UART信号转换为SPI信号，其中，所述SPI信号中每4个字节对应所述UART信号的一帧，所述SPI信号的波特率等于所述UART信号的波特率的两倍，所述SPI信号符合家庭总线系统HBS协议；所述Microchip芯片通过所述SPI输出管脚发送所述SPI信号；
    所述HBS通讯芯片配置为接收所述SPI信号并输出差分模拟信号。
  3. 根据权利要求2所述的家庭总线系统HBS电路，其中，所述Microchip芯片配置为通过以下方式将所述UART信号转换为SPI信号：
    将所述UART信号中数据位的比特值“0”对应转换为所述SPI信号中数据位的两位比特值“01”；
    将所述UART信号中数据位的比特值“1”对应转换为所述SPI信号中数据位的两位比特值“11”。
  4. 根据权利要求2所述的家庭总线系统HBS电路，其中，所述UART信号的一帧包括起始位、数据主体位、校验位和终止位，所述数据主体位包括8位数据位D0、D1、D2、D3、D4、D5、D6、D7；
    所述Microchip芯片配置为，将所述起始位转换为SPI信号的第一个字节的最后两个数据位，将所述D0、D1、D2、D3数据位转换为SPI 信号的第二个字节，将所述D4、D5、D6、D7数据位转换为SPI信号的第三个字节，将所述校验位和终止位转换为SPI信号的第四个字节前四个数据位。
  5. 根据权利要求4所述的家庭总线系统HBS电路，其中，所述Microchip芯片配置为，使所述SPI信号的第一个字节的前六个数据位为0，使所述SPI信号的第四个字节的后四个数据位为0。
  6. 根据权利要求2所述的家庭总线系统HBS电路，其中，所述UART信号的一帧包括起始位、数据主体位、校验位和终止位，所述数据主体位包括8位数据位D0、D1、D2、D3、D4、D5、D6、D7；
    所述Microchip芯片配置为，将所述起始位、D0、D1、D2转换为SPI信号的第一个字节，将所述D3、D4、D5、D6数据位转换为SPI信号的第二个字节，将所述D7、校验位和终止位转换为SPI信号的第三个字节的前六个数据位。
  7. 根据权利要求6所述的家庭总线系统HBS电路，其中，所述Microchip芯片配置为，使所述SPI信号的第三个字节的后两个数据位为0，使所述SPI信号的第四个字节的全部数据位为0。
  8. 根据权利要求1所述的家庭总线系统HBS电路，其中，所述Microchip芯片不具有同步时钟I/O端口。
  9. 一种信号转换装置，包括：
    控制芯片，配置为将欲发送的通讯信号转换为同步模拟信号，所述同步模拟信号符合家庭总线系统HBS协议；
    HBS通讯器，配置为将所述同步模拟信号转化为用于HBS通讯的差分模拟信号。
  10. 根据权利要求9所述的信号转换装置，其中，所述控制芯片包括：
    处理器，配置为通过查找预先设置的调制翻译表，将所述通讯信号转换为所述同步模拟信号；
    存储器，配置为存储所述调制翻译表，所述调制翻译表包括所述通讯信号与所述同步模拟信号的对应关系。
  11. 根据权利要求10所述的信号转换装置，其中，所述处理器包括：
    获取模块，配置为按预设的分组方式，读取所述通讯信号的一个消息帧的各组比特值，其中，所述消息帧的一组比特值包括所述消息帧的一位或多位比特位的取值；
    模拟模块，配置为通过查找所述调制翻译表，将读取到的每组比特值转换为所述同步模拟信号的一个字节；其中，所述调制翻译表包括多个翻译子表，每个翻译子表包括一组比特位的所有可能取值到所述同步模拟信号的对应字节的映射。
  12. 根据权利要求9所述的信号转换装置，其中，所述通讯信号为符合UART通信协议的UART信号，所述同步模拟信号为符合SPI通信协议的SPI信号；所述控制芯片配置为通过以下方式将所述UART信号转换为SPI信号：
    将所述UART信号中数据位的比特值“0”对应转换为所述SPI信号中数据位的两位比特值“01”；
    将所述UART信号中数据位的比特值“1”对应转换为所述SPI信号中数据位的两位比特值“11”。
  13. 根据权利要求9所述的信号转换装置，其中，所述控制芯片包括串行外设接口，所述串行外设接口的输出管脚配置为输出所述同步模拟信号；
    所述HBS通讯芯片包括输入管脚，所述输入管脚配置为接收所述同步模拟信号。
  14. 根据权利要求13所述的信号转换装置，其中，还包括电平转换器，
    所述串行外设接口的输出管脚通过所述电平转换器连接到所述HBS通讯芯片的输入管脚；
    所述电平转换器配置为所述串行外设接口的输出管脚输出的所述同步模拟信号进行电平反转，以匹配所述HBS通讯芯片的输入管脚的要求。
  15. 根据权利要求14所述的信号转换装置，其中，所述电平转换器包括：三极管、电阻和电容，其中，
    所述三极管的基极连接至所述串行外设接口的输出管脚以及所述电容的第一端，所述电阻的第二端连接至电源，所述三极管的发射极接地，所述三极管的集电极连接至所述电阻的第一端以及所述HBS通讯芯片的输入管脚，所述电容的第二端接地。
  16. 根据权利要求15所述的信号转换装置，其中，所述控制芯片采用同步发送异步接收的方式通讯；
    所述控制芯片的第一逻辑通讯端口的输入管脚配置为UART信号接收端口，所述控制芯片的第一逻辑通讯端口的输出管脚配置为SPI信号发送端口；或者，
    所述控制芯片的第二逻辑通讯端口的输入管脚配置为UART信号接收端口，第二逻辑通讯端口的输出管脚配置为接地；所述第三逻辑通讯端口的输出管脚配置为SPI信号发送端口，所述第三逻辑通讯端口的输入管脚配置为接地。
  17. 根据权利要求9所述的信号转换装置，其中，所述HBS通讯器为HBS通讯芯片。
  18. 根据权利要求9所述的信号转换装置，其中，所述控制芯片不具有同步时钟I/O端口。
  19. 一种家庭总线系统HBS电路，包括权利要求9-18任一项所述的信号转换装置。
  20. 一种用户设备，包括权利要求19任一项所述的信号转换装置，或者包括权利要求1-4任一项所述的家庭总线系统HBS电路。
  21. 一种信号转换方法，包括：
    获取欲发送的通讯信号；
    将所述通讯信号转换为符合家庭总线系统HBS协议的同步模拟信号；
    将所述同步模拟信号转化为差分模拟信号。
  22. 根据权利要求21所述的方法，其中，将所述通讯信号转换为 符合家庭总线系统HBS协议的同步模拟信号时没有参考同步时钟信号。
  23. 根据权利要求21所述的方法，其中，
    所述通讯信号为符合UART通信协议的UART信号，所述同步模拟信号为符合SPI通信协议的SPI信号；
    所述SPI信号中每4个字节对应所述UART信号的一个字节，所述SPI信号的波特率等于所述UART信号的波特率的两倍。
  24. 根据权利要求23所述的方法，其中，所述UART信号的一帧包括1比特的起始位、8比特的数据主体位、1比特的奇偶检验位、1比特的终止位，8比特的有效数据主体位包括D0、D1、D2、D3、D4、D5、D6、D7；其中，所述起始位和所述数据主体位的D0、D1、D2对应所述SPI信号的第一字节，所述数据主体位的D3、D4、D5、D6对应所述SPI信号的第二字节所述数据主体位的D7、所述奇偶检验位和所述终止位对应所述SPI信号的第三字节，
    所述SPI信号的第四字节设置为延时字节。
  25. 根据权利要求24所述的方法，其中，所述D7、校验位和终止位数据位对应SPI信号的第三个字节的前六个数据位。
  26. 根据权利要求25所述的方法，其中，所述SPI信号的第三个字节的后两个数据位为0，使所述SPI信号的第四个字节的全部数据位为0。
  27. 根据权利要求23所述的方法，其中，所述UART信号的一帧包括1比特的起始位、8比特的数据主体位、1比特的奇偶检验位、1比特的终止位，8比特的数据主体位包括D0、D1、D2、D3、D4、D5、D6、D7；
    所述起始位对应所述SPI信号的第一字节，所述数据主体位的D0、D1、D2、D3对应所述SPI信号的第二字节，所述数据主体位的D4、D5、D6、D7对应所述SPI信号的第三字节，所述奇偶检验位和所述终止位对应所述SPI信号的第四字节。
  28. 根据权利要求27所述的方法，其中，所述起始位对应为SPI信号的第一个字节的最后两个数据位，所述校验位和终止位对应为SPI 信号的第四个字节前四个数据位。
  29. 根据权利要求28所述的方法，其中，所述SPI信号的第一个字节的前六个数据位为0，使所述SPI信号的第四个字节的后四个数据位为0。
  30. 根据权利要求24所述的方法，其中，所述对应是指通过查找调制翻译表的方式进行转换，所述调制翻译表包括所述UART信号与所述SPI信号的对应关系。
  31. 根据权利要求24所述的方法，其中，所述对应是将所述UART信号中的“0”数据位转换成SPI信号中的“0,1”两个数据位，将所述UART信号中的“1”数据位转换成SPI信号中的“1,1”两个数据位。
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