WO2019058874A1 - 仮想化システム、仮想化プログラム、及び、記憶媒体 - Google Patents

仮想化システム、仮想化プログラム、及び、記憶媒体 Download PDF

Info

Publication number
WO2019058874A1
WO2019058874A1 PCT/JP2018/031416 JP2018031416W WO2019058874A1 WO 2019058874 A1 WO2019058874 A1 WO 2019058874A1 JP 2018031416 W JP2018031416 W JP 2018031416W WO 2019058874 A1 WO2019058874 A1 WO 2019058874A1
Authority
WO
WIPO (PCT)
Prior art keywords
core
hardware
data
unit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/031416
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
正剛 隈部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of WO2019058874A1 publication Critical patent/WO2019058874A1/ja
Priority to US16/816,813 priority Critical patent/US11494221B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45541—Bare-metal, i.e. hypervisor runs directly on hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • the present disclosure relates to a virtualization system, a virtualization program, and a storage medium that cause a computer to virtually operate as a plurality of computers by operating a plurality of guest OSs on a computer having an entity.
  • a virtual computer is a computer formed by logically dividing a computer having an entity (a so-called physical computer), and is also called a virtual machine or a logical computer.
  • the guest OS is basic software that implements a virtual computer.
  • the type of virtualization system includes a hypervisor type virtualization system and a host OS type virtualization system.
  • the hypervisor type virtualization system is a virtualization system of a method of operating a guest OS on a virtualization dedicated OS (a so-called hypervisor).
  • the hypervisor operates directly on hardware and controls allocation of computing resources to the guest OS and access to hardware (so-called peripherals) by the guest OS.
  • the hardware here corresponds to the physical layer for the OS.
  • the hardware includes a configuration (so-called I / O device) for converting a logic signal into an actual electrical signal in an interface such as Ethernet (registered trademark) or UART (a so-called I / O device), a flash memory, a hard disk, and the like.
  • I / O devices that support various communication standards are often implemented as chipsets (so-called PHY chips).
  • the host OS type virtualization system is a virtualization system in which another OS (that is, a guest OS) is virtually operated as an application on the host OS.
  • the host OS is basic software that operates on a physical computer.
  • the host OS can also execute applications other than the application for operating the guest OS (virtualized application).
  • the virtualization application of the host OS also plays a role in controlling access to hardware by the guest OS. That is, the virtualization application included in the host OS is also software that provides the same function as the hypervisor.
  • each guest OS is provided with a device driver for using various hardware, and uses the device driver to use the hardware.
  • the guest OS and the hardware are associated 1: 1 by the hypervisor, and the other guest OS can not be used.
  • Patent Document 1 discloses a host side communication means for performing data input / output by serial port communication on a host OS in order to improve the stability of serial port communication between the host OS and a guest OS as a host OS type virtualization system. And guest side communication means for inputting and outputting data by serial port communication on the guest OS, and communication path securing means for establishing a communication path between the host side communication means and the guest side communication means simultaneously with activation of the guest OS.
  • a virtualization system is disclosed.
  • the configuration described in Patent Document 1 corresponds to a configuration in which a guest OS and a hypervisor are communicably connected to each other by a communication pipe conforming to a predetermined communication standard.
  • a hypervisor In a conventional virtualization system, allocation of computing resources to virtual machines and access to hardware by virtual machines are controlled by a hypervisor. In addition, when a certain virtual machine uses a certain hardware, the virtual machine and the hardware are associated 1: 1 by the hypervisor, and the other virtual machines can not be used.
  • the present disclosure aims to provide a virtualization system, a virtualization program, and a storage medium capable of suppressing a delay in communication between a virtual computer and hardware.
  • a virtualization system is a virtualization system in which a plurality of virtual machines operate on a single physical machine having a plurality of cores, and a plurality of hardware and a plurality of hardware are used.
  • a hardware control core which is a core for controlling each operation, a plurality of virtual machine cores which are cores for operating a guest OS which is an OS of a virtual machine, a hardware control core and a plurality of virtual machine cores
  • one virtual computer is set to operate exclusively using one or more virtual computer cores, and each of the plurality of virtual computers is configured to operate in parallel.
  • the core controls the operation of multiple hardware by executing device drivers corresponding to each of the multiple hardware.
  • a driver unit is provided, and communication between the hardware control core and the virtual machine core is realized by storing data in the shared memory and reading out the stored data, and the device driver unit uses data stored in the shared memory by the virtual machine. While controlling the operation of the hardware based on it, the data input from the hardware is provided to the virtual computer core by storing it in the shared memory.
  • each virtual computer core can store data in the shared memory at any timing.
  • the device driver unit also operates hardware based on data from the virtual machine core acquired by memory access. Therefore, each virtual machine core can use desired hardware at any timing.
  • one virtual computer core is not shared by multiple guest OSs (in other words, virtual computers). That is, each virtual machine operates by exclusively using one or more cores. Each virtual computer can freely use the computing resources of the virtual computer core allocated to itself regardless of the operating conditions of other virtual computers.
  • each virtual computer can operate using the calculation resources of its own dedicated core and can use desired hardware at an arbitrary timing.
  • the risk of delay in communication between the virtual computer and the hardware can be reduced.
  • a virtualization program is a program that causes a physical computer including a plurality of cores, a physical layer including a plurality of hardware, and a random access memory to operate as a virtualization system.
  • a shared memory setting unit set in the memory stores a program (that is, a virtualization program) for causing a computer to function as the above-described virtualization system.
  • FIG. 1 is a diagram illustrating an example of a hardware configuration and a software configuration of an electronic control unit (ECU) to which a virtualization system according to the present disclosure is applied.
  • the ECU 1 is mounted on a vehicle and connected to a network built in the vehicle.
  • the ECU 1 is configured as one physical computer, and includes a processor 10 including four cores 11 as shown in FIG. 1, a shared memory unit 12, and a plurality of hardware 13a to 13d.
  • a processor 10 including four cores 11 as shown in FIG. 1, a shared memory unit 12, and a plurality of hardware 13a to 13d.
  • FIG. 1 exemplifies a mode in which the core 11 to which the label of Core 0 is given is taken as the core 11 x as an example.
  • the various hardwares 13a to 13d are not distinguished from one another, they are simply described as hardware 13.
  • PHY in the figure is a label indicating that it is hardware 13. Illustration of control lines and information lines is omitted in FIG.
  • the ECU 1 may be realized using a single processor (i.e., a multi-core processor) on which a plurality of cores 11 are mounted, or may be realized using a plurality of processors with one mounted core. Also, it may be realized by combining a plurality of multi-core processors.
  • a single processor four-core processor having four cores 11.
  • the core 11 is a module having one entity in which a logic circuit for performing arithmetic processing, a primary cache, and the like are implemented. Each core 11 is also called a processor core or a physical core. Although the number of cores 11 provided in the ECU 1 is four in the present embodiment, the present invention is not limited to this. The number of cores 11 provided in the ECU 1 may be appropriately designed. The number of cores 11 provided in the ECU 1 may be five or more. The number of cores 11 provided in the ECU 1 may be, for example, six.
  • the shared memory unit 12 is a memory area that each of the plurality of cores 11 can simultaneously access in parallel.
  • the shared memory unit 12 is a memory area shared by the cores 11.
  • the shared memory unit 12 is realized using a random access memory (hereinafter, RAM: Random Access Memory) or the like.
  • RAM Random Access Memory
  • the shared memory unit 12 is connected to each core 11 via an interconnect mechanism such as a bus system, for example. Note that SGI or the like can be adopted as an interface for communication between the shared memory unit 12 and the core 11.
  • the plurality of hardware 13 is configured to provide a physical layer for the processor 10.
  • the plurality of hardwares 13 correspond to peripherals for the processor 10.
  • the hardware 13 is, for example, a device (so-called I / O device) for inputting information from the outside or outputting information to the outside by connecting the ECU 1 to an external device.
  • the hardware 13 may be a non-volatile storage device such as a hard disk drive or a NOR flash memory.
  • the hardware 13a is a circuit module that functions as a physical interface for Ethernet (registered trademark). That is, the hardware 13a is a circuit module that converts a logic signal into an actual electrical signal or performs the conversion in the reverse according to the Ethernet standard.
  • the hardware 13 b is a circuit module that functions as an interface for the UART. That is, the hardware 13b converts logic signals into actual electrical signals and vice versa according to the standard of UART.
  • the hardware 13 c is configured to function as, for example, an interface of USB communication, and converts a logic signal into an actual electrical signal or performs the reverse conversion in accordance with the USB standard.
  • the hardware 13 d is, for example, a NOR type flash memory.
  • a program hereinafter referred to as a boot program
  • Pm1 a program to be executed when the ECU 1 is started
  • guest OS 2a to 2c described later, and the like are stored in the NOR type flash memory as the hardware 13d.
  • the ECU 1 may include, as the hardware 13, an I / O device, a non-volatile storage medium, or the like corresponding to various communication standards other than those described above. It also has a non-volatile storage medium in which various application software is stored. Application software may be stored in the above-described NOR flash memory.
  • the type of hardware 13 that the ECU 1 should have may be designed as appropriate.
  • Various pieces of hardware 13 as peripherals are connected to the processor 10 via, for example, signal lines (not shown). Intercommunication between the hardware 13 and the processor 10 may be provided by a bus system.
  • the ECU 1 equipped with the above components executes a predetermined start-up process (so-called boot strap) triggered by turning on the power to the ECU 1 and operates one of the plurality of cores 11 provided in the ECU 1 with the operation of the hardware 13 It functions as the core to be controlled (hereinafter, hardware control core) 11x.
  • hardware control core 11x software for causing a certain core 11 to function as the hardware control core 11 x will be referred to as hardware control software 3 hereinafter.
  • the hardware control core 11x performs processing as a communication interface between the virtual computer and the hardware 13 when operating the ECU 1 virtually as a plurality of (specifically, three) computers. It corresponds to the core 11 to be executed.
  • the core 11 operated as the hardware control core 11x may be set in advance.
  • the core 11x is set to operate as the hardware control core 11x.
  • each guest OS 2 is basic software (so-called OS: Operating System) for operating the core 11 executing the guest OS 2 as one computer (that is, a virtual computer).
  • OS Operating System
  • Each core 11 starts up and executes a guest OS 2 assigned to itself.
  • a different guest OS 2 is assigned to each core 11.
  • a guest OS 2a shown in the figure is a guest OS 2 allocated to the core 11a, and a guest OS 2b is a guest OS 2 allocated to the core 11b.
  • the guest OS 2 c is a guest OS 2 assigned to the core 11 b.
  • the guest OS 2 allocated to the plurality of cores 11a to c may be set in advance.
  • Each core 11 operates as an independent virtual machine (VM: Virtual Machine) by executing a guest OS 2 assigned to itself.
  • VM Virtual Machine
  • the core 11 to which the guest OS 2 is assigned is also described as a VM core 11.
  • the core 11 as the VM core 11 may be set in advance.
  • the VM core 11 corresponds to a virtual computer core of the present disclosure.
  • the guest OS 2a assigned to the VM core 11a is, for example, an OS (hereinafter, referred to as a driving assistance OS) for operating a computer as a driving assistance ECU.
  • the driving support ECU calculates the distance to an obstacle, etc. based on various information from sensors that capture the situation around the vehicle, such as image sensors and millimeter wave radar sensors, and does not extend out of the lane It is an ECU that determines whether or not.
  • the VM core 11a executes the driving support OS and also executes predetermined application software (hereinafter, driving support application) for providing a function as a driving support ECU. That is, the VM core 11a executes the processing as the driving support ECU.
  • the driving support application is stored in a flash memory or the like (not shown) in association with the driving support OS as the guest OS 2a.
  • the driving support application may be stored in a packaged state with the driving support OS.
  • the driving support application is sequentially read out to the RAM or the like by the VM core 11a after activation of the driving support OS and executed.
  • the guest OS 2 b is, for example, an OS (hereinafter, referred to as ABS-OS) for operating a computer as an ABS-ECU.
  • the ABS-ECU is an ECU that controls the operation of various actuators that constitute an ABS (Antilock Brake System) based on the output of a sensor mounted on the vehicle.
  • the VM core 11b executes the ABS-OS, and also executes predetermined application software (hereinafter, ABS application) for providing a function as an ABS-ECU. That is, the VM core 11b executes processing as an ABS-ECU.
  • the ABS application is stored in a flash memory or the like (not shown) in association with the ABS-OS as the guest OS 2b.
  • the ABS application may be stored packaged with the ABS-OS.
  • the ABS application is sequentially read out to the RAM and executed by the VM core 11b after the activation of the ABS-OS.
  • the guest OS 2c is, for example, an OS (hereinafter, EPS-OS) for operating a computer as an EPS-ECU.
  • the EPS-ECU is an ECU that controls an EPS (Electric Power Steering) motor.
  • the VM core 11c executes not only EPS-OS but also predetermined application software (EPS application) for providing a function as an EPS-ECU. That is, the VM core 11c executes processing as an EPS-ECU.
  • the EPS application is stored in a flash memory or the like (not shown) in association with the EPS-OS as the guest OS 2c.
  • the EPS application may be stored packaged with the EPS-OS. After activation of the EPS-OS, the EPS application is sequentially read out to the RAM by the VM core 11 c and executed.
  • the ECU 1 virtually operates as a travel support ECU 1a, an ABS-ECU 1b, and an EPS-ECU 1c, as shown in FIG.
  • Each of the driving support ECU 1a, the ABS-ECU 1b, and the EPS-ECU 1c accesses various hardware 13 via the hardware control core 11x according to a procedure described later.
  • Each of the travel support ECU 1a, the ABS-ECU 1b, and the EPS-ECU 1c provided by each VM core 11 is a virtual computer that provides a predetermined function.
  • the types of guest OSs 2a to 2c assigned to each of the plurality of cores 11 may be appropriately designed, and are not limited to those exemplified above.
  • the VM cores 11a to 11c are operated as an ECU that provides a function related to travel control of the vehicle, such as running, bending, and stopping, but the present invention is not limited thereto.
  • the VM core 11a may operate as an ECU that provides multimedia functions such as a navigation device and an audio device.
  • the VM core 11a may be operated as an ECU of a body system such as a seat or a power window.
  • the VM core 11a may operate as an ECU that provides a function for performing communication with the outside of the vehicle.
  • An ECU that provides a function for performing communication with the outside of a vehicle is, for example, an ECU that performs processing for wirelessly accessing a wide area communication network, or an ECU that performs inter-vehicle communication.
  • the types of virtually realized ECUs provided by the VM cores 11 b and 11 c may be appropriately designed.
  • the guest OS 2 allocated to each of the VM cores 11a to 11c may be appropriately selected / designed according to the ECU to be provided to each of the VM cores 11a to 11c.
  • the guest OS 2 may be an OS for controlling a predetermined electronic device mounted in a vehicle or an OS providing a function related to communication with the outside of the vehicle.
  • the boot process includes execution of a BIOS (Basic Input Output System) and execution of a process corresponding to a boot loader.
  • BIOS Basic Input Output System
  • UEFI Unified Extensible Firmware Interface
  • the program to be executed when the ECU 1 starts up is preferably implemented with hidden source code that is uniquely created by a developer.
  • FIG. 3 is a block diagram of a program (that is, a boot program) Pm1 executed when the ECU 1 is started.
  • the boot program Pm1 includes a core allocation unit Pm11 and a shared memory setting unit Pm12.
  • the core allocation unit Pm11 is a program module that sets one of the plurality of cores 11 determined in advance as the hardware control core 11x and sets the remaining cores 11 as the VM cores 11a to 11c.
  • the core allocation unit Pm11 causes the hardware control core 11x to execute the hardware control software 3.
  • the core allocation unit Pm11 allocates and activates the guest OS 2 associated in advance to each of the VM cores 11a to 11c.
  • the shared memory setting unit Pm12 is a program module that sets a part or all of the storage area of the RAM in the shared memory unit 12.
  • the boot program Pm1 is stored in a flash memory (that is, a non-volatile storage medium) as the hardware 13d. Note that various non-transitory tangible storage media can be adopted as a storage device of the boot program Pm1.
  • the boot program Pm1 itself may be executed by the cooperation of the hardware and the processor 10.
  • the boot program Pm1 corresponds to a virtualization program of the present disclosure, and a storage device (here, the hardware 13d) storing the boot program Pm1 corresponds to a storage medium of the present disclosure.
  • the interaction between the hardware control core 11x and the VM core 11a after the start-up process of the ECU 1 is completed will be described with reference to FIG.
  • the configuration and functions (in other words, software) of the VM core 11a among the VM cores 11a to 11c will be described as an example, but the other VM cores 11b to 11c are the same.
  • the hardware control core 11x includes an inter-core communication unit F1 and a device driver unit F2, as shown in FIG.
  • the inter-core communication unit F1 includes a reading unit F11 and a storage processing unit F12 as finer functional blocks.
  • the inter-core communication unit F1 is a configuration for the hardware control core 11x to communicate with each VM core 11 (for example, the VM core 11a).
  • Communication between the hardware control core 11x and the VM core 11a is realized by the shared memory unit 12 (in other words, memory access).
  • the VM core 11a wants to use any hardware 13
  • the VM core 11a transfers the data to the hardware control core 11x by storing data (in other words, a bit string) for the hardware 13 in the shared memory unit 12.
  • the hardware control core 11 x transfers the data acquired from the hardware 13 to the VM core 11 a by storing the data in the shared memory unit 12.
  • the white arrows in FIG. 4 indicate the flow of data.
  • M1 illustrated in FIG. 4 is a memory area (hereinafter, downlink memory) in which data addressed to the hardware control core 11x from the VM core 11a is stored.
  • M2 is a memory area (hereinafter, uplink memory) in which data directed from the hardware control core 11x to the VM core 11a is stored.
  • the downlink memory M1 and the uplink memory M2 may be implemented using hardware independent memories, or may be implemented as software (in other words, logically).
  • the downlink memory M1 and the uplink memory M2 may be prepared for each VM core 11 (in other words, for each guest OS 2, for each virtual computer).
  • the hardware control core 11x is configured to be able to write, read, and delete data in the uplink memory M2, but is configured not to write data in the downlink memory M1. That is, the hardware control core 11x is prohibited from storing data in the downlink memory M1.
  • the hardware control core 11x is configured to be able to execute only reading of stored data from the downlink memory M1.
  • the VM core 11a is configured to be able to write, read, delete, etc. data to the downlink memory M1, but is configured not to write data to the uplink memory M2. That is, in the VM core 11a, data storage in the uplink memory M2 is prohibited.
  • the VM core 11a is configured to be able to execute only reading of data stored in the uplink memory M2.
  • the reading unit F11 included in the inter-core communication unit F1 is a configuration for reading data stored in the downlink memory M1.
  • the reading unit F11 outputs the data read from the downlink memory M1 to the device driver unit F2.
  • the reading unit F11 corresponds to the control side reading unit of the present disclosure.
  • the storage processing unit F12 is a configuration for storing data in the uplink memory M2.
  • the storage processing unit F12 stores the data received by the device driver unit F2, which will be described later, as it is (that is, low data) in the uplink memory M2, and outputs an interrupt signal to the VM core 11a.
  • the interrupt signal is a signal requesting reading of stored data.
  • the VM core 11a refers to the uplink memory M2 based on the reception of the interrupt signal output from the storage processing unit F12, and reads the stored data.
  • the output of the interrupt signal accompanying the data storage in the uplink memory M2 is implemented without delay (that is, as quickly as possible) with respect to the completion of the storage of the data in the uplink memory M2.
  • the storage processing unit F12 corresponds to the control-side storage processing unit of the present disclosure.
  • the device driver unit F2 is configured to execute device drivers corresponding to various hardwares 13. That is, the device driver unit F2 communicates with the various hardware 13 and operates normally.
  • the device driver unit F2 operates the hardware 13 based on the data input from the reading unit F11.
  • the data input from the reading unit F11 is, in other words, data acquired by the inter-core communication unit F1 from the VM core 11a via the downlink memory M1.
  • the device driver unit F2 also outputs a bit string (in other words, low data) corresponding to the signal input from the hardware 13 to the inter-core communication unit F1 (more specifically, the storage processing unit F12).
  • the data as a bit string output from the device driver unit F2 to the inter-core communication unit F1 is output to the VM core 11a via the uplink memory M2.
  • the output source information which shows whether it is the data acquired from which hardware 13 is provided to the data which the device driver part F2 outputs. This is to specify which hardware 13 the VM core 11a, which is the receiver of the data, is the data output from.
  • the output data of the device driver unit F2 does not necessarily include the above output source information.
  • the VM core 11a determines the storage location (in other words, the address) of the data in the uplink memory M2. This is because it is possible to specify which hardware 13 the stored data is output from.
  • device drivers corresponding to various types of hardware 13 for realizing the device driver unit F2 are implemented as hidden source code. According to this, it is possible to suppress the possibility that the virtual computer (here, the travel support ECU 1a) provided by the VM core 11a is hacked from the outside.
  • the virtual computer here, the travel support ECU 1a
  • the device driver unit F2 as a device driver exchange raw data with each other
  • virtual hacking is performed according to a normal hacking method This is because it is difficult (substantially impossible) to break into a computer.
  • the VM core 11a includes an inter-core communication unit G1 and a process execution unit G2 as functional blocks.
  • the inter-core communication unit G1 is a configuration for the VM core 11a to bidirectionally communicate with the hardware control core 11x.
  • the inter-core communication unit G1 includes a reading unit G11 and a storage processing unit G12 as finer functional blocks.
  • the reading unit G11 is configured to read the stored data with reference to the uplink memory M2 based on the reception of the interrupt signal output from the storage processing unit F12 of the hardware control core 11x.
  • the reading unit G11 outputs the data read from the uplink memory M2 to the processing execution unit G2.
  • the reading unit G11 corresponds to the virtual computer side reading unit of the present disclosure.
  • the storage processing unit G12 stores the data input from the processing execution unit G2 as it is in the downlink memory M1, and outputs an interrupt signal to the hardware control core 11x.
  • the hardware control core 11x (more specifically, the reading unit F11) refers to the downlink memory M1 based on the reception of the interrupt signal output from the storage processing unit F12, and reads the stored data.
  • the output of the interrupt signal accompanying the data storage to the downlink memory M1 is implemented without delay (that is, as quickly as possible) with respect to the completion of the storage of the data to the downlink memory M1.
  • the storage processing unit G12 corresponds to the virtual computer side storage processing unit of the present disclosure.
  • the process execution unit G2 is a functional block that executes a predetermined process based on data input from the hardware 13.
  • the process execution unit G2 includes an OS unit G21 and an application unit G22 as the subdivided functional blocks.
  • the OS unit G21 is configured to execute a guest OS 2a (here, a driving support OS) assigned to the VM core 11a.
  • the OS unit G21 executes various arithmetic processing using data input from the reading unit G11.
  • the OS unit G21 outputs data as a result of arithmetic processing based on the data input from the reading unit G11 to the inter-core communication unit G1 (more specifically, the storage processing unit G12).
  • the OS unit G21 provides the data input from the reading unit G11 to the application unit G22 as necessary.
  • the application unit G22 is configured to execute application software (here, a travel support application) associated with the guest OS 2a.
  • the application unit G22 executes predetermined arithmetic processing based on the data provided from the OS unit G21.
  • the application unit G22 outputs data for the predetermined hardware 13 to the OS unit G21 according to the result of the calculation process.
  • the data for the hardware 13 output from the application unit G22 to the OS unit G21 is output to the inter-core communication unit G1 via the OS unit G21. That is, when the data for the hardware 13 is input from the application unit G22, the OS unit G21 outputs the input data to the inter-core communication unit G1.
  • the data output from the processing execution unit G2 such as the OS unit G21 and the application unit G22 to the inter-core communication unit F1 is output to the hardware control core 11x via the downlink memory M1.
  • the process execution unit G2 has a two-layer structure of an OS unit G21 that executes an OS and an application unit G22 that executes application software, but the present invention is not limited to this.
  • the process execution unit G2 may include a middleware unit that executes middleware such as a protocol stack and a file system.
  • the specific configuration of the process execution unit G2 is derived from the software configuration of the virtual computer.
  • each guest OS 2 providing a virtual computer does not have to have a device driver.
  • the device driver unit F2 operates the hardware 13 based on data output from each virtual computer.
  • the device driver unit F2 corresponds to a configuration for controlling the hardware 13 instead of each guest OS 2. Further, for the above reason, even if the guest OS 2 has a device driver, the device driver does not operate.
  • the hardware control core 11x specifies which hardware 13 is to be operated based on the received data.
  • the above output information need not necessarily be included in the output data of the processing execution unit G2.
  • the hardware control core 11x is based on the data storage location (in other words, the address) in the downlink memory M1. This is because it is possible to specify which hardware 13 the stored data is for.
  • the ECU 1 causes one of the four cores 11 provided in the ECU 1 to operate as the hardware control core 11 x by the start-up process accompanying the power supply. Also, the remaining three cores 11 execute different guest OSs 2 respectively, and each functions as an independent virtual machine. That is, the ECU 1 virtually operates as a plurality of computers as a whole.
  • the VM cores 11a to 11c and the hardware control core 11x are configured to communicate with each other by memory access.
  • the device driver unit F2 operates the hardware 13 based on the raw data acquired from each of the VM cores 11a to 11c by memory access.
  • each VM core 11a-11c can store data in the shared memory unit 12 at an arbitrary timing.
  • each VM core 11a-11c can operate desired hardware at an arbitrary timing.
  • the data for virtual machines output from the hardware 13 is provided by the device driver unit F2 and the inter-core communication unit F1 to the VM core 11 to be output via the shared memory unit 12.
  • the reading of the data stored in the shared memory unit 12 is performed without delay by the input / output of the interrupt signal.
  • each of the guest OSs 2a to 2c exclusively operates one core 11. That is, one core 11 is never shared by multiple guest OSs 2.
  • Each guest OS 2 can freely use the core computational resources allocated to itself regardless of the operating status of the other guest OS 2.
  • each guest OS 2 can operate using calculation resources provided in its own dedicated core 11, and can use desired hardware at an arbitrary timing. Thus, the possibility of delay in communication between the guest OS 2 and the hardware can be reduced.
  • the hardware control core 11x provides a function as a device driver for each of the VM cores 11a to 11c. Therefore, each guest OS 2 need not have a device driver.
  • a device driver is a large program module including a protocol and a CPU register. According to the present embodiment, since each guest OS 2 does not need to have a device driver, the scale of the software stored in the ECU 1 can be reduced.
  • the device driver for realizing the device driver unit F2 is realized by the concealed source code. Therefore, security against unauthorized access to the virtual computer operating on the ECU 1 can be enhanced.
  • the hardware 13 is operated without being associated with a virtual machine.
  • each piece of hardware 13 can be shared by each virtual computer. Also, along with this, it is possible to omit the process of associating the hardware and the virtual machine, which is required in the conventional virtualization system.
  • the data when a virtual machine outputs data for a certain hardware, the data is once converted into a format according to the communication standard between the guest OS and the hypervisor and is output to the hypervisor. Also, when outputting data acquired from certain hardware to a virtual machine, the hypervisor temporarily converts the data into a format according to the communication standard between the guest OS and the hypervisor and outputs it. Since such a bridge process requires a predetermined time, the bridge process may cause a delay in communication between the virtual computer and the hardware.
  • the configuration of the present embodiment it is not necessary to carry out the bridge processing required in the above-described assumed configuration. According to this embodiment, there is no possibility that the communication delay between the guest OS 2 and the hardware 13 is delayed due to the bridging process because the bridging process itself is not performed. As described above, according to the present embodiment, it is possible to provide a virtualization system in which a plurality of virtual machines can share one piece of hardware and a delay in communication between the virtual machines and the hardware can be suppressed. it can.
  • the communication delay due to the above-mentioned bridge processing can be reduced by enhancing the performance of the processor 10.
  • the ECU 1 for controlling the traveling of the vehicle is used near a heat source such as an engine (that is, under a high temperature environment). If it is attempted to realize the assumed configuration with a processor that can be used under a high temperature environment, the communication delay resulting from the bridge processing may be significant, and desired communication performance may not be obtained.
  • this embodiment can be said to be a more useful configuration when constructing a virtualization system using a physical computer incorporated into a vehicle.
  • the present invention is suitable for virtualizing an ECU according to travel control of a vehicle.
  • the memory in which the hardware control core 11x stores data for the VM core 11a and the memory in which the VM core 11a stores data for the hardware control core 11x are software or hardware-wise
  • the aspect prepared separately was disclosed. In another aspect, they may be undivided. That is, the memory in which the hardware control core 11x stores data for the VM core 11a and the memory in which the VM core 11a stores data for the hardware control core 11x may be the same memory.
  • Modification 2 In the embodiment described above, the aspect of allocating one VM core 11 to one guest OS 2 has been disclosed. That is, the configuration is disclosed in which the guest OS 2 and the VM core 11 are associated one to one. However, the allocation mode of the VM core 11 to the guest OS 2 is not limited to this. As shown in FIG. 5, a plurality of VM cores 11 may be assigned to one guest OS 2. In the example of FIG. 5, two VM cores 11a and 11b are allocated to the first OS 2d as the guest OS 2, and one VM core 11c is allocated to the second OS 2e as the guest OS 2.
  • the guest OS 2 is disclosed as an embedded OS (in other words, a dedicated OS) for providing a limited function according to the application, but the guest OS 2 is an OS used in a general purpose computer (A so-called general-purpose OS) may be used.
  • An embedded OS is, in other words, an OS that supports the execution of one or more specific application software.
  • the general-purpose OS corresponds to an OS that supports a wide variety of application software that can be installed by the user.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
PCT/JP2018/031416 2017-09-21 2018-08-24 仮想化システム、仮想化プログラム、及び、記憶媒体 Ceased WO2019058874A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/816,813 US11494221B2 (en) 2017-09-21 2020-03-12 Hardware control core controlling operation of hardware devices by executing device drivers within the hardware control core used by virtual machine cores via shared memory having an uplink and downlink memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017181565A JP6777050B2 (ja) 2017-09-21 2017-09-21 仮想化システム、仮想化プログラム、及び、記憶媒体
JP2017-181565 2017-09-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/816,813 Continuation US11494221B2 (en) 2017-09-21 2020-03-12 Hardware control core controlling operation of hardware devices by executing device drivers within the hardware control core used by virtual machine cores via shared memory having an uplink and downlink memory

Publications (1)

Publication Number Publication Date
WO2019058874A1 true WO2019058874A1 (ja) 2019-03-28

Family

ID=65811246

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/031416 Ceased WO2019058874A1 (ja) 2017-09-21 2018-08-24 仮想化システム、仮想化プログラム、及び、記憶媒体

Country Status (3)

Country Link
US (1) US11494221B2 (https=)
JP (1) JP6777050B2 (https=)
WO (1) WO2019058874A1 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113326118A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 基于多核处理器的虚拟化方法、系统、多核处理器和电子设备
CN113326109A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 一种虚拟化的方法、设备、板卡及计算机可读存储介质
CN113326226A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 一种虚拟化的方法、装置、板卡及计算机可读存储介质
US12608220B2 (en) 2020-02-28 2026-04-21 Anhui Cambricon Information Technology Co., Ltd. Virtualization method, device, board card and computer readable storage medium

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111174805A (zh) * 2019-04-30 2020-05-19 奥特酷智能科技(南京)有限公司 分布集中式自动驾驶系统
KR102461918B1 (ko) 2019-10-11 2022-11-02 구글 엘엘씨 차량용 확장가능 컴퓨팅 아키텍처
JP2021124902A (ja) 2020-02-04 2021-08-30 トヨタ自動車株式会社 車両制御装置、車両制御方法、及び車両制御プログラム
CN114448963B (zh) * 2020-10-30 2024-03-01 中车株洲电力机车研究所有限公司 一种融合控制架构下外设共享通信的方法及系统
US12236398B2 (en) * 2021-09-15 2025-02-25 Six. One, LLC Systems and methods for an enterprise computing platform
US12086654B2 (en) 2021-09-16 2024-09-10 T-Head (Shanghai) Semiconductor Co., Ltd. Parallel processing unit virtualization
CN115480931A (zh) * 2022-08-12 2022-12-16 黑芝麻智能科技(重庆)有限公司 一种核间通信处理方法、装置及计算机系统
JP2025058755A (ja) 2023-09-28 2025-04-09 日立Astemo株式会社 車両制御装置、車両制御方法
WO2026059390A1 (ko) * 2024-09-13 2026-03-19 엘지전자 주식회사 신호 처리 장치 및 이를 구비하는 차량 제어 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200433A (ja) * 1994-01-07 1995-08-04 Fuji Facom Corp ゲートウエイ
JP2004178115A (ja) * 2002-11-26 2004-06-24 Kyocera Mita Corp データ転送装置
JP2009230549A (ja) * 2008-03-24 2009-10-08 Fujitsu Ltd 情報処理装置、情報処理方法及びコンピュータプログラム
JP2010003257A (ja) * 2008-06-23 2010-01-07 Toshiba Corp 仮想計算機システム及びネットワークデバイス共有方法
JP2015103129A (ja) * 2013-11-27 2015-06-04 日産自動車株式会社 車載情報装置
JP2015170887A (ja) * 2014-03-05 2015-09-28 富士通株式会社 パケット処理方法及びシステム

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7512826B2 (en) 2005-04-20 2009-03-31 International Business Machines Corporation Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer
JP5277434B2 (ja) * 2007-12-17 2013-08-28 エヌエイチエヌ コーポレーション コンテンツ提供方法及びコンテンツ提供システム
US8392917B2 (en) * 2009-03-30 2013-03-05 Microsoft Corporation Timer access from user mode through a shared memory page
JP5434616B2 (ja) * 2010-01-15 2014-03-05 富士通株式会社 仮想計算機、仮想計算機モニタ、および計算機の制御方法
JP2012018515A (ja) * 2010-07-07 2012-01-26 Fujitsu Ltd 情報処理装置，制御方法，制御プログラム
JP5698280B2 (ja) 2013-02-01 2015-04-08 日本電信電話株式会社 仮想化装置、通信方法、およびプログラム
US9158569B2 (en) * 2013-02-11 2015-10-13 Nvidia Corporation Virtual interrupt delivery from a graphics processing unit (GPU) of a computing system without hardware support therefor
US9762497B2 (en) * 2013-11-26 2017-09-12 Avago Technologies General Ip (Singapore) Pte. Ltd. System, method and apparatus for network congestion management and network resource isolation
WO2017005330A1 (en) * 2015-07-09 2017-01-12 Hitachi Data Systems Engineering UK Limited Storage control system managing file-level and block-level storage services, and methods for controlling such storage control system
CN105159753B (zh) * 2015-09-25 2018-09-28 华为技术有限公司 加速器虚拟化的方法、装置及集中资源管理器
US20170103192A1 (en) * 2015-10-12 2017-04-13 Renesas Electronics America Inc. Secure code delivery
US10452572B2 (en) * 2016-10-06 2019-10-22 Vmware, Inc. Automatic system service resource management for virtualizing low-latency workloads that are input/output intensive
US10589628B2 (en) * 2017-02-09 2020-03-17 Medallion Instrumentation Systems, Llc System and method for hosting applications in a graphical instrument
US10853113B2 (en) * 2017-06-07 2020-12-01 Dell Products L.P. Hierarchically nested virtualized functions having a physical function providing processing requests and responses to each level of the hierarchy
CN107479943B (zh) * 2017-07-03 2020-02-21 北京东土科技股份有限公司 基于工业互联网操作系统的多操作系统运行方法及装置
US11888710B2 (en) * 2018-09-25 2024-01-30 Intel Corporation Technologies for managing cache quality of service
US11003484B2 (en) * 2019-06-28 2021-05-11 Intel Corporation Inter-processor interrupt virtualization with pass-through of local interrupt controller

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200433A (ja) * 1994-01-07 1995-08-04 Fuji Facom Corp ゲートウエイ
JP2004178115A (ja) * 2002-11-26 2004-06-24 Kyocera Mita Corp データ転送装置
JP2009230549A (ja) * 2008-03-24 2009-10-08 Fujitsu Ltd 情報処理装置、情報処理方法及びコンピュータプログラム
JP2010003257A (ja) * 2008-06-23 2010-01-07 Toshiba Corp 仮想計算機システム及びネットワークデバイス共有方法
JP2015103129A (ja) * 2013-11-27 2015-06-04 日産自動車株式会社 車載情報装置
JP2015170887A (ja) * 2014-03-05 2015-09-28 富士通株式会社 パケット処理方法及びシステム

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113326118A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 基于多核处理器的虚拟化方法、系统、多核处理器和电子设备
CN113326109A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 一种虚拟化的方法、设备、板卡及计算机可读存储介质
CN113326226A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 一种虚拟化的方法、装置、板卡及计算机可读存储介质
CN113326121A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 一种机器学习设备及板卡
CN113326110A (zh) * 2020-02-28 2021-08-31 安徽寒武纪信息科技有限公司 一种片上系统及板卡
US12608220B2 (en) 2020-02-28 2026-04-21 Anhui Cambricon Information Technology Co., Ltd. Virtualization method, device, board card and computer readable storage medium

Also Published As

Publication number Publication date
US20200210222A1 (en) 2020-07-02
JP2019057162A (ja) 2019-04-11
JP6777050B2 (ja) 2020-10-28
US11494221B2 (en) 2022-11-08

Similar Documents

Publication Publication Date Title
US11494221B2 (en) Hardware control core controlling operation of hardware devices by executing device drivers within the hardware control core used by virtual machine cores via shared memory having an uplink and downlink memory
EP3835988B1 (en) Communication method and computer system
US11681553B2 (en) Storage devices including heterogeneous processors which share memory and methods of operating the same
US8387043B2 (en) USB port shared control method in a plurality of virtual machines
US11983136B2 (en) PCIe device and operating method thereof
CN105264506B (zh) 向内存映射配置分配处理器
US8271707B2 (en) Method and system for PCI hybrid function
US11995019B2 (en) PCIe device with changeable function types and operating method thereof
US12530215B2 (en) Processing system, related integrated circuit, device and method for controlling communication over a communication system having a physical address range
US10140214B2 (en) Hypervisor translation bypass by host IOMMU with virtual machine migration support
EP2423826A2 (en) Computer system, i/o device control method, and i/o drawer
CN115309678B (zh) 处理系统、相关集成电路、设备及方法
JPWO2010097925A1 (ja) 情報処理装置
US20050235083A1 (en) Computer system
JP5578698B2 (ja) 半導体データ処理装置及びデータ処理システム
CN116893988A (zh) 接口设备及其操作方法
JP2020053089A (ja) 中継装置および情報処理システム
EP4092528A1 (en) Virtualized system and method of preventing memory crash of same
US10922149B2 (en) System comprising a plurality of virtualization systems
TWI922652B (zh) PCIe裝置及其操作方法
WO2012143947A2 (en) Multi-host peripheral controller
JP5856220B2 (ja) ナビゲーションシステム
CN115576439A (zh) 一种cpu控制器的扩展方法及装置
KR20160036795A (ko) 컴퓨터 운용체제에서 물리적 디바이스 드라이버를 없애는 디바이스 액세스 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18859653

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18859653

Country of ref document: EP

Kind code of ref document: A1