WO2019057071A1

WO2019057071A1 - Pixel structure and active switch array substrate

Info

Publication number: WO2019057071A1
Application number: PCT/CN2018/106457
Authority: WO
Inventors: 何怀亮
Original assignee: 惠科股份有限公司
Priority date: 2017-09-22
Filing date: 2018-09-19
Publication date: 2019-03-28
Also published as: CN107463044A; CN107463044B

Abstract

A pixel structure (100) and an active switch array substrate (200). The pixel structure (100) comprises: a first scan line (111); a second scan line (112), which is adjacent to the first scan line (111); a first data line (121);, a second data line (122), which is adjacent to the first data line (121); and a pixel electrode (130). The first scan line (111) and the second scan line (112) are arranged to intersect with the first data line (121) and the second data line (122) to jointly enclose a pixel unit region. The pixel electrode (130) is located in the pixel unit region and is electrically connected to the first scan line (111) and the first data line (121), at least one slit (131) extending from the first scan line (111) to the second scan line (112) is arranged on the pixel electrode (130), and the length direction of the slit (131) is inclined with respect to the length direction of the first scan line (111).

Description

Pixel structure and active switch array substrate

Technical field

The present application relates to the field of display technologies, and in particular, to a pixel structure and an active switch array substrate.

Background technique

The liquid crystal display has the advantages of high image quality, small size, light weight, low voltage driving, low power consumption and wide application range. Therefore, it has been widely used in medium and small portable TVs, mobile phones, and video recording. Consumer electronics or computer products such as computers, notebook computers, desktop displays and projection TVs, and gradually replaced the cathode ray tube (CRT) to become the mainstream of the display. However, liquid crystal displays still have problems such as narrow viewing angle range and high price. Therefore, how to increase the range of viewing angles is one of the urgent problems to be improved.

Summary of the invention

Embodiments of the present application provide a pixel structure and an active switch array substrate to achieve a technical effect of increasing a viewing angle.

In one aspect, a pixel structure provided by an embodiment of the present application includes:

First scan line;

a second scan line adjacent to the first scan line;

First data line;

a second data line adjacent to the first data line, wherein the first scan line and the second scan line are disposed to intersect with the first data line and the second data line to form a pixel unit Area;

a pixel electrode, the pixel electrode being located in the pixel unit region and electrically connecting the first scan line and the first data line, wherein the pixel electrode is provided from the first scan line to the second At least one slit extending from the scan line, and a length direction of the slit is inclined with respect to a length direction of the first scan line, and a length direction of the slit is inclined with respect to a length direction of the first scan line The angle range is from 75° to 85°.

In an embodiment of the present application, the pixel structure further includes a first thin film transistor and a second thin film transistor, a source of the first thin film transistor is connected to the first data line, and a gate of the first thin film transistor The first scan line is connected to the first scan line, the drain of the first thin film transistor is connected to the source of the second thin film transistor, and the gate of the second thin film transistor is connected to the first scan line, the second A drain of the thin film transistor is connected to the pixel electrode.

In one embodiment of the present application, the first thin film transistor and the second thin film transistor are NMOS transistors or PMOS transistors.

In one embodiment of the present application, the pixel electrode is made of a transparent conductive material including one or more of ITO, IZO, and ITZO.

On the other hand, a pixel structure provided by an embodiment of the present application includes:

First scan line;

a second scan line adjacent to the first scan line;

First data line;

a pixel electrode, the pixel electrode being located in the pixel unit region and electrically connecting the first scan line and the first data line, wherein the pixel electrode is provided from the first scan line to the second At least one slit extending from the scan line, and a length direction of the slit is inclined with respect to a length direction of the first scan line.

In an embodiment of the present application, a source of the first thin film transistor is connected to the first data line, a gate of the first thin film transistor is connected to the first scan line, and the first thin film transistor is a drain is connected to a source of the second thin film transistor, a gate of the second thin film transistor is connected to the first scan line, a drain of the second thin film transistor is connected to the pixel electrode; and the pixel electrode is used The transparent conductive material is made of one or more of ITO, IZO, and ITZO.

In addition, an active switch array substrate provided by the embodiment of the present application includes:

Transparent substrate;

And a first scan line disposed on the transparent substrate;

a third scan line disposed on the transparent substrate;

a second scan line disposed on the transparent substrate and the second scan line being located between the first scan line and the third scan line;

a first data line disposed on the transparent substrate;

a second data line disposed on the transparent substrate, wherein the first scan line and the second scan line are disposed to intersect with the first data line and the second data line to form a first pixel unit a region, the second scan line and the third scan line are disposed to intersect with the first data line and the second data line to form a second pixel unit adjacent to the first pixel unit area region;

a first pixel electrode disposed on the transparent substrate and the first pixel electrode being located in the first pixel unit region and electrically connecting the first scan line and the first data line, the first pixel The electrode is provided with at least one first slit extending from the first scan line to the second scan line;

a second pixel electrode disposed on the transparent substrate and the second pixel electrode being located in the second pixel unit region and electrically connecting the second scan line and the first data line, the second pixel The electrode is provided with at least one second slit extending from the second scan line to the third scan line;

One end of the first slit adjacent to the second scan line is closer to the first data line than an end of the first slit adjacent to the first scan line;

One end of the second slit adjacent to the second scan line is closer to the first data line than an end of the second slit adjacent to the third scan line.

In an embodiment of the present application, the angle of the longitudinal direction of the first slit relative to the longitudinal direction of the second scanning line ranges from 75° to 85°.

In an embodiment of the present application, the active switch array substrate further includes: a common electrode disposed on the transparent substrate in the same layer as the first pixel electrode and the second pixel electrode.

In an embodiment of the present application, the active switch array substrate further includes: a common electrode disposed between the first pixel electrode and the second pixel electrode and the transparent substrate.

In an embodiment of the present application, the first pixel electrode and the second pixel electrode are each made of a transparent conductive material, and the transparent conductive material includes one or more of ITO, IZO, and ITZO.

The above technical solution has the advantages that a pixel electrode is disposed in a pixel unit region that is mutually enclosed by two adjacent scan lines and two adjacent data lines, and at least one slit is obliquely opened on the pixel electrode. It can preset a certain tilt angle for the arrangement of the liquid crystal molecules, so that the viewing angle of the display device having the pixel structure can be improved.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a schematic layout diagram of a pixel structure in an embodiment of the present application;

2 is a schematic structural diagram of an active switch array substrate according to another embodiment of the present application;

3 is another schematic diagram of an active switch array substrate according to another embodiment of the present application;

4 is a schematic structural diagram of an active switch array substrate according to still another embodiment of the present application;

FIG. 5 is another schematic diagram of an active switch array substrate according to still another embodiment of the present application; FIG.

6 is a schematic structural diagram of a display panel in still another embodiment of the present application;

7 is a schematic structural view of a color filter substrate in still another embodiment of the present application;

8 is a partial schematic view of a color filter substrate in another embodiment of the present application;

FIG. 9 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.

As shown in FIG. 1 , a pixel structure 100 provided in an embodiment of the present invention includes: adjacently disposed scan lines 111 and scan lines 112 , adjacently disposed data lines 121 and data lines 122 , and pixel electrodes 130 . . The

scan lines

111 and 112 are arranged to intersect with the data line 121 and the data line 122 to form a pixel unit area, and the pixel electrode 130 is located in the pixel unit area. Further, the pixel electrode 130 is provided with at least one slit 131 extending from the scanning line 111 to the scanning line 112, and the longitudinal direction of the slit 131 is inclined with respect to the longitudinal direction of the scanning line 111 (for example, the horizontal direction of FIG. 1).

In this embodiment, the scan line 111 and the scan line 112 are disposed substantially in parallel, and the data line 121 and the data line 122 are also disposed substantially in parallel, so that the scan line 111, the scan line 112, the data line 121, and the data line 122 together form a The pixel unit region is substantially quadrangular, and the pixel electrode 130 is located in the pixel unit region and electrically connects the scan line 111 and the data line 121. Furthermore, at least one slit, for example, two slits 131 are provided on the pixel electrode 130, and if there are a plurality of slits 131, the slits 131 are, for example, substantially parallel to each other. Each slit 131 extends from the scanning line 111 to the scanning line 112 and penetrates through the pixel electrode 130, or in other words, the slit 131 has a hollow structure and is closed at both ends. Of course, it may be a hollow structure with one end closed and the other end open. The pixel electrode 130 is typically a transparent electrode such as an ITO (Indium Tin Oxide) electrode, and the length direction of the slit 131 is inclined with respect to the length direction of the scanning line 111, specifically, the slit 131 and the scanning line. The angle α of 111 ranges from 75° to 85°. The pixel electrode 130 is made of a transparent conductive material such as one or more of ITO, IZO (Indium Zinc Oxide, Indium Tin Zinc Oxide, ITZO (Indium Tin Zinc Oxide).

In the above, the pixel structure 100 further includes a thin film transistor 140 and a thin film transistor 150. The source 141 of the thin film transistor 140 is connected to the data line 121, the gate 142 of the thin film transistor 140 is connected to the scan line 111, the drain 143 of the thin film transistor 140 is connected to the source 151 of the thin film transistor 150, and the gate 152 of the thin film transistor 150 is connected to the scan line. 111 and the drain 153 of the thin film transistor 150 are connected to the pixel electrode 130. In other words, the thin film transistor 140 and the thin film transistor 150 are connected in series between the data line 121 and the pixel electrode 130 and the gates 142, 153 of both are connected to the same scan line 111; by passing the thin film transistor 140 and the thin film transistor The series connection of 150 can reduce the leakage current of the pixel structure 100 and maintain the voltage of the pixel electrode 130. Furthermore, it can be seen from the layout structure of the pixel structure 100 of FIG. 1 that the drain electrode 143 of the thin film transistor 140 extends from one side of the data line 121 across the data line 121 and is connected to the source 151 of the thin film transistor 150. The source 141 of the thin film transistor 140 and the drain 153 of the thin film transistor 150 are located on the same side of the scan line 111 (for example, the upper side of the scan line 111 in FIG. 1), and the drain 143 of the thin film transistor 140 and the thin film transistor 150 The source 151 is located on the other opposite side of the scan line 111 (for example, the lower side of the scan line 111 in FIG. 1), so that the overall layout structure of the thin film transistor 140 and the thin film transistor 150 is substantially U-shaped, and the layout manner can be greatly improved. Increase the pixel aperture ratio. In addition, it is worth mentioning that the

thin film transistors

140, 150 may be NMOS transistors or PMOS transistors; of course, the

thin film transistors

140, 150 may also be replaced with other three-terminal active devices.

In summary, the pixel structure 100 provided in this embodiment has one or more slits extending from one scan line 111 of the adjacent two

scan lines

111, 112 to the other scan line 112 in the pixel electrode 130. 131, and the length direction of the slit 131 is inclined with respect to the length direction of the scanning line 111/112, which can preset a certain inclination angle for the arrangement of the liquid crystal molecules, thereby being able to significantly improve the display device having the pixel structure 100. View angle. Further, the double

thin film transistors

140 and 150 are disposed in series to reduce the leakage current of the pixel structure 100 and maintain the voltage of the pixel electrode 130. In addition, the layout structure of the dual

thin film transistors

140, 150 can effectively increase the pixel aperture ratio.

As shown in FIG. 2 and FIG. 3 , an active switch array substrate 200 according to another embodiment of the present invention includes: a transparent substrate 250 and scan lines 211 , scan lines 212 , and scan lines 213 disposed on the transparent substrate 250 . The data line 221, the data line 222, the pixel electrode 230, and the pixel electrode 240, the scan line 212 is located between the scan line 211 and the scan line 213, the scan line 211 is disposed adjacent to the scan line 212, and the scan line 212 is opposite to the scan line 213. Neighbor settings. The scan line 211 and the scan line 212 intersect with the data line 221 and the data line 222 to form a first pixel unit area. The scan line 212 and the scan line 213 are intersected with the data line 221 and the data line 222 to form a second. a pixel unit region, the first pixel unit region being adjacent to the second pixel unit region.

The pixel electrode 230 is located in the first pixel unit region and electrically connects the scan line 211 and the data line 221, and the pixel electrode 230 is provided with at least one slit 231 extending from the scan line 211 to the scan line 212. The pixel electrode 240 is located in the second pixel unit region and electrically connects the scan line 212 and the data line 221, and the pixel electrode 240 is provided with at least one slit 241 extending from the scan line 212 to the scan line 213.

Each slit 231 on the pixel electrode 230 is adjacent to one end of the scan line 212 closer to the data line 221 with respect to an end thereof adjacent to the scan line 211. Each of the slits 241 on the pixel electrode 240 is adjacent to the data line 221 adjacent to one end of the scanning line 212 with respect to an end thereof adjacent to the scanning line 213. Optionally, the inclination angle α of the longitudinal direction of each slit 241 with respect to the longitudinal direction of the scanning line 212 ranges from 75° to 85°; similarly, the length direction of each slit 231 is relative to the scanning. The angle of inclination of the line 212 in the longitudinal direction also ranges from 75° to 85°.

More specifically, the electrical connection between the pixel electrode 230 located in the first pixel unit region and the scan line 211 and the data line 221 may be similar to the pixel electrode 130 in FIG. 1 by two series-connected three-terminal active The device is implemented, for example, by two thin-film transistors connected in series; the electrical connection method in which the double thin film transistors are connected in series can reduce the leakage current of the pixel structure and maintain the voltage of the pixel electrode 230; further, the dual thin film transistor The layout structure can also be U-shaped as shown in FIG. 1, or even other shapes such as a V-shape to increase the pixel aperture ratio. Similarly, the electrical connection between the pixel electrode 240 located in the second pixel unit region and the scan line 212 and the data line 221 may be similar to the pixel electrode 130 in FIG. 1 by two serially connected three-terminal active devices. For example, two thin film transistors connected in series are used; the electrical connection method in which the double thin film transistors are connected in series can reduce the leakage current of the pixel structure and maintain the voltage of the pixel electrode 240; further, the layout of the double thin film transistor The structure may also be U-shaped as shown in FIG. 1, or even other shapes such as V-type to increase the pixel aperture ratio. The pixel electrode 230 and the pixel electrode 240 are both made of a transparent conductive material, such as one or more of ITO, IZO (Indium Zinc Oxide, Indium Tin Zinc Oxide, ITZO (Indium Tin Zinc Oxide) .

As described above, as shown in FIG. 3, the active switch array substrate 200 further includes a common electrode 260. The common electrode 260 is disposed on the transparent substrate 250 in the same layer as the pixel electrode 230 and the pixel electrode 240. Therefore, the technical solution of the embodiment is applicable to a liquid crystal display device of an IPS (In Plane Switching) mode, and has a viewing angle. Large, fine colors and other advantages. Furthermore, it can be seen from FIG. 3 that the common electrode 260 and the pixel electrode 230/240 are alternately arranged in the horizontal direction shown in FIG. 3, so that a plane can be formed between the pixel electrode 230/240 and the common electrode 260 adjacent thereto. An electric field or transverse electric field.

As shown in FIG. 4 and FIG. 5 , an active switch array substrate 300 according to another embodiment of the present application includes: a transparent substrate 350 and scan lines 311 , scan lines 312 , and scan lines 313 disposed on the transparent substrate 350 . The data line 321, the data line 322, the pixel electrode 330, and the pixel electrode 340. The scan line 312 is located between the scan line 311 and the scan line 313. The scan line 311 is disposed adjacent to the scan line 312 and the scan line 312 is opposite to the scan line 313. Neighbor settings. The scan line 311 and the scan line 312 are intersected with the data line 321 and the data line 322 to form a first pixel unit area. The scan line 312 and the scan line 313 are intersected with the data line 321 and the data line 322 to form a second. a pixel unit region, the first pixel unit region being adjacent to the second pixel unit region.

The pixel electrode 330 is located in the first pixel unit region and electrically connects the scan line 311 and the data line 321 , and the pixel electrode 330 is provided with at least one slit 331 extending from the scan line 311 to the scan line 312 . The pixel electrode 340 is located in the second pixel unit region and electrically connects the scan line 312 and the data line 321 , and the pixel electrode 340 is provided with at least one narrow slit 341 extending from the scan line 312 to the scan line 313 .

Each of the slits 331 on the pixel electrode 330 is adjacent to the data line 321 adjacent to one end of the scanning line 312 with respect to an end thereof adjacent to the scanning line 311. Each of the slits 341 on the pixel electrode 340 is adjacent to the data line 321 adjacent to one end of the scanning line 312 with respect to an end thereof adjacent to the scanning line 313. Optionally, the inclination angle α of the longitudinal direction of each slit 331 with respect to the longitudinal direction of the scanning line 312 ranges from 75° to 85°, and similarly, the length direction of each slit 341 is relative to the scanning. The angle of inclination of the line 312 in the longitudinal direction is also α.

More specifically, the electrical connection between the pixel electrode 330 located in the first pixel unit region and the scan line 311 and the data line 321 may be similar to the pixel electrode 130 in FIG. The device is implemented, for example, by two thin-film transistors connected in series; the electrical connection method in which the double thin film transistors are connected in series can reduce the leakage current of the pixel structure and maintain the voltage of the pixel electrode 330; further, the double thin film transistor The layout structure can also be U-shaped as shown in FIG. 1, or even other shapes such as a V-shape to increase the pixel aperture ratio. Similarly, the electrical connection between the pixel electrode 340 located in the second pixel unit region and the scan line 312 and the data line 321 may be similar to the pixel electrode 130 in FIG. 1 by two serially connected three-terminal active devices. For example, two thin film transistors connected in series are used; the electrical connection method in which the double thin film transistors are connected in series can reduce the leakage current of the pixel structure and maintain the voltage of the pixel electrode 340; further, the layout of the double thin film transistor The structure may also be U-shaped as shown in FIG. 1, or even other shapes such as V-type to increase the pixel aperture ratio.

The technical solution of the present embodiment is similar to the foregoing technical solution of the second embodiment, except that the common electrode 360 in the embodiment is disposed between the pixel electrode 330 and the pixel electrode 340 and the transparent substrate 350, and Typically, the common electrode 360 is disposed entirely under the

pixel electrodes

330, 340 such that the

pixel electrodes

330, 340 can form a fringing electric field with the underlying common electrode 360. The scheme is suitable for a liquid crystal display device of FFS (Fringe Field Switching) mode. The FFS technology rotates the liquid crystal molecules which are almost homogeneously arranged in the surface on the surface of the electrode by the fringe electric field, and has a wide viewing angle and high penetration. , low power consumption and other advantages, can achieve high penetration and large viewing angle requirements.

As shown in FIG. 6 and FIG. 7 , a display panel 400 according to another embodiment of the present disclosure includes a thin film transistor substrate 410 , a color filter substrate 420 , and a liquid crystal interposed between the thin film transistor 410 and the color filter substrate 420 . Layer 440.

The active switch array substrate 410 includes a plurality of pixel structures (refer to the pixel structure 100 described in FIG. 1 ), and three pixel electrodes 411 (corresponding to three pixel structures) are illustrated in FIG. 6 as an example. Not shown. Specifically, each of the pixel structures includes, for example, a first scan line, a second scan line adjacent to the first scan line, a first data line, a second data line adjacent to the first data line, and a pixel electrode 411 The first scan line and the second scan line are disposed to intersect with the first data line and the second data line to form a pixel unit area, and the pixel electrode 411 is located in the pixel unit area and is electrically Connecting the first scan line and the first data line, the pixel electrode 411 is provided with at least one slit extending from the first scan line to the second scan line, and each slit is adjacent to the One end of the second scan line is closer to or farther from the first data line with respect to an end thereof adjacent to the first scan line. It is to be understood that the specific structure of the active switch array substrate 410 of the present embodiment is similar to that of the active switch array substrate 410 described in the second and third embodiments, and is not described herein;

The color filter substrate 420 is disposed opposite to the active switch array substrate 410. The color filter substrate 420 is formed with a plurality of color filters 430 respectively corresponding to the plurality of pixel structures having the pixel electrodes 411, and the length of each of the color filters 430. The direction is parallel to the longitudinal direction of the slit of the pixel electrode 411 of the pixel structure corresponding to the color filter 430.

Specifically, each of the color filters 430 on the color filter substrate 420 is, for example, one of a red (R) filter, a green (G) filter, and a blue (B) filter, and each In the one-line color filter 430, the color filters 430 of the three colors are sequentially spaced and each of the color filters 430 corresponds to one pixel electrode 411. Based on such a structure, the display panel 400 can achieve a large viewing angle.

Further, the inclination angle of the longitudinal direction of the slit on the pixel electrode 411 with respect to the longitudinal direction of the second scanning line (refer to α in FIGS. 2 and 4) may be selected from the range of 75° to 85°. To achieve a better viewing angle.

As described above, as shown in FIG. 7, in the column direction, adjacent two color filters 430 extend obliquely in opposite directions. Specifically, the two adjacent color filters 430 include a first color filter 431 and a second color filter 432. The first color filter 431 includes a first end 4311 and a second end 4312. One end 4311 extends obliquely toward the second end 4312, and the second color filter 432 includes a third end 4321 and a fourth end 4322 and extends obliquely from the third end 4321 to the fourth end 4322, and the second end 4312 and the third end Ends 4321 are adjacent.

In other embodiments, for example, as shown in FIG. 8, the first projection 4313 of the first color filter 431 and the second projection 4323 of the second color filter 432 partially overlap in the row direction, in other words, the color filter substrate. The color filters 430 between adjacent rows on 420 are staggered in the row direction. Based on the arrangement, the color filter substrate 420 of the display panel 400 can be better adapted to the active switch array substrate 410 to achieve a larger viewing angle, increase the light transmittance, and also change the color difference to make the display Better results. In addition, it is worth mentioning that the "row direction" and the "column direction" described in the embodiments of the present application may be interchanged.

On the basis of the above embodiments, an embodiment of the present application provides a liquid crystal display 500. For example, as shown in FIG. 9, the backlight module 510 and the display panel 520 are included. The display panel 520 can adopt the display of the above embodiment. Panel 400. Specifically, the light emitted by the backlight module 510 is sequentially passed through the active switch array substrate 521 and the color filter substrate 522 of the display panel 520, and then converted into an image for display to the user.

In the several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Finally, it should be noted that the above embodiments are only used to explain the technical solutions of the present application, and are not limited thereto; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced by the equivalents. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A pixel structure in which:

First scan line;

a second scan line adjacent to the first scan line;

First data line;

a second data line adjacent to the first data line, wherein the first scan line and the second scan line are disposed to intersect with the first data line and the second data line to form a pixel unit Area;

a pixel electrode, the pixel electrode being located in the pixel unit region and electrically connecting the first scan line and the first data line, wherein the pixel electrode is provided from the first scan line to the second At least one slit extending from the scan line, and a length direction of the slit is inclined with respect to a length direction of the first scan line, and a length direction of the slit is inclined with respect to a length direction of the first scan line The angle range is from 75° to 85°.
The pixel structure of claim 1 , wherein the pixel structure further comprises a first thin film transistor and a second thin film transistor, a source of the first thin film transistor being connected to the first data line, the first thin film a gate of the transistor is connected to the first scan line, a drain of the first thin film transistor is connected to a source of the second thin film transistor, and a gate of the second thin film transistor is connected to the first scan line. The drain of the second thin film transistor is connected to the pixel electrode.
The pixel structure according to claim 2, wherein the first thin film transistor and the second thin film transistor are NMOS transistors or PMOS transistors.
The pixel structure according to claim 1, wherein the pixel electrode is made of a transparent conductive material including one or more of ITO, IZO, and ITZO.
A pixel structure in which:

First scan line;

a second scan line adjacent to the first scan line;

First data line;

a second data line adjacent to the first data line, wherein the first scan line and the second scan line are disposed to intersect with the first data line and the second data line to form a pixel unit Area;

a pixel electrode, the pixel electrode being located in the pixel unit region and electrically connecting the first scan line and the first data line, wherein the pixel electrode is provided from the first scan line to the second At least one slit extending from the scan line, and a length direction of the slit is inclined with respect to a length direction of the first scan line.
The pixel structure according to claim 5, wherein the pixel structure further comprises a first thin film transistor and a second thin film transistor, a source of the first thin film transistor is connected to the first data line, the first thin film a gate of the transistor is connected to the first scan line, a drain of the first thin film transistor is connected to a source of the second thin film transistor, and a gate of the second thin film transistor is connected to the first scan line. The drain of the second thin film transistor is connected to the pixel electrode.
The pixel structure according to claim 6, wherein the first thin film transistor and the second thin film transistor are NMOS transistors or PMOS transistors.
The pixel structure according to claim 5, wherein the pixel electrode is made of a transparent conductive material including one or more of ITO, IZO, and ITZO.
The pixel structure according to claim 5, wherein the pixel structure further comprises a first thin film transistor and a second thin film transistor, a source of the first thin film transistor is connected to the first data line, the first thin film a gate of the transistor is connected to the first scan line, a drain of the first thin film transistor is connected to a source of the second thin film transistor, and a gate of the second thin film transistor is connected to the first scan line. The drain of the second thin film transistor is connected to the pixel electrode; the pixel electrode is made of a transparent conductive material, and the transparent conductive material includes one or more of ITO, IZO, and ITZO.
The pixel structure according to claim 9, wherein the first thin film transistor and the second thin film transistor are NMOS transistors or PMOS transistors.
An active switch array substrate, comprising:

Transparent substrate;

And a first scan line disposed on the transparent substrate;

a third scan line disposed on the transparent substrate;

a second scan line disposed on the transparent substrate and the second scan line being located between the first scan line and the third scan line;

a first data line disposed on the transparent substrate;

a second data line disposed on the transparent substrate, wherein the first scan line and the second scan line are disposed to intersect with the first data line and the second data line to form a first pixel unit a region, the second scan line and the third scan line are disposed to intersect with the first data line and the second data line to form a second pixel unit adjacent to the first pixel unit area region;

a first pixel electrode disposed on the transparent substrate and the first pixel electrode being located in the first pixel unit region and electrically connecting the first scan line and the first data line, the first pixel The electrode is provided with at least one first slit extending from the first scan line to the second scan line;

a second pixel electrode disposed on the transparent substrate and the second pixel electrode being located in the second pixel unit region and electrically connecting the second scan line and the first data line, the second pixel The electrode is provided with at least one second slit extending from the second scan line to the third scan line;

One end of the first slit adjacent to the second scan line is closer to the first data line than an end of the first slit adjacent to the first scan line;

One end of the second slit adjacent to the second scan line is closer to the first data line than an end of the second slit adjacent to the third scan line.
The active switch array substrate according to claim 11, wherein an angle at which the longitudinal direction of the first slit is inclined with respect to a longitudinal direction of the second scanning line ranges from 75° to 85°.
The active switch array substrate according to claim 12, wherein the active switch array substrate further comprises: a common electrode disposed on the transparent substrate in the same layer as the first pixel electrode and the second pixel electrode.
The active switch array substrate according to claim 12, wherein the active switch array substrate further comprises: a common electrode disposed between the first pixel electrode and the second pixel electrode and the transparent substrate.
The active switch array substrate according to claim 12, wherein the first pixel electrode and the second pixel electrode are both made of a transparent conductive material, and the transparent conductive material comprises one or more of ITO, IZO, and ITZO. Kind.
The active switch array substrate according to claim 11, wherein the active switch array substrate further comprises: a common electrode disposed on the transparent substrate in the same layer as the first pixel electrode and the second pixel electrode.
The active switch array substrate according to claim 11, wherein the active switch array substrate further comprises: a common electrode disposed between the first pixel electrode and the second pixel electrode and the transparent substrate.
The active switch array substrate according to claim 11, wherein the first pixel electrode and the second pixel electrode are both made of a transparent conductive material, and the transparent conductive material comprises one or more of ITO, IZO, and ITZO. Kind.