WO2019057064A1

WO2019057064A1 - Array substrate and display panel

Info

Publication number: WO2019057064A1
Application number: PCT/CN2018/106447
Authority: WO
Inventors: 黄北洲
Original assignee: 惠科股份有限公司
Priority date: 2017-09-22
Filing date: 2018-09-19
Publication date: 2019-03-28
Also published as: CN107436519A

Abstract

Disclosed are an array substrate (10) and a display panel using the array substrate (10). The array substrate (10) comprises data lines (DL1, DL2), scanning lines (GL1, GL2, GL3), pixel electrodes (PE) and two active switch elements (T1, T2) connected in series, wherein the scanning lines (GL1, GL2, GL3) and the data lines (DL1, DL2) are arranged in an intersecting manner, the pixel electrodes (PE) are arranged at intersections of the scanning lines (GL1, GL2, GL3) and the data lines (DL1, DL2), the pixel electrodes (PE) are provided with at least one slit (ST), the length direction of the slit (ST) is inclined relative to the vertical direction of the scanning lines (GL1, GL2, GL3), and the two active switch elements (T1, T2) connected in series are connected to the scanning lines (GL1, GL2, GL3), the data lines (DL1, DL2) and the pixel electrodes so as to form a switch circuit.

Description

Array substrate and display panel

Technical field

The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display panel.

Background technique

The liquid crystal display has the advantages of high image quality, small size, light weight, low voltage drive, low power consumption and wide application range, so it has been widely used in medium and small portable TVs, mobile phones, video recorders. Consumer electronics or computer products such as notebook computers, desktop monitors, and projection TVs have gradually replaced the cathode ray tube (CRT) display. However, how to improve the pixel aperture ratio of the liquid crystal display and reduce the leakage current, thereby achieving better display quality has always been one of the important research topics.

Summary of the invention

Embodiments of the present disclosure provide an array substrate and a display panel to achieve a technical effect of reducing leakage current and achieving better display quality.

In one aspect, an array substrate is provided, including: a data line; a scan line, the scan line is disposed to intersect with the data line; and a pixel electrode disposed at an intersection of the scan line and the data line Wherein the pixel electrode is provided with at least one slit, the length direction of the slit is inclined with respect to a vertical direction of the scan line; two active switching elements connected in series, and two active switching elements connected in series And connecting the scan line, the data line and the pixel electrode to form a switch circuit; and a common electrode layer disposed in the same layer as the pixel electrode, or stacked with the pixel electrode and separated by an insulating layer; The number of the slits is plural and arranged in parallel with each other, and the plurality of slits are a hollow structure in which both ends of the pixel electrode are closed or a hollow structure in which one end is closed and the other end is open.

In another aspect, an array substrate is provided, including: a data line; a scan line, the scan line is disposed to intersect with the data line; and a pixel electrode, wherein the pixel electrode is disposed on the scan line and the data line At the intersection, the pixel electrode is provided with at least one slit, the length direction of the slit is inclined with respect to a vertical direction of the scanning line; and two active switching elements connected in series, the two actives in series A switching element is coupled to the scan line, the data line, and the pixel electrode to form a switching circuit.

In an embodiment of the present disclosure, an angle at which the longitudinal direction of the slit is inclined with respect to a vertical direction of the scanning line ranges from 2° to 8°.

In an embodiment of the present disclosure, a line width of the scan line is greater than a line width of the data line.

In one embodiment of the present disclosure, the number of the slits is plural and disposed in parallel with each other, and the plurality of slits are hollow structures closed at both ends of the pixel electrode or hollowed out at one end and open at the other end structure.

In an embodiment of the present disclosure, the array substrate further includes: a common electrode layer disposed in the same layer as the pixel electrode.

In an embodiment of the present disclosure, the array substrate further includes: a common electrode layer, and the pixel electrode is stacked and spaced apart by an insulating layer.

In an embodiment of the present disclosure, the two active switching elements include a first active switching element and a second active switching element, and a first electrode end of the first active switching element is connected to the data line a second electrode end of the first active switching element is connected from a side of the data line across the data line to a first electrode end of the second active switching element, the second A second electrode end of the source switching element is coupled to the pixel electrode, and a control electrode end of the first active switching element and a control electrode end of the second active switching element are coupled to the scan line.

In an embodiment of the present disclosure, the pixel electrode is an ITO transparent electrode.

In one embodiment of the present disclosure, the two active switching elements include a first active switching element and a second active switching element, a first electrode end and a second of the first active switching element a second electrode end of the active switching element is located at one side of the scan line, and a second electrode end of the first active switching element and a first electrode end of the second active switching element are located on the scan line On the other side, the control electrode terminal of the first active switching element and the control electrode terminal of the second active switching element are connected to the scan line.

In another aspect, a display panel is provided, including: an array substrate, wherein the array substrate includes a data line, a scan line, a pixel electrode, and two active switching elements connected in series, wherein the scan line is disposed opposite to the data line The pixel electrode is disposed at an intersection of the scan line and the data line, and the pixel electrode is provided with at least one slit, and a length direction of the slit is inclined with respect to a vertical direction of the scan line. The two active switching elements connected in series are connected to the scan line, the data line and the pixel electrode to form a switch circuit; a color filter substrate, the color filter substrate is opposite to the array substrate and a plurality of liquid crystal molecules, the plurality of liquid crystal molecules being located between the array substrate and the color filter substrate; and a sealant, the sealant being located on the array substrate and the color filter An accommodating space is formed between the substrates and the array substrate and the color filter substrate to accommodate the plurality of liquid crystal molecules.

In an embodiment of the present disclosure, the color filter substrate includes a plurality of color filters, and the plurality of color filters include a red filter, a green filter, and a blue filter.

In an embodiment of the present disclosure, the display panel is an in-plane switching mode liquid crystal display panel or a fringe field switching mode liquid crystal display panel; the array substrate further includes: a common electrode layer; the common electrode layer and the pixel The electrodes are disposed in the same layer, or the common electrode layer is laminated with the pixel electrodes and spaced apart by an insulating layer.

One of the above technical solutions has the following advantages: the connection between the pixel electrode and the data line and the scan line is realized by two active switching elements connected in series, which can reduce the leakage current of the pixel structure and maintain the pixel electrode Voltage. Furthermore, by opening one or more slits inclined in the vertical direction with respect to the scanning line on the pixel electrode, it is possible to preset a certain inclination angle for the arrangement of the liquid crystal molecules, thereby significantly increasing the viewing angle of the display panel. . In addition, with the common electrode disposed on the array substrate, it can realize an in-plane switching mode liquid crystal display panel or a fringe field switching mode liquid crystal display panel.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

FIG. 1 is a schematic diagram of a layout of a pixel structure in an embodiment of the present disclosure.

2 is a schematic view showing the layout of an array substrate in still another embodiment of the present disclosure.

FIG. 3 is a schematic structural diagram of an in-plane switching mode liquid crystal display panel according to another embodiment of the present disclosure.

FIG. 4 is a schematic structural diagram of a fringe field switching mode liquid crystal display panel according to still another embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present disclosure. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.

As shown in FIG. 1 , a pixel structure 110 provided in one embodiment of the present disclosure includes: adjacently disposed scan lines GL1 and scan lines GL2, adjacently disposed data lines DL1 and data lines DL2, and switching elements T1 ( A first active switching element), a switching element T2 (second active switching element), and a pixel electrode PE.

The scan lines GL1 and GL2 are arranged to intersect with the data lines DL1 and DL2 to form a pixel area PA (shown by a broken line in FIG. 1), and the pixel electrode PE is located in the pixel area PA and connected to the scan line GL1 through the switching elements T1 and T2. And data line DL1. In other words, the pixel area PA is located at the intersection of the scanning line GL1 and the data line DL1 to which the pixel electrode PE is connected by the switching elements T1 and T2, so that the scanning line GL2 and the data line DL2 may not be used to some extent. A constituent part of the pixel structure 110. Furthermore, it can be seen from FIG. 1 that the scan line GL1 and the scan line GL2 are arranged substantially in parallel, and the data lines DL1 and DL2 are also arranged substantially in parallel, so that the scan line GL1, the scan line GL2, the data line DL1 and the data line DL2 are collectively arranged. It becomes a substantially quadrilateral pixel area PA.

In the above, the source S1 of the switching element T1 is connected to the data line DL1, the gate G1 of the switching element T1 is connected to the scanning line GL1, the drain D1 of the switching element T1 is connected to the source S2 of the switching element T2, and the gate G2 of the switching element T2 The scan line GL1 is connected, and the drain D2 of the switching element T2 is connected to the pixel electrode PE. In other words, the switching element T1 and the switching element T2 are connected in series between the data line DL1 and the pixel electrode PE and the gates G1, G2 of both are connected to the same scanning line GL1; this embodiment passes the switching element T1 and The switching element T2 is connected in series to form a switching circuit, which can reduce the leakage current of the pixel structure 110 and maintain the voltage on the pixel electrode PE. Furthermore, it can be seen from the layout structure of the pixel structure 110 of FIG. 1 that the drain D1 of the switching element T1 extends from one side of the data line DL1 across the data line DL1 and is connected to the source S2 of the switching element T2. The source S1 of the switching element T1 and the drain D2 of the switching element T2 are located on the same side of the scanning line GL1 (for example, the upper side of the scanning line GL1 in FIG. 1), and the drain D1 of the switching element T1 and the switching element T2 The source S2 is located on the other opposite side of the scan line GL1 (for example, the lower side of the scan line GL1 in FIG. 1), so that the overall layout structure of the switching element T1 and the switching element T2 is substantially U-shaped, and the layout manner can be greatly Increase the pixel aperture ratio. In addition, it is worth mentioning that the switching elements T1, T2 may be NMOS transistors or PMOS transistors; of course, the switching elements T1, T2 may also be other three-terminal active switching elements, such as one of the source and the drain They may be collectively referred to as a first electrode terminal and the other as a second electrode terminal, and the gates are collectively referred to as a control electrode terminal. In addition, in other embodiments, the source S1 of the switching element T1, the drain D2 of the switching element T2, the drain D1 of the switching element T1, and the source S2 of the switching element T2 may also be located on the same side of the scanning line GL1.

Further, in order to provide a certain pretilt angle of the liquid crystal molecules to achieve an effect of increasing the viewing angle, the pixel electrode PE is provided with at least one slit ST extending from the scanning line GL1 toward the scanning line GL2, for example, two parallel narrow lines as shown in FIG. The slit ST has a length direction which is inclined with respect to the vertical direction of the scanning line GL1 (that is, the vertical direction in FIG. 1). Optionally, the inclination angle α of the longitudinal direction of the slit ST relative to the vertical direction of the scanning line GL1 ranges from 2° to 8°, so that the liquid crystal molecules have a better pretilt angle, thereby achieving better display effect. Furthermore, it can be seen from FIG. 1 that each of the slits ST extends from the scanning line GL1 to the scanning line GL2 and penetrates through the pixel electrode PE, or in other words, the slit ST is hollowed out and closed at both ends. Of course, it can also be a hollow structure with one end closed and the other end open. Further, the pixel electrode PE is typically a transparent electrode such as an ITO (Indium Tin Oxide) electrode or the like.

In summary, the pixel structure 110 provided in this embodiment realizes the connection between the pixel electrode PE and the data line DL1 and the scan line GL1 through the dual series switching element having a specific layout structure, which can reduce the leakage of the pixel structure 110. The current, the voltage on the pixel electrode PE, and the pixel aperture ratio are effectively increased. Furthermore, one or more slits ST extending from one of the adjacent two scanning lines, for example, GL1, GL2, to the other scanning line GL2 are opened on the pixel electrode PE, and the length of the slit ST is made. The direction is inclined with respect to the vertical direction of the scanning lines GL1/GL2, which can preset a certain inclination angle for the arrangement of the liquid crystal molecules, so that the viewing angle of the display device having the pixel structure 110 can be remarkably improved.

As shown in FIG. 2, an array substrate 10 provided in still another embodiment of the present disclosure includes: a transparent substrate 11, a plurality of scanning lines such as GL1, GL2, GL3, a plurality of data lines such as DL1, DL2, and a plurality of switches Elements such as T1 (first active switching element), T2 (second active switching element), T3 (first active switching element), T4 (second active switching element), and a plurality of pixel electrodes such as PE1, PE2 These scan lines GL1, GL2, GL3, these data lines DL1, DL2, these switching elements T1, T2, T3, T4 and these pixel electrodes PE1, PE2 are disposed on the transparent substrate 11. The scan line GL1 and the scan line GL2 are disposed adjacent to each other, and the scan line GL2 is disposed adjacent to the scan line GL3, so that the scan line GL2 is located between the scan line GL1 and the scan line GL3. The data line DL1 and the data line DL2 are arranged adjacent to each other.

The scanning lines GL1 and GL2 are disposed to intersect with the data lines DL1 and DL2 to form a pixel area PA1. The pixel electrode PE1 is disposed in the pixel area PA1 and is connected to the scanning line GL1 and the data line DL1 via the switching elements T1 and T2. In other words, the pixel area PA1 is located at the intersection of the scanning line GL1 and the data line DL1 to which the pixel electrode PE1 is connected by the switching elements T1 and T2. Furthermore, it can be seen from FIG. 2 that the scan line GL1 and the scan line GL2 are arranged substantially in parallel, and the data lines DL1 and DL2 are also arranged substantially in parallel, so that the scan line GL1, the scan line GL2, the data line DL1 and the data line DL2 are collectively arranged. It becomes a substantially quadrangular pixel area PA1.

In the above, the source S1 of the switching element T1 is connected to the data line DL1, the gate G1 of the switching element T1 is connected to the scanning line GL1, the drain D1 of the switching element T1 is connected to the source S2 of the switching element T2, and the gate G2 of the switching element T2 The scan line GL1 is connected, and the drain D2 of the switching element T2 is connected to the pixel electrode PE1. In other words, the switching element T1 and the switching element T2 are connected in series between the data line DL1 and the pixel electrode PE1 and the gates G1, G2 of both are connected to the same scanning line GL1; this embodiment passes the switching element T1 and The switching element T2 is connected in series to form a switching circuit, which can reduce the leakage current of the pixel structure and maintain the voltage on the pixel electrode PE1. Furthermore, it can be seen from the layout structure shown in FIG. 2 that the drain D1 of the switching element T1 extends from one side of the data line DL1 across the data line DL1 and is connected to the source S2 of the switching element T2. The source S1 of the element T1 and the drain D2 of the switching element T2 are located on the same side of the scanning line GL1 (for example, the upper side of the scanning line GL1 in FIG. 2), and the drain D1 of the switching element T1 and the source of the switching element T2. S2 is located on the other opposite side of the scan line GL1 (for example, the lower side of the scan line GL1 in FIG. 2), so that the overall layout structure of the switching element T1 and the switching element T2 is substantially U-shaped, and the layout can be greatly improved. Pixel aperture ratio. In addition, it is worth mentioning that the switching elements T1, T2 may be NMOS transistors or PMOS transistors; of course, the switching elements T1, T2 may also be other three-terminal active switching elements, such as one of the source and the drain They may be collectively referred to as a first electrode terminal and the other as a second electrode terminal, and the gates are collectively referred to as a control electrode terminal. In addition, in other embodiments, the source S1 of the switching element T1, the drain D2 of the switching element T2, the drain D1 of the switching element T1, and the source S2 of the switching element T2 may also be located on the same side of the scanning line GL1.

Further, in order to provide a certain pretilt angle of the liquid crystal molecules, the pixel electrode PE1 is provided with at least one slit ST1 extending from the scanning line GL1 toward the scanning line GL2, for example, two parallel slits ST1 shown in FIG. 2, and the slit ST1 The length direction is inclined with respect to the vertical direction of the scanning line GL2 (that is, the vertical direction in FIG. 2). Optionally, the inclination angle α of the longitudinal direction of the slit ST1 with respect to the vertical direction of the scanning line GL2 ranges from 2° to 8°, so that the liquid crystal molecules have a better pretilt angle, thereby achieving better display effect. Furthermore, it can be seen from FIG. 2 that each of the slits ST1 extends from the scanning line GL1 to the scanning line GL2 and penetrates through the pixel electrode PE1, or in other words, the slit ST1 is hollowed out and closed at both ends. Of course, it can also be a hollow structure with one end closed and the other end open. In addition, the pixel electrode PE1 is typically a transparent electrode such as an ITO electrode or the like.

Similarly, the scanning lines GL2 and GL3 are arranged to intersect with the data lines DL1 and DL2 to form a pixel area PA2 adjacent to the pixel area PA1. The pixel electrode PE2 is disposed in the pixel area PA2 and is connected to the scanning line GL2 and the data line DL1 through the switching elements T3, T4. In other words, the pixel area PA2 is located at the intersection of the scanning line GL2 and the data line DL1 to which the pixel electrode PE2 is connected by the switching elements T3 and T3. Furthermore, it can be seen from FIG. 2 that the scan line GL2 and the scan line GL3 are arranged substantially in parallel, and the data lines DL1 and DL2 are also arranged substantially in parallel, so that the scan line GL2, the scan line GL3, the data line DL1 and the data line DL2 are collectively arranged. It becomes a substantially quadrangular pixel area PA2.

In the above, the source of the switching element T3 is connected to the data line DL1, the gate of the switching element T3 is connected to the scanning line GL2, the drain of the switching element T3 is connected to the source of the switching element T4, and the gate of the switching element T4 is connected to the scanning line GL2. And the drain of the switching element T4 is connected to the pixel electrode PE2. In other words, the switching element T3 and the switching element T4 are connected in series between the data line DL1 and the pixel electrode PE2 and the gates of both are connected to the same scanning line GL2; this embodiment passes the switching element T3 and the switching element T4. The series connection can reduce the leakage current of the pixel structure and maintain the voltage on the pixel electrode PE2. Furthermore, it can be seen from the layout structure shown in FIG. 2 that the drain of the switching element T3 extends from one side of the data line DL1 across the data line DL1 and is connected to the source of the switching element T4, and the switching element T3 The drain of the source and switching element T4 is located on the same side of the scan line GL2 (for example, the upper side of the scan line GL2 in FIG. 2), and the drain of the switching element T3 and the source of the switching element T4 are both located on the scan line GL2. The other opposite side (for example, the lower side of the scanning line GL2 in FIG. 2), so that the overall layout structure of the switching element T3 and the switching element T3 is substantially U-shaped, this layout can greatly increase the pixel aperture ratio. In addition, it is worth mentioning that the switching elements T3, T4 may be NMOS transistors or PMOS transistors; of course, the switching elements T3, T4 may also be other three-terminal active switching elements, such as one of the source and the drain. They may be collectively referred to as a first electrode terminal and the other as a second electrode terminal, and the gates are collectively referred to as a control electrode terminal. In addition, in other embodiments, the source of the switching element T3, the drain of the switching element T4, the drain of the switching element T3, and the source of the switching element T4 may also be located on the same side of the scanning line GL2.

Further, in order to provide a certain pretilt angle of the liquid crystal molecules, the pixel electrode PE2 is provided with at least one slit ST2 extending from the scanning line GL2 toward the scanning line GL3, for example, two parallel slits ST2 shown in FIG. 2, and the slit ST2 The length direction is inclined with respect to the vertical direction of the scanning line GL2 (that is, the vertical direction in FIG. 2). Optionally, the inclination angle β of the longitudinal direction of the slit ST2 with respect to the vertical direction of the scanning line GL2 ranges from 2° to 8°, so that the liquid crystal molecules have a better pretilt angle, thereby achieving better display effect. Furthermore, it can be seen from FIG. 2 that each of the slits ST2 extends from the scanning line GL2 to the scanning line GL3 and penetrates through the pixel electrode PE2, or in other words, the slit ST2 has a hollow structure and is closed at both ends. Of course, it can also be a hollow structure with one end closed and the other end open. In addition, the pixel electrode PE2 is typically a transparent electrode such as an ITO electrode or the like.

Further, comparing the inclination directions of the slits ST1 and the slits ST2 in FIG. 2, it is also known that the slit ST1 is closer to the data line DL1 than the other end of the scanning line GL1 adjacent to the scanning line GL2, and the slit One end of the ST2 adjacent to the scanning line GL2 is closer to the data line DL1 with respect to the other end thereof adjacent to the scanning line GL3; in short, the slit ST1 and the slit ST2 in the adjacent two rows of pixel electrodes PE1, PE2 are inclined in opposite directions Settings.

In addition, in FIG. 2, since the scan lines GL1, GL2 directly cross the gates of the corresponding switching elements T1, T2, T3, and T4, it is optional to set a scan line having a larger width W1 than the data line. Line width W2.

Referring to FIG. 3, an IPS (In Plane Switching) mode liquid crystal display panel according to another embodiment of the present disclosure includes: an array substrate 20, a color filter substrate 30, a sealant 40, and a plurality of liquid crystal molecules. 50. The array substrate 20 and the color filter substrate 30 are opposite and spaced apart, and the sealant 40 is disposed between the array substrate 20 and the color filter substrate 30 to form an accommodation space together with the array substrate 20 and the color filter substrate 30. The display medium molecules such as these liquid crystal molecules 50 are accommodated.

In the above, the array substrate 20 includes a transparent substrate 21, a pixel electrode PE, and a common electrode layer CE; the pixel electrode PE and the common electrode layer CE are disposed on the transparent substrate 21 in the same layer, thereby applying an appropriate voltage to the pixel electrode PE and the common electrode layer CE. A planar electric field (or transverse electric field) may be formed between the two to deflect the liquid crystal molecules 50. It is worth mentioning here that the structure of the array substrate 20 other than the common electrode layer CE can adopt the structure shown in FIG. 2, and details are not described herein again. A plurality of color filters such as a red color filter R, a green color filter G, and a blue color filter B are disposed on the color filter substrate 30.

Referring to FIG. 4, an FFS (Fringe Field Switching) mode liquid crystal display panel provided by another embodiment of the present disclosure includes: an array substrate 60, a color filter substrate 70, a sealant 80, and a plurality of liquid crystal molecules. 90. The array substrate 60 and the color filter substrate 70 are opposite and spaced apart, and the sealant 80 is disposed between the array substrate 60 and the color filter substrate 70 to form an accommodating space together with the array substrate 60 and the color filter substrate 70. These liquid crystal molecules 90 are accommodated.

In the above, the array substrate 60 includes a transparent substrate 61 and a common electrode layer CE, an insulating layer 63, and a pixel electrode PE disposed on the transparent substrate 61. The pixel electrode PE and the common electrode layer CE are spaced apart by the insulating layer 63, so that the common electrode layer The CE is located between the transparent substrate 61 and the pixel electrode PE. A fringe electric field may be formed between the two when the appropriate voltage is applied to the pixel electrode PE and the common electrode layer CE to deflect the liquid crystal molecules 90. It is worth mentioning here that the structure of the array substrate 60 other than the common electrode layer CE can adopt the structure shown in FIG. 2, and details are not described herein again. A plurality of color filters such as a red color filter R, a green color filter G, and a blue color filter B are disposed on the color filter substrate 70.

In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and/or methods may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

It should be noted that the above embodiments are only for explaining the technical solutions of the present disclosure, and are not intended to be limiting; although the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced by the equivalents. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

An array substrate comprising:

Data line

a scan line, the scan line being disposed across the data line;

a pixel electrode, the pixel electrode is disposed at an intersection of the scan line and the data line, the pixel electrode is provided with at least one slit, and a length direction of the slit is inclined with respect to a vertical direction of the scan line ;

Two active switching elements connected in series, the two active switching elements connected in series are connected to the scan line, the data line and the pixel electrode to form a switching circuit;

a common electrode layer disposed in the same layer as the pixel electrode or laminated with the pixel electrode and separated by an insulating layer;

The number of the slits is plural and arranged in parallel with each other, and the plurality of slits are a hollow structure in which both ends of the pixel electrode are closed or a hollow structure in which one end is closed and the other end is open.
An array substrate comprising:

Data line

a scan line, the scan line being disposed across the data line;

a pixel electrode, the pixel electrode is disposed at an intersection of the scan line and the data line, the pixel electrode is provided with at least one slit, and a length direction of the slit is inclined with respect to a vertical direction of the scan line ;as well as

Two active switching elements are connected in series, and the two active switching elements connected in series are connected to the scan line, the data line and the pixel electrode to form a switching circuit.
The array substrate according to claim 2, wherein an angle at which the longitudinal direction of the slit is inclined with respect to a vertical direction of the scanning line ranges from 2 to 8 degrees.
The array substrate according to claim 2, wherein a line width of the scan line is larger than a line width of the data line.
The array substrate according to claim 2, wherein the number of the slits is plural and arranged in parallel with each other, and the plurality of slits are hollow structures closed at both ends of the pixel electrode or closed at one end and the other end Openwork hollow structure.
The array substrate according to claim 2, further comprising: a common electrode layer disposed in the same layer as the pixel electrode.
The array substrate according to claim 2, further comprising: a common electrode layer laminated with the pixel electrode and separated by an insulating layer.
The array substrate according to claim 2, wherein the two active switching elements comprise a first active switching element and a second active switching element, and a first electrode terminal of the first active switching element is connected a data line, the second electrode end of the first active switching element is connected from a side of the data line across the data line to a first electrode end of the second active switching element, A second electrode end of the second active switching element is coupled to the pixel electrode, and a control electrode end of the first active switching element and a control electrode end of the second active switching element are coupled to the scan line.
The array substrate according to claim 2, wherein the pixel electrode is an ITO transparent electrode.
The array substrate according to claim 2, wherein the two active switching elements comprise a first active switching element and a second active switching element, a first electrode end of the first active switching element a second electrode end of the second active switching element is located at one side of the scan line, and a second electrode end of the first active switching element and a first electrode end of the second active switching element are located at On the other side of the scan line, the control electrode terminal of the first active switching element and the control electrode terminal of the second active switching element are connected to the scan line.
A display panel comprising:

An array substrate including a data line, a scan line, a pixel electrode, and two active switching elements connected in series, the scan line is disposed to intersect with the data line, and the pixel electrode is disposed on the scan line and the At the intersection of the data lines, the pixel electrode is provided with at least one slit, the length direction of the slit is inclined with respect to a vertical direction of the scan line, and the two active switching elements connected in series and the scan The line, the data line and the pixel electrode are connected to form a switching circuit;

a color filter substrate, the color filter substrate being opposite to the array substrate and spaced apart;

a plurality of liquid crystal molecules, the plurality of liquid crystal molecules being located between the array substrate and the color filter substrate;

The frame glue is disposed between the array substrate and the color filter substrate to form an accommodating space with the array substrate and the color filter substrate to accommodate the plurality of liquid crystal molecules.
The display panel according to claim 11, wherein an angle at which the longitudinal direction of the slit is inclined with respect to a vertical direction of the scanning line ranges from 2 to 8 degrees.
The display panel according to claim 11, wherein a line width of the scan line is larger than a line width of the data line.
The display panel according to claim 11, wherein the number of the slits is plural and arranged in parallel with each other, and the plurality of slits are hollow structures closed at both ends of the pixel electrode or one end is closed and the other end is closed. Openwork hollow structure.
The display panel according to claim 11, wherein the two active switching elements comprise a first active switching element and a second active switching element, and the first electrode terminal of the first active switching element is connected a data line, the second electrode end of the first active switching element is connected from a side of the data line across the data line to a first electrode end of the second active switching element, A second electrode end of the second active switching element is coupled to the pixel electrode, and a control electrode end of the first active switching element and a control electrode end of the second active switching element are coupled to the scan line.
The display panel according to claim 11, wherein the pixel electrode is an ITO transparent electrode.
The display panel of claim 11, wherein the two active switching elements comprise a first active switching element and a second active switching element, a first electrode end of the first active switching element a second electrode end of the second active switching element is located at one side of the scan line, and a second electrode end of the first active switching element and a first electrode end of the second active switching element are located at On the other side of the scan line, the control electrode terminal of the first active switching element and the control electrode terminal of the second active switching element are connected to the scan line.
The display panel according to claim 11, wherein the color filter substrate comprises a plurality of color filters, and the plurality of color filters comprise a red filter, a green filter, and a blue filter. Light film.
The display panel according to claim 11, wherein the display panel is an in-plane switching mode liquid crystal display panel; the array substrate further comprises: a common electrode layer disposed in the same layer as the pixel electrode.
The display panel according to claim 11, wherein the display panel is a fringe field switching mode liquid crystal display panel; the array substrate further comprises: a common electrode layer, and the pixel electrode is stacked and spaced apart by an insulating layer.