WO2019052578A1 - Procédé et appareil d'entrelacement - Google Patents

Procédé et appareil d'entrelacement Download PDF

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Publication number
WO2019052578A1
WO2019052578A1 PCT/CN2018/106241 CN2018106241W WO2019052578A1 WO 2019052578 A1 WO2019052578 A1 WO 2019052578A1 CN 2018106241 W CN2018106241 W CN 2018106241W WO 2019052578 A1 WO2019052578 A1 WO 2019052578A1
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WO
WIPO (PCT)
Prior art keywords
interleaver
interleaved
bits
bit
written
Prior art date
Application number
PCT/CN2018/106241
Other languages
English (en)
Chinese (zh)
Inventor
陈莹
张公正
乔云飞
王桂杰
罗禾佳
李榕
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2019052578A1 publication Critical patent/WO2019052578A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2717—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions the interleaver involves 3 or more directions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • FIG. 21 is a structural block diagram of an interleaving apparatus according to an embodiment of the present application.
  • FIG. 26 is a structural block diagram of another interleaving apparatus according to an embodiment of the present application.
  • the order of the numbers to be interleaved in the bit sequence is the order in which the bit sequence to be interleaved is written into the interleaver. For example, the number 1 is the first bit written to the interleaver, the number 2 is the second bit written to the interleaver, and so on.
  • the method shown in Figure 4 provides an interleaving method with lower complexity but better interleaving performance.
  • Figure 8 is a schematic illustration of another write to the interleaver in the diagonal direction of the interleaver.
  • the order of reading of any two bits having the same writing order is the same.
  • the bit numbered 3 and the number 6 as an example, when reading two interleavers, the bit numbered 3 is always read before the bit numbered 6.
  • the interleaving method provided in the embodiment of the present invention can ensure that the order of reading any two bits with the same sequence number in the bit sequence to be interleaved of different lengths is the same in the interleaving method provided in the embodiment of the present application.
  • the regularity of the interleaving manner provided by the above technical solution is lower than the regularity of the interleaving manner. Therefore, the performance of the interleaving method is higher than that of the interleaving mode.
  • the interleaving performance of the interleaving method is good.
  • 1 to 9 as shown in FIG. 13 indicate the order in which bits in the bit sequence to be interleaved are written into the interleaver.
  • the number of bits in the bit sequence to be interleaved is the same as the order in which the bits in the bit sequence to be interleaved are written into the interleaver. For example, the number 1 is the first bit written to the interleaver, the number 2 is the second bit written to the interleaver, and so on.
  • the 12 bits are written to the interleaver in the column direction of the interleaver starting from one corner of the interleaver.
  • the bits written into the interleaver form a rectangular two-dimensional array as shown in FIG.
  • the method shown in Figure 17 provides an interleaving method with lower complexity but better interleaving performance.
  • Some or all of the interleaving methods shown in FIG. 17 can be implemented by software using the interleaving device 2400.
  • the memory 2401 may be a physically separate unit or may be integrated with the processor 2402.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé et un appareil d'entrelacement. Le procédé consiste à : acquérir une séquence de bits à entrelacer (401) ; écrire des bits en une séquence de bits à entrelacer dans un entrelaceur (402) ; et lire, à partir de l'entrelaceur, les bits écrits dans l'entrelaceur (403), deux bits quelconques ayant la même séquence d'écriture dans les séquences de bits à entrelacer de longueurs différentes ayant les mêmes séquences de lecture. Le procédé et l'appareil fournissent un procédé d'entrelacement de faible complexité et de bonne performance d'entrelacement.
PCT/CN2018/106241 2017-09-18 2018-09-18 Procédé et appareil d'entrelacement WO2019052578A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710841684.1 2017-09-18
CN201710841684.1A CN109525255B (zh) 2017-09-18 2017-09-18 交织方法和交织装置

Publications (1)

Publication Number Publication Date
WO2019052578A1 true WO2019052578A1 (fr) 2019-03-21

Family

ID=65722447

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/106241 WO2019052578A1 (fr) 2017-09-18 2018-09-18 Procédé et appareil d'entrelacement

Country Status (2)

Country Link
CN (1) CN109525255B (fr)
WO (1) WO2019052578A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112804026A (zh) * 2019-11-13 2021-05-14 中国科学院上海高等研究院 一种ofdm系统中频率、时频交织方法及系统

Citations (5)

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Publication number Priority date Publication date Assignee Title
CN1642275A (zh) * 2004-03-05 2005-07-20 上海交通大学 一种用于数字电视地面传输的比特交织方法
CN101217349A (zh) * 2007-01-05 2008-07-09 中兴通讯股份有限公司 一种混合自动重传请求中比特收集的装置与方法
US20100002792A1 (en) * 2007-01-16 2010-01-07 Koninklijke Philips Electronics, N.V. System, apparatus and method for interleaving data bits or symbols
CN103166736A (zh) * 2011-12-15 2013-06-19 无锡中星微电子有限公司 一种交织器读写方法
CN105490776A (zh) * 2015-11-26 2016-04-13 华为技术有限公司 交织方法及交织器

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CN101442383B (zh) * 2007-11-22 2012-11-28 中兴通讯股份有限公司 一种高阶调制中的比特优先映射方法
CN101453292B (zh) * 2007-11-30 2011-09-28 大唐移动通信设备有限公司 信道交织方法及装置
KR102157667B1 (ko) * 2014-05-15 2020-09-18 삼성전자주식회사 천공 장치 및 그의 천공 방법
US10231121B2 (en) * 2015-06-24 2019-03-12 Lg Electronics Inc. Security communication using polar code scheme
CN104993837B (zh) * 2015-07-24 2018-08-03 丽水博远科技有限公司 一种卷积交织方法和卷积交织器
CN107863970A (zh) * 2016-09-22 2018-03-30 华为技术有限公司 交织方法与解交织方法及设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1642275A (zh) * 2004-03-05 2005-07-20 上海交通大学 一种用于数字电视地面传输的比特交织方法
CN101217349A (zh) * 2007-01-05 2008-07-09 中兴通讯股份有限公司 一种混合自动重传请求中比特收集的装置与方法
US20100002792A1 (en) * 2007-01-16 2010-01-07 Koninklijke Philips Electronics, N.V. System, apparatus and method for interleaving data bits or symbols
CN103166736A (zh) * 2011-12-15 2013-06-19 无锡中星微电子有限公司 一种交织器读写方法
CN105490776A (zh) * 2015-11-26 2016-04-13 华为技术有限公司 交织方法及交织器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112804026A (zh) * 2019-11-13 2021-05-14 中国科学院上海高等研究院 一种ofdm系统中频率、时频交织方法及系统

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CN109525255B (zh) 2022-04-05
CN109525255A (zh) 2019-03-26

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