WO2019047392A1 - 一种差分线路测试信息确定方法及设备 - Google Patents

一种差分线路测试信息确定方法及设备 Download PDF

Info

Publication number
WO2019047392A1
WO2019047392A1 PCT/CN2017/114422 CN2017114422W WO2019047392A1 WO 2019047392 A1 WO2019047392 A1 WO 2019047392A1 CN 2017114422 W CN2017114422 W CN 2017114422W WO 2019047392 A1 WO2019047392 A1 WO 2019047392A1
Authority
WO
WIPO (PCT)
Prior art keywords
information
test
differential line
circuit board
differential
Prior art date
Application number
PCT/CN2017/114422
Other languages
English (en)
French (fr)
Inventor
杨连卫
叶宗顺
许弘
Original Assignee
南京协辰电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京协辰电子科技有限公司 filed Critical 南京协辰电子科技有限公司
Publication of WO2019047392A1 publication Critical patent/WO2019047392A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance

Definitions

  • the invention relates to the technical field of circuit board testing, and in particular to a method and a device for determining differential line test information.
  • the embodiment of the present invention provides a method and a device for determining differential line test information, so as to solve the differential impedance test of the circuit board in the prior art, the test efficiency is low and cannot be tested.
  • An embodiment of the present invention provides a method for determining differential line test information, including: acquiring a printed circuit board design file; determining a network name of the differential line pair according to the printed circuit board design file; according to the network name and the The printed circuit board design file determines test indicator information for the differential line pair.
  • the printed circuit board design file includes a network information file, where the network information file records a network name and whether each network is an identifier of a differential network; and the determining the differential line according to the printed circuit board design file.
  • the network name of the pair includes: extracting, from the network information file, a network name of the differential line pair according to a network name in the network information file and an identifier of each network as a differential network.
  • the printed circuit board design file includes a test point information file, where the test point information file records a network name and corresponding endpoint coordinate information; and the test indicator information includes the same end test of the differential line pair. Point coordinate information.
  • the determining the test indicator information of the differential line pair according to the network name and the printed circuit board design file including: querying, in the test point information file, a network name of the differential line pair And corresponding endpoint coordinate information; determining coordinate information of the same end test point according to the coordinate information of the endpoint.
  • the determining, according to the endpoint coordinate information, coordinate information of the same end test point including: determining end point coordinate information with the same abscissa value; and selecting a set of end point coordinate information with the same abscissa value The information is used as coordinate information of the same end test point.
  • test indicator information further includes angle information between the peer test points.
  • the method further includes: using an arctangent formula to obtain angle information between the peer test points.
  • test indicator information further includes distance information between the peer test points.
  • the method further includes: calculating distance information between the test points at the same end by using a distance formula between two points and coordinate information of the same end test point.
  • the printed circuit board design file includes a line width information file, where the line width information file records a network name and corresponding line length information of the layer; the test indicator information includes line length information of the layer at the layer .
  • the determining the test indicator information of the differential line pair according to the network name and the printed circuit board design file including: querying, in the line width information file, a network name of the differential line pair And comparing the line length information of the layer corresponding to the network name of the differential line pair that is queried; extracting the line length information of the layer having the maximum value.
  • the printed circuit board design file includes a line width information file and a impedance design value file, where the line width information file records a network name and corresponding layer information and line length information of the layer; the impedance The design value file records at least one of layer information and corresponding line width information, corresponding impedance information, and corresponding tolerance information; the test index information includes at least one of line width information, impedance information, and tolerance information.
  • the determining, according to the network name and the printed circuit board design file, the test indicator information of the differential line pair comprises: querying, in the line width information file, the network of the differential line pair a name; comparing the line length information of the layer corresponding to the network name of the differential line pair that is queried; extracting the layer information corresponding to the line length information of the layer having the largest value; and querying and extracting in the impedance design value file At least one of the line width information corresponding to the layer information, the corresponding impedance information, and the corresponding tolerance information.
  • the printed circuit board design file includes a line width information file, where the line width information file records a network name and corresponding line total length information; and the test indicator information includes line total length information.
  • the determining, according to the network name and the printed circuit board design file, the test indicator information of the differential line pair comprises: querying, in the line width information file, the network of the differential line pair Name; extracts the total line length information corresponding to the network name that is queried.
  • the embodiment of the present invention further provides a computer readable storage medium having stored thereon a computer program, the computer program being executed by the processor to implement the differential line test information determination according to any one of claims 1-15 method.
  • Embodiments of the present invention also provide a computer device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores a computer executable by the at least one processor a program executed by the at least one processor to cause the at least one processor to perform the differential line test information determining method of any one of claims 1-15.
  • Embodiments of the present invention provide a method and a device for determining differential line test information, the method comprising: first obtaining a printed circuit board design file, and the printed circuit board design file includes all network information, test point information, etc. of the printed circuit board. Information, determining the network name of the differential line pair according to the printed circuit board design file, and determining the test index information of the differential line pair according to the network name of the differential line pair and the printed circuit board design file.
  • the automatic device After the differential line test information determining method provided by the embodiment of the present invention, after extracting the test index information of the differential line pair, the automatic device reads the information, and performs automatic test according to the point information, thereby greatly improving the test efficiency and accuracy.
  • the impedance information of the entire circuit board can be tested, and the problem of the differential impedance test for the circuit board in the prior art is solved, the test efficiency is low, and the internal impedance strip of the circuit board cannot be tested.
  • FIG. 1 is a flow chart of a method for determining differential line test information according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a network of differential line pairs of a method for determining differential line test information according to an embodiment of the present invention
  • FIG. 3 is a flow chart of a method for determining coordinate information of a differential line end-to-end test point according to a preferred embodiment of the present invention
  • FIG. 4 is a flowchart of a method for determining line length information of a layer in which a differential line has a maximum value according to a preferred embodiment of the present invention
  • FIG. 5 is a flow chart of a method for determining differential line test information in accordance with a preferred embodiment of the present invention
  • FIG. 6 is a flow chart of a method for determining differential line total length information in accordance with a preferred embodiment of the present invention
  • FIG. 7 is a schematic diagram showing the hardware structure of a computer device for determining a differential line test information according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for determining differential line test information according to an embodiment of the present invention, as shown in FIG. Including the following steps:
  • S101 obtaining a printed circuit board design file; after the PCB printed circuit board design is completed, the printed circuit board design file can be automatically extracted according to the design software cadence, and the printed circuit board design file includes various types, for example, a test point information file, The line width information file, the impedance design value file, and the like can be obtained by the present invention.
  • S102 Determine a network name of the differential line pair according to the printed circuit board design file; and determine, in the extracted printed circuit board design file, all network information of the PCB, and whether it is a differential network or the like, thereby determining the difference The network name of the line pair.
  • S103 Determine test indicator information of the differential line pair according to the network name of the differential line pair and the printed circuit board design file.
  • the printed circuit board design file includes various information, such as test point information, line width information, impedance design value information, etc., according to the network name of the differential line pair, the differential line to be tested can be extracted from various files.
  • the test indicator information of the pair such as the location of the test point, the distance between the test points, the length of the differential line, and so on.
  • the printed circuit board design file is obtained, and the network name of the differential line pair is determined according to the printed circuit board design file, and determined according to the network name and the printed circuit board design file.
  • the test indicator information of the differential line pair can automatically determine the indicators to be detected by all the differential line pairs on the circuit board.
  • the automation device can automatically detect the circuit board based on the information, and compare the detected information with the extracted test index information to determine whether the differential line pair on the circuit board is There is an abnormality.
  • This solution greatly improves the test efficiency and accuracy of the board, and thus can test the impedance information of the entire board and solve the problem.
  • the test efficiency is low and the internal impedance strip of the circuit board cannot be tested.
  • the printed circuit board design file includes a network information file, where the network information file records the network name and whether each network is an identifier of the differential network, such as recording all network information of the PCB, including the network name, whether it is a differential network. , the electrical length, the number of PINs, and the like, the above step S102 relates to determining the network name of the differential line pair according to the printed circuit board design file.
  • the identity of the network extracts the network name of the differential line pair from the network information file, for example:
  • a set of differential test pair network information $40I575 ⁇ DDRH_DQS3_N and $40I575 ⁇ DDRH_DQS3_P are extracted, and the extracted differential line pair network diagram is shown in FIG. 2, and all the extraction methods are extracted according to the extraction method. Differential line pair.
  • the printed circuit board design file includes a test point information file, typically in the IPC-356 file format, which records the network name, coordinates, and location of each point.
  • the layer and other information that is, the test point information file records the network name and the corresponding endpoint coordinate information
  • the test indicator information of the differential line includes the coordinate information of the same end test point of the differential line pair.
  • the step S103 is to determine the test index information of the differential line pair according to the network name of the differential line pair and the printed circuit board design file. As shown in FIG. 3, the step S103 may specifically include the following steps:
  • S1032A determines coordinate information of the same end test point according to the coordinate information of the end point.
  • the automatic detection device can search for the same end test point on the circuit board according to the coordinate information of the same end test point, and judge whether the position indicated by the coordinate information exists at the same end test point according to the impedance signal, thereby determining the actual end end test on the circuit board. Whether the position of the test point at the same end is consistent with the design point. When the point is inconsistent, the detected end point test point abnormality can be recorded.
  • the S1032A may specifically include the following steps:
  • S1032A2 select a set of endpoint coordinate information with the same horizontal coordinate value as the coordinate information of the same end test point.
  • a differential test pair has a total of four endpoint coordinate information values, and finds two endpoint coordinates with the same abscissa value, which is the coordinate information of the same end test point.
  • the network names of the differential line pairs are $40I575 ⁇ DDRH_DQ S3_N and $40I575 ⁇ DDRH_DQS3_P, and the corresponding coordinate information is as follows:
  • the coordinates of one end point corresponding to the network name $40I575 ⁇ DDRH_DQS3_N are (13517, -1376)
  • the coordinates of one end point corresponding to the network name $40I575 ⁇ DDRH_DQS3_P are (13517, -1927)
  • the endpoint coordinates (13517, - 1376) and (13517, -1927) have the same abscissa value, indicating that the two endpoints are the same end coordinate point, so the two coordinates are the coordinate information of the same end test point, and the automation device according to the design of the same end test point position To determine whether the actual coordinates of the same end test point are abnormal.
  • the printed circuit board design file includes a test point information file, where the test point information file records a network name and corresponding endpoint coordinate information, and the test indicator information includes coordinate information of the same end test point of the differential line pair. It also includes angle information between the test points on the same end.
  • the angle information between the same end test points is obtained by using the arctangent formula. Specifically, after acquiring the coordinate information of the same end test point of the differential line pair, for example, the coordinate values of the two end test points are: point 1 coordinate value is (x 1 , y 1 ), and point 2 coordinate value is (x) 2 , y 2 ), then the angle between the two points can be based on the arctangent formula: Find the angle information between the two points. For example, for the above-mentioned peer test point coordinates (13517, -1376) and (13517, -1927), the angle formed by the two endpoints is 270° by the arctangent formula:
  • the automation device After the automation device reads the angle information between the test points at the same end, it determines whether the angles of the actual test points at the same end are consistent according to the angle information of the test points at the same end of the design. Record the detected end point test point abnormalities and improve the detection efficiency.
  • the printed circuit board design file includes a test point information file, where the test point information file records a network name and corresponding endpoint coordinate information, and the test indicator information includes coordinate information of the same end test point of the differential line pair. It also includes distance information between the test points on the same end.
  • the distance information between the same end test point is calculated by using a distance formula between two points and coordinate information of the same end test point.
  • the coordinate values of two peer test points are: point 1 coordinate value is (x 1 , y 1 ), point 2 coordinate value is (x 2 , y 2 ), then the distance between two points can be based on two points.
  • Distance formula calculation For example, for the same-end test point coordinates (13517, -1376) and (13517, -1927), the distance between the two endpoints is calculated by the distance formula between two points:
  • the automatic device After the automatic device reads the distance information between the same end test points, it determines whether the distance between the actual end test points is consistent according to the distance information of the same end test point at the design time. If the distance is inconsistent, the detected end test point is abnormal. Improve detection efficiency.
  • the printed circuit board design file includes a line width information file, where the line width information file records the network name and the corresponding line length information of the layer, and the test indicator information includes the difference line length information of the layer. .
  • step S103 may include the following steps:
  • S1033B extracting the line length information of the layer where the maximum value is located.
  • a PCB circuit board there may be multiple circuit board layers, and the length of the differential lines on each layer of the circuit board will be different. According to the network name of the extracted differential line pair, the printed circuit board of each layer corresponds. The length of the differential line on the upper part extracts the length of the differential line of the layer with the largest value.
  • the automation device compares the extracted differential line length information with the differential line length information at the design time to determine whether the differential line length arrangement in the circuit board is reasonable.
  • the printed circuit board design file includes a line width information file and an impedance design value file
  • the line width information file records the network name and the corresponding layer information and the line length information of the layer, and the impedance design value.
  • the file records at least one of layer information and corresponding line width information, corresponding impedance information, and corresponding tolerance information
  • the test index information includes at least one of line width information, impedance information, and tolerance information.
  • step S103 may include the following steps:
  • S1031C Query the network name of the differential line pair in the online wide information file;
  • the printed circuit board design file includes a line width information file and an impedance design value file, and the line width information file records the network name and the corresponding layer information and the layer at the layer Line length information;
  • the obtained line width information table of the differential line is as shown in Table 1.
  • the data required for the second line and the fourth action is obtained from Table 1, that is, the layer where the difference line is located is the ART22 layer.
  • the impedance design value file records at least one of layer information and corresponding line width information, corresponding impedance information, and corresponding tolerance information; for example, an impedance design value information table As shown in table 2.
  • step S1033C the layer where the difference line is located is the ART22 layer, so the data in the second row of Table 2 is the required data.
  • S1035C Extract at least one of line width information, corresponding impedance information, and corresponding tolerance information corresponding to the layer information of the query. Specifically, the information of the differential line pair in Table 1 and Table 2 is combined, and the obtained differential line test information data is as shown in Table 3.
  • the printed circuit board design file includes a line width information file
  • the line width information file records the network name and the corresponding line total length information
  • the test indicator information includes the total line length information
  • step S103 may include the following steps:
  • the S1032D extracts the total length information of the line corresponding to the queried network name.
  • the total length of the differential line includes the total length of the differential line through each layer of the board.
  • the total length information of the differential line is 219.54 mils.
  • the automation device After the automation device reads the line length information of the layer having the maximum value, the line width information, the impedance information, the tolerance information, and the spacing information between the test points, the actual impedance value is calculated, if the impedance value is within the designed impedance value range The differential circuit design is qualified. If the impedance value exceeds the design impedance design value range, the differential line impedance design is recorded as unsatisfactory.
  • the differential line test information determining method in the embodiment of the present invention can automatically extract all differential line pair data in the PCB design file, and the automatic device reads the data, and automatically tests according to the point information, thereby greatly improving the test efficiency. And accuracy, the impedance test can be performed on the entire printed circuit board.
  • the embodiment of the present invention further provides a computer readable storage medium, where the computer storage medium stores computer executable instructions, which can execute the differential line test information determining method in any of the foregoing method embodiments.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random storage memory (Random). Access Memory (RAM), Flash Memory, Hard Disk Drive (HDD), or Solid-State Drive (SSD), etc.; the storage medium may further include a combination of the above types of memories. .
  • FIG. 7 is a schematic diagram showing the hardware structure of a computer device for determining a differential line test information according to an embodiment of the present invention.
  • the device includes one or more processors 710 and a memory 720, and one processor in FIG. Take 710 as an example.
  • the apparatus that performs the differential line test information determining method may further include: an input device 730 and an output device 740.
  • the processor 710, the memory 720, the input device 730, and the output device 740 may be connected by a bus or other means, as exemplified by a bus connection in FIG.
  • the processor 710 can be a Central Processing Unit (CPU).
  • the processor 710 can also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or Other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., or a combination of the above various types of chips.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 720 is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as the difference in the embodiment of the present application.
  • the line test information determines the program instruction/module corresponding to the method.
  • the processor 710 executes various functional applications and data processing of the server by running non-transitory software programs, instructions, and modules stored in the memory 720, that is, implementing the differential line test information determining method in the foregoing method embodiments.
  • the memory 720 may include a storage program area and an storage data area, wherein the storage program area may store an operating system, an application required for at least one function; the storage data area may store data created by use of the differential line test information determining device, and the like.
  • memory 720 can include high speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device.
  • memory 720 can optionally include memory remotely located relative to processor 710 that can be connected to the processing device determined by the differential line test information over a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the input device 730 can receive the input digital or character information and generate a key signal input related to user settings and function control of the differential line test information determination processing device.
  • the output device 740 can include a display device such as a display screen.
  • the one or more modules are stored in the memory 720, and when executed by the one or more processors 710, the methods illustrated in Figures 1 through 6 are performed.
  • embodiments of the present invention can be provided as a method, system, Or a computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide functions for implementing a process in a flow or a flow and/or a block diagram in a block or blocks. A step of.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

本发明提供了一种差分线路测试信息确定方法及设备，该方法包括获取印制电路板设计文件，印制电路板设计文件中含有印制电路板的所有网络信息，测试点信息等信息，根据该印制电路板设计文件确定差分线路对的网络名称，根据差分线路对的网络名称和印制电路板设计文件确定差分线路对的测试指标信息。通过本发明提供的差分线路测试信息确定方法，在提取出差分线路对的测试指标信息之后，自动化设备读取这些信息，根据点的信息进行自动化测试，极大地提高了测试效率和准确度，可以测试整个电路板的阻抗信息，解决了现有技术中针对线路板差分阻抗测试，测试效率低且不能测试线路板内部阻抗条的问题。

Description

一种差分线路测试信息确定方法及设备 技术领域
本发明涉及线路板测试技术领域，具体涉及一种差分线路测试信息确定方法及设备。
背景技术
为了提高传输速率和传输距离，计算机行业和通信行业越来越多的采用高速串行总线，在芯片之间、板卡之间、背板和业务板之间实现高速互联。这些高速串行总线的速率从以往USB2.0、LVDS以及FireWire1394的几百Mbps，到今天的PCI-Express G1/G2、SATA G1/G2、XAUI/2XAUI、XFI的几个Gbps乃至30Gbps。计算机以及通信行业的PCB客户对差分走线的阻抗控制要求越来越高，这使PCB生产商以及高速PCB设计人员所面临的前所未有的挑战，这些PCB设计出来怎么去对这些差分线路进行测试也是一个问题。
目前，PCB厂的普遍做法是在线路板边上增加几个阻抗条，然后人工测一下这几个阻抗条，这并不能反映线路板内阻抗线路的实际情况。如果测试线路板内的阻抗条，则测试点数太多，人工无法进行测试。
发明内容
有鉴于此，本发明实施例提供了一种差分线路测试信息确定方法及设备，以解决现有技术中针对线路板差分阻抗测试，测试效率低且不能测试 线路板内部阻抗条的问题。
为此，本发明实施例提供了如下技术方案：
本发明实施例提供了一种差分线路测试信息确定方法，包括：获取印制电路板设计文件；根据所述印制电路板设计文件确定差分线路对的网络名称；根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息。
可选地，所述印制电路板设计文件包括网络信息文件，所述网络信息文件记录有网络名称以及各个网络是否为差分网络的标识；所述根据所述印制电路板设计文件确定差分线路对的网络名称，包括：根据所述网络信息文件中的网络名称以及各个网络是否为差分网络的标识从所述网络信息文件中提取所述差分线路对的网络名称。
可选地，所述印制电路板设计文件包括测试点信息文件，所述测试点信息文件记录有网络名称以及对应的端点坐标信息；所述测试指标信息包括所述差分线路对的同端测试点坐标信息。
可选地，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息，包括：在所述测试点信息文件中查询所述差分线路对的网络名称以及对应的端点坐标信息；根据所述端点坐标信息确定同端测试点坐标信息。
可选地，所述根据所述端点坐标信息确定同端测试点坐标信息，包括：确定横坐标值相同的端点坐标信息；选择一组横坐标值相同的端点坐标信 息作为同端测试点坐标信息。
可选地，所述测试指标信息还包括所述同端测试点间的角度信息。
可选地，在确定所述同端测试点坐标信息之后，还包括：利用反正切公式得到所述同端测试点间的角度信息。
可选地，所述测试指标信息还包括所述同端测试点间的距离信息。
可选地，在确定所述同端测试点坐标信息之后，还包括：利用两点间距离公式和所述同端测试点坐标信息，计算所述同端测试点间的距离信息。
可选地，所述印制电路板设计文件包括线宽信息文件，所述线宽信息文件记录有网络名称以及对应的所在层的线长度信息；所述测试指标信息包括所在层的线长度信息。
可选地，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息，包括：在所述线宽信息文件中查询所述差分线路对的网络名称；比较查询到的所述差分线路对的网络名称对应的所在层的线长度信息；提取具有最大值的所在层的线长度信息。
可选地，所述印制电路板设计文件包括线宽信息文件和阻抗设计值文件，所述线宽信息文件记录有网络名称以及对应的所在层信息和所在层的线长度信息；所述阻抗设计值文件记录有层信息以及对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个；所述测试指标信息包括线宽信息、阻抗信息、公差信息中的至少一个。
可选地，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息的步骤包括：在所述线宽信息文件中查询所述差分线路对的网络名称；比较查询到的所述差分线路对的网络名称对应的所在层的线长度信息；提取具有最大值的所在层的线长度信息对应的所在层信息；在所述阻抗设计值文件中查询提取的所在层信息；提取查询到的所在层信息对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个。
可选地，所述印制电路板设计文件包括线宽信息文件，所述线宽信息文件记录有网络名称以及对应的线路总长度信息；所述测试指标信息包括线路总长度信息。
可选地，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息的步骤包括：在所述线宽信息文件中查询所述差分线路对的网络名称；提取与查询到的网络名称对应的线路总长度信息。
本发明实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1-15中任一项所述的差分线路测试信息确定方法。
本发明实施例还提供了一种计算机设备，包括：至少一个处理器；以及与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的计算机程序，所述计算机程序被所述至少一个处理器执行，以使所述至少一个处理器执行权利要求1-15中任一项所述的差分线路测试信息确定方法。
本发明实施例技术方案，具有如下优点：
本发明实施例提供了一种差分线路测试信息确定方法及设备，该方法包括先获取印制电路板设计文件，印制电路板设计文件中含有印制电路板的所有网络信息，测试点信息等信息，根据该印制电路板设计文件确定差分线路对的网络名称，根据差分线路对的网络名称和印制电路板设计文件确定差分线路对的测试指标信息。通过本发明实施例提供的差分线路测试信息确定方法，在提取出差分线路对的测试指标信息之后，自动化设备读取这些信息，根据点的信息进行自动化测试，极大地提高了测试效率和准确度，可以测试整个电路板的阻抗信息，解决了现有技术中针对线路板差分阻抗测试，测试效率低且不能测试线路板内部阻抗条的问题。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明实施例的差分线路测试信息确定方法的流程图；
图2是根据本发明实施例的差分线路测试信息确定方法的差分线路对的网络示意图；
图3是根据本发明优选实施例的差分线路同端测试点坐标信息确定方法的流程图；
图4是根据本发明优选实施例的差分线路具有最大值的所在层的线长度信息确定方法的流程图；
图5是根据本发明优选实施例的差分线路测试信息确定方法的一个流程图；
图6是根据本发明优选实施例的差分线路总长度信息确定方法的流程图；
图7是根据本发明实施例的差分线路测试信息确定方法的计算机设备的硬件结构示意图。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
在本实施例中提供了一种差分线路测试信息确定方法，图1是根据本发明实施例的差分线路测试信息确定方法的流程图，如图1所示，该流程 包括如下步骤：
S101：获取印制电路板设计文件；在PCB印制电路板设计完成后，根据设计软件cadence可以自动提取印制电路板设计文件，印制电路板设计文件包括多种，例如测试点信息文件、线宽信息文件、阻抗设计值文件等，本发明可以获取其中的一种或多种。
S102：根据印制电路板设计文件确定差分线路对的网络名称；在提取出的印制电路板设计文件中，包含有PCB的所有网络信息、以及是否为差分网络等信息，以此可以确定差分线路对的网络名称。
S103：根据差分线路对的网络名称和印制电路板设计文件确定差分线路对的测试指标信息。具体地，印制电路板设计文件中包括多种信息，例如测试点信息、线宽信息、阻抗设计值信息等，根据差分线路对的网络名称，可以从各种文件中提取需要测试的差分线路对的测试指标信息，如测试点位置、测试点间的距离、差分线路的长度等。
根据本发明实施例提供的差分线路测试信息确定方法，通过获取印制电路板设计文件，根据印制电路板设计文件确定差分线路对的网络名称，根据该网络名称和印制电路板设计文件确定差分线路对的测试指标信息，根据上述方法可以自动确定电路板上所有的差分线路对所需检测的指标。在提取出差分线路对的测试指标信息之后，自动化设备可以基于这些信息，对电路板进行自动化检测，将检测得到的信息与提取出的测试指标信息进行比较以确定电路板上的差分线路对是否存在异常，本方案极大地提高了电路板测试效率和准确度，并由此可以测试整个电路板的阻抗信息，解决 了现有技术中针对线路板差分阻抗测试，测试效率低且不能测试线路板内部阻抗条的问题。
具体地，印制电路板设计文件包括网络信息文件，该网络信息文件记录有网络名称以及各个网络是否为差分网络的标识，如记录了PCB的所有网络信息，包括了网络名称，是否为差分网络，电气长度，PIN数量等信息，上述步骤S102涉及到根据印制电路板设计文件确定差分线路对的网络名称，在一个具体实施方式中，根据网络信息文件中的网络名称以及各个网络是否为差分网络的标识从网络信息文件中提取差分线路对的网络名称，例如：
Item3(NET)
Net Name：$40I575\DDRH_DQS3_N
Member of Diff Pair：$40I575\DDRH_DQS3_
Item 7(NET)
Net Name：$40I575\DDRH_DQS3_P
Member of Diff Pair：$40I575\DDRH_DQS3_
根据此“Member of Diff Pair”信息提取出一组差分测试对网络信息$40I575\DDRH_DQS3_N和$40I575\DDRH_DQS3_P，提取出的差分线路对网络示意图如图2所示，依据此提取方法，提取出所有差分线路对。
在一个可选实施方式中，印制电路板设计文件包括测试点信息文件，通常为IPC-356文件格式，该文件记录了每个点的网络名称、坐标、所在 层等信息，即该测试点信息文件记录有网络名称以及对应的端点坐标信息，差分线路的测试指标信息包括差分线路对的同端测试点坐标信息。上述步骤S103涉及到根据差分线路对的网络名称和印制电路板设计文件确定差分线路对的测试指标信息，如图3所示，步骤S103具体可以包括如下步骤：
S1031A，在测试点信息文件中查询差分线路对的网络名称以及对应的端点坐标信息；
S1032A，根据端点坐标信息确定同端测试点坐标信息。
自动化检测设备可以按照同端测试点坐标信息去寻找电路板上的同端测试点，并根据阻抗信号判断坐标信息指示的位置是否存在同端测试点，由此确定电路板上的实际同端测试点与设计时同端测试点位置是否一致，当不一致时可以记录所检测的同端测试点异常。
S1032A具体可以包括如下步骤：
S1032A1，确定横坐标值相同的端点坐标信息；
S1032A2，选择一组横坐标值相同的端点坐标信息作为同端测试点坐标信息。例如一个差分测试对一共有四个端点坐标信息值，找到横坐标值相同的两个端点坐标，即为同端测试点坐标信息。
例如在一个具体实施方式中，差分线路对的网络名称$40I575\DDRH_DQ S3_N和$40I575\DDRH_DQS3_P，对应的坐标信息如下：
$40I575\DDRH_DQS3_N A01X+013517Y-001376X0180Y0180R270 S0
$40I575\DDRH_DQS3_P A01X+013517Y-001927X0200Y0200R270 S1
由此可得，网络名称$40I575\DDRH_DQS3_N对应的一个端点坐标为(13517，-1376)，网络名称$40I575\DDRH_DQS3_P对应的一个端点坐标为(13517，-1927)，因为端点坐标(13517，-1376)和(13517，-1927)横坐标值相同，则说明这两个端点是同端坐标点，因此这两个坐标为同端测试点坐标信息，自动化设备根据设计时的同端测试点位置来判断实际的同端测试点坐标是否异常。
在一个可选实施方式中，印制电路板设计文件包括测试点信息文件，该测试点信息文件记录有网络名称以及对应的端点坐标信息，测试指标信息包括差分线路对的同端测试点坐标信息，还包括同端测试点间的角度信息。
利用反正切公式得到所述同端测试点间的角度信息。具体地，在获取到差分线路对的同端测试点坐标信息之后，例如两个同端测试点的坐标值为：点1坐标值为(x1，y1)，点2坐标值为(x2，y2)，则两点之间的角度可根据反正切公式：
Figure PCTCN2017114422-appb-000001
求出两点之间的角度信息。例如对于上述同端测试点坐标(13517，-1376)和(13517，-1927)，通过反正切公式得到这两个端点形成的角度为270°：
Figure PCTCN2017114422-appb-000002
自动化设备读取同端测试点间的角度信息之后，根据设计时的同端测试点的角度信息来确定实际的同端测试点的角度是否一致，如果不一致则 记录所检测的同端测试点异常，提高检测效率。
在一个可选实施方式中，印制电路板设计文件包括测试点信息文件，该测试点信息文件记录有网络名称以及对应的端点坐标信息，测试指标信息包括差分线路对的同端测试点坐标信息，还包括同端测试点间的距离信息。
在确定所述同端测试点坐标信息之后，利用两点间距离公式和所述同端测试点坐标信息，计算所述同端测试点间的距离信息。例如两个同端测试点的坐标值为：点1坐标值为(x1，y1)，点2坐标值为(x2，y2)，则两点之间的距离可根据两点间距离公式计算：
Figure PCTCN2017114422-appb-000003
例如对于同端测试点坐标(13517，-1376)和(13517，-1927)，通过两点间距离公式计算这两个端点的距离为：
Figure PCTCN2017114422-appb-000004
自动化设备读取同端测试点间的距离信息之后，根据设计时的同端测试点的距离信息来确定实际的同端测试点的距离是否一致，如果不一致则记录所检测的同端测试点异常，提高检测效率。
在一个可选实施方式中，印制电路板设计文件包括线宽信息文件，该线宽信息文件记录有网络名称以及对应的所在层的线长度信息，测试指标信息包括所在层的差分线长度信息。
如图4所示，上述步骤S103可以包括以下步骤：
S1031B，在线宽信息文件中查询差分线路对的网络名称；
S1032B，比较查询到的差分线路对的网络名称对应的所在层的线长度信息；
S1033B，提取具有最大值的所在层的线长度信息。在PCB电路板中，可能存在多个线路板层，而差分线在每一层电路板上布线的长度会有不同，根据提取出的差分线路对的网络名称对应的所在每层印制电路板上的差分线长度，提取出具有最大值的所在层的差分线长度。
自动化设备根据提取出的差分线长度信息，与设计时的差分线长度信息对比，判断线路板中的差分线长度布置是否合理。
在一个可选实施方式中，印制电路板设计文件包括线宽信息文件和阻抗设计值文件，线宽信息文件记录有网络名称以及对应的所在层信息和所在层的线长度信息，阻抗设计值文件记录有层信息以及对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个，测试指标信息包括线宽信息、阻抗信息、公差信息中的至少一个。
如图5所示，上述步骤S103可以包括以下步骤：
S1031C，在线宽信息文件中查询差分线路对的网络名称；印制电路板设计文件包括线宽信息文件和阻抗设计值文件，线宽信息文件记录有网络名称以及对应的所在层信息和所在层的线长度信息；
S1032C，比较查询到的差分线路对的网络名称对应的所在层的线长度信息；
S1033C，提取具有最大值的所在层的线长度信息对应的所在层信息；
例如，根据差分线路对的网络名称差分线路对的网络名称$40I575\DDRH_DQ S3_N和$40I575\DDRH_DQS3_P，获取的差分线的线宽信息表如表1所示。
表1
网络名 层名 总长度(mils) 线宽(mils) 所在层长度(mils)
$40I575\DDRH_DQS3_N TOP 219.54 5 22.3
$40I575\DDRH_DQS3_N ART22 219.54 4.5 197.24
$40I575\DDRH_DQS3_P TOP 219.54 5 22.3
$40I575\DDRH_DQS3_P ART22 219.54 4.5 197.24
根据差分线路对的网络名称和差分线在电路板中的线长比较长的特点，从表1中得到第2行也第4行为所需数据，即差分线所在层为ART22层。
S1034C，在阻抗设计值文件中查询提取的所在层信息；阻抗设计值文件记录有层信息以及对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个；例如阻抗设计值信息表如表2所示。
表2
层 单端/差分 线宽 阻抗 公差
TOP 差分 5 50 10％
ART22 差分 4.5 50 10％
步骤S1033C中得到差分线所在层为ART22层，因此表2中第2行数据为所需数据。
S1035C，提取查询到的所在层信息对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个。具体地，综合表1和表2中差分线路对的信息，获取的差分线路测试信息数据如表3所示。
表3
Figure PCTCN2017114422-appb-000005
在一个可选实施方式中，印制电路板设计文件包括线宽信息文件，线宽信息文件记录有网络名称以及对应的线路总长度信息；测试指标信息包括线路总长度信息。
如图6所示，上述步骤S103可以包括以下步骤：
S1031D，在线宽信息文件中查询差分线路对的网络名称；线宽信息文件记录有网络名称以及对应的线路总长度信息；
S1032D，提取与查询到的网络名称对应的线路总长度信息。在印制电路板中，差分线路的总长度包括了差分线穿过每层电路板的总长度。例如在差分线的线宽信息表表1中，差分线路的总长度信息为219.54mils。
通过上述具体实施方式中的差分线路测试信息确定方法，最终获取的自动化测试需要的一组测试对数据如表5所示：
表5
Figure PCTCN2017114422-appb-000006
自动化设备读取具有最大值的所在层的线长度信息、线宽信息、阻抗信息、公差信息、以及测试点间的间距信息之后，计算实际的阻抗值，如果该阻抗值在设计阻抗值范围内，则该差分线路设计合格，如果该阻抗值超出设计阻抗设计值范围，则记录该差分线路阻抗设计不合格。
通过本发明实施例的差分线路测试信息确定方法，能够自动提取出PCB设计文件中的所有差分线路对数据，自动化设备读入这些数据，根据点的信息进行自动化测试，极大的提高了测试效率和准确度，能够对整个印制电路板进行阻抗测试。
实施例2
本发明实施例还提供了一种计算机可读存储介质，所述计算机存储介质存储有计算机可执行指令，该计算机可执行指令可执行上述任意方法实施例中的差分线路测试信息确定方法。其中，所述存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)、随机存储记忆体(Random  Access Memory，RAM)、快闪存储器(Flash Memory)、硬盘(Hard Disk Drive，缩写：HDD)或固态硬盘(Solid-State Drive，SSD)等；所述存储介质还可以包括上述种类的存储器的组合。
实施例3
图7是根据本发明实施例的差分线路测试信息确定方法的计算机设备的硬件结构示意图，如图7所示，该设备包括一个或多个处理器710以及存储器720，图7中以一个处理器710为例。
执行差分线路测试信息确定方法的设备还可以包括：输入装置730和输出装置740。
处理器710、存储器720、输入装置730和输出装置740可以通过总线或者其他方式连接，图7中以通过总线连接为例。
处理器710可以为中央处理器(Central Processing Unit，CPU)。处理器710还可以为其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等芯片，或者上述各类芯片的组合。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
存储器720作为一种非暂态计算机可读存储介质，可用于存储非暂态软件程序、非暂态计算机可执行程序以及模块，如本申请实施例中的差分 线路测试信息确定方法对应的程序指令/模块。处理器710通过运行存储在存储器720中的非暂态软件程序、指令以及模块，从而执行服务器的各种功能应用以及数据处理，即实现上述方法实施例中的差分线路测试信息确定方法。
存储器720可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储差分线路测试信息确定装置的使用所创建的数据等。此外，存储器720可以包括高速随机存取存储器，还可以包括非暂态存储器，例如至少一个磁盘存储器件、闪存器件、或其他非暂态固态存储器件。在一些实施例中，存储器720可选包括相对于处理器710远程设置的存储器，这些远程存储器可以通过网络连接至差分线路测试信息确定的处理装置。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置730可接收输入的数字或字符信息，以及产生与差分线路测试信息确定处理装置的用户设置以及功能控制有关的键信号输入。输出装置740可包括显示屏等显示设备。
所述一个或者多个模块存储在所述存储器720中，当被所述一个或者多个处理器710执行时，执行如图1至图6所示的方法。
上述产品可执行本发明实施例所提供的方法，具备执行方法相应的功能模块和有益效果以及未在本实施例中详尽描述的技术细节，具体可参见如图1至图6所示的实施例中的相关描述。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、 或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能 的步骤。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (17)

  1. 一种差分线路测试信息确定方法，其特征在于，包括：
    获取印制电路板设计文件；
    根据所述印制电路板设计文件确定差分线路对的网络名称；
    根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息。
  2. 根据权利要求1所述的差分线路测试信息确定方法，其特征在于，所述印制电路板设计文件包括网络信息文件，所述网络信息文件记录有网络名称以及各个网络是否为差分网络的标识；所述根据所述印制电路板设计文件确定差分线路对的网络名称，包括：
    根据所述网络信息文件中的网络名称以及各个网络是否为差分网络的标识从所述网络信息文件中提取所述差分线路对的网络名称。
  3. 根据权利要求1所述的差分线路测试信息确定方法，其特征在于，所述印制电路板设计文件包括测试点信息文件，所述测试点信息文件记录有网络名称以及对应的端点坐标信息；所述测试指标信息包括所述差分线路对的同端测试点坐标信息。
  4. 根据权利要求3所述的差分线路测试信息确定方法，其特征在于，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息，包括：
    在所述测试点信息文件中查询所述差分线路对的网络名称以及对应的端点坐标信息；
    根据所述端点坐标信息确定同端测试点坐标信息。
  5. 根据权利要求4所述的差分线路测试信息确定方法，其特征在于，所述根据所述端点坐标信息确定同端测试点坐标信息，包括：
    确定横坐标值相同的端点坐标信息；
    选择一组横坐标值相同的端点坐标信息作为同端测试点坐标信息。
  6. 根据权利要求3所述的差分线路测试信息确定方法，其特征在于，所述测试指标信息还包括所述同端测试点间的角度信息。
  7. 根据权利要求6所述的差分线路测试信息确定方法，其特征在于，在确定所述同端测试点坐标信息之后，还包括：
    利用反正切公式得到所述同端测试点间的角度信息。
  8. 根据权利要求3所述的差分线路测试信息确定方法，其特征在于，所述测试指标信息还包括所述同端测试点间的距离信息。
  9. 根据权利要求8所述的差分线路测试信息确定方法，其特征在于，在确定所述同端测试点坐标信息之后，还包括：
    利用两点间距离公式和所述同端测试点坐标信息，计算所述同端测试点间的距离信息。
  10. 根据权利要求1所述的差分线路测试信息确定方法，其特征在于，所述印制电路板设计文件包括线宽信息文件，所述线宽信息文件记录有网络名称以及对应的所在层的线长度信息；所述测试指标信息包括所在层的线长度信息。
  11. 根据权利要求10所述的差分线路测试信息确定方法，其特征在于，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息，包括：
    在所述线宽信息文件中查询所述差分线路对的网络名称；
    比较查询到的所述差分线路对的网络名称对应的所在层的线长度信息；
    提取具有最大值的所在层的线长度信息。
  12. 根据权利要求1所述的差分线路测试信息确定方法，其特征在于，所述印制电路板设计文件包括线宽信息文件和阻抗设计值文件，所述线宽信息文件记录有网络名称以及对应的所在层信息和所在层的线长度信息；所述阻抗设计值文件记录有层信息以及对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个；所述测试指标信息包括线宽信息、阻抗信息、公差信息中的至少一个。
  13. 所述权利要求12所述的差分线路测试信息确定方法，其特征在于，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息的步骤包括：
    在所述线宽信息文件中查询所述差分线路对的网络名称；
    比较查询到的所述差分线路对的网络名称对应的所在层的线长度信息；
    提取具有最大值的所在层的线长度信息对应的所在层信息；
    在所述阻抗设计值文件中查询提取的所在层信息；
    提取查询到的所在层信息对应的线宽信息、对应的阻抗信息、对应的公差信息中的至少一个。
  14. 根据权利要求1所述的差分线路测试信息确定方法，其特征在于，所述印制电路板设计文件包括线宽信息文件，所述线宽信息文件记录有网络名称以及对应的线路总长度信息；所述测试指标信息包括线路总长度信息。
  15. 根据权利要求14所述的差分线路测试信息确定方法，其特征在于，所述根据所述网络名称和所述印制电路板设计文件确定所述差分线路对的测试指标信息的步骤包括：
    在所述线宽信息文件中查询所述差分线路对的网络名称；
    提取与查询到的网络名称对应的线路总长度信息。
  16. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1-15中任一项所述的差分线路测试信息确定方法。
  17. 一种计算机设备，其特征在于，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的计算机程序，所述计算机程序被所述至少一个处理器执行，以使所述至少一个处理器执行权利要求1-15中任一项所述的差分线路测试信息确定方法。
PCT/CN2017/114422 2017-09-07 2017-12-04 一种差分线路测试信息确定方法及设备 WO2019047392A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710801731.X 2017-09-07
CN201710801731.XA CN107656187B (zh) 2017-09-07 2017-09-07 一种差分线路测试信息确定方法及设备

Publications (1)

Publication Number Publication Date
WO2019047392A1 true WO2019047392A1 (zh) 2019-03-14

Family

ID=61129209

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/114422 WO2019047392A1 (zh) 2017-09-07 2017-12-04 一种差分线路测试信息确定方法及设备

Country Status (2)

Country Link
CN (1) CN107656187B (zh)
WO (1) WO2019047392A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112444676A (zh) * 2019-08-27 2021-03-05 南京泊纳莱电子科技有限公司 一种电阻检测方法、装置、电阻检测机及可读存储介质
CN112946365B (zh) * 2021-03-01 2024-05-28 广州广合科技股份有限公司 自动制作阻抗测试文件的方法、电子设备及存储介质

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090105983A1 (en) * 2007-10-23 2009-04-23 Texas Instruments Incorporated Test definer, a method of automatically determining and representing functional tests for a pcb having analog components and a test system
CN103164559A (zh) * 2011-12-15 2013-06-19 鸿富锦精密工业（深圳）有限公司 信号线检查系统及方法
CN103164553A (zh) * 2011-12-14 2013-06-19 鸿富锦精密工业（深圳）有限公司 信号线检查系统及方法
CN103366023A (zh) * 2012-03-26 2013-10-23 鸿富锦精密工业（深圳）有限公司 差分信号走线布线系统及方法
CN103577615A (zh) * 2012-07-18 2014-02-12 鸿富锦精密工业（深圳）有限公司 高速差分信号线过孔自动检查系统及方法
CN105675990A (zh) * 2016-01-01 2016-06-15 广州兴森快捷电路科技有限公司 多层互连线路板的链路阻抗测试方法
CN105744731A (zh) * 2016-04-27 2016-07-06 浪潮电子信息产业股份有限公司 一种确定差分过孔位置的方法及一种pcb

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361122C (zh) * 2004-11-29 2008-01-09 华为技术有限公司 Ict测试用转换pcb的自动设计方法
CN101807217A (zh) * 2009-02-16 2010-08-18 英业达股份有限公司 建立差分走线测试条的方法
CN101989221B (zh) * 2009-08-07 2014-04-30 鸿富锦精密工业（深圳）有限公司 印刷电路板测试参数设定文档生成系统及方法
CN102651037A (zh) * 2011-02-25 2012-08-29 鸿富锦精密工业（深圳）有限公司 电子线路筛选系统及方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090105983A1 (en) * 2007-10-23 2009-04-23 Texas Instruments Incorporated Test definer, a method of automatically determining and representing functional tests for a pcb having analog components and a test system
CN103164553A (zh) * 2011-12-14 2013-06-19 鸿富锦精密工业（深圳）有限公司 信号线检查系统及方法
CN103164559A (zh) * 2011-12-15 2013-06-19 鸿富锦精密工业（深圳）有限公司 信号线检查系统及方法
CN103366023A (zh) * 2012-03-26 2013-10-23 鸿富锦精密工业（深圳）有限公司 差分信号走线布线系统及方法
CN103577615A (zh) * 2012-07-18 2014-02-12 鸿富锦精密工业（深圳）有限公司 高速差分信号线过孔自动检查系统及方法
CN105675990A (zh) * 2016-01-01 2016-06-15 广州兴森快捷电路科技有限公司 多层互连线路板的链路阻抗测试方法
CN105744731A (zh) * 2016-04-27 2016-07-06 浪潮电子信息产业股份有限公司 一种确定差分过孔位置的方法及一种pcb

Also Published As

Publication number Publication date
CN107656187A (zh) 2018-02-02
CN107656187B (zh) 2020-02-28

Similar Documents

Publication Publication Date Title
JP7141669B2 (ja) Ｐｃｂ設計レイアウトの回路開放短絡検査方法、検出システム及び電子デバイス
US8458645B2 (en) Electronic device and method for checking layout of printed circuit board
US8413097B2 (en) Computing device and method for checking design of printed circuit board layout file
US20150242380A1 (en) Checking testing coverage
WO2017181631A1 (zh) 工程文件的容量信息处理方法及装置
CN109492310B (zh) 一种线路检查的方法及检查装置
TW201405144A (zh) 高速差分訊號線過孔自動檢查系統及方法
WO2019047392A1 (zh) 一种差分线路测试信息确定方法及设备
CN103185560A (zh) Pcb板线路的线宽检测系统及方法
US20120331434A1 (en) Computing device and method for checking signal transmission lines
US8904330B2 (en) Phase determination for extraction from scattering parameters
WO2022078009A1 (zh) 一种计算机存储系统性能测试装置、方法及其存储介质
TWI468965B (zh) 佈線檢查系統及方法
CN108052441A (zh) 一种硬盘效能状态的测试方法、系统、装置及存储介质
CN106358220A (zh) 异常联系人信息的检测方法、装置及系统
CN104598598A (zh) 一种关系型数据标准性的评估方法
TW201436675A (zh) 訊號線檢查系統及方法
CN109522373B (zh) 数据处理方法、装置、电子设备及存储介质
US10755008B2 (en) Circuit comparing method and electronic device
US20130006561A1 (en) Computing device, storage medium, and method for analyzing signal group delay of printed circuit board
CN112946365B (zh) 自动制作阻抗测试文件的方法、电子设备及存储介质
TWI748184B (zh) 瑕疵檢測方法、電子裝置及電腦可讀存儲介質
TW201426366A (zh) 訊號線檢查系統及方法
TW201211808A (en) System and method for checking electrical rules
CN107145579B (zh) 地理信息线要素伪节点检查方法及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17924762

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17924762

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17924762

Country of ref document: EP

Kind code of ref document: A1