WO2019041903A1 - 一种基于非易失存储的计算装置及其使用方法 - Google Patents

一种基于非易失存储的计算装置及其使用方法 Download PDF

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WO2019041903A1
WO2019041903A1 PCT/CN2018/088166 CN2018088166W WO2019041903A1 WO 2019041903 A1 WO2019041903 A1 WO 2019041903A1 CN 2018088166 W CN2018088166 W CN 2018088166W WO 2019041903 A1 WO2019041903 A1 WO 2019041903A1
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memory
data
storage
area
chip
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PCT/CN2018/088166
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English (en)
French (fr)
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韩银和
许浩博
王颖
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中国科学院计算技术研究所
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering

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  • the present invention relates to improvements in the structure of computing devices.
  • a computer or computing device based on the von Neumann architecture capable of storing or storing programs, data, intermediate results, and final computational results over a long period of time, capable of delivering required programs and data to a computer or computing device, and capable of targeting
  • the data is processed by a logical operation or the like, and the program can control the direction of the program and the data, coordinate the corresponding operations, and output the processing to the user or input to a computer or a computing device for storage.
  • Figure 1 shows a schematic diagram of a conventional von Neumann architecture computing device.
  • a three-level approach is used to store programs and data.
  • On-chip memory (first level) is integrated on the chip of the processor, and has memory (second level) in addition to the processor and external storage (third level), which is commonly referred to as a hard disk.
  • on-chip memory is integrated on the processor, so it has the fastest memory access speed, its high cost and usually very limited storage capacity.
  • the memory is connected to the processor, and most applications usually have data.
  • the memory storage capacity is limited, and the on-chip storage is a volatile memory, such as static random access memory or dynamic random access memory, such volatile memory will lose data after the system is powered off.
  • external storage at the third level uses non-volatile memory such as tape, disk, and flash memory, which has the largest storage capacity and the slowest memory access speed, and the stored data is lost in the system. It will not be lost after the electricity.
  • processors on-chip memory and/or memory integrated on the processor, and
  • An energy storage device for storing electrical energy when powered on, and providing electrical energy when power is off to store unsaved data on the processor to the on-chip storage and/or the memory;
  • the on-chip storage and/or the memory adopts a non-volatile memory having a read/write speed of the order of nanoseconds for storing programs and data.
  • the energy storage device further comprises a capacitor circuit for powering the computing device when power is lost.
  • non-volatile memory used for the on-chip storage and/or the memory is selected from the group consisting of: phase change memory, magnetic random access memory, spin torque conversion random access memory, ferroelectric random access memory, and resistance Variable random access memory.
  • the memory is further for storing a configuration file that launches the device.
  • the on-chip storage comprises a storage area and a boot area
  • the boot area is set to be unreadable and writable during normal power supply and to store programs and data that have not been saved when power is lost
  • the storage area is set to adopt a write back manner.
  • the on-chip storage comprises a storage area and a boot area
  • the boot area is set to be in a write-through manner, and can be read and written during normal power supply, and used when power is lost.
  • the storage area is set to adopt a writeback manner.
  • a method of using the device comprising:
  • the control unit stores the request for acquiring data on the nonvolatile chip, the requested data is respectively looked up in the storage area and the boot area:
  • the requested data is found in the storage area from the off-chip storage, and the replaced data in the storage area is written into the boot area, and only the boot area is filled with data.
  • Data is written to the storage area, and write penetration is performed to exchange all data in the boot area with off-chip storage;
  • the data in the boot area is exchanged with the storage area.
  • a method of using the device comprising:
  • the method further includes:
  • the energy storage device is charged when the device is powered.
  • a method of using the device comprising:
  • the data is stored to the memory and/or the on-chip storage.
  • a computing device having a two-level or one-level storage structure that is capable of adapting to the needs of a computing device is provided.
  • the computing device does not take a long time to perform operations such as reading, writing, and transmitting data at medium and long distances.
  • the third-level memory is not provided, but the memory and the hard disk are combined as the second-level memory, it is not necessary to perform the operation of releasing the memory space after the program ends, simplifying the operation process and the control station. The complexity required.
  • a nonvolatile memory having a read/write speed of the order of nanoseconds is used, and data loss in the memory does not occur when the system is powered off.
  • the present invention further provides an energy storage device that stores electrical energy when powered on, and supplies power when the power is turned off to store data that has not been saved on the processor, since only the memory is set in the present invention.
  • Faster memory and/or on-chip storage so the present invention can store more data while consuming the same electrical energy than in a conventional computing device, and thus has the advantage of energy saving.
  • the memory capacity of the memory set by the present invention is much larger than the storage capacity of the conventional memory, so that more or larger applications can be run in the same period of time.
  • FIG. 1 is a schematic diagram of a conventional computing device having a three-level memory in the prior art
  • FIG. 2 is a schematic diagram of a non-volatile storage-based computing device of a two-level storage structure in accordance with one embodiment of the present invention
  • FIG. 3 is a block diagram of a non-volatile storage based computing device in accordance with yet another embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of using the computing device of FIG. 2 or FIG. 3 in accordance with an embodiment of the present invention.
  • Figure 5 (a) is a block diagram showing the structure of the non-volatile on-chip memory of Figure 3 in accordance with one embodiment of the present invention.
  • Figure 5(b) is a diagram showing the boot area of Figure 5(a) being set up to enable read and write of stored data in the case of normal power supply, in accordance with one embodiment of the present invention.
  • Figure 6 is a diagram showing the use of Figures 5(a) and (b) in accordance with one embodiment of the present invention.
  • the operating speed of a conventional computing device is limited by the speed of access of the tertiary memory.
  • the computing device stores data in an external storage of a third level when not initiating.
  • the configuration file used for booting is first read into the processor through the memory of the second level from the external storage of the third level; and according to the available capacity in the memory and the required use.
  • the amount of data the data is exchanged from the external storage of the third level to the memory of the second level, and the processor reads the data that needs to be logically operated from the memory of the second level for corresponding processing, and will calculate The latter data is returned to the second level of memory for program operation; if there is a small amount of data that is repeatedly executed logically, the lesser portion of data can be cached in the first level of on-chip storage in the processor.
  • the memory needs to be released, that is, the data in the second level of memory is exchanged to the external storage of the third level for storage to prevent data loss.
  • non-volatile memory is not suitable for on-chip storage and memory. This is because the field generally believes that non-volatile memory such as tape, disk and flash memory is very slow to access, which makes it possible to use traditional non-volatile memory for on-chip memory and memory that requires fast memory access to data. Memory does not implement their functionality, that is, in order to cache data or host applications, memory and on-chip storage must have fairly fast access speeds.
  • the inventors have proposed a computing device based on a nonvolatile memory device by studying the defects in the prior art, which breaks the inherent knowledge that the computing device needs to have a three-level memory structure in the prior art, and the new type is not easy.
  • the combination of lost memory and computing device overcomes the situation of data loss caused by power failure during operation, and ensures the security of the computing device.
  • a hard disk which can adopt an on-chip storage or an on-chip storage combined with a memory, thereby overcoming the storage hierarchy, control complexity and expansion in the original computer system. Poor sex.
  • the computing device of the present invention also improves the stability and reliability of the system, and can quickly store the unsaved data in the processor in the on-chip storage or the memory after the power is turned off, and can quickly start up after the power is restored. And restore the data.
  • the inventors have found that the newly developed new non-volatile memory can save data for a long time in the case of power failure, and has lower power consumption and higher storage density while taking into consideration non-volatility, so that it can It has a storage capacity close to a few hundred GB, and its speed of fetching data can reach the order of nanoseconds close to the dynamic random access memory (DRAM) read and write speed.
  • DRAM dynamic random access memory
  • the computing device employs a two-stage memory structure including non-volatile on-chip storage (first stage) integrated on a chip of the processor, and non-volatile memory associated with the processor (first Level 2).
  • first stage non-volatile on-chip storage
  • second Level 2 non-volatile memory associated with the processor
  • the storage capacity stored on the non-volatile chip is related to the area occupied by the chip, so the storage capacity stored on the set non-volatile chip can be determined according to the size requirement of the processor chip. Since a two-stage memory structure is employed in the present invention, the nonvolatile memory needs to assume the role of external storage in FIG. 1, and therefore, in the present invention, a nonvolatile memory having a relatively large storage capacity is preferably employed.
  • Non-volatile memory such as 100GB or more.
  • the startup of the required configuration file, the data requiring the processor to perform the logical operation, the program to be run, and the like are stored in the non-volatile memory.
  • the configuration file used for booting is read by the processor from the non-volatile memory of the second level; after the configuration is completed, the processor reads from the non-volatile memory of the second level.
  • the lesser portion of data is cached in the first level of non-volatile on-chip storage in the processor to save memory access time; when the running program is finished, there is no need to release the non-volatile memory in the non-volatile memory.
  • the programs and data running and the data in the non-volatile on-chip memory are not lost after power-down.
  • computing devices employing a primary storage structure may also be provided in other embodiments of the present invention without the second level of non-volatile memory being provided. Such an embodiment is suitable for applications where the size of the chip is not critical and the storage capacity is not critical.
  • a nonvolatile memory device such as a phase change memory (PCM), a magnetic random access memory (MRAM), and a spin torque conversion random access memory may be employed in the present invention.
  • PCM phase change memory
  • MRAM magnetic random access memory
  • RRAM Resistive Random Access Memory
  • the energy storage device can be further increased in the above computing device.
  • the computing device provided by the present invention includes: a control core, a storage unit, an input/output interface, a capacitor energy storage module, and a power module.
  • the control core is used to control the flow of data and manipulate the corresponding data for logical operations. It can be a central processing unit or other control unit such as a programmable logic controller, and can be implemented by an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (Field Programmable Gate Array). FPGA) implementation. A logical operation unit for performing logical operations on data is not shown in FIG.
  • a storage unit for storing data for storing data.
  • a two-stage or one-stage storage structure may be employed in the present invention to provide non-volatile on-chip storage and/or non-volatile memory.
  • the memory unit can store memory data, system files, application software files, and the like, and is connected to the control core through a bus, so that the control core can control reading, writing, and running of data and/or programs in the storage unit.
  • An input and output interface for providing an input interface for inputting data and outputting data to the computing device for connection to input and/or output devices such as a display, a mouse, and a keyboard.
  • a power module for providing power to the computing device (including the capacitor energy storage module).
  • the capacitor energy storage module is an important module based on the non-volatile storage computing device provided by the present invention, and is used for providing power to the computing device after the system is powered off, so that the computing device can store unsaved data in the processor, such as a control unit.
  • the data in is stored in a non-volatile memory unit.
  • the capacitor energy storage module comprises a capacitor circuit and a peripheral control circuit, wherein the capacitor circuit collects charge storage power in a case where the system is normally powered, and the peripheral control circuit controls charging and discharging of the adjustment capacitor circuit.
  • the operational modes of the capacitive energy storage modules according to the present invention can be divided into two categories: electrical energy storage and electrical energy release.
  • the capacitor energy storage module When the system is normally powered, the capacitor energy storage module enters an electrical energy storage state, and the computing device charges the capacitor through the control unit and the capacitor peripheral control circuit in the capacitor energy storage module to store the charge into the capacitor.
  • the capacitor energy storage module When the system is abnormally powered off or enters the sleep state, the capacitor energy storage module enters the power release state, and the capacitor energy storage module supplies power to the computing device through the power module of the computing device, and the control core stores the data that is run when the abnormal power is cut off.
  • a non-volatile memory device In a non-volatile memory device.
  • the control core and the capacitor peripheral control circuit close the capacitor discharge path, turn off the charge discharge, prevent the capacitor energy loss, save energy, and at the same time, when the computing device restores the power supply, the battery can be charged on the basis of the original power of the capacitor to speed up Charging time.
  • the method includes:
  • Step S1 the computing device is in a normal power supply state, the computing device works normally, and the capacitor energy storage module enters an electrical energy storage state;
  • Step S2 when the computing device is powered off or triggers a sleep command, the computing device system stands by;
  • Step S3 the capacitor energy storage module is switched to the power release state, and the data in the control unit is saved in the memory unit by discharging the capacitor;
  • Step S4 the power is turned on, the computing device is started, and the capacitor energy storage module enters a capacitor storage state;
  • step S5 the control unit reads the startup configuration file from the storage device, starts from the power-off point, restarts the computer device, and restores the state before power-off or sleep.
  • the present invention provides a computing device based on a nonvolatile memory device, which uses a nonvolatile memory device to store an intermediate running file of a computing device, a startup configuration file, and when the device is suddenly powered off,
  • the non-volatile memory device can still store the content of the running data, ensuring the power-off security of the device, and at the same time achieving the purpose of quick start.
  • the invention breaks the storage system of the traditional computing device, adopts the integrated structure of memory and external storage, overcomes the problems of multiple storage layers, complicated control and poor expansion in the original computer system, and improves the stability of the system and reliability.
  • a computing device for a non-volatile memory device provides a fabric and data exchange mechanism for non-volatile on-chip storage.
  • FIG. 5(a) is a schematic structural diagram of the non-volatile on-chip storage of FIG. 3, and it can be seen that two different parts of the storage area and the boot area are divided on the non-volatile on-chip storage. .
  • the memory area can be used for normal read and write storage when the system is powered normally.
  • the boot area is another storage area that is configured outside the storage area and can be used to save programs that are running when power is off and data.
  • the user of the computing device may choose to set the boot area such that, in the case of normal powering, the boot area cannot be used to read and write stored data.
  • the boot area saves running programs and data only after the system is powered down, and cannot read or write to the memory area during normal operation without power failure.
  • the boot area and the memory area are independent of each other.
  • the storage area can be written back, that is, the data is written back to the memory only when it is invalid (that is, there is no data available in the storage area), and the boot area does not read or write any content during normal power supply, and is used for Stores running programs and data when it is powered.
  • the operation steps for reading and writing data for this embodiment are as follows:
  • Step a1 when the power is normally supplied, the on-chip memory area is read and written, and the storage area is in a write back mode;
  • Step a2 when the system is powered off, the capacitor energy storage device releases the power, and writes the running program and data to the startup area;
  • step a3 when the system is powered on, the program executed before the power-off is resumed from the boot area stored on the non-volatile chip.
  • control unit and the arithmetic logic unit can read and write the storage area normally and the global access speed is consistent, but the storage space of the boot area is sacrificed.
  • the user of the computing device may choose to set the boot area to be capable of reading and writing stored data in the event of normal powering.
  • the boot area and the memory area stored on the nonvolatile chip can be used to write or read data, and a power failure occurs.
  • the running area is used to store running programs and data. This can expand the actual storage capacity stored on the non-volatile on-chip (ie, the extended memory area in Figure 5(b)), thereby increasing the efficiency of the system.
  • the storage area and the boot area use different on-chip-chip storage data exchange mechanisms.
  • the booting area adopts a write-through mode, that is, when the control unit writes to the on-chip storage for writing, the same data is simultaneously written into the corresponding space in the off-chip memory, and the storage area is written back, that is, only Write the data back to memory when it is invalid.
  • the operation steps for reading and writing data for this embodiment are as follows:
  • step b1 if the system is powered normally, when the read/write is performed on the non-volatile on-chip storage, the boot area adopts a write-through mode, and the storage area adopts a write-back mode;
  • Step b2 if the system is powered off, the capacitor energy storage device releases the power, and writes the running program and data to the startup area;
  • step b3 when the system is powered on again, the program executed before the power failure is resumed from the boot area.
  • the stored content can be stored or accessed quickly, and the stored content also has a backup in the off-chip memory, once the system is broken.
  • the power and the running program and data are written into the boot area.
  • the coverage of the stored data in the boot area does not cause data loss. Since on-chip resources are very limited for most applications, on-chip memory resources can be fully utilized by this embodiment.
  • the method may result in different access rates when accessing the boot area and the storage area, causing imbalance in load processing.
  • the write-through method is used to read and write the boot area, and the bus is needed to write the backup of the data into the memory, which will occupy the bus for a long time and affect the overall running performance of the device.
  • the present invention also provides a cache replacement mechanism for the scheme illustrated in FIG. 5(b).
  • the boot area is configured as an area for the storage area to be backed up, and the boot area and the external storage area (for example, memory) adopt a fully connected mapping mode, that is, each storage block in the storage area. Both are connected to each memory block in the external storage.
  • the boot area and the external storage area for example, memory
  • the control unit stores the request for acquiring data on the nonvolatile chip, the requested data is respectively looked up in the storage area and the boot area:
  • the data is found from off-chip storage (for example, in memory) and stored in the storage area, and the replaced data in the storage area is written into the boot area, only in the boot area. Data is written to the memory area when full data is written, and write pass is performed to exchange all data in the boot area with off-chip storage;
  • off-chip storage for example, in memory
  • the data in the boot area is exchanged with the storage area.
  • Figure 6 illustrates a method of use in which Figures 5(a), (b) are integrated in accordance with one embodiment of the present invention.

Abstract

本发明提供一种基于非易失存储的计算装置，包括：处理器、集成在处理器上的片上存储、和/或内存，以及储能装置，用于在通电时存储电能，并在掉电时提供电能以将所述处理器上尚未保存的数据存储到所述片上存储和/或所述内存；其中，所述片上存储和/或所述内存采用读写速度为纳秒数量级的非易失存储器，用于向所述处理器提供对执行运算的数据的访存。

Description

一种基于非易失存储的计算装置及其使用方法 技术领域
本发明涉及对计算装置的结构的改进。
背景技术
基于美籍匈牙利数学家冯.诺依曼于1946年提出的存储程序原理，即将程序本身当作数据来对待，以将程序和该程序处理的数据用同样的方式储存，使得现代计算机的存储和应用得到了长足的发展。
时至今日，大多数的计算机仍沿用了基于冯.诺依曼计算机的组织结构，这样的计算机架构被称作为冯.诺依曼体系结构。基于冯.诺依曼体系结构的计算机或计算装置，具备长期存储或记忆程序、数据、中间结果及最终运算结果的能力，能够将需要的程序和数据送至计算机或计算装置中，并且能够针对数据进行逻辑运算等加工处理，能够通过指令控制程序和数据的走向、协调相应的操作，并将处理输出给用户或者输入计算机或计算装置中进行存储。
图1示示意性地出了传统的冯.诺依曼体系结构的计算装置的示意图，现今绝大多数市售的PC、笔记本电脑、平板电脑、手机等均使用这样的结构，可以看到其采用了三级的方式来存储程序和数据。在处理器的芯片上集成有片上存储(第一级)，并且在处理器之外还具有内存(第二级)以及通常被称作为硬盘的外部存储(第三级)。在上述三级中，片上存储集成在处理器上，因而具备最快的访存速度，其造价高昂并且通常存储容量极其有限，内存与处理器相连接，绝大多数的应用程序的数据通常会在内存上运行，内存的存储容量有限，其与片上存储均属于易失存储器，例如静态随机存储器或动态随机存储器，这样的易失存储器在系统掉电后会丢失数据。相比之下，位于第三级的外部存储采用例如磁带、磁盘及闪存等非易失存储器，所述外部存储具有最大的存储容量以及最慢的访存速度，其所存储的数据在系统掉电后不会丢失。
然而，上述传统的具有三级存储器的计算装置在读写数据以及运行程 序的过程中，数据需要在各个层级的存储器之间相互传输，致使系统不得不花费相当多的时间来执行中等距离甚至是远距离的数据读取、写入、传输以及释放片上存储和内存的空间等操作，由此限制了计算装置的运行速度。并且，如前文中所述，在上述传统的计算装置中，片上存储以及内存所采用的均为易失存储器，如若在所述计算装置运行期间发生了掉电，那么缓存在片上存储、以及运行在内存上的程序和数据则会丢失，从而影响使用者的体验，甚至会为使用者带来难以挽回的数据损失。此外，在传统的计算装置中，用于执行绝大多数应用程序的内存的存储容量有限，限制了其在同一时间段内可运行的应用程序的数量或大小。
发明内容
因此，本发明的目的在于克服上述现有技术的缺陷，提供一种基于非易失存储的计算装置，包括：
处理器、集成在处理器上的片上存储和/或内存，以及
储能装置，用于在通电时存储电能，并在掉电时提供电能以将所述处理器上尚未保存的数据存储到所述片上存储和/或所述内存；
其中，所述片上存储和/或所述内存采用读写速度为纳秒数量级的非易失存储器，用于存储程序以及数据。
优选地，根据所述装置，其中所述储能装置中还包括电容电路，用于在掉电时为所述计算装置供电。
优选地，根据所述装置，其中所述片上存储和/或所述内存所采用的非易失存储器选自：相变存储器、磁性随机存储器、自旋扭矩转换随机存储器、铁电随机存储器、阻变随机存储器。
优选地，根据所述装置，其中所述内存还用于存储启动所述装置的配置文件。
优选地，根据所述装置，其中所述片上存储包括存储区和启动区，所述启动区被设置为在正常供电时无法被读写以及在掉电时用于存储尚未被保存的程序和数据，所述存储区被设置为采用写回的方式。
优选地，根据所述装置，其中所述片上存储包括存储区和启动区，所述启动区被设置为采用写穿透的方式、以及在正常供电时可以被读写、以及在掉电时用于存储尚未被保存的程序和数据，所述存储区被设置为采用 写回的方式。
以及，一种针对所述装置的使用方法，包括：
在控制单元向非易失片上存储请求获取数据时，在存储区和启动区中分别查找所请求的数据：
若是存储区和启动区中均没有所请求的数据，则从片外存储中找到所请求的数据存入存储区，存储区中替换的数据写入启动区中，仅在启动区已写满数据的情况下才将数据写入存储区，以及执行写穿透以将启动区中的全部数据与片外存储进行交换；
若是存储区中没有所请求的数据，启动区中包含所请求的数据，则将启动区中的所述数据与存储区进行交换。
以及，一种针对所述装置的使用方法，包括：
1)在所述装置断电或触发休眠指令时，由所述储能装置将所述处理器中运算的数据存入所述片上存储和/或所述内存；
2)在所述装置恢复通电或启动时，重新启动存储在所述片上存储和/或所述内存中的所述数据，恢复断电或休眠前的状态。
根据所述方法，其中还包括：
在所述装置通电时，对所述储能装置充电。
以及，一种针对所述装置的使用方法，包括：
在启动所述装置时，从所述内存中读取所述装置的配置文件；或者
在执行访问数据时，由所述处理器从所述内存和/或所述片上存储中读取数据以进行运算；或者
在执行写入数据时，将数据存储到所述内存和/或所述片上存储。
与现有技术相比，本发明的优点在于：
打破了计算装置需要采用三级存储结构的固有认知，减少了数据传输、交换的层级数量。在保证内存和/或片上存储的访存速度的情况下，提供了容量能够适宜于计算装置需求的具有两级或一级存储结构的计算装置。计算装置无需花费长时间来执行中远距离的数据读取、写入、传输等操作。此外，在本发明中，由于没有设置第三级存储器，而是将内存与硬盘相结合作为第二级存储器，因此在程序结束运行后无需执行释放内存空间的操作，简化了操作过程和控制所需的复杂度。并且，在本发明中采用了读写速度为纳秒数量级的非易失存储器，在系统掉电时不会出现存储器 中数据丢失的现象。并且进一步地，本发明中还设置了储能装置，在通电时存储电能，并在掉电时提供电能以将所述处理器上尚未保存的数据进行存储，由于本发明中仅设置了访存速度较快的内存和/或片上存储，因此相较于在普通计算装置中设置电容电路而言，在消耗相同电能的情况下，本发明可以存储更多的数据，因而还具备节能的优点。除此之外，本发明所设置的内存的存储容量远远大于传统内存的存储容量，因此在同一时间段内可运行更多或更大的应用程序。
附图说明
以下参照附图对本发明实施例作进一步说明，其中：
图1是现有技术中传统的具有三级存储器的计算装置的示意图；
图2是根据本发明的一个实施例的两级存储结构的基于非易失存储的计算装置的示意图；
图3是根据本发明的又一个实施例的基于非易失存储的计算装置的模块示意图；
图4是根据本发明的一个实施例对图2或图3中的计算装置的使用方法的流程图。
图5(a)是根据本发明的一个实施例针对图3中的非易失片上存储的结构示意图。
图5(b)是根据本发明的一个实施例将图5(a)中的启动区设置为在正常供电的情况下启动区能够用于读写存储数据的示意图。
图6是根据本发明的一个实施例将图5(a)、(b)综合起来的使用方法。
具体实施方式
下面结合附图和具体实施方式对本发明作详细说明。
如背景技术中所介绍地，传统的计算装置的运行速度受限于三级存储器的访存速度。参考图1，所述计算装置在未启动时，将数据存储在第三级的外部存储中。当启动所述计算装置时，首先从第三级的外部存储中将启动所使用的配置文件通过第二级的内存读入处理器中进行配置；并且根据内存中可用的容量及所需使用的数据量大小，将数据从第三级的外部存储中交换至第二级的内存中，由处理器从第二级的内存中读取需要进行逻 辑运算的数据以进行相应的处理，并将计算后的数据返回到第二级的内存中以进行程序的运行；若是存在少部分数据被反复地执行逻辑运算过程，则可以将所述少部分的数据缓存在处理器中第一级的片上存储中，以节省访存时间；对于结束运行的程序，则需要对内存进行释放，即将第二级的内存中的数据交换至第三级的外部存储进行保存，以防止数据丢失。
可以看出，数据在上述三级的结构中需要逐级地传输或交换，存储器距离处理器的核心越远，则传输或交换数据所消耗的时间越长。并且，通常情况下第一级、第二级、第三级存储器访存数据的速度逐级递减，这使得上述计算装置的运行速度、进行控制的复杂度受到三层结构的限制和影响。此外，本领域中普遍认为不宜采用非易失存储器来实现片上存储以及内存。这是由于，本领域通常认为诸如磁带、磁盘及闪存等非易失存储器的访存速度非常慢，这使得对于需要具备能够快速访存数据的片上存储以及内存来说，采用传统的非易失存储器并不能实现他们的功能，即为了缓存数据或者承载应用程序，内存和片上存储必须具备相当较快的访存速度。
发明人通过研究现有技术中的缺陷，提出了一种基于非易失存储器件的计算装置，其打破了现有技术中关于计算装置需要具备三级存储器结构的固有认知，将新型非易失存储器与计算装置相结合，克服了在运行过程中掉电而发生数据丢失的情况，保证了计算装置的安全性。在本发明的计算装置中，无需再单独设置称作为硬盘的外部存储，其可以采用片上存储或片上存储与内存相结合的方式，克服了原有计算机体系机构中存储层次多、控制复杂和扩展性差的问题。并且，本发明的计算装置还提高了系统的稳定性和可靠性，在掉电后可以快速地将处理器中尚未保存的数据存储在片上存储或内存中，当电源恢复后，可以快速地启动并恢复数据。
发明人发现近年来新开发出的新型非易失存储器可以在断电的情况下长期保存数据，在兼顾非易失性的同时，具备更低的能耗、更高的存储密度，致使其可以具有接近几百GB的存储容量，并且其访存数据的速度可以达到接近动态随机存取存储器(DRAM)读写速度的纳秒数量级。具有这样特征的非易失存储器尤其适合于根据本发明的计算装置。
图2示出了根据本发明的一个实施例的基于非易失存储器件的计算装置。参考图2，所述计算装置采用了两级的存储结构，包括集成在处理器的芯片上的非易失片上存储(第一级)、以及与所述处理器关联的非易失 内存(第二级)。其中，所述非易失片上存储的存储容量与其在芯片上所占面积相关，因此可以根据对处理器芯片的尺寸要求来决定所设置非易失片上存储的存储容量。由于在本发明中采用了两级的存储结构，所述非易失内存需要承担起图1中外部存储的作用，因此在本发明中优选地采用存储容量相对较大的非易失存储器作为所述非易失内存，例如100GB以上。
在根据本发明的上述计算装置在未启动时，启动所需的配置文件、需要处理器进行逻辑运算的数据、需要运行的程序等均存储在所述非易失内存中。当启动所述计算装置时，由处理器从第二级的非易失内存中读取启动所使用的配置文件；在完成配置之后，处理器从第二级的非易失内存中读取需要进行逻辑运算的数据以进行相应的处理，并将计算后的数据返回到第二级的非易失内存中以进行程序的运行；若是存在少部分数据被反复地执行逻辑运算过程，则可以将所述少部分的数据缓存在处理器中第一级的非易失片上存储中，以节省访存时间；在结束运行的程序时，无需对非易失内存进行释放，在非易失内存上运行的程序和数据以及非易失片上存储中的数据在掉电后不会发生丢失。
应当理解，在本发明的其他实施例中还可以设置采用一级存储结构的计算装置，而不设置第二级的非易失内存。这样的实施方式适合于对芯片的尺寸要求不高、并且对存储容量要求不高的应用。
优选地，在本发明中可以采用诸如下述非易失存储器件，包括：相变存储器(phase change memory，PCM)、磁性随机存储器(Magnetic Random Access Memory，MRAM)、自旋扭矩转换随机存储器(Spin Torque Transfer Random Access Memory，STT-RAM)、铁电随机存储器(Ferroelectric RAM，FeRAM)、阻变随机存储器(RRAM)。这样的非易失存储器件，不会因为计算装置掉电而丢失其中的数据，具有较高的安全性，并且其还具备功耗低、噪声小、鲁棒性高、散热低等优点。
根据本发明的一个实施例，还可以在上述计算装置中进一步地增加储能装置。参考图3示出的示例，本发明提供的计算装置中包括：控制核心、存储单元、输入输出接口、电容储能模块及电源模块。
其中，控制核心，用于控制数据的流向以及操纵相应的数据进行逻辑运算。其可以为中央处理器，也可以为可编程逻辑控制器等其他控制单元，具体可以采用专用集成电路(Application Specific Integrated Circuit，ASIC)实现，也可采用现场可编程门阵列(Field Programmable Gate Array，FPGA) 实现。在图3中未示出用于对数据执行逻辑运算的逻辑运算单元。
存储单元，用于存储数据。如前述实施例中介绍地，本发明中可以采用两级或一级的存储结构，来设置非易失片上存储和/或非易失内存。在存储单元中可以存储内存数据、系统文件及应用软件文件等，其与控制核心通过总线相连，使得控制核心能够控制对存储单元中的数据和/或程序进行读写、运行。
输入输出接口，用于为所述计算装置提供输入数据和输出数据的接口以与诸如显示器、鼠标及键盘等输入和/或输出设备进行连接。
电源模块，用于为所述计算装置(包括电容储能模块)提供电能。
电容储能模块是本发明提供的基于非易失存储计算装置的重要模块，其用于在系统断电后为计算装置提供电能，使得计算装置可以将处理器中尚未保存的数据，例如控制单元中的数据存储至非易失存储单元中。优选地，电容储能模块包括电容电路和外围控制电路，其中电容电路在系统正常供电的情形采集电荷存储电能，外围控制电路则控制调节电容电路的充放电。
可以将根据本发明的电容储能模块的工作模式分为两类：电能存储和电能释放。在系统正常供电时，电容储能模块进入电能存储状态，所述计算装置通过控制单元及电容储能模块内电容器外围控制电路对电容进行充电，将电荷存储至电容器中。当系统发生异常断电或进入休眠状态时，电容储能模块进入电能释放状态，电容储能模块通过计算装置的电源模块为计算装置供电，控制核心将发生异常断电时所运行的数据存储至非易失存储装置中。当数据存储结束后，控制核心及电容外围控制电路关闭电容放电通路，关闭电荷放电，防止电容电能流失，节约电能，同时在计算装置恢复供电时，可在电容原有电量基础上进行充电，加快充电时间。
下面将具体介绍上述具有电容储能模块的计算装置的使用方法。参考图4，所述方法包括：
步骤S1，所述计算装置处于正常供电状态，计算装置正常工作，电容储能模块进入电能存储状态；
步骤S2，当所述计算装置断电或触发休眠指令时，计算装置系统待机；
步骤S3，电容储能模块切换至电能释放状态，通过电容放电，将控制单元中的数据保存在内存单元中；
步骤S4，电源接通，所述计算装置启动，电容储能模块进入电容存储 状态；
步骤S5，控制单元从存储装置读取启动配置文件，将从断电处开始运行，计算机装置重新启动，恢复断电或休眠前的状态。
本发明通过上述技术方案提供了一种基于非易失存储器件的计算装置，所述计算装置采用非易失存储器件存储计算装置的中间运行文件、启动配置文件，在装置突然断电时，所述非易失存储装置依旧可以保存运行数据的内容，保证了装置的掉电安全，同时可以达到快速启动的目的。同时，本发明打破了传统计算装置的存储体系，采用内存和外存一体化结构，克服了原有计算机体系机构中存储层次多、控制复杂和扩展性差的问题，同时提高了系统的稳定性和可靠性。
为了进一步地保证正在运行的数据在掉电后可以保存至片上存储中，并且不会覆盖其原有数据，从而确保计算装置能够在恢复供电之后正常启动，本发明还针对前文中所述的基于非易失存储器件的计算装置，提供了一种用于非易失性片上存储的结构和数据交换机制。
如图5(a)示出了针对图3中的非易失片上存储的结构示意图，可以看出，在所述非易失片上存储上划分出了存储区和启动区这两个不同的部分。该存储区可被用于系统正常供电时的常规读写存储，相比之下，启动区是在存储区之外另配置的一块存储区域，可被用于保存掉电时正在运行的程序和数据。
根据本发明的一个实施例，计算装置的使用者可以选择将启动区设置为，在正常供电的情况下，启动区不能够用于读写存储数据。例如，启动区仅在系统掉电后保存正在运行的程序和数据，而在没有发生掉电的正常运行时，不能对存储区进行读写操作。
在此实施例中，启动区和存储区是相互独立的。其中，存储区可以采用写回的方式，即仅在其无效(即存储区内没有可用数据)时再将数据写回内存中，启动区在正常供电时不读写任何内容，用于在掉电时存储正在运行的程序和数据。针对该实施例读写数据的操作步骤为：
步骤a1，正常供电时，读写片上存储区，存储区采用写回方式；
步骤a2，系统断电时，电容储能装置释放电量，将正在运行的程序和数据写入至启动区；
步骤a3，系统上电时，从非易失片上存储的启动区中恢复执行断电前所执行的程序。
采用所述方法，控制单元和运算逻辑单元可以正常读写存储区且全局访问速度一致，但是会牺牲启动区的存储空间。
根据本发明的又一个实施例，计算装置的使用者可以选择将启动区设置为，在正常供电的情况下，启动区能够用于读写存储数据。例如，图5(b)所示出地，在没有掉电的情况下，所述非易失片上存储的启动区和存储区均可以用于写入或者读取数据，而在发生了掉电时，由启动区来存储正在运行的程序和数据。这样做可以扩展非易失片上存储的实际存储容量(即图5(b)中的扩展存储区)，从而提高系统的效率。
在此实施例中，存储区和启动区采用不同的片上-片下存储数据交换机制。其中，启动区采用写穿透的方式，即在控制单元向片上存储进行写操作时，同时将相同的数据写入片外的内存中的对应空间，存储区则采用写回的方式，即仅在其无效时再将数据写回内存中。针对该实施例读写数据的操作步骤为：
步骤b1，若系统正常供电，则在对非易失片上存储进行读写时，启动区采用写穿透方式，存储区采用写回方式；
步骤b2，若系统断电，则电容储能装置释放电量，将正在运行的程序和数据写入至启动区；
步骤b3，当系统再次上电时，从启动区中恢复执行断电前所执行的程序。
采用所述方法，由于启动区采用了写穿透的方式，使得其所存储的内容既可以快速地被存储或访问，同时其所存储的内容在片外的内存中也具有备份，一旦系统断电，并将正在运行的程序和数据写入至启动区中，此时由于具有备份的原因，对启动区中存储数据的覆盖不会造成数据丢失。由于对于大多数应用而言，片上资源是非常有限地，通过本实施例可以充分地利用片上存储资源。
考虑到由于启动区和存储区的数据交换机制不同，该方法会导致访问启动区和存储区时的访存速率不同，引起负载处理的不均衡。
并且，采用写穿透的方式对启动区进行读写，需要使用总线来将数据的备份写入内存，会长时间地占用总线，影响装置整体的运行性能。
对此，本发明还提供了一种针对图5(b)所示出的方案的缓存替换机制。
根据本发明的一个实施例，将启动区配置为用于存储区进行备份的区域，且该启动区与外部的存储区(例如内存)采用全相连的映射模式，即 存储区内每个存储块均与外部存储中的每个存储块相连。
在控制单元向非易失片上存储请求获取数据时，在存储区和启动区中分别查找所请求的数据：
若是存储区和启动区中均没有所请求的数据，则从片外存储(例如内存中)找到该数据，存入存储区，存储区中替换的数据写入启动区中，仅在启动区已写满数据的情况下才将数据写入存储区，以及执行写穿透以将启动区中的全部数据与片外存储进行交换；
若是存储区中没有所请求的数据，启动区中包含所请求的数据，则将启动区中的所述数据与存储区进行交换。
可以看到，在上述缓存替换机制中，区别于许多现有技术中直接将未存储在非易失片上存储的存储区中数据进行替换，而是优先将这些数据存入启动区中。采用这种机制，一方面可以更有效利用程序的局部性，启动区采用全相联的映射方式，提高了效率，另一方面可以减少启动区与片外存储器之间的交换。
图6示出了根据本发明的一个实施例将图5(a)、(b)综合起来的使用方法。
需要说明的是，上述实施例中介绍的各个步骤并非都是必须的，本领域技术人员可以根据实际需要进行适当的取舍、替换、修改等。
最后所应说明的是，以上实施例仅用以说明本发明的技术方案而非限制。尽管上文参照实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，对本发明的技术方案进行修改或者等同替换，都不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (10)

  1. 一种基于非易失存储的计算装置，包括：
    处理器、集成在处理器上的片上存储和/或内存，以及
    储能装置，用于在通电时存储电能，并在掉电时提供电能以将所述处理器上尚未保存的数据存储到所述片上存储和/或所述内存；
    其中，所述片上存储和/或所述内存采用读写速度为纳秒数量级的非易失存储器，用于存储程序以及数据。
  2. 根据权利要求1所述的装置，其中所述储能装置中还包括电容电路，用于在掉电时为所述计算装置供电。
  3. 根据权利要求1-2中任意一项所述的装置，其中所述片上存储和/或所述内存所采用的非易失存储器选自：相变存储器、磁性随机存储器、自旋扭矩转换随机存储器、铁电随机存储器、阻变随机存储器。
  4. 根据权利要求3所述的装置，其中所述内存还用于存储启动所述装置的配置文件。
  5. 根据权利要求4所述的装置，其中所述片上存储包括存储区和启动区，所述启动区被设置为在正常供电时无法被读写以及在掉电时用于存储尚未被保存的程序和数据，所述存储区被设置为采用写回的方式。
  6. 根据权利要求4所述的装置，其中所述片上存储包括存储区和启动区，所述启动区被设置为采用写穿透的方式、以及在正常供电时可以被读写、以及在掉电时用于存储尚未被保存的程序和数据，所述存储区被设置为采用写回的方式。
  7. 一种针对权利要求6中所述装置的使用方法，包括：
    在控制单元向非易失片上存储请求获取数据时，在存储区和启动区中分别查找所请求的数据：
    若是存储区和启动区中均没有所请求的数据，则从片外存储中找到所请求的数据存入存储区，存储区中替换的数据写入启动区中，仅在启动区已写满数据的情况下才将数据写入存储区，以及执行写穿透以将启动区中的全部数据与片外存储进行交换；
    若是存储区中没有所请求的数据，启动区中包含所请求的数据，则将启动区中的所述数据与存储区进行交换。
  8. 一种针对权利要求1-4中任意一项所述装置的使用方法，包括：
    1)在所述装置断电或触发休眠指令时，由所述储能装置将所述处理 器中运算的数据存入所述片上存储和/或所述内存；
    2)在所述装置恢复通电或启动时，重新启动存储在所述片上存储和/或所述内存中的所述数据，恢复断电或休眠前的状态。
  9. 根据权利要求8所述的方法，其中还包括：
    在所述装置通电时，对所述储能装置充电。
  10. 一种针对权利要求1-4中任意一项所述装置的使用方法，包括：
    在启动所述装置时，从所述内存中读取所述装置的配置文件；或者
    在执行访问数据时，由所述处理器从所述内存和/或所述片上存储中读取数据以进行运算；或者
    在执行写入数据时，将数据存储到所述内存和/或所述片上存储。
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