WO2019041763A1 - 供电设备和以太网供电的节能方法 - Google Patents

供电设备和以太网供电的节能方法 Download PDF

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Publication number
WO2019041763A1
WO2019041763A1 PCT/CN2018/076740 CN2018076740W WO2019041763A1 WO 2019041763 A1 WO2019041763 A1 WO 2019041763A1 CN 2018076740 W CN2018076740 W CN 2018076740W WO 2019041763 A1 WO2019041763 A1 WO 2019041763A1
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WIPO (PCT)
Prior art keywords
power supply
power
supply port
pse chip
port
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Application number
PCT/CN2018/076740
Other languages
English (en)
French (fr)
Inventor
陈华
付世勇
庄艳
华睿
董歧
顾超
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18850429.4A priority Critical patent/EP3664368B1/en
Publication of WO2019041763A1 publication Critical patent/WO2019041763A1/zh
Priority to US16/802,974 priority patent/US11368321B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3209—Monitoring remote activity, e.g. over telephone lines or network connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result

Definitions

  • the present invention relates to the field of communications, and in particular, to a power supply device and a power saving method for power over Ethernet.
  • PoE Power over Ethernet
  • PSE Power Sourcing Equipment
  • PD Power Device
  • PoE is a wired Power over Ethernet technology. PoE allows data and power coupling to be transmitted to the powered device through the network cable. Data and power can be separated and transmitted to the powered device through the network cable.
  • PoE Institute of Electrical and Electronics Engineers
  • the PSE can provide 15.4W of power to the PD.
  • the high-power PoE standard IEEE 802.3at was released.
  • the PSE can provide 30W of power to the PD.
  • PoE The standard is still evolving and will cover the 90W power range.
  • the present application provides a power supply device and a method for powering a power over Ethernet, which can reduce the power consumption of the power supply device and avoid wasting resources.
  • a power supply device including a power supply port, a power supply device PSE chip, a low power consumption detecting component, a control switch, and a power switch; the power supply port is connected to the control switch, the PSE chip And the low power control component is respectively connected to the control switch, and the PSE chip is connected to the power switch;
  • the low power consumption detecting component is configured to detect the power supply port when the power supply port is connected to the power supply port, and send a first instruction when the power supply port accesses a valid PD, where the first instruction is used Instructing the control switch to turn on the PSE chip and the power supply port, disconnecting the low power consumption detecting component from the power supply port, instructing the power switch to turn on the PSE chip and a power supply;
  • the control switch is configured to turn on the PSE chip and the power supply port according to the first instruction, and disconnect the low power consumption detecting component from the power supply port;
  • the power switch is configured to turn on a power supply of the PSE chip according to the first instruction.
  • the low-power detecting component detects that the power port is connected to the effective PD
  • the PSE chip and the power supply port are turned on
  • the low-power detecting component and the power supply port are disconnected
  • the power switch is turned on to turn on the PSE chip and the power supply. .
  • the power supply of the PSE chip is not always on, so power consumption can be reduced and resources can be wasted.
  • the PSE chip when the PSE chip is connected to the power supply port, and the PSE chip is powered on, the PSE chip is configured to detect the Sending a status notification to the low power detection component when the power supply port is in a non-powered state, the status notification is used to instruct the low power control component to send a second instruction, the second instruction is used to indicate the control Disabling the PSE chip and the power supply port, turning on the low power consumption detecting component and the power supply port, instructing the power switch to disconnect the PSE chip and a power supply;
  • the control switch is further configured to disconnect the PSE chip and the power supply port according to the second instruction, and turn on the low power consumption detecting component and the power supply port;
  • the power switch is further configured to disconnect the PSE chip and the power supply according to the second instruction.
  • the power supply port when the power supply port is in a non-power supply state, it means that it is not necessary to supply power to the PSE chip, and in order to reduce power loss, the PSE chip and the power supply can be disconnected.
  • the PSE chip in a case that the PSE chip is connected to the power supply port, and the PSE chip is powered on, the PSE chip is specifically configured to detect the power supply port. When the detection result of the power supply port is valid, the normal supply voltage is output.
  • the normal supply voltage is output only when the detection result of the power supply port is valid.
  • the PSE chip in a case that the PSE chip is connected to the power supply port, and the PSE chip is powered on, the PSE chip is specifically used to directly connect to the power supply port.
  • the normal supply voltage is output.
  • the PSE chip in order to supply power to the PD in time, can directly output a normal power supply voltage at the power supply port.
  • the operating voltage of the low power consumption detecting component is greater than or equal to 10 volts.
  • the operating voltage of the low power consumption detecting component needs to be greater than or equal to 10 volts.
  • the low power consumption detecting component is in a power supply device PSE chip.
  • the low power detection component is in the PSE chip, so that the integration degree of the PSE chip is high, thereby avoiding external interference.
  • a method for powering a power supply is provided, which is applied to a power supply device including a power supply port, a low power consumption detecting component, and a power supply device PSE chip, where the method includes:
  • the low power detection component detects whether the power supply port is connected to the active power receiving device PD, wherein the power supply port is connected to the low power consumption control component, and the power supply port is disconnected from the PSE chip.
  • the PSE chip is disconnected from the power supply;
  • the power supply method of the present application provides that the PSE chip is disconnected from the power supply, and the low-power component operating at a low voltage detects whether the power supply port is connected to a valid PD, and after detecting that the power supply port is connected to the valid PD, The PSE chip and the power supply are connected again, so that the power supply can continue to output power before the power supply device is connected to the effective PD, thereby reducing the power consumption of the power supply device.
  • the method further includes:
  • the power port When the power port is not connected to a valid PD, the power port is kept connected to the low power control component, the power port is disconnected from the PSE chip, and the PSE chip is disconnected from the power supply.
  • the low power detection component continues to detect the power port.
  • the PSE chip and the power supply port are turned on, the low power consumption detecting component and the power supply port are disconnected, and the PSE chip and the power supply are turned on.
  • the method further includes:
  • the PSE chip detects that the PD connected to the power port is in a non-powered state, disconnecting the PSE chip and the power supply, disconnecting the PSE chip from the power supply port, and turning on the low power detection component. And the power supply port, such that the low power detection component detects the power supply port.
  • the PSE chip and the power supply port are turned on, the low power consumption detecting component and the power supply port are disconnected, and the PSE chip and the power supply are turned on.
  • the method further includes:
  • the PSE chip detects the power supply port, and outputs a normal power supply voltage when the detection result of the power supply port is valid;
  • the PSE chip directly outputs the normal supply voltage at the power supply port.
  • a third aspect provides a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the method of the second aspect described above.
  • a fourth aspect provides a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the methods described in the various aspects above.
  • a fifth aspect provides a power supply system including a power receiving device and the power supply device of the first aspect described above.
  • FIG. 1 is a schematic structural diagram of a power supply device according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a power supply device according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a power supply device according to still another embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of an energy saving method for power over Ethernet in an embodiment of the present invention.
  • the connection between the PSE chip and the power supply port is turned on, the connection between the low power detection component and the power supply port is disconnected, and the power of the PSE chip is turned on. . Since the power of the PSE chip is not always on, the power of the PSE chip can be turned on when certain conditions are met, thereby reducing power loss and avoiding wasting resources.
  • the PSE specifically includes a power supply, a PSE chip, and a power supply port.
  • the power supply supplies voltage to the PSE chip, and the voltage of the PSE chip is controlled by a switch inside the PSE chip, and the PSE chip performs continuous PD detection through the power supply port. After detecting a valid PD, the PSE chip outputs a voltage to the power supply port to provide power to the PD.
  • the voltage supplied by the power supply to the PSE chip is a standard specified operating voltage, that is, a normal supply voltage, for example, 48 volts (V).
  • the switch inside the PSE chip may specifically be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the power supply device specifically includes a power supply port 101, a PSE chip 102, a low power consumption detecting component 103, a control switch 104, and a power switch 105.
  • the power supply port 101 is connected to the control switch 104; the PSE chip 102 and the low power consumption detecting component 103 are respectively connected to the control switch 104; the PSE chip 102 is connected to the power switch 105.
  • the PSE chip 102 performs the associated functions in the manner defined in the standard.
  • the low power consumption detecting component 103 is configured to detect whether the power supply port 101 is connected to a valid PD in the case of being connected to the power supply port 101.
  • the low power consumption detecting component 103 detects when the operating voltage is a low voltage.
  • the low voltage at which the low power component operates, and the supply voltage output to the power supply port, are independent of each other, but are all from the power management system of the power supply device.
  • the power management system outputs voltage according to the requirements of various devices in the power supply device.
  • a portion of the power management system of the power supply device that supplies power to the power supply port is referred to as a power supply.
  • the process of detecting the power supply port is specifically as follows. Two different detection voltages are outputted at the power supply port 101, and the interval between two different voltages is greater than or equal to 1V. The impedance is then calculated based on the two different current values detected and the two different detection voltages. If the impedance is within the preset range, it is determined that the power supply port 101 is connected to the valid PD; if the impedance is not within the preset range, it is determined that the power supply port 101 is not connected to the valid PD.
  • the power supply port 101 When all the power supply ports are idle, that is, when the valid PD is not connected, the power supply port 101 is kept connected to the low power consumption detecting component 103, the power supply port 101 is disconnected from the PSE chip 102, and the PSE chip 102 is disconnected from the power supply, and the power consumption is low. Detection component 103 continues to detect power supply port 101.
  • the low power consumption detecting component 103 When detecting that the power supply port 101 is connected to the active PD, the low power consumption detecting component 103 transmits a first instruction for turning on the power supply of the PSE chip 102, and turning on the connection between the PSE chip 102 and the power supply port 101. The connection of the low power consumption detecting component 103 to the power supply port 101 is disconnected.
  • control switch 104 is configured to turn on the connection of the PSE chip 102 and the power supply port 101 according to the first instruction, and disconnect the low power consumption detecting component 103 from the power supply port 101.
  • the power switch 105 is configured to turn on the power supply of the PSE chip 102 according to the first instruction.
  • the low power consumption detecting component 103 can detect the power supply port 101 when the operating voltage is a low voltage.
  • the low power consumption detecting component 103 detects that the power supply port 101 is connected to a valid PD, the power supply of the PSE chip 102 is turned on.
  • the power supply voltage of the PSE chip 102 is not always in an on state, so that power loss can be reduced and waste of resources can be avoided.
  • the PSE chip 102 when the PSE chip 102 is connected to the power supply port 101, and the PSE chip 102 is powered on, the PSE chip is low-powered when detecting that the power supply port 101 is in a non-power supply state.
  • the consumption detection component 103 sends a status notification.
  • the status notification is used to instruct the low power detection component to send a second instruction, the second instruction is used to instruct the control switch 104 to disconnect the PSE chip 102 and the power supply port 101, turn on the low power detection component 103 and the power supply port 101, and indicate the power supply.
  • the switch 105 disconnects the PSE chip 102 from the power supply.
  • the control switch 104 is configured to disconnect the PSE chip 102 from the power supply port 101 according to the second instruction, and turn on the connection of the low power consumption detecting component 103 and the power supply port 101.
  • the power switch 105 is configured to disconnect the PSE chip 102 and the power supply according to the second instruction.
  • the PD connected to the power supply port 101 is in a non-power supply state, which means that it is not necessary to provide power supply to the PD, and in order to reduce power loss, the power supply can be disconnected.
  • the PSE chip 102 when the PSE chip 102 is connected to the power supply port 101, and the PSE chip 102 is powered on, the PSE chip 102 can detect the power supply port, and the detection result at the power supply port 101 is valid. When the normal supply voltage is output.
  • the PSE chip 102 outputs a low voltage (detection voltage, gradation voltage, power-on voltage, etc.) or a normal supply voltage to the power supply port 101.
  • the power supply port 101 outputs a low voltage when the PSE chip 102 does not detect a valid PD; and outputs a normal power supply voltage when the PSE chip 102 detects a valid PD.
  • the power supply port 101 is detected: the PSE chip 102 sends a detection voltage to the PD to detect the common mode resistance in the PD.
  • the PSE chip 102 may perform physical layer grading on the PD. Specifically, the PSE chip 102 can apply a voltage of 15 to 20 V to the PD and determine the level of the PD by testing the magnitude of the current.
  • the PSE device starts to supply power from the low voltage to the PD during the startup period of a configurable time.
  • the PSE chip 102 in order to power the PD quickly, in the case that the PSE chip 102 is connected to the power supply port 101 and the PSE chip 102 is powered on, the PSE chip 102 does not need to be powered on. When the power supply port 101 is detected again, the normal power supply voltage can be directly outputted at the power supply port 101.
  • the low power consumption detecting component 103 has an operating voltage greater than or equal to 10V. This makes it easy to detect the power supply port 101.
  • the low power detection component 103 can be in the PSE chip 102.
  • FIG. 2 is a schematic structural diagram of a power supply device according to another embodiment of the present invention.
  • the power supply 204 supplies power to the PSE chip 201 through the power switch 205.
  • the PSE chip 201 and the low power consumption detecting component 202 are respectively connected to the control switch 203.
  • the low power detection component 202 detects whether the power port 206 is connected to a valid PD. If the power port 206 is not connected to a valid PD, the power port 206 is kept connected to the low power detection component 202. 206 is disconnected from the PSE chip 201, the PSE chip 201 is disconnected from the power supply, and the low power detection component 202 continues to detect the power supply port. If the power supply port 206 is connected to the active PD, the power supply of the PSE chip 201 is turned on by the power switch 205, the connection between the PSE chip 201 and the power supply port 206 is turned on, and the connection between the low power detection component 202 and the power supply port 206 is disconnected. .
  • the low power detection component 202 is located outside the PSE chip 201, and the control switch 203 and the power switch 205 are also located outside the PSE chip 201, that is, the structure of the PSE chip is unchanged.
  • a low power detection component 202, a control switch 203, and a power switch 205 are added external to the PSE chip to control the output voltage of the power supply port 206. Therefore, the output voltage of the power supply port 206 can be controlled on the basis of the PSE chip without changing the PSE chip.
  • the power supply device may further include a processor and a memory, and the processor, the memory, and the power supply interface 206 may be connected to each other through a bus.
  • the processor can be one or more Central Processing Units (CPUs).
  • CPUs Central Processing Units
  • the CPU may be a single core CPU or a multi-core CPU.
  • the memory may be one or more of, but not limited to, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM), a compact disk read only memory (CD-ROM), a hard disk, and the like. kind.
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • the memory can also be used to store program code.
  • FIG. 3 is a schematic structural diagram of a power supply device according to still another embodiment of the present invention.
  • the power supply 304 is connected to the PSE chip 301 through a power switch 305.
  • the PSE chip 301 and the low power consumption detecting component 302 are respectively connected to the power supply port 306 with the control switch 303.
  • the low power detection component 302 is located inside the PSE chip 301, and the low power detection component 302 and the PSE chip 301 are respectively connected to the power supply port 306 through different pins.
  • the low power detection component 302 detects the power supply port 306. If the power supply port 306 is not connected to the active PD, the power supply port 306 is kept connected to the low power consumption detecting component 302, and the power supply port 306 is disconnected from the PSE chip 301. The PSE chip 301 is disconnected from the power supply, and the low power detection component 302 continues to detect the power supply port.
  • the low power detection component 302 detects the power supply port 306.
  • the power supply port 306 is connected to the active PD, the power supply of the PSE chip 301 is turned on by the power switch, and the connection between the PSE chip 301 and the power supply port 306 is turned on, and the low power consumption is disconnected. The connection of the component 302 to the power port 306 is detected.
  • the low power detection component 302 is located inside the PSE chip 301, so that the integration degree of the PSE chip 301 is high, thereby avoiding external interference and improving the reliability of detecting whether the power supply port 306 is connected to an effective PD.
  • the power supply apparatus may further include a processor and a memory, and the processor, the memory, and the power supply interface 306 are connected to each other through a bus.
  • the processor can be one or more CPUs.
  • the processor or processor is a CPU
  • the CPU can be a single core CPU or a multi-core CPU.
  • the memory may be one or more of, but not limited to, a RAM, a ROM, an EPROM, a CD-ROM, a hard disk, and the like.
  • the memory is used to store program code.
  • FIG. 4 is a schematic flowchart of a power-saving method for powering over a power supply in the embodiment of the present invention, which is used in the power supply device shown in FIG.
  • the low power detection component detects the power supply port.
  • the power supply port is connected to the low power control component, the power supply port is disconnected from the PSE chip, the PSE chip is disconnected from the power supply, and the low power detection component detects whether the power supply port is connected to a valid PD, and can be performed at a low voltage. Detection.
  • two different detection voltages are output at the power supply port, and the interval between two different detection voltages is greater than or equal to 1V.
  • the impedance is then calculated based on the two different current values detected and the two different detection voltages. If the impedance is within the preset range, it is determined that the power port is connected to the valid PD, and S403 is performed; if the impedance is not within the preset range, it is determined that the power port is not connected to the valid PD, and S402 is performed.
  • the PSE chip does not need to be powered. Only the low-power detection component needs to be connected to the power port to detect whether a valid PD is connected.
  • control switch When detecting that the power port is connected to the valid PD, the control switch turns on the connection between the PSE chip and the power supply port, disconnects the low power detection component from the power supply port, and the power switch turns on the PSE chip and the power supply.
  • the PSE chip After detecting that the power port is connected to a valid PD, it indicates that the PSE chip needs to be powered. Then, the connection between the PSE chip and the power supply port needs to be connected, the connection between the low-power detection component and the power supply port is disconnected, and the power supply of the PSE chip is turned on. power supply.
  • the power supply of the PSE chip when it is detected that the power port is connected to the effective PD, the power supply of the PSE chip is turned on. In this way, the supply voltage is not always on, so power consumption can be reduced and resources can be wasted.
  • the PSE chip when the PSE chip is in an ON state with the power supply, and the PSE chip detects that the PD connected to the power supply port is in a non-power supply state, it means that the PD is not provided with power supply. Then disconnect the PSE chip and the power supply, disconnect the PSE chip and the power supply port, and turn on the low-power detection component and the power supply port, so that the low-power detection component detects the power supply port.
  • the PD connected to the power supply port is in a non-power supply state, which means that it is not necessary to supply power to the PD, and in order to reduce power loss, the power supply of the PSE chip can be disconnected.
  • the PSE chip in order to ensure the validity of the power supply port connecting the PD, the PSE chip detects the power supply port again, and when the detection result of the power supply port is valid, the normal power supply voltage is outputted at the power supply port.
  • the PSE chip directly outputs the normal supply voltage at the power supply port.
  • the operating voltage of the low power detecting component may be greater than or equal to 10V. This makes it easy to detect the power supply port.

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Abstract

一种供电设备和以太网供电的节能方法，所述供电设备包括：低功耗检测组件，用于在与所述供电端口接通的情况下，检测所述供电端口；在所述供电端口接入有效的受电设备PD时发送第一指令，所述第一指令用于指示所述控制开关接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，指示所述电源开关接通所述PSE芯片与供电电源；控制开关，用于根据所述第一指令，接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口；电源开关，用于根据所述第一指令，接通所述PSE芯片的供电电源。采用本发明实施例后，能够减少电力的损耗，避免浪费资源。

Description

供电设备和以太网供电的节能方法 技术领域
本发明涉及通信领域，尤其涉及一种供电设备和以太网供电的节能方法。
背景技术
以太网供电(Power over Ethernet，PoE)包括供电设备(Power Sourcing Equipment，PSE)和受电设备(Power Device，PD)。PoE是一种有线以太网供电技术，PoE允许数据和电源耦合通过网线传递给受电设备，也可以把数据和电源分离通过网线传递给受电设备。
2003年电气和电子工程师协会(IEEE)发布了PoE标准IEEE 802.3af，PSE可给PD提供15.4W的功率；2009年大功率PoE标准IEEE 802.3at发布，PSE可给PD提供30W的功率；目前PoE标准仍然在演进，要覆盖到90W功率范围。
随着越来越多的PoE设备普及应用，PD对于电力的损耗也日益凸显。
发明内容
本申请提供了一种供电设备和以太网供电的方法，能够减少供电设备的电量的损耗，避免浪费资源。
第一方面，提供一种供电设备，所述供电设备包括供电端口，供电设备PSE芯片，低功耗检测组件、控制开关和电源开关；所述供电端口连接到所述控制开关，所述PSE芯片和所述低功耗控制组件分别连接所述控制开关，所述PSE芯片连接所述电源开关；
所述低功耗检测组件，用于在与所述供电端口接通的情况下，检测所述供电端口；在所述供电端口接入有效的PD时发送第一指令，所述第一指令用于指示所述控制开关接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，指示所述电源开关接通所述PSE芯片与供电电源；
所述控制开关，用于根据所述第一指令，接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口；
所述电源开关，用于根据所述第一指令，接通所述PSE芯片的供电电源。
在上述技术方案中，低功耗检测组件检测供电端口接入有效的PD时，接通PSE芯片与供电端口，断开低功耗检测组件与供电端口，指示电源开关接通PSE芯片与供电电源。这样，PSE芯片的供电电源并非始终处于接通状态，因此能够减少电力的损耗，避免浪费资源。
结合第一方面，在第一种可能的实现方式中，所述PSE芯片接通所述供电端口，且所述PSE芯片接通供电电源的情况下，所述PSE芯片用于在检测到所述供电端口为非供电状态时，向所述低功耗检测组件发送状态通知，所述状态通知用于指示所述低功耗控制组件发送第二指令，所述第二指令用于指示所述控制开关断开所述PSE芯片与所述供电端口，接通所述低功耗检测组件与所述供电端口，指示所述电源开关断开所述PSE芯片与供电电源；
所述控制开关，还用于根据所述第二指令，断开所述PSE芯片与所述供电端口，接通所述低功耗检测组件与所述供电端口；
所述电源开关，还用于根据所述第二指令，断开所述PSE芯片与供电电源。
在上述技术方案中，供电端口为非供电状态时，则说明无需向PSE芯片供电，为了减少 电力的损耗，则可以断开PSE芯片与供电电源。
结合第一方面，在上述可能的实现方式中，在所述PSE芯片接通所述供电端口，且所述PSE芯片接通供电电源的情况下，所述PSE芯片具体用于检测所述供电端口，在所述供电端口的检测结果为有效时，输出正常供电电压。
在上述技术方案中，为了减少电力的损耗，只有在供电端口的检测结果为有效时，再输出正常供电电压。
结合第一方面，在上述可能的实现方式中，所述PSE芯片接通所述供电端口，且所述PSE芯片接通供电电源的情况下，所述PSE芯片具体用于直接在所述供电端口输出正常供电电压。
在上述技术方案中，为了及时为PD供电，PSE芯片可以直接在供电端口输出正常供电电压。
结合第一方面，在上述可能的实现方式中，所述低功耗检测组件的工作电压大于等于10伏。
在上述技术方案中，为了能够检测供电端口接入有效的PD，低功耗检测组件的工作电压需要大于等于10伏。
结合第一方面，在上述可能的实现方式中，所述低功耗检测组件在供电设备PSE芯片中。
在上述技术方案中，低功耗检测组件在PSE芯片中，这样PSE芯片的集成度较高，从而避免外部的干扰。
第二方面，提供一种以太网供电的方法，应用于包括供电端口、低功耗检测组件和供电设备PSE芯片的供电设备中，所述方法包括：
所述低功耗检测组件检测供电端口是否接入有效的受电设备PD，其中，所述供电端口与所述低功耗控制组件接通，所述供电端口与所述PSE芯片断开，所述PSE芯片与供电电源断开；
当检测到所述供电端口接入有效的PD时，接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，并接通所述PSE芯片与供电电源。
本申请提供的以太网供电方法，PSE芯片与供电电源断开，由工作在低电压的低功耗组件检测供电端口是否接入有效的PD，并在检测到供电端口接入有效的PD之后，再接通PSE芯片与供电电源，这样可以避免供电设备接入有效的PD之前，供电电源也持续输出电力，从而可以减少供电设备的电力消耗。
结合第二方面，在第一种可能的实现方式中，所述方法还包括：
当所述供电端口未接入有效的PD时，保持所述供电端口与所述低功耗控制组件接通，所述供电端口与所述PSE芯片断开，所述PSE芯片与供电电源断开，所述低功耗检测组件继续检测供电端口。
结合第二方面，在以上可能的实现方式中，在接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，并接通所述PSE芯片与供电电源之后，所述方法还包括：
若所述PSE芯片检测到所述供电端口连接的PD为非供电状态，断开所述PSE芯片与供电电源，断开所述PSE芯片与所述供电端口，接通所述低功耗检测组件与所述供电端口，以便所述低功耗检测组件检测所述供电端口。
结合第二方面，在上述可能的实现方式中，在接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，并接通所述PSE芯片与供电电源之后，所述方法还包 括：
所述PSE芯片检测所述供电端口，在所述供电端口的检测结果为有效时，输出正常供电电压；
或，
所述PSE芯片直接在所述供电端口输出所述正常供电电压。
第三方面提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第二方面所述的方法。
第四方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
第五方面提供了一种供电系统，包括受电设备和上述第一方面所述的供电设备。
附图说明
图1是本发明实施例中供电设备的结构示意图；
图2是本发明另一个实施例中供电设备的结构示意图；
图3是本发明再一个实施例中供电设备的结构示意图；
图4是本发明实施例中以太网供电的节能方法流程示意图。
具体实施方式
在本发明实施例中，在检测到供电端口接入有效的PD时，则接通PSE芯片与供电端口的连接，断开低功耗检测组件与供电端口的连接，以及接通PSE芯片的电源。由于PSE芯片的电源并非始终处于接通状态，在满足一定条件时PSE芯片的电源才可以接通，因此能够减少电力的损耗，避免浪费资源。
PSE具体包括供电电源、PSE芯片和供电端口。供电电源向PSE芯片提供电压，通过PSE芯片内部的开关控制PSE芯片的电压，PSE芯片通过供电端口进行持续的PD检测。检测到有效的PD后，PSE芯片向供电端口输出电压，为PD提供电力。
其中，供电电源向PSE芯片提供的电压是标准规定的工作电压即正常供电电压，例如48伏(V)。PSE芯片内部的开关具体可以是金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。
即使在供电端口处于空闲状态即未接入有效的PD，供电电源也会为供电端口一直提供48V电压。在供电端口处于空闲状态，依然提供48V电压，显然存在电力的不必要损耗，浪费资源。
参见图1是本发明实施例中供电设备的结构示意图，供电设备具体包括供电端口101、PSE芯片102、低功耗检测组件103、控制开关104和电源开关105。供电端口101连接到控制开关104；PSE芯片102和低功耗检测组件103分别连接控制开关104；PSE芯片102连接电源开关105。PSE芯片102按照标准中定义的方式执行相关的功能。
低功耗检测组件103用于在与供电端口101接通的情况下，检测供电端口101是否接入有效的PD。低功耗检测组件103在工作电压为低电压下进行检测。
低功耗组件工作的低电压，以及向供电端口输出的供电电压，相互独立，但是都来自所述供电设备的电源管理系统。电源管理系统按照供电设备内各个器件的需求，输出电压。本发明实施例中，将供电设备的电源管理系统中为供电端口提供电力的部分称为供电电源。
检测供电端口的过程具体如下，在供电端口101输出两个不同的检测电压，两个不同的电压的间隔大于等于1V。然后再根据侦测到的两个不同电流值和上述两个不同检测电压计算阻抗。若阻抗在预设范围内，则确定供电端口101接入有效的PD；若阻抗不在预设范围内，则确定供电端口101未接入有效的PD。
在所有供电端口空闲即未接入有效的PD时，保持供电端口101与低功耗检测组件103接通，供电端口101与PSE芯片102断开，PSE芯片102与供电电源断开，低功耗检测组件103继续检测供电端口101。
低功耗检测组件103在检测到供电端口101接入有效的PD时，发送第一指令，该第一指令用于接通PSE芯片102的供电电源，接通PSE芯片102与供电端口101的连接，断开低功耗检测组件103与供电端口101的连接。
具体来说，控制开关104，用于根据上述第一指令，接通PSE芯片102与供电端口101的连接，断开低功耗检测组件103与供电端口101的连接。
具体来说，电源开关105，用于根据上述第一指令，接通PSE芯片102的供电电源。
低功耗检测组件103可以在工作电压为低电压下检测供电端口101。
本发明实施例中，利用低功耗检测组件103检测供电端口101接入有效的PD，则接通PSE芯片102的供电电源。这样，PSE芯片102的供电电压并非始终处于接通状态，因此能够减少电力的损耗，避免浪费资源。
在本发明一个可选的实施例中，在PSE芯片102接通供电端口101，且PSE芯片102接通供电电源的情况下，PSE芯片在检测到供电端口101为非供电状态时，向低功耗检测组件103发送状态通知。状态通知用于指示低功耗检测组件发送第二指令，第二指令是用于指示控制开关104断开PSE芯片102与供电端口101，接通低功耗检测组件103与供电端口101，指示电源开关105断开PSE芯片102与供电电源。
控制开关104用于根据上述第二指令，断开PSE芯片102与供电端口101的连接，接通低功耗检测组件103与供电端口101的连接。
电源开关105，用于根据上述第二指令，断开PSE芯片102与供电电源。
在上述技术方案中，接入供电端口101的PD处于非供电状态，则说明无需向该PD提供供电电源，为了减少电力的损耗，则可以断开供电电源。
在本发明一个可选的实施例中，在PSE芯片102接通供电端口101，且PSE芯片102接通供电电源的情况下，PSE芯片102可以检测供电端口，在供电端口101的检测结果为有效时，输出正常供电电压。
PSE芯片102向供电端口101输出低电压(检测电压、分级电压、上电电压等)或正常供电电压。供电端口101在PSE芯片102未检测到有效的PD时，输出低电压；在PSE芯片102检测到有效的PD时输出正常供电电压。
其中，检测供电端口101：PSE芯片102会发送一个检测电压给PD以探测PD中的共模电阻。
可选的，当检测到PD之后，PSE芯片102可以对PD进行物理层分级。具体地，PSE芯片102可以向PD施加15～20V电压，并通过测试电流大小来确定PD的级别。
若执行分级，则分级完成后，或没有执行分级，则检测到有效的PD之后，在一个可配置时间的启动期，PSE设备开始从低电压向PD供电。
在上述技术方案中，为了确保供电端口101连接PD的有效性，PSE芯片102可以再次检测供电端口101后，检测结果为有效时，则给电即输出正常供电电压。
在本发明一个可选的实施例中，为了迅速给PD供电，在PSE芯片102接通供电端口101，且PSE芯片102接通供电电源的情况下，PSE芯片102，在接通电源后，无需再次检测供电端口101，就可以直接在供电端口101输出正常供电电压。
在本发明一个可选的实施例中，低功耗检测组件103的工作电压大于等于10V。这样便于检测供电端口101。
在本发明一个可选的实施例中，低功耗检测组件103可以在PSE芯片102中。
参见图2是本发明另一个实施例中供电设备的结构示意图。供电电源204通过电源开关205向PSE芯片201供电。PSE芯片201、低功耗检测组件202分别与控制开关203连接。
具体来说，低功耗检测组件202检测供电端口206是否接入了有效的PD，若供电端口206未接入有效的PD，则保持供电端口206与低功耗检测组件202接通，供电端口206与PSE芯片201断开，PSE芯片201与供电电源断开，低功耗检测组件202继续检测供电端口。若供电端口206接入有效的PD，则通过电源开关205接通PSE芯片201的供电电源，接通PSE芯片201与供电端口206的连接，断开低功耗检测组件202与供电端口206的连接。
低功耗检测组件202位于PSE芯片201外，控制开关203和电源开关205也位于PSE芯片201外，也就是说PSE芯片的结构没有变化。在PSE芯片的外部增加低功耗检测组件202、控制开关203和电源开关205以控制供电端口206的输出电压。因此可以在PSE芯片的基础上，实现对供电端口206输出电压的控制，无需改动PSE芯片。
此外，供电设备还可以包括处理器和存储器，处理器、存储器和供电接口206可以通过总线相互连接。
处理器可以是一个或多个中央处理器(Central Processing Unit，CPU)。在处理器或处理器是一个CPU的情况下，该CPU可以是单核CPU，也可以是多核CPU。
存储器可以是但不限于随机存储存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM)、光盘只读存储器(CD-ROM)、硬盘等中的一种或多种。存储器还可用于存储程序代码。
在本发明一个可选的实施例中，低功耗检测组件可以在PSE芯片内。参见图3是本发明再一个实施例中供电设备的结构示意图。
供电电源304通过电源开关305连接PSE芯片301。PSE芯片301、低功耗检测组件302分别与控制开关303连接供电端口306。
低功耗检测组件302位于PSE芯片301内部，低功耗检测组件302和PSE芯片301通过不同的引脚分别与供电端口306连接。
具体来说，低功耗检测组件302检测供电端口306，供电端口306未接入有效的PD，则保持供电端口306与低功耗检测组件302接通，供电端口306与PSE芯片301断开，PSE芯片301与供电电源断开，低功耗检测组件302继续检测供电端口。
低功耗检测组件302检测供电端口306，供电端口306接入有效的PD，则通过电源开关接通PSE芯片301的供电电源，接通PSE芯片301与供电端口306的连接，断开低功耗检测组件302与供电端口306的连接。
低功耗检测组件302位于PSE芯片301内部，这样PSE芯片301的集成度较高，从而避免外部的干扰，提高检测供电端口306是否接入有效的PD的可靠性。
此外，供电设备还可以包括处理器和存储器，处理器、存储器和供电接口306通过总线相互连接。
处理器可以是一个或多个CPU。在处理器或处理器是一个CPU的情况下，该CPU可以 是单核CPU，也可以是多核CPU。
存储器可以是但不限于RAM、ROM，EPROM、CD-ROM、硬盘等中的一种或多种。存储器用于存储程序代码。
参见图4，图4是本发明实施例中以太网供电的节能方法流程示意图，用于如图1所示的供电设备中，具体包括以下步骤：
S401、低功耗检测组件检测供电端口。
首先，供电端口与低功耗控制组件接通，供电端口与PSE芯片断开，PSE芯片与供电电源断开，低功耗检测组件检测供电端口是否接入有效的PD，可以在低电压下进行检测。
具体来说，在供电端口输出两个不同的检测电压，两个不同的检测电压的间隔大于等于1V。然后再根据侦测到的两个不同电流值和上述两个不同检测电压计算阻抗。若阻抗在预设范围内，则确定供电端口接入有效的PD，执行S403；若阻抗不在预设范围内，则确定供电端口未接入有效的PD，执行S402。
S402、在所有供电端口未接入有效的PD时，保持供电端口与低功耗检测组件接通，供电端口与PSE芯片断开，PSE芯片与供电电源断开，低功耗检测组件继续检测供电端口。
所有供电端口未接入有效的PD，则说明无需为PSE芯片供电，仅需要低功耗检测组件与供电端口保持连接，以检测是否接入有效的PD。
S403、在检测到供电端口接入有效的PD时，控制开关接通PSE芯片与供电端口的连接，断开低功耗检测组件与供电端口的连接，电源开关接通PSE芯片与供电电源。
在检测到供电端口接入有效的PD，则说明需要为PSE芯片供电，那么需要接通PSE芯片与供电端口的连接，断开低功耗检测组件与供电端口的连接，接通PSE芯片的供电电源。
本发明实施例中，在检测到供电端口接入有效的PD，则接通PSE芯片的供电电源。这样，供电电压并非始终处于接通状态，因此能够减少电力的损耗，避免浪费资源。
在本发明一个可选的实施例中，PSE芯片在与供电电源处于接通状态，PSE芯片检测到供电端口连接的PD为非供电状态，则说明无需为该PD提供供电电源。则断开PSE芯片与供电电源，断开PSE芯片与供电端口，接通低功耗检测组件与供电端口，以便低功耗检测组件检测供电端口。
在上述技术方案中，接入供电端口的PD处于非供电状态，则说明无需向该PD供电，为了减少电力的损耗，则可以断开PSE芯片的供电电源。
在本发明一个可选的实施例中，为了确保供电端口连接PD的有效性，PSE芯片再次检测供电端口，在供电端口的检测结果为有效时，在供电端口输出正常供电电压。
或，为了迅速为PD供电，PSE芯片直接在供电端口输出正常供电电压。
在本发明一个可选的实施例中，低功耗检测组件的工作电压可以大于等于10V。这样便于检测供电端口。
本说明书的各个部分均采用递进的方式进行描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点介绍的都是与其他实施例不同之处。尤其，对于方法实施例而言，由于其基本相似于装置实施例，所以描述的比较简单，相关之处参见装置实施例部分的说明即可。

Claims (11)

  1. 一种供电设备，其特征在于，所述供电设备包括供电端口，供电设备PSE芯片，低功耗检测组件、控制开关和电源开关；所述供电端口连接到所述控制开关，所述PSE芯片和所述低功耗控制分别连接所述控制开关，所述PSE芯片连接所述电源开关；
    所述低功耗检测组件，用于在与所述供电端口接通的情况下，检测所述供电端口；在所述供电端口接入有效的受电设备PD时发送第一指令，所述第一指令用于指示所述控制开关接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，指示所述电源开关接通所述PSE芯片与供电电源；
    所述控制开关，用于根据所述第一指令，接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口；
    所述电源开关，用于根据所述第一指令，接通所述PSE芯片的供电电源。
  2. 根据权利要求1所述供电设备，其特征在于，在所述PSE芯片接通所述供电端口，且所述PSE芯片接通供电电源的情况下，所述PSE芯片用于在检测到所述供电端口为非供电状态时，向所述低功耗检测组件发送状态通知，所述状态通知用于指示所述低功耗检测组件发送第二指令，所述第二指令用于指示所述控制开关断开所述PSE芯片与所述供电端口，接通所述低功耗检测组件与所述供电端口，指示所述电源开关断开所述PSE芯片与供电电源；
    所述控制开关，还用于根据所述第二指令，断开所述PSE芯片与所述供电端口，接通所述低功耗检测组件与所述供电端口；
    所述电源开关，还用于根据所述第二指令，断开所述PSE芯片与供电电源。
  3. 根据权利要求1或2所述供电设备，其特征在于，在所述PSE芯片接通所述供电端口，且所述PSE芯片接通供电电源的情况下，所述PSE芯片具体用于检测所述供电端口，在所述供电端口的检测结果为有效时，输出正常供电电压。
  4. 根据权利要求1或2所述供电设备，其特征在于，在所述PSE芯片接通所述供电端口，且所述PSE芯片接通供电电源的情况下，所述PSE芯片具体用于直接在所述供电端口输出正常供电电压。
  5. 根据权利要求1-4任一所述供电设备，其特征在于，所述低功耗检测组件的工作电压大于等于10伏。
  6. 根据权利要求1-5任一所述供电设备，其特征在于，所述低功耗检测组件在所述PSE芯片中。
  7. 一种以太网供电的节能方法，其特征在于，应用于包括供电端口、低功耗检测组件和供电设备PSE芯片的供电设备中，所述方法包括：
    所述低功耗检测组件检测供电端口是否接入有效的受电设备PD，其中，所述供电端口与所述低功耗控制组件接通，所述供电端口与所述PSE芯片断开，所述PSE芯片与供电电源断开；
    当检测到所述供电端口接入有效的PD时，接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，并接通所述PSE芯片与供电电源。
  8. 根据权利要求7所述以太网供电的节能方法，其特征在于，还包括：
    当所述供电端口未接入有效的PD时，保持所述供电端口与所述低功耗检测组件接通，所述供电端口与所述PSE芯片断开，所述PSE芯片与供电电源断开，所述低功耗检测组件继续检测供电端口。
  9. 根据权利要求7或8所述以太网供电的节能方法，其特征在于，在接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，并接通所述PSE芯片与供电电源之后，所述方法还包括：
    若所述PSE芯片检测到所述供电端口连接的PD为非供电状态，断开所述PSE芯片与供电电源，断开所述PSE芯片与所述供电端口，接通所述低功耗检测组件与所述供电端口，以便所述低功耗检测组件检测所述供电端口。
  10. 根据权利要求7或8所述以太网供电的节能方法，其特征在于，在接通所述PSE芯片与所述供电端口，断开所述低功耗检测组件与所述供电端口，并接通所述PSE芯片与供电电源之后，所述方法还包括：
    所述PSE芯片检测所述供电端口，在所述供电端口的检测结果为有效时，输出正常供电电压；
    或，
    所述PSE芯片直接在所述供电端口输出所述正常供电电压。
  11. 一种供电系统，其特征在于，包括：受电设备和如权利要求1-6任一项所述的供电设备；
    所述受电设备连接所述供电设备的供电端口。
PCT/CN2018/076740 2017-08-28 2018-02-13 供电设备和以太网供电的节能方法 WO2019041763A1 (zh)

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