WO2019022825A2 - Génération d'histogrammes de tension - Google Patents

Génération d'histogrammes de tension Download PDF

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Publication number
WO2019022825A2
WO2019022825A2 PCT/US2018/033975 US2018033975W WO2019022825A2 WO 2019022825 A2 WO2019022825 A2 WO 2019022825A2 US 2018033975 W US2018033975 W US 2018033975W WO 2019022825 A2 WO2019022825 A2 WO 2019022825A2
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WIPO (PCT)
Prior art keywords
signal
delay
voltage
stage
integrated circuit
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PCT/US2018/033975
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English (en)
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WO2019022825A3 (fr
Inventor
Ryan Michael Coutts
Shahin Solki
Paul Ivan Penzes
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Qualcomm Incorporated
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Priority to CN201880049595.6A priority Critical patent/CN110945788A/zh
Publication of WO2019022825A2 publication Critical patent/WO2019022825A2/fr
Publication of WO2019022825A3 publication Critical patent/WO2019022825A3/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

Definitions

  • This disclosure relates generally to voltage levels in integrated circuits that are used in electronic devices and, more specifically, to enabling an integrated circuit (IC) to generate an on-chip voltage histogram indicative of different voltage levels that are present on the integrated circuit over time.
  • IC integrated circuit
  • Integrated circuit chips function as the brains behind most modern electronic devices. Such chips are present in everything from smart phones to laptops, vehicles to home appliances, and tools to industrial equipment. Integrated circuits are therefore responsible for enabling communication, navigation, entertainment, manufacturing, and other capabilities. These capabilities are provided by processing signals within the integrated circuits.
  • the signals are typically created using voltage levels or current levels that are produced by an integrated circuit. To ensure that the signal processing is performed properly, the integrated circuit maintains the voltage and current levels within some prescribed range. This can be difficult, however, due to the variabilities that arise during manufacturing and the changing environmental factors that occur during operation.
  • process encompasses how an integrated circuit is expected to perform based on how circuit components, such as transistors, were constructed on a semiconductor wafer.
  • circuit components such as transistors
  • operational environment an example of a changing environmental factor is temperature.
  • individual integrated circuit chips perform differently based on, for example, process, temperature, and voltage.
  • designers want to ensure that an integrated circuit will work correctly in accordance with published specifications. This consistent performance is expected to be maintained regardless of an integrated circuit's process parameters, current voltage level, or actual temperature.
  • margining implies that extra flexibility, or headroom, is designed into the operation of an integrated circuit such that proper functioning is likely even if a variable deviates from an ideal value, or even slightly from a preferred range of values.
  • digital logic is typically partitioned into timing and voltage budgets that are assigned margins separately. With conventional design approaches, these two budgets are over-margined and determined independently of each other.
  • Voltage margining is typically instituted based on a potential worst-case voltage level scenario, but this approach forfeits some available performance headroom.
  • voltage margining can be instituted based on an average voltage level.
  • a ring oscillator with a terminal counter can be used. An oscillating signal propagates around the ring oscillator. The speed of propagation of the oscillating signal through the ring oscillator is voltage dependent. The terminal counter increments each time the oscillating signal propagates completely through the ring. Thus, the higher the count held by the terminal counter after some period of time, the higher the average voltage level that existed while the oscillating signal propagated around the ring oscillator.
  • a ring oscillator can therefore be used to determine an average voltage level over time.
  • An integrated circuit that can generate a voltage histogram.
  • the integrated circuit includes control circuitry, multiple delay stages, and multiple counters.
  • the control circuitry is configured to control propagation of a first signal on a first signaling path and a second signal on a second signaling path.
  • the multiple delay stages are coupled in series and include a first signaling path, a second signaling path, and multiple time-of-arrival detection circuits.
  • the first signaling path is configured to propagate the first signal at a first propagation speed, with the first propagation speed being voltage-dependent.
  • the second signaling path is configured to propagate the second signal at a second propagation speed, with the second propagation speed being voltage-dependent.
  • Each respective delay stage of the multiple delay stages includes a respective time-of-arrival detection circuit of the multiple time-of-arrival detection circuits.
  • Each respective time-of-arrival detection circuit is configured to generate a respective stage timing signal indicative of a relative arrival time between the first signal and the second signal at the respective delay stage.
  • the multiple counters are respectively coupled to the multiple delay stages. Each respective counter has a respective counter value and is configured to increment the respective counter value responsive to the respective stage timing signal.
  • an integrated circuit includes multiple delay stages, multiple counters, and control circuitry.
  • the multiple delay stages are coupled in series in a chained arrangement.
  • Each respective delay stage includes means for propagating a first signal at a first propagation speed that is voltage-dependent and means for propagating a second signal at a second propagation speed that is voltage-dependent. The second propagation speed is relatively faster than the first propagation speed.
  • Each respective delay stage also includes means for generating a respective stage timing signal indicative of a relative arrival time between the first signal and the second signal at the respective delay stage.
  • the multiple counters are respectively coupled to the multiple delay stages. Each respective counter has a respective counter value and is configured to increment the respective counter value responsive to the respective stage timing signal.
  • the control circuitry is configured to initiate a first propagation of the first signal and a second propagation of the second signal.
  • a method for generating a voltage histogram includes propagating a first signal along a first signaling path at a first propagation speed that is based on a current voltage level.
  • the method also includes propagating a second signal along a second signaling path at a second propagation speed that is based on the current voltage level, with the second propagation speed being faster than the first propagation speed.
  • the method additionally includes detecting a relative arrival time between the first signal and the second signal at each delay stage of multiple delay stages.
  • the method further includes tracking occurrences of multiple voltage levels over time based on the detecting to generate the voltage histogram.
  • an integrated circuit includes a voltage histogram circuit.
  • the voltage histogram circuit includes multiple delay stages and multiple counters.
  • a delay stage of the multiple delay stages includes a first buffer configured to transit a first signal with a first delay time and a second buffer configured to transit a second signal with a second delay time.
  • the delay stage also includes a time-of-arrival detection circuit coupled to the first buffer and the second buffer.
  • the time-of-arrival detection circuit is configured to determine a relative time of arrival between the first signal and the second signal at the delay stage.
  • the time of-arrival detection circuit is also configured to generate a stage timing signal based on the relative time of arrival.
  • the multiple counters are respectively coupled to the multiple delay stages. Each respective counter of the multiple counters has a respective counter value of multiple counter values.
  • a counter that corresponds to the delay stage is configured to increment a counter value thereof responsive to the stage timing signal.
  • FIG. 1 illustrates an example histogram graph and corresponding counter value hardware to capture a number of occurrences per voltage level.
  • FIG. 2 illustrates an example voltage histogram circuit having multiple delay stages and multiple counters for generating voltage histograms.
  • FIG. 3 illustrates example first and second signaling paths established by the multiple delay stages for propagating first and second signals along the voltage histogram circuit.
  • FIG. 4 illustrates example first and second buffers for the first and second signaling paths at each delay stage, in conjunction with associated control circuitry for the multiple delay stages.
  • FIG. 5 illustrates an example implementation of a delay stage of the multiple delay stages for the voltage histogram circuit.
  • FIG. 6 illustrates an example implementation of the control circuitry of FIG. 4 for the voltage histogram circuit.
  • FIG. 7 illustrates another example implementation of a delay stage of the multiple delay stages, with the first and second buffers having different threshold voltages.
  • FIG. 8 depicts multiple graphs illustrating example scenarios for semiconductor devices with different threshold voltages.
  • FIG. 9 illustrates an example voltage histogram circuit that includes multiple gates respectively coupled between multiple delay stages and multiple counters.
  • FIG. 10 illustrates an example voltage histogram circuit that includes circuitry for implementing a programmable frequency for repeating voltage determination cycles.
  • FIG. 11 is a flow diagram illustrating an example process for generating a voltage histogram.
  • FIG. 12 illustrates an example electronic device including an integrated circuit that can implement a voltage histogram circuit.
  • a single voltage-level value fails to provide a range of likely voltage levels for an integrated circuit. Further, even if a worst-case voltage level is determined, conventional approaches fail to provide insight about how often this worst-case voltage level might occur. Similarly, an average voltage level does not provide information about how frequently any particular voltage level occurs. Without frequency or other probabilistic information, more sophisticated statistical-based techniques for voltage margining cannot be employed. Consequently, integrated circuit chips that have been margined using conventional approaches are underused. First, in some cases, a portion of the processing performance that is actually attainable by a given integrated circuit is forfeited by requiring the chips to stay within a margin that was established based on a single voltage-level value. Second, in other cases, chips that can safely provide a satisfactory level of performance are excluded from deployment because of margining that was based on a single voltage-level value.
  • margining can be performed using statistical-based techniques by implementing the circuits and processes described herein. For example, using a described voltage histogram circuit, frequency or probabilistic data for multiple voltage levels can be obtained.
  • a voltage histogram can include frequency counts of each voltage level that a circuit experiences across a range of multiple voltage levels. Such a voltage histogram is therefore indicative of a probability distribution that is representative of a likelihood that a particular voltage level will occur at any give time.
  • an on-die voltage histogram sensor generates a voltage histogram. The voltage histogram sensor provides respective frequency count values of different respective voltage levels that are experienced by an integrated circuit over some time period.
  • the frequency at which some voltage level occurs, and the probability of that voltage level recurring, can therefore be computed from the voltage histogram.
  • the probabilistic nature of voltage and signal timing can be jointly addressed to enable the adoption of flexible, statistical approaches to the margining of individual chips. Consequently, a greater percentage of integrated circuit chips can be deployed, and those chips that are deployed can be pushed to higher performance levels based on the probabilistic voltage information.
  • a voltage histogram circuit having multiple delay stages that realize a ring signaling topology is used to generate a voltage histogram.
  • the multiple delay stages are coupled in series into a chained arrangement of delay stages.
  • Each delay stage of the multiple delay stages corresponds to a particular voltage level of multiple voltage levels.
  • the delay stages establish two signaling paths— a first signaling path with a relatively slower propagation speed and a second singling path with a relatively faster propagation speed.
  • a ring signal is separated into two parts: a first signal and a second signal.
  • the first signal propagates over the relatively slower first signaling path, and the second signal propagates over the relatively faster second signaling path.
  • the two signals travel along the two signaling paths at two different speeds, with these two different speeds being dependent on a current voltage level.
  • the second signal that is to travel on the faster second signaling path is delayed at the start of the chained arrangement of delay stages for some delay period, which may have a programmable length.
  • the first and second signals then race along their respective slower and faster signaling paths.
  • the multiple delay stages detect relative arrival times of the first and second signals at each delay stage to make a voltage determination during each looping of the signals around the ring signaling topology.
  • each voltage determination cycle a particular delay stage is detected at which the delayed, but faster, second signal catches the slower first signal.
  • the voltage level corresponding to that particular delay stage is determined as the voltage level under which the voltage histogram circuit is currently operating.
  • Each delay stage of the multiple delay stages is also respectively associated with a counter of multiple counters. Accordingly, the counter that is associated with the particular delay stage increases a counter value thereof.
  • Voltage determination cycles are repeated a number of times as the first and second signals are looped back to the start of the chained arrangement of delay stages.
  • Each counter and the counter value thereof along the chain of delay stages respectively corresponds to a relative voltage level.
  • the counter values therefore represent a number of occurrences for different voltage levels over time, and the voltage histogram circuit effectively functions as a voltage histogram sensor.
  • Principles of a voltage histogram are described below with reference to FIG. 1.
  • Example implementations of a voltage histogram circuit are then described with reference to FIGS. 2-4.
  • each delay stage includes a first buffer and a second buffer.
  • the first buffer is disposed along the slower, first signaling path
  • the second buffer is disposed along the faster, second signaling path.
  • the first buffer institutes a first delay time that is relatively longer than a second delay time that is instituted by the second buffer.
  • These first and second delay times vary based on a current voltage level.
  • the first buffer and the second buffer can be built from semiconductor devices that respond more slowly or more quickly, respectively, under a given voltage level.
  • buffers with different threshold voltages can be used to realize the first and second buffers.
  • Example implementations for the delay stages, the voltage-sensitive buffers, and related control circuitry are described with reference to FIGS. 5-8.
  • gating circuitry is employed to ensure that a counter value is incremented where the second signal initially overtakes the first signal while previous and subsequent counter values remain unchanged during any single voltage determination cycle.
  • Example implementations of a voltage histogram circuit with gating circuitry are described below with reference to FIG. 9.
  • a frequency of voltage determination cycles can be adjusted by changing a length of the portion of the chained arrangement of delay stages that is employed for a given cycle. To do so, the first signal and the second signal are looped back to a first delay stage from a selected one of multiple tap nodes that are placed at different locations along the chained arrangement, e.g., using a selectable multiplexer.
  • Example implementations of a voltage histogram circuit with a programmable frequency are described with reference to FIG. 10.
  • FIG. 1 illustrates generally at 100 an example histogram graph 102 and corresponding counter value hardware to capture a number of occurrences 112 per voltage level 104.
  • the example histogram graph 102 includes a voltage level axis 108, which is the horizontal or abscissa axis, and a frequency axis 110, which is the vertical or ordinate axis.
  • the frequency axis 110 represents different numbers of occurrences per voltage level 104, which are represented along the voltage level axis 108.
  • the example frequency axis 110 extends from zero (0) to forty (40) occurrences, but other ranges may be applicable in a given situation.
  • the voltage level axis 108 represents different voltage levels, with each voltage level 104 corresponding to a particular number of occurrences 112.
  • the example voltage level axis 108 extends across multiple voltage levels 104-1, 104-2, 104-3 ... 104-n, with "n" representing some positive integer.
  • Each respective voltage level 104- 1 , 104-2, 104-3 ... 104-n corresponds to a respective number of occurrences 112-1, 112-2, 112-3 ... 1 12-n.
  • a first voltage level 104-1 corresponds to a first number of occurrences 112-1, which is ten (10) occurrences in this example.
  • a second voltage level 104-2 corresponds to a second number of occurrences 112-2, which is shown to total twenty (20) occurrences.
  • a third voltage level 104-3 corresponds to a third number of occurrences 112-3, which equals thirty-five (35) occurrences here.
  • An "nth" voltage level 104-n corresponds to an "nth" number of occurrences 1 12-n, which has eight (8) occurrences.
  • the histogram graph 102 represents a frequency at which different voltage levels occur over time.
  • a voltage histogram incorporates data that provides a probability distribution of a likelihood that a particular voltage level 104 will occur at any given time. For example, the probability that the third voltage level 104-3 is to occur is determinable by dividing 35 by the total number of observed occurrences across the multiple voltage levels 104-1 ... 104-n.
  • counter value hardware can store the multiple numbers of occurrences 112-1 ... 112-n to realize in circuitry the frequency data or probabilities provided by the histogram graph 102.
  • each number of occurrences 112 corresponds to an observed voltage level 104 of the multiple voltage levels 104-1 ... 104-n.
  • the counter value hardware can effectively implement a voltage histogram in circuitry.
  • each of the multiple numbers of occurrences 112-1, 112-2, 1 12-3 ... 112-n is respectively stored as one counter value 106 of multiple counter values 106-1, 106-2, 106-3 ... 106-n.
  • Each respective counter value 106 of the multiple counter values 106-1, 106-2, 106-3 ... 106-n corresponds to a respective voltage level 104 of the multiple voltage levels 104-1, 104-2, 104-3 ... 104-n that can be experienced by an integrated circuit over some range of time.
  • the multiple counter values 106-1, 106-2, 106-3 ... 106-n and the multiple voltage levels 104-1, 104-2, 104-3 ... 104-n are also shown in FIG. 2 to illustrate a voltage histogram circuit.
  • FIG. 2 illustrates an example voltage histogram circuit 200 having multiple delay stages 202-1, 202-2, 202-3 ... 202-n and multiple counters 206-1, 206-2, 206-3 ... 206-n for generating voltage histograms.
  • the multiple delay stages 202-1, 202-2, 202-3 ... 202-n are coupled in series with one another in a chained arrangement of delay stages.
  • an initial or first delay stage 202-1 is coupled to a second delay stage 202-2
  • the second delay stage 202-2 is coupled to a third delay stage 202-3.
  • the sequence of delay stages continues to a final or "nth" delay stage 202-n.
  • Each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n respectively corresponds to a voltage level 104 of the multiple voltage levels 104-1, 104-2, 104-3 ... 104-n.
  • the multiple delay stages 202-1, 202-2, 202-3 ... 202-n can form a ring.
  • the multiple delay stages 202-1, 202-2, 202-3 ... 202-n are configured such that a signal propagates through at least a portion of the delay stages and is then fed back into the series of delay stages, such as at the first delay stage 202-1.
  • a ring signal 208 propagates over the chained arrangement of the multiple delay stages 202-1, 202-2, 202-3 ... 202 -n in accordance with a ring topology. In an example operation, propagation of the ring signal 208 is initiated at the first delay stage 202-1.
  • Propagation continues through the second delay stage 202-2, the third delay stage 202-3, other intermediate delay stages (not shown), and the "nth" delay stage 202-n.
  • the ring signal 208 is then fed back to the first delay stage 202-1 to implement a circuit with a ring topology.
  • Each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n respectively corresponds to a counter 206 of the multiple counters 206-1, 206-2, 206-3 ... 206-n.
  • Each counter 206 of the multiple counters 206-1, 206-2, 206-3 ... 206-n includes, or is configured to produce, a respective counter value 106 of the multiple counter values 106-1, 106-2, 106-3 ... 106-n.
  • each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n respectively generates a stage timing signal 204 of multiple stage timing signals 204-1, 204-2, 204-3 ... 204-n.
  • Each respective delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n provides a respective stage timing signal 204 of the multiple stage timing signals 204-1, 204-2, 204-3 ... 204-n to a respective counter 206 of the multiple counters 206-1, 206-2, 206-3 ... 206-n.
  • the ring signal 208 propagates across the multiple delay stages 202-1, 202-2, 202-3 ... 202-n and is fed back to implement a ring topology.
  • a delay stage 202 is triggered based on a current voltage level 104 that the voltage histogram circuit 200 is experiencing. For example, if the current voltage level is the third voltage level 104-3, the third delay stage 202-3 is triggered. Responsive to such triggering, the third delay stage 202-3 asserts the third stage timing signal 204-3.
  • the third delay stage 202-3 also provides an asserted third stage timing signal 204-3 to the third counter 206-3.
  • the third counter 206-3 increments (e.g., by the third counter value 106-3.
  • a counter 206 increments the corresponding counter value 106 based on the current voltage level 104.
  • FIG. 3 illustrates another example implementation of the voltage histogram circuit 200.
  • the multiple delay stages 202-1, 202-2, 202-3 ... 202-n establish a first signaling path 302 and a second signaling path 304.
  • the first signaling path 302 provides a first propagation speed 306 that is voltage-dependent.
  • the second signaling path 304 provides a second propagation speed 308 that is voltage-dependent.
  • the voltage histogram circuit 200 also includes control circuitry 316, which is coupled to the chained arrangement of multiple delay stages 202-1 ... 202-n.
  • the ring signal 208 includes at least two portions: a first signal 312 and a second signal 314.
  • the portion of the ring signal 208 that extends from a last delay stage, such as the "nth" delay stage 202-n, to the control circuitry 316 is labeled as a loopback signal 310.
  • the loopback signal 310 represents a feedback portion of the ring signal 208.
  • the first signal 312 propagates along the first signaling path 302 at the first propagation speed 306, and the second signal 314 propagates along the second signaling path 304 at the second propagation speed 308.
  • the first propagation speed 306 and the second propagation speed 308 are both voltage-dependent.
  • the propagation speeds can depend on a voltage level 104 under which the voltage histogram circuit 200 is currently operating. Due to the propagation speed difference, the propagation of signals on one signaling path is faster than the propagation of signals on the other signaling path.
  • the first propagation speed 306 can be slower than the second propagation speed 308.
  • the second signal 314 propagates over the second signaling path 304 faster than the first signal 312 propagates over the first signaling path 302.
  • the control circuitry 316 launches the first signal 312 and the second signal 314 at different times.
  • the control circuitry 316 delays a second start to propagation of the second signal 314 along the second signaling path 304 relative to a first start to propagation of the first signal 312 along the first signaling path 302. Because the first signal 312 and the second signal 314 respectively propagate over the first signaling path 302 and the second signaling path 304 at different speeds, the two signals arrive at different delay stages at different relative times that also vary along the chained arrangement.
  • Each respective delay stage 202 asserts a respective stage timing signal 204 based on a relative arrival time between the first signal 312 and the second signal 314 at the respective delay stage 202. Further, because the second signal 314 propagates more quickly than the first signal 312, the second signal 314 eventually overtakes the first signal 312 along the chained arrangement of the multiple delay stages 202-1 ... 202-n.
  • the control circuitry 316 delays the launch of the faster signal, which is the second signal 314 here.
  • a first propagation of the first signal 312 along the first signaling path 302 at the first propagation speed 306 is therefore initiated first.
  • the control circuitry 316 initiates a second propagation of the second signal 314 along the second signaling path 304 at the second propagation speed 308.
  • the second propagation speed 308 is faster than the first propagation speed 306
  • the second signal 314 eventually catches the first signal 312 at some delay stage 202.
  • the third delay stage 202-3 asserts the corresponding third stage timing signal 204-3.
  • the third counter 206-3 increments the third counter value 106-3.
  • each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n respectively corresponds to a voltage level 104 of the multiple voltage levels 104-1, 104-2, 104-3 ... 104-n (as shown in FIG. 2).
  • a location along the chained arrangement of the multiple delay stages 202-1 ... 202-n at which the second signal 314 catches the first signal 312 corresponds to a relative voltage level 104 that differs from other instances of the multiple voltage levels 104-1, 104-2, 104-3 ... 104-n.
  • This relationship between different delay stages and different relative voltage levels is described further below.
  • the voltage histogram circuit 200 can take a voltage level measurement each voltage determination cycle, or each looping of the ring signal 208 through the chained arrangement of the multiple delay stages 202-1 ... 202-n.
  • FIG. 4 illustrates another example implementation of the voltage histogram circuit 200.
  • the first signaling path 302 includes multiple first buffers
  • the second signaling path 304 includes multiple second buffers.
  • a respective first buffer 402 and a respective second buffer 404 are included at each respective delay stage 202 along the chained arrangement of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n.
  • the control circuitry 316 includes an enablement circuit 406 and a signal delay circuit 408 to control the flow of the signals through the voltage histogram circuit 200.
  • Each first buffer 402 of the multiple delay stages 202-1 ... 202-n contributes to creating the first propagation speed 306 for the first signal 312 along the first signaling path 302.
  • each second buffer 404 of the multiple delay stages 202-1 ... 202-n contributes to creating the second propagation speed 308 for the second signal 314 along the second signaling path 304. Examples of the first buffer 402 and the second buffer 404 are described further herein with reference to FIGS. 5, 7, and 8, especially with regard to establishing a propagation speed that is voltage-dependent.
  • the control circuitry 316 includes the enablement circuit 406 and the signal delay circuit 408.
  • the enablement circuit 406 is coupled to the signal delay circuit 408.
  • the enablement circuit 406 receives an enable signal 410 and the loopback signal 310.
  • the enablement circuit 406 produces the first signal 312 and provides the first signal 312 to both the signal delay circuit 408 and the first signaling path 302.
  • the signal delay circuit 408 receives the first signal 312 from the enablement circuit 406 and produces the second signal 314.
  • the signal delay circuit 408 provides the second signal 314 to the second signaling path 304.
  • the control circuitry 316 initiates a looping of the ring signal 208 along the chained arrangement of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n based on the enable signal 410.
  • the enablement circuit 406 controls whether the ring signal 208 is looping and thus whether the voltage histogram circuit 200 is detecting different voltage levels as a voltage histogram sensor. For example, if the enable signal 410 is not asserted, the enablement circuit 406 prevents the ring signal 208 from propagating. On the other hand, responsive to an asserted enable signal 410, the enablement circuit 406 initiates a first propagation of the first signal 312 along the first signaling path 302 at the first buffer 402 of the first delay stage 202-1. Subsequently, the enablement circuit 406 sends another voltage change (e.g. , from high to low or from low to high) as part of the first signal 312 responsive to receiving the loopback signal 310.
  • another voltage change e.g. , from high to low or from low to high
  • the control circuitry 316 is generally configured to launch the first signal 312 and the second signal 314 along the first signaling path 302 and the second signaling path 304, respectively, at different times.
  • the signal delay circuit 408 provides functionality for delaying an initiation of a second propagation of the second signal 314 relative to an initiation of a first propagation of the first signal 312. To do so, the signal delay circuit 408 implements a delay period by providing, e.g., a variable delay period that is programmable. Responsive to receipt of the first signal 312, the signal delay circuit 408 starts a timer corresponding to the delay period.
  • the signal delay circuit 408 initiates a second propagation of the second signal 314 along the second signaling path 304 at the second buffer 404 of the first delay stage 202-1.
  • the delay period can be adjustable to account for different voltage level ranges of interest, current operating parameters, and so forth. Example components of the enablement circuit 406 and the signal delay circuit 408 are described with reference to FIG. 6.
  • FIG. 5 illustrates generally at 500 an example implementation of a delay stage 202 of the chained arrangement of the multiple delay stages 202-1 ... 202-n of FIG. 4.
  • the delay stage 202 includes a first buffer 402, a second buffer 404, and a time-of-arrival detection circuit 506.
  • the first buffer 402 receives the first signal 312, slows a traversal of the first signal 312 across the first buffer 402, and then outputs the first signal 312 for forwarding to a subsequent, consecutive delay stage (not shown in FIG. 5).
  • the first buffer 402 slows the traversal of the first signal 312 by causing a first delay time 502 to elapse while the first signal 312 traverses the first buffer 402.
  • the first buffer 402 forwards the first signal 312.
  • the second buffer 404 receives the second signal 314, slows a traversal of the second signal 314 across the second buffer 404, and then outputs the second signal 314 for forwarding to the same subsequent, consecutive delay stage (not shown in FIG. 5).
  • the second buffer 404 slows the traversal of the second signal 314 by causing a second delay time 504 to elapse while the second signal 314 traverses the second buffer 404.
  • the second buffer 404 forwards the second signal 314.
  • the second delay time 504 is shorter than the first delay time 502 so that the second signal 314 can propagate faster than the first signal 312.
  • the time-of-arrival detection circuit 506 is coupled to the first buffer 402 and the second buffer 404.
  • the first buffer 402 transits the first signal 312 with the first delay time 502 and then provides the first signal 312 to the time-of-arrival detection circuit 506.
  • the second buffer 404 transits the second signal 314 with the second delay time 504 and then provides the second signal 314 to the time-of-arrival detection circuit 506.
  • the time-of-arrival detection circuit 506 receives the first signal 312 from the first buffer 402 and the second signal 314 from the second buffer 404.
  • the time-of-arrival detection circuit 506 determines which signal arrived at the delay stage 202 first, if one signal arrived after another signal, if the second signal 314 arrived prior to the first signal 312, some combination thereof, and so forth.
  • the time-of-arrival detection circuit 506 produces the stage timing signal 204 based on a relative time-or-arrival detection.
  • the stage timing signal 204 is indicative of a relative arrival time between the first signal 312 and the second signal 314 at the delay stage 202.
  • the time-of-arrival detection circuit 506 can assert the stage timing signal 204 if the second signal 314 arrives at the delay stage 202 prior to the first signal 312.
  • Example implementations for the time-of-arrival detection circuit 506, as well as the two buffers, is described below with reference to FIG. 7.
  • time-of-arrival detection circuit 506 receives the first signal 312 and the second signal 314 after buffering within the delay stage 202, the time-of-arrival detection circuit 506 can alternatively receive one or more of the signals prior to the internal buffering by the first buffer 402 and the second buffer 404.
  • FIG. 6 illustrates an example implementation of the control circuitry 316 of the voltage histogram circuit 200 (e.g., of FIGS. 3 and 4).
  • the control circuitry 316 includes the enablement circuit 406 and the signal delay circuit 408.
  • the enablement circuit 406 receives the enable signal 410 and the loopback signal 310 and produces the first signal 312 based thereon.
  • the first signal 312 is provided to the first delay stage 202-1 and to the signal delay circuit 408.
  • the signal delay circuit 408 receives the first signal 312 in addition to a programmable delay length signal 606. Based on the first signal 312 and the programmable delay length signal 606, the signal delay circuit 408 outputs the second signal 314 after a delay period 612.
  • the signal delay circuit 408 provides the second signal 314 to the first delay stage 202-1.
  • signals are asserted with a logical one or a high voltage value.
  • the enablement circuit 406 can be realized using at least one NAND gate 602.
  • the NAND gate 602 drives the first signal 312 to have the opposite value as that of the loopback signal 310. Consequently, the first signal 312 flips values (e.g., from “0" to "1” or vice versa) after each propagation or loop through the series of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n (e.g., of FIGS. 3 and 4) for each voltage determination cycle.
  • the enablement circuit 406 supplies the first signal 312 to the signal delay circuit 408.
  • the signal delay circuit 408 includes a multiplexer 604 (Mux) and multiple delay lines 610-1, 610-2, 610-3, and 610-4.
  • the multiplexer 604 includes four inputs, one control input, and one output.
  • the first signal 312 is coupled to each of the multiple delay lines 610-1, 610-2, 610-3, and 610-4.
  • Each delay line 610 may include one or more delay buffers 608, only some of which are explicitly indicated with the reference number "608" for clarity.
  • a first delay line 610-1 includes no delay buffers.
  • a second delay line 610-2 includes three delay buffers 608.
  • a third delay line 610-3 includes six delay buffers 608.
  • a fourth delay line 610-4 includes nine delay buffers 608.
  • Each delay buffer 608 slows or delays propagation of the first signal 312 within the signal delay circuit 408 by one delay unit.
  • the second delay line 610-2 delays the first signal 312 by three delay units.
  • the third delay line 610-3 delays the first signal 312 for twice as long as the second delay line 610-2, and the fourth delay line 610-4 delays the first signal 312 for three times as long or nine delay units.
  • Each of the multiple delay lines 610-1, 610-2, 610-3, and 610-4 is coupled to one of the four inputs of the multiplexer 604.
  • the programmable delay length signal 606 is coupled to the control input of the multiplexer 604. With four separate delay lines 610-1, 610-2, 610-3, and 610-4, the programmable delay length signal 606 can be realized using, for instance, two bit lines.
  • the output of the multiplexer 604 provides the second signal 314.
  • a value of the programmable delay length signal 606 effectively selects a delay line 610 from among the multiple delay lines 610-1, 610-2, 610-3, and 610-4 using the multiplexer 604 to thereby determine the delay period 612 of the signal delay circuit 408.
  • the delay period 612 in this example can last for zero, three, six, or nine delay units by selecting from among zero, three, six, or nine delay buffers, respectively, that form part of the four illustrated delay lines.
  • the delay period 612 can be programmed to a length of time that enables the first signal 312 to propagate through most of the delay stages before being overtaken by the second signal 314 at a highest voltage level to increase a voltage level granularity.
  • the multiplexer 604 selects one of the four delay lines 610-1, 610-2, 610-3, and 610-4.
  • the multiplexer 604 therefore outputs the second signal 314 as a version of the first signal 312 that has been delayed by the selected delay period 612.
  • four delay lines 610-1, 610-2, 610-3, and 610-4 are shown in FIG. 6 and described above to realize different delay periods, more or fewer delay lines may alternatively be implemented as part of the signal delay circuit 408 to realize more or fewer different delay periods.
  • each delay line 610 includes a certain number of delay buffers (e.g., zero, three, six, or nine), a different number of delay buffers per delay line 610 may alternatively be implemented.
  • FIG. 7 illustrates generally at 700 another example implementation of a delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n, e.g., of FIG. 4.
  • the voltage dependency of the first propagation speed 306 and the voltage dependency of the second propagation speed 308 result from the first buffer 402 and the second buffer 404 having different respective threshold voltages.
  • the first signal 312 and the second signal 314 are separated into two parts.
  • the first signal 312 includes an incoming first signal 702 before the first buffer 402 and an outgoing first signal 706 after the first buffer 402.
  • the second signal 314 includes an incoming second signal 704 before the second buffer 404 and an outgoing second signal 708 after the second buffer 404.
  • the time-of-arrival detection circuit 506 (of FIG. 5) is implemented as a flip-flop 710.
  • the first buffer 402 has a first threshold voltage
  • the second buffer 404 has a second threshold voltage.
  • the first threshold voltage is, for example, relatively higher than the second threshold voltage.
  • the first threshold voltage of the first buffer 402 is referred to herein as the higher threshold voltage (Higher Vt)
  • the second threshold voltage of the second buffer 404 is referred to herein as the lower threshold voltage (Lower Vt).
  • the flip-flop 710 is realized as a "DQ" flip-flop having a "D" input or data input, a "Q" output, and a clocking input.
  • other flip-flop types can alternatively be implemented.
  • a first input of the first buffer 402 receives the incoming first signal 702.
  • a first output of the first buffer 402 provides the outgoing first signal 706 after the first delay time 502, which is based on the higher threshold voltage (Higher Vt).
  • a second input of the second buffer 404 receives the incoming second signal 704.
  • a second output of the second buffer 404 provides the outgoing second signal 708 after the second delay time 504, which is based on the lower threshold voltage (Lower Vt).
  • the data input of the flip-flop 710 receives the outgoing first signal 706, and the clocking input of the flip-flop 710 receives the outgoing second signal 708.
  • the output of the flip-flop 710 provides the stage timing signal 204.
  • a value of the stage timing signal 204 is based on a value of the outgoing first signal 706 when the clocking input of the flip-flop 710 is triggered by the outgoing second signal 708.
  • the first signal 312 has a first propagation speed 306 that is slower than the second propagation speed 308 of the second signal 314 due to the higher threshold voltage of the first buffer 402 as compared to the lower threshold voltage of the second buffer 404.
  • the effect of different threshold voltages on the relative signal propagation speeds is described below with reference to graphs of FIG. 8.
  • the first signal 312 is propagating more slowly along the first signaling path 302 than the second signal 314 is along the second signaling path 304.
  • the first signal 312 is provided a "head start" over the second signal 314 due to the delay period 612 instituted by the signal delay circuit 408.
  • the second signal 314 Because of the lower threshold voltage of each second buffer 404 of each delay stage 202, the second signal 314 gains on the first signal 312. Eventually, the second signal 314 catches and even passes the first signal 312 along the chained arrangement of the multiple delay stages 202-1 ... 202-n.
  • the flip-flop 710 provides functionality for asserting a respective stage timing signal 204 responsive to the second signal 314 arriving at the respective delay stage 202 prior to the first signal 312. To do so, the flip-flop 710 detects at what delay stage 202 the second signal 314 catches, or has passed, the first signal 312 based on one or more signal values. In a first scenario, the first signal 312 is still ahead of the second signal 314 at the illustrated delay stage 202. Thus, the outgoing first signal 706 has already taken a current value for the current voltage determination cycle when a voltage change for the outgoing second signal 708 arrives to trigger the flip-flop 710 via the clocking input. With this first scenario, the output of the flip-flop 710 provides the current value for the stage timing signal 204.
  • the second signal 314 catches the first signal 312 and therefore arrives at the output of the second buffer 404 at the illustrated delay stage 202 prior to the first signal 312 arriving at the output of the first buffer 402.
  • the outgoing first signal 706 therefore still has a previous value for the previous voltage determination cycle when a voltage change for the outgoing second signal 708 arrives to trigger the flip-flop 710 via the clocking input thereof.
  • the output of the flip-flop 710 provides the previous value for the stage timing signal 204.
  • the delay stage 202 provides a value for the stage timing signal 204 that is indicative of a relative time-of-arrival between the first signal 312 and the second signal 314.
  • the current value of the two signals for the current voltage determination cycle is output at each delay stage 202 for which the first signal 312 still leads the second signal 314.
  • the previous value of the two signals for the previous voltage determination cycle is output at each delay stage 202 for which the second signal 314 has caught the first signal 312.
  • FIG. 8 depicts a collection of graphs 800 that illustrate example scenarios for circuitries with different threshold voltages.
  • the top half of the collection of graphs 800 includes a multi-voltage graph 802, and the bottom half includes a first voltage graph 812, a second voltage graph 814, and a third voltage graph 816.
  • the collection of graphs 800 jointly illustrate how buffers with two different threshold voltages can establish two different delay times in the buffers. These two different delay times result in two different propagation speeds for two different signaling paths by respectively allocating buffers having the two different threshold voltages to the two different signaling paths.
  • a horizontal or abscissa axis represents a voltage between a gate and a source of a transistor, or a Vgs axis 804.
  • a vertical or ordinate axis represents a current through a drain of the transistor, or an Id axis 806.
  • the gate-to-source voltage (Vgs) represents the minimum voltage differential at which an appreciable or adequate current can flow between source and drain terminals.
  • FETs field effect transistors
  • BJTs bipolar junction transistors
  • Three different voltage differentials across the gate and source terminals of a transistor are marked in the multi -voltage graph 802 and indicated with vertical dashed lines: a first voltage (VI), a second voltage (V2), and a third voltage (V3).
  • Two threshold voltage (Vt) curves are depicted across the multi-voltage graph 802.
  • a solid curved line represents a lower threshold voltage curve (Lower Vt).
  • a dotted curved line represents a higher threshold voltage curve (Higher Vt).
  • the lower threshold voltage curve is graphed above the higher threshold voltage curve. This graphing indicates that, at any given gate-to-source voltage (Vgs) level, the drain current (Id) level is higher with the lower threshold voltage curve.
  • Vgs gate-to-source voltage
  • Id drain current
  • the drain current (Id) differentials between the higher and lower threshold voltages decrease as the Vgs voltage level increases.
  • the current differential decreases between the first voltage (VI) and the second voltage (V2) and again between the second voltage (V2) and the third voltage (V3).
  • the temporal effects on signaling that result from these different voltage levels are illustrated with the three graphs in the bottom half of the collection of graphs 800.
  • these three lower graphs illustrate how much time elapses before a faster signal catches a slower signal along a chained arrangement of multiple delay stages 202-1 ... 202-n.
  • the first voltage graph 812 corresponds to the first voltage (VI)
  • the second voltage graph 814 corresponds to the second voltage (V2)
  • the third voltage graph 816 corresponds to the third voltage (V3).
  • Each of the graphs 812, 814, and 816 has the same axes.
  • the illustrated axes are: a horizontal or abscissa time axis 808 and a vertical or ordinate stage axis 810.
  • Each graph includes two lines, with each line depicting movement of a signal through an increasing number of delay stages as time elapses.
  • the solid line represents a signal propagating over a signaling path that is formed from multiple buffers with a relatively lower threshold voltage (Lower Vt).
  • the dotted line represents a signal propagating over a signaling path that is formed from multiple buffers with a relatively higher threshold voltage (Higher Vt). Consequently, the solid lines for the signals flowing through the Lower- Vt buffers are steeper, or have a greater slope, than the dotted lines for the signals flowing through the Higher- Vt buffers.
  • the relative steepness between the two lines, or the differential between the two slops decreases between graphs from left to right.
  • the solid and dotted lines intersect at a first point that corresponds to a first particular time and a first particular delay stage.
  • the solid and dotted lines intersect at a second point that corresponds to a second, later time and a second, later delay stage.
  • the solid and dotted lines intersect at a third point that corresponds to a third, even later time and a third, even later delay stage.
  • the delay stage 202 at which the faster signal (e.g., the second signal 314) catches the slower signal (e.g., the first signal 312) is therefore located further along the chained arrangement of the multiple delay stages 202-1 ... 202 -n as the voltage level 104 increases.
  • FIG. 9 illustrates another example implementation of the voltage histogram circuit 200 that includes multiple gates 902-1, 902-2, 902-3 ... 902-n.
  • the multiple gates 902-1, 902-2, 902-3 ... 902-n are respectively coupled between multiple delay stages 202-1, 202-2, 202-3 ... 202-n and multiple counters 206-1, 206-2, 206-3 ... 206-n.
  • the multiple delay stages 202-1 ... 202-n in FIG. 9 correspond to the example implementation of FIG. 7.
  • the delay stages may be implemented in alternative manners.
  • each gate 902 can be implemented as, for example, an exclusive-or gate (XOR gate).
  • each gate 902 of the multiple gates 902-1 ... 902-n can be implemented using a different type of gate, multiple gates, and so forth.
  • each respective gate 902 is coupled to a respective delay stage 202 to receive a respective stage timing signal 204.
  • Each respective gate 902 is also coupled to another delay stage 202, which is coupled consecutively in series with the respective delay stage 202, so as to also receive another stage timing signal 204 from the other delay stage 202.
  • each gate 902 receives at two inputs thereof two stage timing signals from two different, but consecutive, delay stages. Based on these two stage timing signals, each gate 902 produces a gated stage timing signal 904 at an output thereof.
  • the second gate 902-2 receives the first stage timing signal 204-1 and the second stage timing signal 204-2 and produces the second gated stage timing signal 904-2.
  • each respective gate 902 of the multiple gates 902-1, 902-2, 902-3 ... 902-n generates a respective gated stage timing signal 904 of multiple gated stage timing signal 904-1, 904-2, 904-3 ... 904-n.
  • Each respective gate 902 of the multiple gates 902-1, 902-2, 902-3 ... 902-n provides a respective gated stage timing signal 904 of multiple gated stage timing signal 904-1, 904-2, 904-3 ... 904-n to a respective counter 206 of the multiple counters 206-1, 206-2, 206-3 ... 206-n.
  • a gated stage timing signal 904 refers to a stage timing signal 204 that has been processed or routed through at least one gate 902.
  • the first gate 902-1 also receives a voltage 906 that is tied to a low value or a high value such that the first gate 902-1 asserts the first gated stage timing signal 904-1 if the first stage timing signal 204-1 indicates that the second signal 314 has already caught the first signal 312 at the first delay stage 202-1.
  • the multiple gates 902-1, 902-2, 902-3 ... 902-n are employed to ensure that the earliest delay stage 202 at which the second signal 314 catches the first signal 312 causes a corresponding counter 206 to increment the associated counter value 106 while other, subsequent counters 206 are excluded from incrementing their counter values.
  • each respective gate 902 To enable the earliest counter 206 along the chained arrangement of the multiple delay stages 202-1 ... 202-n to increment an associated counter value 106, each respective gate 902 considers the value of the respective stage timing signal 204 and the value of a consecutive (e.g., previous as shown) stage timing signal 204. With an XOR gate implementation for each gate 902, a logical XOR operation is implemented. Accordingly, the respective gated stage timing signal 904 is asserted if the two adjacent stage timing signals have different values, but not if the two adjacent stage timing signals have the same value.
  • the second gate 902-2 receives two stage timing signals (e.g., the first stage timing signal 204-1 and the second stage timing signal 204-2) with different values.
  • subsequent gates such as the third gate 902-3, receive two stage timing signals with the same value, so the subsequent gated stage timing signals are not asserted. In this manner, the counter value 106 of the earliest counter 206 is incremented, but other counter values are unchanged.
  • FIG. 10 illustrates another example implementation of the voltage histogram circuit 200.
  • the voltage histogram circuit 200 includes circuitry for implementing a programmable frequency for voltage determination cycles.
  • Each voltage determination cycle is one pass of the first signal 312 and the second signal 314 through the chained arrangement of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n.
  • Each voltage determination cycle therefore includes an incrementation of one counter value 106 at an associated counter 206 and a feeding back of the loopback signal 310 from a last delay stage 202 to the first delay stage 202-1 or to the control circuitry 316 (e.g., of FIGS. 4 and 6).
  • the last delay stage 202 in a voltage determination cycle can be programmable to thereby change a frequency at which voltage determination cycles occur, as is explained with reference to FIG. 10.
  • the example implementation of the voltage histogram circuit 200 as shown in FIG. 10 is similar to that of FIG. 9. In FIG. 10, however, components to enable a programmable frequency of operation are depicted above the chained arrangement of the multiple delay stages 202-1 ... 202-n. As shown, the implementation includes a multiplexer 1004 with multiple inputs and one output, multiple tap nodes 1008-1, 1008-2, and 1008-3 at multiple delay stages, and multiple loopback signals 310-1, 310-2, and 310-3. In other words, instead of a single loopback signal 310, which is depicted in FIG. 4, multiple loopback signals are respectively coupled between the multiple different tap nodes and the multiple inputs of the multiplexer 1004.
  • a first tap node 1008-1 is disposed at the first delay stage 202-1
  • a second tap node 1008-2 is disposed at the third delay stage 202-3
  • a third tap node 1008-3 is disposed at the "nth" delay stage 202-n.
  • Each tap node 1008 corresponds to an output node of a corresponding delay stage 202 along the first signaling path over which the first signal 312 propagates.
  • the tap nodes can correspond to different nodes of the chained arrangement of delay stages. Also, a different number of loopback signals can alternatively be implemented. Further, the tap nodes can be disposed at different delay stages than those that are described herein.
  • the first, second, and third loopback signals 310-1, 310-2, and 310-3 are respectively coupled between the first, second, and third tap nodes 1008-1, 1008-2, and 1008-3 and the first, second, and third inputs of the multiplexer 1004.
  • the multiplexer 1004 produces a selected loopback signal 1002 based on a programmable frequency signal 1006 that selects one of the loopback signals coupled to the inputs of the multiplexer 1004.
  • the selected loopback signal 1002 is then fed back to the control circuitry 316 (not shown in FIG. 10). If the first delay stage 202-1 is to be the last delay stage for a given voltage determination cycle, the multiplexer 1004 is programmed to select the first loopback signal 310-1.
  • the multiplexer 1004 is programmed to select the second loopback signal 310-2. And if the "nth" delay stage 202-n is to be the last delay stage for a given voltage determination cycle, the multiplexer 1004 is programmed to select the third loopback signal 310-3.
  • the multiplexer 1004 can select a number of traversed delay stages that the first signal 312 and the second signal 314 traverse each voltage determination cycle using the different loopback signals. This can be accomplished by selecting a tap node 1008 of the multiple tap nodes 1008-1, 1008-2, and 1008-3 to change a length of the first signaling path 302 and the second signaling path 304 (e.g., of FIG. 4).
  • the multiplexer 1004 and the multiple loopback signals 310-1, 310-2, and 310-3 provide functionality for adjusting a frequency of the voltage determination cycle by selectively changing, for the loopback signal 310, a tap node 1008 along the chained arrangement of the multiple delay stages 202-1 ... 202-n.
  • each delay stage 202 or counter 206 corresponds to a voltage level 104.
  • each associated counter value 106 represents a number of occurrences for the corresponding voltage level 104.
  • a voltage value for a given voltage level 104 can be ascertained by performing a calibration process. To calibrate a voltage histogram circuit 200, a range of different known voltages are applied to the voltage histogram circuit 200. For each known voltage, a value of the first tap is read out after a waiting period. The voltage levels are then calculated by interpolating the tap values based on the known voltages.
  • Vdd 500mV:5mV:900mV
  • V interp(Tap, Vdd, T); % Converts tap to voltage.
  • FIG. 1 1 is a flow diagram illustrating an example process 1 100 for generating a voltage histogram.
  • the process 1100 is described in the form of a set of blocks 1 102-1108 that specify operations that can be performed. However, operations are not necessarily limited to the order shown in FIG. 1 1 or described herein, for the operations may be implemented in alternative orders or in fully or partially overlapping manners. Operations represented by the illustrated blocks of the process 1 100 may be performed by a voltage histogram circuit 200 (e.g., of FIG. 2, 3, 4, 9, or 10). More specifically, the operations of the process 1100 may be performed by the multiple delay stages 202-1, 202-2, 202-3 ... 202-n; the multiple counters 206-1, 206-2, 206-3 ...
  • a voltage histogram circuit 200 e.g., of FIG. 2, 3, 4, 9, or 10
  • a first signal propagates along a first signaling path at a first propagation speed that is based on a current voltage level.
  • a voltage histogram circuit 200 can propagate a first signal 312 along a first signaling path 302 at a first propagation speed 306 that is based on a current voltage level 104.
  • the first signal 312 may traverse a first buffer 402 in each of multiple delay stages 202-1 ... 202-n along the first signaling path 302, with the first buffer 402 having a relatively higher threshold voltage.
  • a second signal propagates along a second signaling path at a second propagation speed that is based on the current voltage level, with the second propagation speed being faster than the first propagation speed.
  • the voltage histogram circuit 200 can propagate a second signal 314 along a second signaling path 304 at a second propagation speed 308 that is based on the current voltage level 104.
  • the second signal 314 may traverse a second buffer 404 in each of the multiple delay stages 202-1 ... 202-n along the second signaling path 304, with the second buffer 404 having a relatively lower threshold voltage.
  • the second propagation speed 308 is faster than the first propagation speed 306 because each second buffer 404 has a lower threshold voltage than each first buffer 402.
  • a relative arrival time between the first signal and the second signal is detected at each delay stage of multiple delay stages.
  • the voltage histogram circuit 200 can detect a relative arrival time between the first signal 312 and the second signal 314 at each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n.
  • a newly-arriving second signal 314 may trigger a flip-flop 710 to latch a value of the first signal 312 to detect if the value corresponds to a current value or a previous value for a voltage determination cycle around the voltage histogram circuit 200.
  • occurrences of multiple voltage levels are tracked over time based on the detecting.
  • the voltage histogram circuit 200 can track numbers of occurrences 112-1, 112-2, 112-3 ... 112-n of multiple voltage levels 104-1, 104-2, 104-3 ... 104-n over time based on the detection of relative arrival times.
  • a counter 206 that corresponds to a respective voltage level 104 may, for instance, increment an associated counter value 106 each time the respective voltage level 104 is detected over some tacking period by the voltage histogram circuit 200.
  • An example implementation of the first signal propagation at block 1102 can include propagating the first signal 312 using multiple first semiconductor devices configured to operate relatively more slowly at a given voltage level.
  • An example implementation of the second signal propagation at block 1104 can include propagating the second signal 314 using multiple second semiconductor devices configured to operate relatively more quickly at the given voltage level.
  • the first semiconductor devices and the second semiconductor devices can be realized using, for instance, transistors with different threshold voltages as described above with reference to FIGS. 7 and 8.
  • An example implementation of the detection at block 1106 can include detecting if the second signal 314 arrives earlier than the first signal 312 at each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n.
  • the time-of-arrival detection circuit 506, which may be implemented as a flip-flop 710, can detect a relative arrival time between two signals based on what signal value is output when a clocking input of the flip-flop 710 is triggered.
  • the detecting at block 1 106 can further include generating a respective stage timing signal 204 at a respective delay stage 202 based on a first value (e.g., "0" or "1") of the first signal 312 and a second value (e.g., a changing value) of the second signal 314 at the respective delay stage 202.
  • a first value e.g., "0" or "1”
  • a second value e.g., a changing value
  • An example implementation of the tracking at block 1 108 can include generating frequency data for different voltages for a histogram graph 102 by creating multiple counter values 106-1, 106-2, 106-3 ... 106-n that are respectively representative of multiple numbers of occurrences 112-1, 112-2, 112-3 ... 112-n for corresponding ones of the multiple voltage levels 104-1, 104-2, 104-3 ... 104-n based on the relative arrival time at each delay stage 202 of the multiple delay stages 202-1, 202-2, 202-3 ... 202-n over multiple voltage determination cycles.
  • the tracking at block 1108 can further include determining the earliest delay stage 202, along a chained arrangement of the multiple delay stages 202-1 ... 202-n, at which the second signal 314 overtakes the first signal 312.
  • Example implementations of the process 1100 can further include an operation of changing the frequency of the voltage determination cycles. To do so, a frequency can be changed at which the first signal 312 or the second signal 314 is looped back to begin another propagation along the first signaling path 302 or the second signaling path 304, respectively. This can be accomplished by using a multiplexer 1004 to select from among multiple tap nodes 1008-1, 1008-2, and 1008-3 that are distributed at different locations along the chained arrangement of the multiple delay stages 202-1 ... 202-n.
  • FIG. 12 depicts an example electronic device 1202 that includes an integrated circuit 1210 (IC) having multiple cores.
  • the electronic device 1202 includes an antenna 1204, a transceiver 1206, and a user input/output interface 1208 in addition to the integrated circuit 1210.
  • Illustrated examples of the integrated circuit 1210, or cores thereof include a microprocessor 1212, a graphics processing unit 1214 (GPU), a memory array 1216, and a modem 1218.
  • circuits and techniques for voltage histogram generation as described herein can be implemented by the integrated circuit 1210.
  • the integrated circuit 1210 as a whole, or individual cores thereof can include a voltage histogram circuit 200 or can be margined using a voltage histogram that is generated as described herein.
  • the electronic device 1202 can be a mobile or battery-powered device or a fixed device that is designed to be powered by an electrical grid.
  • Examples of the electronic device 1202 include a server computer, a network switch or router, a blade of a data center, a personal computer, a desktop computer, a notebook or laptop computer, a tablet computer, a smart phone, an entertainment appliance, and a wearable computing device such as a smartwatch, intelligent glasses, or an article of clothing.
  • An electronic device 1202 can also be a device, or a portion thereof, having embedded electronics. Examples of the electronic device 1202 with embedded electronics include a passenger vehicle, industrial equipment, a refrigerator or other home appliance, a drone or other unmanned aerial vehicle (UAV), and a power tool.
  • UAV unmanned aerial vehicle
  • the electronic device 1202 includes an antenna 1204 that is coupled to a transceiver 1206 to enable reception or transmission of one or more wireless signals.
  • the integrated circuit 1210 may be coupled to the transceiver 1206 to enable the integrated circuit 1210 to have access to received wireless signals or to provide wireless signals for transmission via the antenna 1204.
  • the electronic device 1202 as shown also includes at least one user input/output interface 1208. Examples of the user input/output interface 1208 include a keyboard, a mouse, a microphone, a touch-sensitive screen, a camera, an accelerometer, a haptic mechanism, a speaker, a display screen, and a projector.
  • the integrated circuit 1210 may comprise, for example, one or more instances of a microprocessor 1212, a graphics processing unit 1214, a memory array 1216, a modem 1218, and so forth. Different parts, or processing cores, of the integrated circuit 1210 may be individually powered on or off.
  • the microprocessor 1212 may function as a central processing unit (CPU) or other general -purpose processor.
  • the graphics processing unit 1214 may be especially adapted to process visual-related data for display.
  • the memory array 1216 stores data for the microprocessor 1212 or the graphics processing unit 1214.
  • Example types of memory for the memory array 1216 include random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM); flash memory; and so forth.
  • the modem 1218 demodulates a signal to extract encoded information or modulates a signal to encode information into the signal.
  • the integrated circuit 1210 may include additional or alternative parts than those that are shown, such as an I/O interface, a sensor such as an accelerometer, a transceiver or another part of a receiver chain, a customized or hard-coded processor such as an application-specific integrated circuit (ASIC), and so forth.
  • ASIC application-specific integrated circuit
  • the integrated circuit 1210 may also comprise a system on a chip (SOC).
  • SOC system on a chip
  • An SOC may integrate a sufficient number of different types of components to enable the SOC to provide computational functionality as a notebook computer, a mobile phone, or another electronic apparatus using one chip, at least primarily.
  • Components of an SOC, or an integrated circuit 1210 generally, may be termed cores or circuit blocks.
  • a core or circuit block of an SOC may be powered down if not in use. Examples of cores or circuit blocks include, in addition to those that are illustrated in FIG.
  • a voltage regulator a main memory or cache memory block, a memory controller, a general-purpose processor, a cryptographic processor, a video or image processor, a vector processor, a radio, an interface or communications subsystem, a wireless controller, or a display controller.
  • a processing or GPU core may further include multiple internal cores or circuit blocks.

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Abstract

L'invention concerne un circuit intégré pour la génération d'histogrammes de tension. Dans un aspect donné à titre d'exemple, le circuit intégré comprend de multiples étages de retard couplés en série et de multiples compteurs. Les multiples étages de retard comprennent un premier trajet de signalisation pour propager un premier signal à une première vitesse de propagation et un second trajet de signalisation pour propager un second signal à une seconde vitesse de propagation. La première vitesse de propagation est inférieure à la seconde vitesse de propagation, et les deux vitesses dépendent de la tension. Les multiples étages de retard comprennent également un circuit de détection de temps d'arrivée (TOA) respectif pour chaque étage de retard respectif. Le circuit de détection de TOA respectif génère un signal de synchronisation d'étage respectif indiquant un temps d'arrivée relatif entre les premier et second signaux à l'étage de retard respectif. Les multiples compteurs sont respectivement couplés aux multiples étages de retard et ont des valeurs de compteur respectives. Les valeurs de compteur respectives sont incrémentées en réponse au signal de synchronisation d'étage respectif.
PCT/US2018/033975 2017-07-28 2018-05-22 Génération d'histogrammes de tension WO2019022825A2 (fr)

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