WO2019015551A1 - Dispositif de traitement de sortie vidéo et processeur de matrice vidéo - Google Patents

Dispositif de traitement de sortie vidéo et processeur de matrice vidéo Download PDF

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Publication number
WO2019015551A1
WO2019015551A1 PCT/CN2018/095841 CN2018095841W WO2019015551A1 WO 2019015551 A1 WO2019015551 A1 WO 2019015551A1 CN 2018095841 W CN2018095841 W CN 2018095841W WO 2019015551 A1 WO2019015551 A1 WO 2019015551A1
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Prior art keywords
video
interface
serial
input
processing
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PCT/CN2018/095841
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English (en)
Chinese (zh)
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王伙荣
宗靖国
葛敏锋
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北京嗨动视觉科技有限公司
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Publication of WO2019015551A1 publication Critical patent/WO2019015551A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching

Definitions

  • the present application relates to the field of video processing technologies, and in particular, to a video output processing device and a video matrix processor.
  • Video interface technology and LED display technology make the bandwidth of the video interface larger and larger, and the resolution of the LED display screen becomes larger and larger. These promote the scale of the video processing equipment and the function becomes stronger and stronger. Processing power is also growing stronger.
  • Common video matrix processors generally include four main components: video input processing device, video output processing device, backplane, and main control card.
  • the video output processing device is the key core of video processing, and its processing power is determined.
  • the advantages and disadvantages of the equipment have a great effect on the positioning and marketing of the products.
  • the existing video output processing device mostly uses a dedicated video processing chip as the processing core, and the input and output of the dedicated video processing chip mostly adopt the TTL level standard, so it is necessary to configure the necessary video decoder on the input side of the dedicated video processing chip to
  • the differential signal (such as TMDS signal) is converted into a TTL level signal, and the number of processing channels of the dedicated video processing chip is fixed and the algorithm cannot be updated, which causes the existing video output processing device to have a complicated system structure and poor scalability. .
  • Embodiments of the present application provide a video output processing apparatus and a video matrix processor to overcome the defects of the system structure and poor scalability in the prior art.
  • a video output processing apparatus includes: a first programmable logic device, a second programmable logic device, a first memory, a second memory, a microcontroller, and a multi-channel video encoder.
  • the microcontroller is coupled to the first programmable logic device and the second programmable logic device, and the first memory and the second memory are respectively connected to the first programmable logic device and the first Two programmable logic devices.
  • the second programmable logic device is coupled between the first programmable logic device and the multi-channel video encoding device
  • the first programmable logic device is configured to be used for multiple of multiple input sources
  • the first input source is subjected to a scaling process, input to the second programmable logic device via a SerDes bus, and the plurality of second input sources of the plurality of input sources are not scaled and input to the a second programmable logic device
  • the second programmable logic device is configured to perform a scaling process on the plurality of second input sources, and perform superposition processing on the plurality of first input sources after the scaling process to obtain an overlay
  • the result is output to some or all of the multi-channel video encoder; or the second programmable logic device and the first programmable logic device are interconnected, the first video encoder of the multi-channel video encoder is connected On an output side of the first programmable logic device, a second video encoder of the multi-channel video encoder is coupled to an output side of the second programmable logic device,
  • a video output processing apparatus includes: a first video processing unit, a second video processing unit, a video encoding module, and a control unit.
  • the first video processing unit is configured with a plurality of first video input interfaces, a multi-channel video loop-out interface, and a plurality of first video output interfaces, and the multi-channel first video input interface and the multi-channel video loop-out interface
  • the multi-channel first video output interface is a serial interface
  • the second video processing unit is configured with a plurality of second video input interfaces and at least one second video output interface, where the multiple second video input interfaces are The serial interface, a part of the second video input interface of the multiple video input interfaces is respectively connected to the multiple video loop out interface, and another part of the second video input interface is the second video.
  • the input interface is respectively connected to the multiple first video output interfaces
  • the video encoding module is connected to the at least one second video output interface
  • the control unit is connected to the first video processing unit and the second video Processing
  • the serial interface is a serializer/deserializer based serial interface
  • the first video processing unit and the second video processing unit are programmable logic devices.
  • the control unit is a microcontroller.
  • the first video processing unit includes a multi-channel first serial transceiver, a multi-path image scaling processing sub-unit, and a multi-channel second serial transceiver, the multi-channel first string
  • the row transceivers are respectively connected to the plurality of first video input interfaces, and a part of the first serial transceivers of the plurality of first serial transceivers are further connected to the multiple image scaling processing subunits, respectively.
  • a portion of the second serial transceivers of the second serial transceiver are respectively connected to the multiple video loop out interfaces and are also respectively connected to another part of the plurality of first serial transceivers, the first serial transceiver And another part of the plurality of second serial transceivers, the second serial transceiver, respectively, the multi-path image scaling processing sub-unit and also respectively connected to the multi-channel first video output interface.
  • the second image processing unit includes an image superimposition subunit, a multiplexed second image scaling processing subunit, and a multiplexed third serial transceiver, and the multiplexed third serial transceiver And respectively connecting the plurality of second video input interfaces, a part of the third serial transceivers of the plurality of third serial transceivers are respectively connected to the image superposition subunit and another part of the third serial transceiver
  • the plurality of second image scaling processing subunits are respectively connected to the image superposition subunit, and the at least one second video output interface is connected to the image superposition subunit.
  • the video encoding module includes a multi-channel video decoder, the at least one second video output interface is a multi-channel second video output interface, and the multi-channel video decoder is respectively connected to the Multi-channel second video output interface.
  • a video matrix processor includes: a backplane and any one of the foregoing video output processing devices; the backplane includes a video input processing device interface, a video output processing device interface, and a main control a device interface, a matrix switching module, and a data communication module, the matrix switching module being connected between the video input processing device interface and the video output processing device interface, the matrix switching module being connected to the main control device interface and including a matrix switching chip, the data communication module is connected to the main control device interface, the video input processing device interface, and the video output processing device interface, the multi-channel first video input interface of the first video processing unit Connecting the video output processing device interface.
  • a video output processing apparatus includes: a first video processing unit, a second video processing unit, a first video encoding module, a second video encoding module, and a control unit.
  • the first video processing unit includes a plurality of first video input interfaces, at least one first video data sharing interface, and at least one first video output interface, and the multiple first video input interfaces and at least one first video data sharing The interface is a serial interface;
  • the second video processing unit includes a plurality of second video input interfaces, at least one second video data sharing interface, and at least one second video output interface, the multiple second video input interfaces and at least
  • the first video data sharing interface is a serial interface, and the at least one second video data sharing interface is connected to the at least one first video data sharing interface;
  • the first video decoding module is connected to the The at least one first video output interface of the first video processing unit;
  • the second video decoding module is coupled to the at least one second video output interface of the second video processing unit; and the control unit is connected to the first video
  • the serial interface is a serializer/deserializer based serial interface
  • the first video processor and the second video processor are programmable logic devices.
  • the first video processing unit includes a multiple first serial transceiver, a multiple image scaling processing subunit, an image superposition subunit, and at least one second serial transceiver, a plurality of first serial transceivers respectively connected to the plurality of first video input interfaces and also connected to the image superposition subunits by the multipath image scaling processing subunit, respectively, the at least one second serial transceiver
  • the image superimposing subunit and the at least one first video data sharing interface are connected to the at least one first video output interface.
  • a video matrix processor includes: a backplane and any one of the foregoing video output processing devices; the backplane includes a video input processing device interface, a video output processing device interface, and a main a control device interface, a matrix switching module, and a data communication module, the matrix switching module being connected between the video input processing device interface and the video output processing device interface, wherein the matrix switching module is connected to the main control device interface and Included as a matrix switch chip, the data communication module is coupled to the master device interface, the video input processing device interface, and the video output processing device interface, the multiple video first input of the first video processing unit The interface and the plurality of second video input interfaces of the second video processing unit are each coupled to the video output processing device interface.
  • the data communication module includes: a third programmable logic device; a plurality of first network physical transceivers connected to the video input processing device interface and the third programmable logic device And a plurality of second network physical transceivers connected between the video output processing device interface and the third programmable logic device.
  • the above technical solution may have one or more advantages or benefits as follows: a) reducing the complexity of the hardware: the input sources are all input in the form of a serial bus such as a serial bus based on SerDes, without a dedicated receiving chip, only The data processing unit such as FPGA can complete the data receiving and transmitting, and the structure is simple; b) the switching capability is strong: each channel based on the SerDes serial bus input can complete the transmission of one video source, without multiple parallel connection (such as the traditional TDMS signal) to complete the transmission of a single input source, improve the utilization of the matrix switch chip on the backplane, reduce the channel requirements of the matrix switch chip, improve the switching capability; c) strong processing power: each video Processing units such as FPGAs have at least 6 1080P layers of processing power.
  • FIG. 1 is a schematic structural diagram of a video output processing apparatus according to a first embodiment of the present application
  • FIG. 2 is a schematic diagram of a specific structure of a video processing unit shown in FIG. 1.
  • FIG. 3 is a schematic diagram of a specific structure of another video processing unit shown in FIG. 1.
  • FIG. 4 is a schematic structural diagram of a video output processing apparatus according to a second embodiment of the present application.
  • FIG. 5 is a schematic diagram of a specific structure of a video processing unit shown in FIG. 4.
  • FIG. 6 is a schematic diagram of a specific structure of another video processing unit shown in FIG. 4.
  • FIG. 7 is a schematic structural diagram of a video matrix processor according to a third embodiment of the present application.
  • FIG. 8A is a schematic diagram of a specific structure of the data communication module shown in FIG. 7.
  • FIG. 8A is a schematic diagram of a specific structure of the data communication module shown in FIG. 7.
  • FIG. 8B is a schematic structural view of a main control device suitable for being plugged into the interface of the main control device shown in FIG. 7.
  • FIG. 8B is a schematic structural view of a main control device suitable for being plugged into the interface of the main control device shown in FIG. 7.
  • a video output processing apparatus 10 provided in the first embodiment of the present application mainly includes a video processing unit 11, a video processing unit 13, a video encoding module 15, and a control unit 17.
  • the video processing unit 11 is configured with a multi-channel video input interface 110, a multi-channel video loop-out interface 111a, and a multi-channel video output interface 111b.
  • the video processing unit 13 is configured with a plurality of video input interfaces 130 and at least one video output interface 131. A part of the video input interfaces 130 are respectively connected to the multi-channel video loop-out interface 111a. Another portion of the video input interface 130 in the video input interface 130 is connected to the multi-channel video output interface 111b.
  • the video encoding module 15 is connected to the at least one video output interface 131, and the control unit 17 is connected to the video processing unit 11 and the video processing unit 13, and is, for example, a microcontroller like an MCU or the like, and the video processing unit 11 and the video processing unit 13 are respectively externally connected.
  • the control unit 17 serves as, for example, a controller of the video processing unit 11 and the video processing unit 13 to coordinate the work of both, even as a controller that interacts with an external device such as a host computer.
  • the video encoding module 15 includes, for example, one or more video encoders, such as DVI (Digital Visual Interface), HDMI (High Definition Multimedia Interface), and the like. Analog video encoders such as VGA (Video Graphics Array) are used, depending on actual needs.
  • DVI Digital Visual Interface
  • HDMI High Definition Multimedia Interface
  • VGA Video Graphics Array
  • the multiple video input interface 110, the multiple video loop out interface 111a, the multiple video output interface 11b, and the multiple video input interface 130 in this embodiment are based on a serial interface, for example, based on Serial interface of Serializer/Deserializer (SerDes), so that SerDes bus can be used as transmission of video data between video processing unit 11 and front-end device and between video processing unit 11 and video processing unit 13.
  • SerDes Serializer/Deserializer
  • Channels, each with a rate of up to 6.5 Gbps, can transmit 1080P images with bit depths up to 36 bits each.
  • the video output processing device 10 has a plurality of 16 data processing sub-units, such as an image scaling processing sub-unit (Scaler), and each of which can process an image of 1080 P size, when the video output processing device 10 only outputs 1080P. Up to 16 layers can be output, and when the on-load output is 4K ⁇ 2K, up to 4 layers can be output.
  • image scaling processing sub-unit Scaler
  • the video processing unit 11 and the video processing unit 13 in the embodiment are preferably programmable logic devices such as an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device). )Wait.
  • the two video processing units 11 and 13 are cascaded to realize simultaneous processing of multiple pictures.
  • the video processing units 11 and 13 are responsible for the processing of part of the input source, and the video processing unit 13 is also responsible for multiple
  • the final overlay display of the layer and the result of the overlay processing is output from the at least one video output interface 131 to the video encoding module 15 for display on the upper screen.
  • the following uses the SerDes bus between the video processing units 11 and 13 for data transmission, and the video output processing device 10 can access 16 input sources as an example, and the present invention is combined with FIG. 2 and FIG.
  • the specific structure and working principle of the video output processing apparatus 10 of the embodiment are described as follows:
  • the video processing unit 11 includes multiple channels (for example, 16 in addition to the multi-channel video input interface 110, the multi-channel video loop-out interface 111a, and the multi-channel video output interface 111b.
  • the multiple serial transceivers 113 are respectively connected to the multiple video input interfaces 110, and a part of the serial transceivers 113 of the multiple serial transceivers 113 are also respectively connected to the multiple image scaling processing sub-unit 115.
  • a plurality of serial transceivers 117 of the plurality of serial transceivers 117 are respectively connected to the multiple video loop-out interfaces 111a and are also respectively connected to another partial serial transceivers of the multiple serial transceivers 113. 113.
  • Another partial serial transceiver 117 of the multiple serial transceivers 117 is respectively connected to the multiple image scaling processing sub-unit 115 and is also respectively connected to the multiple video output interfaces 111b.
  • the video processing unit 13 includes a multi-channel (for example, 16-channel) serial transceiver 133 and multiple channels (for example, 6 channels) in addition to the multi-channel video input interface 130 and the at least one video output interface 131.
  • the plurality of serial transceivers 133 are respectively connected to the multiple video input interfaces 130, and a part of the serial transceivers 133 of the multiple serial transceivers 133 are respectively connected to the image superposition sub-unit 139 and another part
  • the serial transceiver 133 is connected to the image superposition sub-unit 139 by the multi-path image scaling processing sub-unit 135, and the at least one video output interface 131 is connected to the output side of the image superposition sub-unit 139.
  • the video processing unit 11 receives 16 input sources In1-In16 from the backplane of the front end device such as the video matrix processor through the receiving end (Rx) of the 16-channel serial transceiver 113. And invoking its embedded 10-way image scaling processing sub-unit 115, processing 10 of the input sources In7-In16, and processing the results Rslt1-Rslt10 through the transmitting end (Tx) of the 10-way serial transceiver 117 To the video processing unit 13; the other six input sources In1-In6 are directly output to the video processing unit 13 through the transmitting end (Tx) loop of the six-way serial transceiver 117.
  • the video processing unit 13 calls its built-in 6-way image scaling processing sub-unit 135 to process the 6 input sources Src1-Src6 coming from the loop, and then the 6-way result processed by the image superimposition sub-unit (Blender) 139 (corresponding The six layers are superimposed with the 10-way processing results Rslt1-Rslt10 (corresponding to 10 layers) processed by the video processing unit 11, and the superimposed results are output to the video encoding module 15 through the at least one video output interface 131. For the upper display.
  • the six input sources In1-In6 not processed in the video processing unit 11 need to be transmitted in a loop mode. To reduce transmission delays.
  • the allocation of the image scaling processing sub-units 115, 135 in the video processing unit 11 and the video processing unit 13 needs to be balanced in the consumption of the resources and the memories 11a, 13a, for example, DDR bandwidth, to avoid a situation where the load is heavy and the load is light.
  • a video output processing apparatus 40 provided in the second embodiment of the present application mainly includes a video processing unit 41, a video processing unit 43, a video encoding module 45a, a video encoding module 45b, and a control unit 47.
  • the video processing unit 41 is configured with a plurality of video input interfaces 410, at least one video output interface 411, and at least one video data sharing interface 412.
  • the at least one video output interface 411 is connected to the video encoding module 45a.
  • the video processing unit 43 is configured with a multi-channel video input interface 430, at least one video output interface 431, and at least one video data sharing interface 432.
  • the at least one video output interface 431 is connected to the video encoding module 45b.
  • the at least one video data sharing interface 432 is connected to the at least one video data sharing interface 412 in one-to-one correspondence.
  • the control unit 47 is connected to the video processing unit 41 and the video processing unit 43, and is, for example, a microcontroller like an MCU or the like.
  • the control unit 47 serves as, for example, a controller of the video processing unit 41 and the video processing unit 43 to coordinate the work of both, even as a controller that interacts with an external device such as a host computer.
  • the video processing unit 41 and the video processing unit 43 are externally connected with memories 41a, 43a as buffers in the video image processing.
  • the video encoding module 45a includes, for example, one or more video encoders, such as digital video encoders such as DVI and HDMI. Of course, analog video encoders such as VGA can also be used, which may be determined according to actual needs.
  • the video encoding module 45b includes, for example, one or more video encoders, such as digital video encoders such as DVI and HDMI. Of course, analog video encoders such as VGA can also be used, which may be determined according to actual needs.
  • the multiple video input interface 410, the at least one video data sharing interface 412, the multiple video input interface 430, and the at least one video data sharing interface 432 in the embodiment are serial interfaces, for example.
  • a SerDes bus can be used as a transmission channel for video data between the video processing units 41, 43 and the front end device and between the video processing unit 41 and the video processing unit 43.
  • Each channel can be up to 6.5Gbps, and each channel can transmit 1080P images with a bit depth of up to 36bit.
  • the video processing unit 41 and the video processing unit 43 in this embodiment are preferably devices such as a programmable logic device such as an FPGA or a CPLD. As shown in FIG. 4, the two video processing units 41 and 43 are connected in parallel and the data are shared with each other to realize simultaneous processing of multiple pictures.
  • the video processing units 41 and 43 are respectively responsible for accessing multiple input sources and implementing multiple layers.
  • the processing and the superimposing tasks, the respective superimposed results can also be shared by the video data sharing interfaces 412, 432 to the other party, and then the final superposition; the final superimposed result can be output to the video encoding through the at least one video output interface 411.
  • the module 45a is for display on the upper screen and/or output to the video encoding module 45b through the at least one video output interface 431 for display on the upper screen.
  • the following uses the SerDes bus between the video processing units 41, 43 for data transmission and the video output processing device 40 can access up to 16 input sources as an example, and the present invention is combined with FIG. 5 and FIG.
  • the specific structure and working principle of the video output processing device 40 of the embodiment are described as follows:
  • the video processing unit 41 includes multiple channels (for example, 8 in addition to the multiple video input interface 410, the at least one video output interface 411, and the at least one video data sharing interface 412.
  • the multi-channel serial transceivers 413 are respectively connected to the multi-channel video input interface 410 and are also connected to the image superposition sub-unit 419 by the multi-path image scaling processing sub-unit 415, and the image superposition sub-units 419 are connected.
  • the at least one video output interface 411 is also connected to the at least one video data sharing interface 412 via a serial transceiver 416, where the serial transceiver 416 is preferably multiplexed for transmitting the overlay result data RsltA, respectively. And receiving the superimposed result data RsltB.
  • the video processing unit 43 includes multiple channels (for example, 8 in addition to the multiple video input interface 430, the at least one video output interface 431, and the at least one video data sharing interface 432.
  • the multiple serial serial transceivers 433 are respectively connected to the multiple video input interfaces 430 and are also connected to the image superposition sub-unit 439 through the multi-path image scaling processing sub-unit 435, and the image superimposition sub-units 439 are connected.
  • the at least one video output interface 431 is also connected to the at least one video data sharing interface 432 via a serial transceiver 436, where the serial transceiver 436 is preferably multiplexed for transmitting the overlay result data RsltB, respectively. And receiving the overlay result data RsltA.
  • the video processing unit 41 receives eight input sources In1-In8 from the backplane of the front end device such as the video matrix processor through the receiving end (Rx) of the eight-way serial transceiver 413. And calling the embedded 8-way image scaling processing sub-unit 415 to process the eight input sources In1-In8, and the processed result is sent to the image superposition sub-unit 419 for superposition processing to obtain the superimposed result RsltA, which can be serialized.
  • the transmitting end (Tx) of the transceiver 416 and the at least one video data sharing interface 412 are sent to the video processing unit 43, so that the superimposed result RsltA can be transmitted and received via the at least one video data sharing interface 432 of the video processing unit 43
  • the receiving end (Rx) of the 436 is received by the image superposition sub-unit 439 for final superposition.
  • the video processing unit 43 receives the eight input sources In9-In16 from the backplane of the front end device, such as the video matrix processor, through the receiving end (Rx) of the 8-way serial transceiver 433, and calls the embedded 8 thereof.
  • the road image scaling processing sub-unit 435 processes the eight input sources In9-In16, and the processed result is sent to the image superimposition sub-unit 439 for superposition processing to obtain the superimposed result RsltB, which can pass through the transmitting end of the serial transceiver 436 (Tx).
  • the at least one video data sharing interface 432 is sent to the video processing unit 41, so that the superimposed result RsltB can be via the at least one video data sharing interface 412 of the video processing unit 41 and the receiving end (Rx) of the serial transceiver 416.
  • the image superimposition sub-unit 419 is received for final superposition.
  • the control unit 47 can issue a corresponding control command for control. Thereafter, the superimposed result obtained by the last superimposition may be output by the image superimposition subunit 419 via the at least one video output interface 411 of the video processing unit 41 for display on the upper screen or by the image superimposition subunit 439 via the video processing unit 43.
  • the at least one video output interface 431 is output for display on the upper screen.
  • a video matrix processor 70 mainly includes a backplane, a video input processing device 73, and a video output processing device 75.
  • the backplane includes a video input processing device interface 711, a video output processing device interface 715, a matrix switching module 713, a main control device interface 717, and a data communication module 719.
  • the matrix switching module 713 is connected between the video input processing device interface 711 and the video output processing device interface 715.
  • the matrix switching module 713 and the data communication module 719 are respectively connected to the main control device interface 717, and the data communication module 719 is also connected to the video input processing device interface. 711 and video output processing device interface 715.
  • the video input processing device interface 711 can be plugged into a plurality of video input processing devices 73.
  • the plugged video input processing device 73 is mainly used for video image access and pre-processing (such as gamma conversion, color gamut conversion, filtering, etc.) operations, which include, for example, video image access and pre-processing capabilities.
  • Programmable logic devices like FPGAs and microcontrollers connected to programmable logic devices like MCUs.
  • the video output processing device interface 715 can be plugged into a plurality of video output processing devices 75.
  • the video output processing device 75 is mainly used for operations of video post-processing operations such as image scaling, image overlay, and the like.
  • the video output processing device 75 can use the video output processing devices 10 and 40 described in the foregoing first embodiment and/or the second embodiment. For the specific structure, reference may be made to the foregoing description, and thus no further details are provided herein.
  • the main control device interface 717 is used for plugging in the main control device, which can communicate with the data communication module 719 through a FSMC (Flexible Static Memory Controller) bus, and is plugged into the video input through the data communication module 719.
  • the processing device interface 711 and the card on the video output processing device interface 715 perform data transmission.
  • the data communication module 719 is typically configured with a programmable logic device such as an FPGA and a first network physical layer transceiver group and a second network physical layer transceiver group connected to the programmable logic device (as shown in FIG. 8A).
  • the programmable logic device in the data communication module 719 can be connected to the video input processing device interface 711 through each of the network physical transceivers (PHYs) in the first network physical layer transceiver group, and can be transceived through the second network physical layer.
  • Each of the network physical transceivers (PHYs) in the group is connected to a video output processing device interface 715.
  • the data communication module 719 is not limited to the configuration programmable logic device shown in FIG. 8, and may be replaced with a microcontroller like an MCU or an embedded microprocessor like ARM.
  • the master device interface 717 and The communication bus used between the data communication module 719 can select a serial bus such as I2C, SPI, RS485, and the MCU or ARM can further select a serial bus such as I2C, SPI or RS485 to connect to the video input processing device interface 711 and video.
  • Output processing device interface 715 a serial bus such as I2C, SPI, RS485, and the MCU or ARM can further select a serial bus such as I2C, SPI or RS485 to connect to the video input processing device interface 711 and video.
  • Output processing device interface 715 can select a serial bus such as I2C, SPI, RS485, and the MCU or ARM can further select a serial bus such as I2C, SPI or RS485 to connect to the video input processing device interface 711 and video.
  • Output processing device interface 715 a serial bus such as I2C, SPI, RS485, and the MCU or ARM can further select a serial bus
  • the master device plugged into the master device interface 717 employs, for example, an MCU as a primary control unit, and the eMMC and Flash function as a cache function for data storage and programs.
  • the main control device also provides RS232, USB and RJ45 interfaces to interconnect the host computer with the MCU of the main control device, so that the computer software controls the system.
  • the WIFI module of the main control device enables other mobile devices to connect to the system.
  • various data buses such as FMC/FSMC, I2C, and SPI of the MCU of the main control device are connected to the backplane through the FCI interface, and the entire control system is completed with the upper computer software and the lower backplane. Interconnection.
  • the main control device is equipped with a U disk drive, providing a separate USB interface as a USB flash drive to save offline files, offline upgrades, etc.; the internal RTC module provides a real-time clock for the entire control system.
  • the matrix switching module 713 includes, for example, a matrix switching chip, such as a CrossPoint Switch chip, and switches the output data of the corresponding video input processing device 73 to the corresponding video output processing device according to the switching instruction sent by the main control device plugged into the main control device interface 717. 75 input.
  • the matrix switch module 713 preferably connects the video input processing device interface through a serial bus such as a SerDes-based high-speed serial bus.
  • the bus and matrix switching module 713 performs video image data transmission.
  • the video output processing devices 10, 30, and 75 in the foregoing embodiments may further integrate a combination circuit of a transmission card logic circuit such as a video decoding module, a programmable logic device, and a network transmission module, such that The video output processing device configured with the sending card logic circuit can directly carry the LED display with the receiving card through the network cable.
  • a transmission card logic circuit such as a video decoding module, a programmable logic device, and a network transmission module
  • the foregoing embodiments of the present application may achieve one or more of the following beneficial effects: a) reducing the complexity of the hardware: the input sources are all input in the form of a serial bus such as a serial bus based on SerDes, without special The receiving chip can only receive and transmit data by using a video processing unit such as an FPGA, and has a simple structure; b) strong switching capability: each channel can realize the transmission of one video source based on the serial bus input of SerDes, without passing through Multi-channel parallel connection (such as traditional TDMS signal) to complete the transmission of single input source, improve the utilization of matrix switch chip on the backplane, reduce the channel requirements of the matrix switch chip, improve the switching capability; c) processing capability Strong: Each video processing unit, such as an FPGA, has at least 6 1080P layers of processing power.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • Embodiments of the present application may achieve one or more of the following advantages or benefits: a) reducing the complexity of the hardware: the input sources are all input in the form of a serial bus such as a SerDes-based serial bus, without the need for a dedicated receiving chip.
  • each Video processing unit such as FPGA can complete the data receiving and transmitting, the structure is simple; b) the switching ability is strong: each channel based on the SerDes serial bus input can complete the transmission of one video source, without multiple parallel connection The method (such as the traditional TDMS signal) completes the transmission of the single input source, improves the utilization of the matrix switching chip on the backplane, reduces the channel requirement of the matrix switching chip, and improves the switching capability; c) the processing capability is strong: each Video processing units, such as FPGAs, have at least six 1080P layers of processing power.
  • Scalability Select programmable logic device as the video processing unit, its built-in algorithm can be updated in real time, On completion of a platform according to the different needs of different processing tasks, upgrade better, less resource consumption algorithm improves the scalability of the system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

L'invention concerne un dispositif de traitement de sortie vidéo et un processeur de matrice vidéo utilisant le dispositif de traitement de sortie vidéo. Le dispositif de traitement de sortie vidéo traite une vidéo au moyen d'une pluralité d'unités de traitement vidéo en cascade ou d'une pluralité d'unités de traitement vidéo connectées en parallèle et partageant des données les unes avec les autres. De plus, le mode d'accès au signal vidéo du dispositif de traitement de sortie vidéo et le mode de transmission de signal entre la pluralité d'unités de traitement vidéo utilisent tous deux un mode de bus série. Ainsi, la présente invention présente les avantages de simplifier la complexité du système et d'améliorer l'extensibilité du système.
PCT/CN2018/095841 2017-07-17 2018-07-16 Dispositif de traitement de sortie vidéo et processeur de matrice vidéo WO2019015551A1 (fr)

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US20110099407A1 (en) * 2009-10-28 2011-04-28 Ati Technologies Ulc Apparatus for High Speed Data Multiplexing in a Processor
CN102737614A (zh) * 2011-04-13 2012-10-17 宁波奇科威智能科技有限公司 在拼接屏上实现多层图像显示的方法及其拼接屏
CN102881159A (zh) * 2011-07-14 2013-01-16 中国大恒(集团)有限公司北京图像视觉技术分公司 一种嵌入式双dsp信息数据处理装置和方法
CN204515756U (zh) * 2014-12-22 2015-07-29 北京淳中视讯科技有限公司 拼接处理器
CN105721795A (zh) * 2016-01-21 2016-06-29 西安诺瓦电子科技有限公司 视频矩阵拼接器及其交换底板
CN206865611U (zh) * 2017-05-22 2018-01-09 西安诺瓦电子科技有限公司 视频拼接处理器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110099407A1 (en) * 2009-10-28 2011-04-28 Ati Technologies Ulc Apparatus for High Speed Data Multiplexing in a Processor
CN102737614A (zh) * 2011-04-13 2012-10-17 宁波奇科威智能科技有限公司 在拼接屏上实现多层图像显示的方法及其拼接屏
CN102881159A (zh) * 2011-07-14 2013-01-16 中国大恒(集团)有限公司北京图像视觉技术分公司 一种嵌入式双dsp信息数据处理装置和方法
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CN105721795A (zh) * 2016-01-21 2016-06-29 西安诺瓦电子科技有限公司 视频矩阵拼接器及其交换底板
CN206865611U (zh) * 2017-05-22 2018-01-09 西安诺瓦电子科技有限公司 视频拼接处理器

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