WO2019015251A1

WO2019015251A1 - Soi cmos radio frequency switch, radio frequency transceiving front end, and mobile terminal

Info

Publication number: WO2019015251A1
Application number: PCT/CN2017/117891
Authority: WO
Inventors: 赵鹏; 王秀; 刘刚; 曾真; 王肖莹; 贾斌
Original assignee: 锐迪科微电子科技（上海）有限公司
Priority date: 2017-07-18
Filing date: 2017-12-22
Publication date: 2019-01-24
Also published as: CN109274358B; CN109274358A

Abstract

A SOI CMOS radio frequency switch, comprising a fixed connection end (S1) and a plurality of selective connection ends (S2, S3). A channel is formed between each selective connection end (S2, S3) and the fixed connection end (S1). A main path of each channel comprises three or more cascaded transistors (T1, T2, T3). A capacitor (C5, C6) is connected between the sources and the drains of the transistors (T1, T3) at both ends of each channel, a resistor (R2) is connected between the source and the drain of the intermediate transistor (T2) of each channel, and the gates of all of the transistors of each channel are connected to the same control voltage (VT). The control voltage connected to each channel is further connected to any position of the main path of the channel, except for the two ends, via a branch comprising a forward inverter (I1) and a resistor (R21) in series. At any moment, only one control voltage is a positive voltage, and a channel connected to the positive voltage is closed. The remaining control voltages are all zero, and channels connected to the zero voltages are all disconnected. The SOICMOS radio frequency switch features a simplified overall circuit structure, low cost, and a small area.

Description

SOI CMOS RF switch and RF transceiver front end, mobile terminal

Technical field

The present application relates to a radio frequency switch, and more particularly to an RF switch implemented in a CMOS process on an SOI (Silicon On Insulator) material.

Background technique

With the development of mobile communication technology, a situation in which multiple mobile communication standards coexist has emerged. For example, in China, there are coexistence of mobile communication standards such as GSM, cdmaOne, W-CDMA, TD-SCDMA, CDMA2000, LTE-FDD, and LTE-TDD. Each mobile communication standard defines one or more operating frequency bands. For example, the GSM standard defines 14 working frequency bands. In order to improve compatibility and versatility in different countries and regions, mobile terminals represented by mobile phones need to support as many mobile communication standards as possible. This is called multi-model. Accordingly, mobile terminals also need to support as many different operating bands as possible of one or more mobile communication standards, which is referred to as multi-frequency characteristics. In order to realize multi-mode multi-frequency characteristics, taking into account the functions of Bluetooth, GPS, WLAN (wireless local area network), radio, etc., multiple RF power amplifiers are often arranged inside the mobile terminal, and each RF power amplifier can only be used for one frequency band. Or signal amplification of multiple frequency bands with close frequency ranges, and use RF switches to switch the required RF power amplifiers to the corresponding paths. In addition, RF switches are also used for time division multiplexing (Time-division In the multiplexing, TDM) system, it is used to switch between the transmit channel and the receive channel. For example, the GSM standard is implemented by a time division multiplexing system.

In a radio frequency transceiver, the RF front end usually refers to all circuit structures from the antenna to the mixer. Usually in the RF front end of the mobile terminal, the RF power amplifier is implemented by a GaAs (gallium arsenide) HBT (heterojunction bipolar transistor) process, and the RF switch adopts SOI. CMOS process implementation.

Referring to Figure 1, this is a single pole double throw RF switch for switching between transmit and receive channels. The RF switch has three connection ends: a terminal S1 is connected to the antenna, a terminal 2 is connected to the transmission channel, and a terminal 3 is connected to the reception channel. The RF switch has two control signals VT and VR. Under the action of the two control signals VT and VR, at any time, the terminal S1 or the terminal S2 is closed, and at this time, the terminal S1 and the terminal three S3 is disconnected; the terminal S1 is closed or closed with the terminal S3, and the terminal S1 is disconnected from the terminal S2. This achieves the single-pole double-throw function of switching the transmitting channel and the receiving channel.

Please refer to FIG. 2, which is a specific circuit implemented by the SOI CMOS process of the single-pole double-throw RF switch shown in FIG. The radio frequency switch includes a transmitting channel and a receiving channel. The main path of the transmitting channel is from the terminal two S2 through the DC blocking capacitor C1, and then through the cascaded three switching tubes T1 to T3 to the terminal one S1, the transmitting signal TX follows the path to the antenna. The main path of the receiving channel is from the terminal one S1 through the cascaded three switching tubes T4 to T6, and then through the blocking capacitor two C2 to the terminal three S3, the receiving signal RX leaves the antenna according to the path. The switching tubes T1 to T6 are all implemented by an SOI CMOS process, such as an NMOS device. A resistor R1 to R6 are respectively connected between the source and the drain of the switching transistors T1 to T6. The gates of the switching transistors T1 to T3 on the main path of the transmitting channel are respectively connected to the control voltage VT through a resistor R11 to R13. The gates of the switching transistors T4 to T6 on the main path of the receiving channel are respectively connected to the control voltage VR through a resistor R14 to R16. The connection between the DC blocking capacitor C1 and the switching transistor T1 is grounded through a resistor R21. The connection between the switch tube T6 and the DC blocking capacitor C2 is grounded through a resistor R22.

In the RF switch shown in Figure 2, only one of the two control signals VT and VR is a positive voltage and the other is a negative voltage at any time. When the control signal VT is a positive voltage, the resistor R21 keeps the channel DC voltage of the three switching tubes ST1 to ST3 at 0V, which causes the transmitting channel to be closed; and the control signal 2 VR is a negative voltage, which causes the receiving channel to be disconnected. . Vice versa, when the control signal 2 VR is a positive voltage, the resistor R22 keeps the DC voltage of the three switching tubes ST4 to ST6 at 0V, which will close the receiving channel; at the same time, the control signal VT is a negative voltage, which will cause The transmit channel is disconnected. At any time, the transmitting channel and the receiving channel are only one closed and the other is disconnected, realizing a single-pole double-throw RF switch. The values of the positive voltage and the negative voltage are usually the source voltage Vs of the MOSFET or the negative source voltage -Vs whose sign is inverted. The communication DC voltage refers to the source-drain voltage when the switch tube is turned on. When the switch tube is turned on, the source voltage and the drain voltage are equal to the channel voltage. Since the channel DC voltage of each of the switching transistors is maintained at 0V, the maximum value of the source voltage Vs depends on the NMOS device safety voltage using the SOI CMOS process. For example, a SOI CMOS process with a feature size of 0.18 μm requires a safe voltage of 2.5 V. Therefore, the absolute values of the two control signals VT and VR should be less than 2.5 V, otherwise the reliability of the RF switch will be reduced. The RF switch requires positive and negative voltages as control signals, and needs to include a positive voltage generating circuit and a negative voltage generating circuit. Therefore, the overall circuit structure is complicated, the area is large, and the cost is high.

Please refer to FIG. 3, which is another specific circuit implemented by the SOI CMOS process of the single-pole double-throw RF switch shown in FIG. Compared with FIG. 2, FIG. 3 has two main differences in circuit structure. One is that a DC blocking capacitor C3 is added at the end of the main path of the transmitting channel adjacent to the terminal two S2, and a DC blocking capacitor C4 is added at a position close to the terminal S1 at the leading end of the main path of the receiving channel. The second is to change the ground terminal of the resistor R21 to the output of the inverter I1, the input of the inverter I1 is used to receive the control signal VT; the original ground of the resistor R22 is reversed. The output of the second I2 and the input of the inverter II are used to receive the control signal VR.

After making the above improvements, in the RF switch shown in FIG. 3, the two control signals VT and VR have only one positive voltage and the other zero voltage at any time. When the control signal VT is a positive voltage, the transmission channel is closed; at the same time, the control signal VR is zero voltage, which will disconnect the receiving channel. Vice versa, when the control signal VR is a positive voltage, the receiving channel is closed; at the same time, the control signal VT is zero voltage, which will make the transmitting channel open. At any time, the transmitting channel and the receiving channel are only one closed and the other is disconnected, realizing a single-pole double-throw RF switch. The RF switch requires only a positive voltage and a zero voltage as control signals, and only needs to include a positive voltage generating circuit, omitting the negative voltage generating circuit, so that the overall circuit structure is simplified and the cost is reduced. However, in the main path of the transmitting channel, two blocking capacitors C1 and C3 are connected in series, and the switching on-resistance of the transmitting channel in the low frequency band is determined by the switching tubes T1 to T3 and the DC blocking capacitors C1 and C3, in order to avoid the low frequency band. When the on-resistance of the switch is large and the insertion loss is large, the series-connected DC capacitors C1 and C3 need to take a large capacitance value, usually ten or even several tens of pF. Correspondingly, two other DC blocking capacitors C2 and C4 are connected in series with the main path of the receiving channel, and a large capacitance value is also used to optimize the insertion loss of the low frequency band. A larger capacitance value will increase the area of the overall circuit structure of the RF switch.

technical problem

One of the technical problems to be solved by the present application is to provide an RF switch using a SOI CMOS process, which has the characteristics of simple circuit structure and small area.

The second technical problem to be solved by the present application is to provide a radio frequency transceiver front-end circuit including the SOI CMOS radio frequency switch, which adopts a multi-power mode and has high efficiency.

The third technical problem to be solved by the present application is to provide a mobile terminal including the radio frequency transceiver front-end circuit of the multi-power mode, which has the characteristics of high efficiency.

Technical solution

To solve one of the above technical problems, the SOI CMOS RF switch of the present application comprises a fixed connection end and a plurality of selective connection ends, forming a single-pole multi-throw switch; each selective connection end and the fixed connection end form a channel; The main path of the channel is three or more cascaded switching tubes, and the switching tubes are all SOI CMOS transistor; a capacitor is connected between the source and the drain of the switch tube at each end of each channel, and the middle switch tube of each channel (ie, other switch tubes except the switch tubes at both ends in the main path of each channel) A resistor is connected between the source and the drain, and the gates of all the switching tubes of each channel are connected to the same control voltage; the control voltage connected to each channel is also connected through a series of forward inverters and resistors. The main path of the channel is connected to any position except the two ends; at any time, only one control voltage is a positive voltage, and the remaining control voltages are all zero voltage; at any time, the control voltage for the positive voltage is connected. The channel is closed and the channel connected to the zero voltage control voltage is disconnected.

Further, the radio frequency switch comprises a fixed connection end and n selective connection ends, n is a natural number ≥ 2, and constitutes a single-pole n-throw switch. A common application for single-pole, n-throw switches is the single-pole, double-throw switch. For example, the fixed connection end is connected to the antenna, wherein one selective connection end is connected to the transmission channel, and the other selective connection end is connected to the reception channel, and the single-pole double-throw RF switch is used for switching the transmission channel and the reception channel. For another example, the fixed connection end is connected to the antenna, and the two selective connection ends are respectively connected to two different transmission channels, and the single-pole double-throw RF switch is used for switching two different transmission channels. Another common application for single-pole, n-throw switches is the single-pole, three-throw switch. For example, the fixed connection end is connected to the antenna, and the three selective connection ends are respectively connected to three different transmission channels, and the single-pole three-throw RF switch is used for switching three different transmission channels.

Further, m single-pole n-throw switches are stacked side by side, m is a natural number ≥ 2, and the m single-pole n-throw switches are a single-pole n1 throw switch, a single-pole n2 throw switch, ..., a single-pole nm-throw switch, and constitute a m-knife. (n1+n2+...+nm) throw the switch. Common applications for m-knife multi-throw switches are double-pole multi-throw RF switches and three-pole multi-throw RF switches. This parallel stacking method extends the SOI of the present application. The range of applications for CMOS RF switches.

Further, the number of cascaded switches in the main path of each channel is either the same or different; it depends on whether the RF power passed by each channel is the same. This provides greater flexibility in circuit design and extends the range of applications.

Further, the number of cascaded switching tubes in the main path of each channel is determined by the amount of RF power that the channel needs to bear and the amount of RF power that each switching transistor can withstand. Assuming that each switch tube can withstand the same RF power, then the greater the number of cascaded switches on the main path of each channel, the greater the RF power that the channel can withstand; the main path for each channel The smaller the number of switches in the upper cascade, the smaller the RF power that the channel can withstand. This provides greater flexibility in circuit design and extends the range of applications.

Further, the series branch of the inverter and the resistor of each channel is connected to one or more locations of the main path of the channel, and each access location is not the both ends of the main path of the channel. This facilitates circuit design and implementation.

Further, the switch transistor is an SOI CMOS transistor. In this case, by adjusting the SOI The size of a CMOS transistor can be used to adjust the amount of RF power that a single switch can withstand.

Further, the switching transistor is a plurality of SOI CMOS transistors connected in series. In this case, by adjusting the SOI Series number of CMOS transistors and / or SOI The size of a CMOS transistor can be used to adjust the amount of RF power that a single switch can withstand.

Further, the switch tube is an NMOS device fabricated on an SOI material. MOSFETs are the most common CMOS devices that can be fabricated on common silicon substrates or SOI substrates. The SOI CMOS RF switches of this application can be implemented by the most common NMOS devices, reflecting their excellent process compatibility and process maturity. . Compared with PMOS devices, NMOS devices can achieve lower on-resistance and smaller turn-off capacitance in a small volume, which is beneficial to improve the insertion performance and isolation of RF.

Further, the source and the drain of the switching transistor are interchangeable. This is due to the interchangeable nature of the source and drain of SOI CMOS devices, which greatly facilitates circuit design and manufacturing.

To solve the above technical problem, the RF transceiver front-end of the present application includes a power mode controller, p transmit channel RF power amplifiers corresponding to different power modes, and RF switches as described above. p is a natural number ≥ 2. The RF switch is a single pole n throw.

Further, the RF transceiver front end further includes q receiving channel RF power amplifiers; q is a natural number. The RF switch is a single pole p+q throw.

In order to solve the above technical problem, the mobile terminal of the present application includes a baseband control chip, a front end chip, and a multi-power mode radio frequency transceiver front-end and an antenna according to any of the foregoing.

Beneficial effect

The technical effect achieved by the SOI CMOS RF switch of the present application is that only a positive voltage and a zero voltage are required as control signals, and only a positive voltage generating circuit is included, the negative voltage generating circuit is omitted, and the single power supply can be operated, so the overall circuit structure Simplified and cost reduced. In addition, the main path of each channel does not contain a capacitor, and the capacitor is only between the source and the drain of the switch tube at each end of each channel, which allows the value of the capacitor to be small, thereby ensuring that the RF switch is in the low frequency band. The insertion loss is low, which reduces the area of the overall circuit.

The technical effect obtained by the RF transceiver front-end of the present application is that the RF power amplifier of different power modes is selected by the RF switch according to the output power level, thereby improving the efficiency of the RF power amplification and reducing the energy consumption. At the same time, the SOI provided by this application is adopted. CMOS RF switch, low insertion loss and low area.

The technical effect obtained by the mobile terminal of the present application is that the radio frequency transceiver front-end of the multi-power mode is adopted in the process of transmitting the radio frequency signal, thereby improving the efficiency of the radio frequency power amplification and reducing the energy consumption. At the same time, the SOI provided by this application is adopted. CMOS RF switch, low insertion loss and low area.

DRAWINGS

Figure 1 is a simplified schematic of a single pole double throw RF switch.

2 is a circuit implementation diagram of a conventional SOI CMOS single-pole double-throw RF switch.

FIG. 3 is a circuit implementation diagram of another conventional SOI CMOS single-pole double-throw RF switch.

4 is a circuit implementation diagram of Embodiment 1 (single pole double throw) of the SOI CMOS RF switch provided by the present application.

Figure 5 is a variation of the circuit of Figure 4.

Figure 6 is a simplified schematic of a single pole three throw switch.

7 is a circuit implementation diagram of Embodiment 2 (single pole three throw) of the SOI CMOS RF switch provided by the present application.

FIG. 8 is a schematic structural diagram of Embodiment 1 of a single switch tube in an SOI CMOS RF switch provided by the present application.

FIG. 9 is a schematic structural diagram of Embodiment 2 of a single switch tube in an SOI CMOS RF switch provided by the present application.

FIG. 10 is a schematic structural diagram of Embodiment 1 of a radio frequency transmitting front end circuit provided by the present application.

FIG. 11 is a schematic structural diagram of Embodiment 2 of a radio frequency transmitting front end circuit provided by the present application.

FIG. 12 is a schematic structural diagram of Embodiment 3 of a radio frequency transmitting front end circuit provided by the present application.

FIG. 13 is a schematic structural diagram of an embodiment of a mobile terminal provided by the present application.

The reference numerals in the figure indicate: S1 to S4 are the respective connection ends of the RF switch; VT, VR, VP, VQ are control signals; A is the antenna; TX, TX1 to TX3 are the transmission signals; RX is the reception signal; T1 to T9 For the switch; R1 to R9, R11 to R19, R21 to R23 are resistors; C1 to C10 are DC blocking capacitors; I1 to I3 are inverters; N1 to N5 are NMOS devices; G is the gate; D is the drain ; S is the source; 51, 61, 71 are the power mode controller; 52, 62, 72 are the high power mode RF power amplifier; 63, 73 are the medium power mode RF power amplifier; 53, 64, 74 are the low power mode RF power amplifier; 59, 69, 79 are RF switches; 81 is a baseband control chip; 82 is a front-end chip; 83 is a multi-power mode RF transceiver front-end.

Embodiments of the invention

Please refer to FIG. 4 , which is a first embodiment of the SOI CMOS RF switch provided by the present application, which is a specific circuit implemented by the SOI CMOS process of the single pole double throw RF switch shown in FIG. 1 . The radio frequency switch includes a transmitting channel and a receiving channel. The main path of the transmitting channel is from the terminal two S2 through the cascaded three switching tubes T1 to T3 to the terminal one S1, and the transmitting signal TX follows the path to reach the antenna. The main path of the receiving channel is from the terminal one S1 through the cascaded three switching tubes T4 to T6 to the terminal three S3, and the receiving signal RX leaves the antenna according to the path. The switching tubes T1 to T6 are all implemented by an SOI CMOS process, such as an NMOS device. A DC blocking capacitor C5, a resistor R2, a DC blocking capacitor C6, a DC blocking capacitor C7, a resistor R5, and a DC blocking capacitor C8 are respectively connected between the source and the drain of the switching transistors T1 to T6. The gates of the switching transistors T1 to T3 on the main path of the transmitting channel are respectively connected to the control voltage VT through a resistor R11 to R13. The control voltage VT is also connected between the switching transistors T1 and T2 of the main path of the transmitting channel through a series connection of the forward-connected inverter I1 and the resistor R21. The gates of the switching transistors T4 to T6 on the main path of the receiving channel are respectively connected to the control voltage VR through a resistor R14 to R16. The control voltage VR is also connected between the switching transistors T5 and T6 of the main path of the receiving channel through a series connection of the forward-connected inverters II2 and R22.

The MOSFETs implemented in the SOI CMOS process are only NMOS devices and PMOS devices. Since the RF switch needs to be as low as possible when turned on, the turn-off capacitor when turned off is as small as possible. In the on state, compared with the NMOS device, the PMOS device must pass several times the size to obtain the same on-resistance, and the larger the size, the larger the turn-off capacitance, thereby degrading the insertion loss and isolation of the RF. Important performance such as degree. So in SOI In CMOS RF switch designs, NMOS devices are typically used instead of PMOS devices.

In the RF switch shown in Figure 4, only one of the two control signals VT and VR is a positive voltage and the other is a zero voltage at any time. When the control signal VT is a positive voltage, the positive voltage is respectively connected to the gates of the switching tubes T1 to T3 through the resistors R11 to R13, and the positive voltage is connected to the zero voltage through the inverter-I1 and the resistor R21. The drain of the switch T1 and the source of the switch T2. Due to the presence of the resistor two R2, the drain voltage of the switching transistor two T2 and the source voltage of the switching transistor three T3 are zero voltage. Therefore, the voltage difference between the gate and the source (or the drain) of the three switching tubes T1 to T3 on the main path of the transmitting channel is the positive voltage, and when the positive voltage is greater than the threshold voltage of the switching tube, the switching tube T1 Turning on to T3 will cause the transmit channel to close. At the same time, the control signal two VR is zero voltage, and the zero voltage is respectively connected to the gates of the switching tubes T4 to T6 through the resistors R14 to R16, and the zero voltage is converted into a positive voltage to the switch through the inverter two T2 and the resistor R22. Tube five T5's drain and switch tube six T6 source. Due to the presence of the resistor R5, the source voltage of the switching transistor five T5 and the drain voltage of the switching transistor four T4 are positive voltages. Therefore, the voltage difference between the gate and the source (or the drain) of the three switching tubes T4 to T6 on the main path of the receiving channel is a negative value, which is necessarily smaller than the threshold voltage of the switching tube, and the switching tubes T4 to T6 are all turned off. Will disconnect the receiving channel. Vice versa, when the control signal VR is a positive voltage, the receiving channel is closed; at the same time, the control signal VT is zero voltage, which will make the transmitting channel open. At any time, the transmitting channel and the receiving channel are only one closed and the other is disconnected, realizing a single-pole double-throw RF switch.

In the first embodiment, the single-pole double-throw RF switch is used for switching the transmitting channel and the receiving channel, and can also be used for switching any two channels. Referring to FIG. 5, this is a variant of the first embodiment, which is schematically used to switch the radio frequency signals TX1 and TX2 of two different transmission channels. The RF switch shown in Figure 5 includes channel one and channel two. The main path of the channel one is from the terminal two S2 through the cascade of three switching tubes T1 to T3 to the terminal one S1, and the signal one TX follows the path to reach the antenna. The main path of the channel 2 is from the terminal three S3 through the cascade of three switching tubes T4 to T6 to the terminal one S1, and the signal two TX2 follows the path to the antenna. The implementation principle of the RF switch shown in Figure 5 is the same as that of the RF switch shown in Figure 4, and will not be described again.

In the first embodiment, the main path of each channel has only three switching tubes cascaded. Optionally, the number of cascading switches in each channel may be between 3 and 15. The main factor determining the number of cascaded switches in the main path of each channel is the amount of RF power that the RF switch is required to withstand and the RF power that each switch can withstand. Assuming that the RF power of a single switch tube can not be changed, if the RF switch needs to withstand a large RF power, then a larger number of switch tubes need to be cascaded in the main path of each channel; and vice versa, if the RF The switch only has to withstand a small amount of RF power, so only a small number of switches are cascaded in the main path of each channel.

If the number of switching tubes of the main path of each channel is more than three, then only the source and the drain of the two switching tubes at both ends of the main path of each channel are connected to the DC blocking capacitor, and each channel is connected. The main path is connected to the resistor between the source and the drain of each of the switching tubes in the middle except the two ends.

In the first embodiment, the same number of switching tubes are cascaded in the main path of each channel. Alternatively, the number of cascaded switching tubes in each channel may be the same or different. The number of cascading switches in the main path of each channel is determined by the power of the RF signal that the channel passes. If the RF signals passed by different channels of the RF switch have the same power, then the same number of switches are cascaded in the main path of each channel. If the radio frequency signals passing through different channels of the RF switch have different powers, the channel through which the higher power RF signal passes may be cascaded with a larger number of switching tubes, and the channels through which the lower power RF signals pass may be cascaded with a smaller number of channels. turning tube.

In the first embodiment, the series branch formed by the forward-connected inverter-I1 and the resistor R21 may be changed to any position other than the two ends of the main path of the transmission channel or the channel one. The two ends of the main path of the transmitting channel or channel one refer to terminal one S1 and terminal two S2. In Fig. 4 or Fig. 5, the branch of the inverter I1 can be connected between the switching tube two T2 and T3 of the transmission path or the channel of the channel. Similarly, the series branch formed by the forward-connected inverter II 2 and the resistor R22 can be changed to any position other than the two ends of the main path connected to the receiving channel or channel 2. Both ends of the main path of the receiving channel or channel 2 refer to terminal one S1 and terminal three S3. In Fig. 4 or Fig. 5, the branch of the inverter II2 can be connected between the switching tubes T4 and T5 of the receiving path or the channel 2 main path. Changing the access position of the inverter branch has no effect on the performance of the RF switch. This is because each channel except the switch tube at both ends, the source and the drain of the middle switch tube are connected by a resistor, so the source voltage and the drain voltage of the middle switch tube are connected to the inverter branch. The in-point voltage remains the same and does not change with the access position of the inverter branch. Correspondingly, the positions of the inverter paths of the different channels entering the main path may be the same position, the symmetrical position, or may not be the same or symmetric positions, and only need to satisfy the two ends of the main path where the access position is not the channel. Accordingly, the inverter branch of each channel can access one or more locations of the primary path of the channel, only to satisfy that each access location is not the two ends of the primary path of the channel.

Referring to Figure 6, this is a single-pole, three-throw RF switch for switching three channels. The RF switch has four connection ends: a terminal S1 is connected to the antenna, a terminal S2 is connected to the channel 1, a terminal 3 is connected to the channel 2, and a terminal 4 is connected to the channel 3. The RF switch has two control signals VT and VR. Under the action of the two control signals VT and VR, at any time, the terminal S1 or the terminal S2 is closed, and the terminal one S1 and the other two The terminals S3 and S4 are disconnected; the terminal S1 or the terminal S3 is closed, and the terminal S1 is disconnected from the other two terminals S2 and S4; the terminal S1 or the terminal four S4 When it is closed, the terminal S1 is disconnected from the other two terminals S2 and S3. This achieves a single-pole, three-throw function that switches three channels.

Please refer to FIG. 7 , which is a second embodiment of the SOI CMOS RF switch provided by the present application, which is a specific circuit implemented by the SOI CMOS process shown in FIG. 6 , which is schematically used to switch three Radio frequency signals TX1, TX2 and TX3 of different transmission channels. The radio frequency switch includes three channels. The main path of the channel one is from the terminal two S2 through the cascaded three switching tubes T1 to T3 to the terminal one S1, and the signal one TX1 follows the path to reach the antenna. The main path of the channel 2 is from the terminal three S3 through the cascade of three switching tubes T4 to T6 to the terminal one S1, and the signal two TX2 follows the path to the antenna. The main path of the channel three is from the terminal four S4 through the cascade of three switching tubes T7 to T9 up to the terminal one S1, and the signal three TX3 follows the path to reach the antenna. The switching tubes T1 to T9 are all implemented by an SOI CMOS process, such as an NMOS device. A DC blocking capacitor C5, a resistor R2, a DC blocking capacitor C6, a DC blocking capacitor C7, a resistor R5, a DC blocking capacitor C8, and a DC blocking capacitor are respectively connected between the source and the drain of the switching transistors T1 to T9. Straightening capacitor C9, a resistor R8, a DC blocking capacitor C10. The gates of the switching transistors T1 to T3 on the channel-main path are respectively connected to the control voltage VT through a resistor R11 to R13. The control voltage VT is also connected between the switching transistors T1 and T2 of the channel-main path through a series connection of the forward-connected inverter I1 and the resistor R21. The gates of the switching transistors T4 to T6 on the main path of the channel 2 are respectively connected to the control voltage two VP through a resistor R14 to R16. The control voltage two VP is also connected between the switching tubes T4 and T5 of the channel two main paths through the series connection of the forwardly connected inverter two I2 and the resistor R22. The gates of the switching transistors T7 to T9 on the three main paths of the channel are respectively connected to the control voltage three VQ through a resistor R17 to R19. The control voltage three VQ is also connected between the switching transistors T7 and T9 of the three main paths of the channel through the series connection of the forwardly connected inverter three I3 and the resistor R23.

In the RF switch shown in Figure 7, the three control signals VT, VP, and VQ have only one positive voltage at any time, and the other two are zero voltages. When the control signal VT is a positive voltage, the channel is closed; at the same time, the other two control signals VP, VQ are zero voltage, which will make both channel 2 and channel 3 open. When the control signal two VP is a positive voltage, the channel two is closed; at the same time, the other two control signals VT, VQ are zero voltage, which will disconnect both channel one and channel three. When the control signal three VQ is a positive voltage, the channel three is closed; at the same time, the other two control signals VT, VP are zero voltage, which will disconnect both channel one and channel two. At any time, only one of the three channels is closed and the other two are disconnected, realizing a single-pole three-throw RF switch.

In the second embodiment, the single-pole three-throw RF switch is used for switching three transmission channels, and can also be used to switch any three channels.

In the second embodiment, the main path of each channel has only three switching tubes cascaded. Optionally, the number of cascading switches in each channel may be between 3 and 15. If the number of switching tubes of the main path of each channel is more than three, then only the source and the drain of the two switching tubes at both ends of the main path of each channel are connected to the DC blocking capacitor, and each channel is connected. The main path is connected to the resistor between the source and the drain of each of the switching tubes in the middle except the two ends. Alternatively, the number of cascaded switching tubes in each channel may be the same or different. These are the same as those in the first embodiment and will not be described again.

In the second embodiment, the inverter branch can be connected to any position other than the two ends of the main path of each channel. The positions of the inverter paths of the different channels to the main path may be the same position, the symmetrical position, or the same or symmetric position, and only need to satisfy the two ends of the main path where the access position is not the channel. The inverter branch of each channel can access one or more locations of the primary path of the channel, only to satisfy that each access location is not the two ends of the primary path of the channel. These are the same as those in the first embodiment and will not be described again.

Compared with the existing SOI CMOS RF switch, the SOI CMOS RF switch provided by the present application has the following beneficial effects and features.

First, the SOI CMOS RF switch provided by the present application only needs a positive voltage and a zero voltage as control signals, and only needs a positive voltage generating circuit, and a negative voltage generating circuit is omitted, so that the overall circuit structure is simplified and the cost is reduced.

Second, in the SOI CMOS RF switch provided by the present application, the main path of each channel is composed only of a plurality of cascaded switching tubes, and does not include a DC blocking capacitor. At this time, the on-resistance of the switch in the low frequency band of each channel is determined only by the switch itself, and this value is generally small, in the range of 1 to 5 ohms. The DC blocking capacitor that is transferred from the main path of each channel does not need to take a large capacitance value, and can take a smaller capacitance value according to the required power, usually taking a few pF, so as to maintain the insertion loss of the low frequency band. The lower, the overall circuit area of the RF switch is greatly reduced.

Third, in the SOI CMOS RF switch provided by the present application, the DC blocking capacitor is transferred between the source and the drain of the switching transistor at both ends of the main path of each channel. When a channel is disconnected, the voltage of the RF signal is approximately evenly distributed across the switches on that channel. Since the switching transistors at both ends of the channel are connected with a DC blocking capacitor, the equivalent capacitance of the source terminal and the drain terminal is larger than the equivalent capacitance of the source terminal and the drain terminal of the intermediate switching transistor of the channel, which may result in The voltage difference between the source and the drain of the switch tube at both ends of the channel is larger than the voltage difference between the source and the drain of the middle switch tube of the channel, so that the switch tubes at both ends of the channel are more likely to be struck than the intermediate switch tube. wear. SOI provided by this application if other conditions remain unchanged CMOS RF switch and SOI shown in Figure 2. Compared to CMOS RF switches, each channel can withstand slightly less power. If the value of the DC blocking capacitor is larger, the difference is less obvious; vice versa, if the value of the DC blocking capacitor is smaller, the difference is more obvious. SOI provided by this application In the CMOS RF switch, the DC blocking capacitor generally takes a few pF to meet the balance of various performance indicators.

In each of the above embodiments, a single switching transistor can be implemented by one NMOS device. Referring to FIG. 8, the switch T1 is an NMOS device N1. At this time, the source, the drain, and the gate of the NMOS device N1 are the source S, the drain D, and the gate G of the switch T1, wherein the source S and The drain D can be interchanged. By adjusting the size of the NMOS device, it can be used to adjust the amount of RF power that a single switch can withstand.

In the various embodiments above, a single switch transistor can be implemented by a plurality of NMOS devices in series. Referring to FIG. 9, this is to form a switching transistor T1 by connecting five NMOS devices N1 to N5 connected in series. The sources and drains of the respective NMOS devices N1 to N5 are cascaded with each other, and both ends of the cascade are used as the source S and the drain D of the switching transistor T1. The gates of the respective NMOS devices N1 to N5 are connected together as the gate G of the switching transistor T1. By adjusting the number of series connections of NMOS devices and/or the size of NMOS devices, it can be used to adjust the amount of RF power that a single switch can withstand.

In the above embodiments, the source and the drain of all the switches T1 to T9 are interchangeable, and the source and drain drawn or labeled in FIG. 4 to FIG. 5 and FIG. 7 to FIG. 9 are only one type. Indicate. This is because the source and drain of the MOSFET implemented by the SOI CMOS process are interchangeable.

The above two embodiments respectively disclose a single-pole double-throw switch and a single-pole three-throw switch implemented by the SOI CMOS process, and can also design an SOI based on the same principle. The single-pole multi-throw switch realized by the CMOS process is, for example, a single-pole 4 to 16-throw switch. The current double-pole multi-throw switch and three-pole multi-throw switch are each composed of a single-pole multi-throw switch and a simple parallel stack. For example, a double-pole, four-throw switch is a superposition of two single-pole and double-throw switches, and a double-pole, five-throw switch is a single-pole double-throw switch and a single-pole three-throw switch, and a three-pole, six-throw switch is three single-pole and double-throw switches. The switch is superimposed. By analogy, based on the same principle, a double-pole multi-throw switch such as a double-pole 2 to 21-throw switch and a three-pole multi-throw switch such as a three-pole 2-to-one throw switch can be designed.

Please refer to FIG. 10 , which is a first embodiment of the radio frequency transceiver front-end provided by the present application, and is used for radio frequency transmission in two power modes. The RF transceiver front end includes a power mode controller 51, a high power mode RF power amplifier 52, a low power mode RF power amplifier 53 and an RF switch 59. The power mode controller 51 is configured to select a certain RF power amplifier according to the output power of the position of the antenna A. For example, a coupler (not shown) couples the output power according to a certain ratio for detection, thereby selecting a certain RF power amplifier. Each RF power amplifier contains a power amplifier chip and a matching network. The two RF power amplifiers 52, 53 respectively output high and low levels of RF power. Each RF power amplifier is individually designed for its respective output power level, thus ensuring high efficiency in all power modes. For example, a high power mode RF power amplifier 52 can be selected for amplification of high power signals. As another example, the low power mode RF power amplifier 53 can be selected for amplification of the low power signal. The RF switch 59 is a single pole double throw RF switch, as shown in Figure 1. The RF switch 59 can be fabricated using the SOI CMOS single-pole double-throw RF switch shown in FIG. The RF input signal RFin enters the input terminals of the two RF power amplifiers 52, 53. The outputs of the two RF power amplifiers 52, 53 are respectively connected to the terminal 2 S2 of the RF switch 59, the terminal 3 S3, and the terminal of the RF switch 59 is S1. Antenna A outputs an amplified RF output signal RFout. The power mode controller 51 provides two control signals VT and VR for the RF switch 59. The two control signals VT and VR have only one positive voltage and the other zero voltage at any time. At any time, only one terminal of terminal two S2, terminal three S3 is closed with terminal one S1 and the other terminal is disconnected from terminal one S1, realizing single-pole double-throwing RF switch. By switching the RF switch 59, the RF input signal RFin can select the appropriate power mode for RF power amplification in both power modes while maintaining high efficiency.

Please refer to FIG. 11 , which is a second embodiment of the radio frequency transceiver front-end provided by the present application, and is used for radio frequency transmission in a three-power mode. The radio frequency transceiver front end includes a power mode controller 61, a high power mode radio frequency power amplifier 62, a medium power mode radio frequency power amplifier 63, a low power mode radio frequency power amplifier 64, and a radio frequency switch 69. The power mode controller 61 is configured to select a certain RF power amplifier according to the output power of the position of the antenna A. For example, a coupler (not shown) couples the output power according to a certain ratio for detection, thereby selecting a certain RF power amplifier. Each RF power amplifier contains a power amplifier chip and a matching network. The three RF power amplifiers 62 to 64 output high, medium and low levels of RF power, respectively. Each RF power amplifier is individually designed for its respective output power level, thus ensuring high efficiency in all power modes. The RF switch 69 is a single pole triple throw RF switch, as shown in FIG. The RF switch 69 can be fabricated by the SOI CMOS single-pole triple-throw RF switch shown in FIG. The RF input signal RFin enters the input terminals of the three RF power amplifiers 62 to 64. The outputs of the three RF power amplifiers 62 to 64 are respectively connected to the terminal 2 S2 of the RF switch 69 to the terminal 4 S4, and the terminal of the RF switch 69 is S1. Antenna A outputs an amplified RF output signal RFout. The power mode controller 61 provides three control signals VT, VP, and VQ for the RF switch 69. The three control signals VT, VP, and VQ are only one positive voltage at any time, and the other two are zero voltages. At any time, only one of the terminals 2 S2 to 4 S4 is closed with the terminal S1 and the other two terminals are disconnected from the terminal S1, realizing a single-pole three-throw RF switch. By switching the RF switch 69, the RF input signal RFin can select the appropriate power mode for RF power amplification in the three power modes while maintaining high efficiency.

Please refer to FIG. 12 , which is a third embodiment of the radio frequency transceiver front-end provided by the present application, for radio frequency reception and radio frequency transmission in three power modes. The RF transceiver front end includes a power mode controller 71, a high power mode RF power amplifier 72, a medium power mode RF power amplifier 73, a low power mode RF power amplifier 74, a receive channel RF power amplifier 75, and an RF switch 79. The power mode controller 71 is configured to select a certain RF power amplifier of the transmission channel according to the output power of the position of the antenna A, for example, a coupler (not shown) couples the output power according to a certain ratio for detection, thereby selecting a transmission channel. An RF power amplifier. Each RF power amplifier contains a power amplifier chip and a matching network. The three RF power amplifiers 72 to 74 of the transmission channel respectively output high, medium and low levels of RF power. Each RF power amplifier in the transmit channel is individually designed for its respective output power level, thus ensuring high efficiency in all power modes. The receive channel RF power amplifier 75 is, for example, a low noise amplifier (LNA). The RF switch 79 is a single pole, four throw RF switch. The RF transmission input signal RFin1 enters the input terminals of the three RF power amplifiers 72 to 74 of the transmission channel. The outputs of the three RF power amplifiers 72 to 74 are respectively connected to the terminal 2 S2 of the RF switch 79 to the terminal 4 S4, and the RF switch 79 The terminal one S1 outputs the amplified RF output signal RFout to the antenna A. Alternatively, the terminal S1 of the RF switch 79 receives the RF signal from the antenna A, that is, the RF receives the input signal RFin2. The terminal five S5 of the RF switch 79 is connected to the input end of the receiving channel RF power amplifier 75, and the output of the receiving channel RF power amplifier 75 outputs the amplified RF receiving output signal RFout2.

When the third embodiment of the radio frequency transceiver front-end is used for radio frequency transmission, the terminal S1 of the radio frequency switch 79 is disconnected from the terminal S55. At this time, the power mode controller 71 provides three control signals VT, VP, and VQ for the RF switch 79. The three control signals VT, VP, and VQ are only positive at any time for RF transmission, and the other two are Zero voltage. At any time for RF transmission, only one terminal of terminal two S2 to terminal S4 is closed with terminal one S1 and the other two terminals are disconnected from terminal one S1, realizing single-pole three-throw RF switch . By switching the RF switch 79, the RF input signal RFin can select the appropriate power mode for RF power amplification in the three power modes while maintaining high efficiency.

When the third embodiment of the radio frequency transceiver front-end is used for radio frequency reception, the terminal S1 of the radio frequency switch 79 is closed between the terminal S1 and the terminal S5, and the terminal S1 is disconnected from the other terminals.

Please refer to FIG. 13, which is a schematic structural diagram of a mobile terminal. The mobile terminal includes a baseband control chip 81, a front end chip (ie, a radio frequency transceiver) 82, a multi-power mode radio frequency transceiver front end 83, and an antenna A. The baseband control chip 81 is used to synthesize the baseband signal to be transmitted or to decode the received baseband signal. The front end chip 82 is configured to process the baseband signal transmitted from the baseband control chip 81 to generate a radio frequency signal, and send the generated radio frequency transmission signal to the multi-power mode radio frequency transceiver front-end 83; or to the multi-power mode radio frequency transceiver front-end transceiver The transmitted radio frequency received signal is processed to generate a baseband signal, and the generated baseband signal is transmitted to the baseband control chip 81. The multi-power mode RF transceiver front-end 83 may be the RF transceiver front-end shown in any one of FIG. 10 to FIG. 12, for performing processing such as power amplification on the radio frequency transmission signal transmitted from the front-end chip 82, or receiving the radio frequency signal and The radio frequency received signal is processed and sent to the front end chip 82. The antenna A is used for externally transmitting the radio frequency transmission signal transmitted from the multi-power mode radio frequency transceiver front end 83 or receiving the radio frequency signal from the outside. By adopting the multi-power mode radio frequency transceiver front-end provided by the present application, the efficiency of the entire mobile terminal when transmitting the radio frequency signal can be improved.

The above are only the preferred embodiments of the present application and are not intended to limit the application. Various changes and modifications can be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application are intended to be included within the scope of the present application.

Industrial applicability

The SOI CMOS RF switch provided by the present application can be implemented by an NMOS device (preferably) or a PMOS device.

The RF transceiver front end provided by the present application can be implemented by a power mode controller, a radio frequency power amplifier, and an SOI CMOS RF switch provided by the present application.

The mobile terminal provided by the present application can be implemented by a baseband control chip, a front end chip, an antenna, and a radio frequency transceiver front end provided by the present application.

Claims

An SOI CMOS RF switch includes a fixed connection end and a plurality of selective connection ends to form a single-pole multi-throw switch; wherein: each of the selective connection ends and the fixed connection end form a channel; each channel The main path is three or more cascaded switching tubes, and the switching tubes are all SOI CMOS transistors; capacitors are connected between the source and the drain of the switching tubes at both ends of each channel, and the intermediate switching tubes of each channel A resistor is connected between the source and the drain, and the gates of all the switching tubes of each channel are connected to the same control voltage; the control voltage connected to each channel is also connected through a forward inverter and a series branch of the resistor. The main path connected to the channel is at any position except the two ends; at any time, only one control voltage is a positive voltage, and the remaining control voltages are all zero voltage; at any time, the control voltage of the positive voltage is connected The channel is closed and the channel connected to the zero voltage control voltage is disconnected.

2. The SOI CMOS radio frequency switch according to claim 1, wherein said RF switch comprises a fixed connection end and n selective connection ends to form a single-pole n-throw switch.

3. The SOI CMOS radio frequency switch according to claim 2, wherein m single-pole n-throw switches according to claim 2 are stacked side by side, and the m single-pole n-throw switches are single-pole n1 throw switches and single-pole n2 switches, respectively. Throw switch, ..., single-pole nm-throw switch, constitute m-knife (n1+n2+...+nm) throw switch.

4. The SOI CMOS radio frequency switch of claim 1 wherein the number of cascaded switching transistors in the main path of each channel is the same or different.

5. The SOI CMOS radio frequency switch according to claim 4, wherein the number of the cascaded switching tubes in the main path of each channel is the magnitude of the RF power that the channel needs to bear and the RF that each switching transistor can withstand. The power size is determined together.

6. The SOI CMOS radio frequency switch of claim 1 wherein the series of inverters and resistors of each channel are connected to one or more locations of the main path of the channel, each access location Not both ends of the main path of the channel.

7. The SOI CMOS radio frequency switch of claim 1, wherein the switching transistor is an SOI CMOS transistor or a plurality of SOI CMOS transistors connected in series.

8. The SOI CMOS radio frequency switch of claim 7 wherein said SOI CMOS transistor is an NMOS device fabricated from SOI material.

9. The SOI CMOS radio frequency switch according to claim 7, wherein the source and the drain of the switching transistor are arbitrarily interchanged; and the source and the drain of the SOI CMOS transistor are arbitrarily interchanged.

A radio frequency transceiver front-end, comprising: a power mode controller, p transmit channel radio frequency power amplifiers respectively corresponding to different power modes, and the radio frequency switch according to any one of claims 1 to 9; The RF switch is a single-pole p-throw.

11. The radio frequency transceiver front-end according to claim 10, further comprising q receiving channel RF power amplifiers; wherein the RF switches are single-pole p+q throws.

12. A mobile terminal, comprising: a baseband control chip, a front end chip, a multi-power mode radio frequency transceiver front end and an antenna according to claim 10 or 11.